JP2018073995A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can achieve scaling or high integration.SOLUTION: A semiconductor device includes: a first insulator arranged on a substrate; a first oxide arranged on the first insulator; a second oxide arranged in contact with at least part of an upper surface of the first oxide; a second insulator arranged on the second oxide; a first conductor arranged on the second insulator; a second conductor arranged on the first conductor; a sidewall insulator arranged in contact with lateral faces of the second insulator, the first conductor and the second conductor; and a third insulator arranged in contact with an upper surface of the second oxide and a lateral face of the sidewall insulator, in which an upper surface of the sidewall insulator and an uppermost surface of the third insulator are almost flush with an uppermost surface of the second conductor, and the third insulator contains one of or both of hydrogen and nitrogen.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for driving the semiconductor device. One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

  Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  A technique for forming a transistor using a semiconductor thin film has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

  For example, a technique for manufacturing a display device using a transistor including zinc oxide or an In—Ga—Zn-based oxide as an active layer as an oxide semiconductor is disclosed (see Patent Documents 1 and 2). .

  In recent years, a technique for manufacturing an integrated circuit of a memory device using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3). In addition to memory devices, arithmetic devices and the like have been manufactured using transistors including oxide semiconductors.

JP 2007-123861 A JP 2007-96055 A JP 2011-119694 A

  By the way, with the increase in performance, size, and weight of electronic devices, integrated circuits are highly integrated and transistors are miniaturized. In accordance with this, process rules for manufacturing transistors are also decreasing year by year, such as 45 nm, 32 nm, and 22 nm. Accordingly, a transistor including an oxide semiconductor is required to have a fine structure and good electrical characteristics as designed.

  An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

  An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is a transistor including an oxide semiconductor, in which a sidewall insulator is provided in contact with a side surface of a gate electrode and a gate insulator. Note that the sidewall insulator is preferably formed by an atomic layer deposition (ALD) method. By forming the sidewall insulator by the ALD method, a sidewall insulator made of a film with good coverage or a dense film can be obtained. By providing such an insulator in contact with the side surface of the gate insulating film, oxygen in the gate insulating film is prevented from diffusing to the outside, and impurities such as water or hydrogen are prevented from entering the gate insulating film. be able to.

  In addition, when the source region and the drain region of the transistor are formed, the sidewall insulator is formed, so that a region overlapping with the gate electrode of the oxide semiconductor is hardly lowered. Accordingly, even in a miniaturized transistor, the source region and the drain region can be prevented from extending more than necessary to the gate side, and favorable electrical characteristics can be given to the transistor.

  One embodiment of the present invention includes a first insulator disposed over a substrate, a first oxide disposed over the first insulator, and at least a part of an upper surface of the first oxide. A second oxide disposed in contact with the second oxide; a second insulator disposed on the second oxide; a first conductor disposed on the second insulator; A second conductor disposed on the second conductor, a second insulator, the first conductor, and a sidewall insulator disposed in contact with a side surface of the second conductor; A third insulator disposed in contact with an upper surface of the oxide and in contact with a side surface of the sidewall insulator, and the upper surface of the sidewall insulator and the uppermost surface of the third insulator are This is a semiconductor device characterized in that it substantially coincides with the uppermost surface of the two conductors.

  In the above, it is preferable that the first oxide and the second oxide each include In, an element M (M is Al, Ga, Y, or Sn), and Zn.

  In another embodiment of the present invention, at least one of the first insulator disposed on the substrate, the first oxide disposed on the first insulator, and the top surface of the first oxide. A second oxide disposed in contact with the portion, a third oxide disposed on the second oxide, a second insulator disposed on the third oxide, A first conductor disposed on the second insulator; a second conductor disposed on the first conductor; a second insulator; a first conductor; A sidewall insulator disposed in contact with the side surface of the second conductor, and a third insulator disposed on the second oxide and in contact with the side surface of the sidewall insulator; And the upper surface of the sidewall insulator and the uppermost surface of the third insulator substantially coincide with the uppermost surface of the second conductor.

  In the above structure, the side surface of the third oxide may be in contact with the sidewall insulator, and the third insulator may be in contact with the upper surface of the second oxide.

  In the above structure, the side surface of the third oxide may substantially coincide with the side surface of the second oxide, and the third insulator may be in contact with the upper surface of the third oxide.

  In the above, it is preferable that each of the first to third oxides contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.

  In the above, the region overlapping the third insulator of the second oxide has a higher concentration of at least one of hydrogen and nitrogen than the vicinity of the center of the region overlapping the second insulator of the second oxide. It may be configured.

  In the above, the region overlapping the third insulator and the sidewall insulator of the second oxide has at least hydrogen and nitrogen from the vicinity of the center of the region overlapping the second insulator of the second oxide. One density may be large.

  In addition, in the above, the third insulator of the second oxide, the sidewall insulator, and the region overlapping with the vicinity of both ends of the second insulator overlap with the second insulator of the second oxide. A configuration in which the concentration of at least one of hydrogen and nitrogen is higher than the vicinity of the center of the region may be adopted.

  In the above, the sidewall insulator is preferably formed using the ALD method. In the above, the sidewall insulator preferably contains either aluminum oxide or hafnium oxide.

  In the above, the first conductor preferably includes a conductive oxide. In the above, it is preferable that the third insulator includes one or both of hydrogen and nitrogen. In addition, in the above, the second conductor, the first conductor, and the third conductor disposed so as to have a region overlapping with the second conductor are provided below the first insulator. Is preferred.

  In the above, the semiconductor device further includes a buffer layer disposed on at least a part of the second conductor, and the buffer layer includes the second conductive in at least a part of the region overlapping with the second oxide. The side surface of the buffer layer may be in contact with the sidewall insulator without overlapping the body, and the upper surface of the buffer layer may be substantially coincident with the uppermost surface of the second conductor.

  In the above, the buffer layer may include an insulator. In the above, the buffer layer may include a conductor.

  In another embodiment of the present invention, a first insulator is formed over a substrate, a first oxide film and a second oxide film are sequentially formed over the first insulator, The first oxide film and the second oxide film are processed into an island shape to form a first oxide and a second oxide, and the first insulating film and the first oxide are formed on the second oxide. The conductive film, the second conductive film, and the first buffer layer are sequentially formed, and the first insulating film, the first conductive film, the second conductive film, and the first buffer layer are etched. , Forming a second insulator, a first conductor, a second conductor, and a second buffer layer, the first insulator, the first oxide, the second oxide, the second A third insulating film is formed using the ALD method so as to cover the insulator, the first conductor, the second conductor, and the second buffer layer, and dry etching treatment is performed on the third insulating film. Go to the second absolute A first sidewall insulator is formed in contact with a side surface of the body, the first conductor, the second conductor, and the second buffer layer, and the first insulator, the first oxide, A fourth insulating film is formed by PECVD, covering the oxide, the first sidewall insulator, and the second buffer layer, and the fifth insulating film is formed on the fourth insulating film. And the second buffer layer, the first sidewall insulator, the fourth insulating film, and a part of the fifth insulating film are removed until a part of the second conductor is exposed. Then, a third buffer layer, a second sidewall insulator, a third insulator, and a fourth insulator are formed.

  In the above, the thickness of the first buffer layer is preferably 10 nm or more and 100 nm or less. In the above, it is preferable that the fourth insulating film be formed in an atmosphere containing nitrogen. In the above, it is preferable that the third buffer layer, the second sidewall insulator, the third insulator, and the fourth insulator are formed by CMP treatment. In the above, it is preferable to form the first conductive film using a sputtering treatment in an atmosphere containing oxygen.

  According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

  Alternatively, a semiconductor device capable of holding data for a long period can be provided. Alternatively, a semiconductor device with high information writing speed can be provided. Alternatively, a semiconductor device with a high degree of design freedom can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views of a transistor according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. The figure explaining the range of atomic ratio of the metal oxide which concerns on this invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. 10A and 10B are a flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component. FIG. 14 illustrates an electronic device according to one embodiment of the present invention.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may not be described in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

  In this specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  In addition, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

  In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.

  Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. By including impurities, for example, DOS (Density of States) of a semiconductor may increase or crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by mixing impurities. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

  Note that in this specification and the like, a silicon oxynitride film has a higher oxygen content than nitrogen in its composition. For example, preferably oxygen is 55 atomic% to 65 atomic%, nitrogen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range. The silicon nitride oxide film has a nitrogen content higher than that of oxygen. For example, preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, the term “insulator” can be restated as an insulating film or an insulating layer. In addition, the term “conductor” can be restated as a conductive film or a conductive layer. In addition, the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.

  The transistors described in this specification and the like are field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

  Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  Note that in this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing as an OS FET, it can be said to be a transistor including an oxide or an oxide semiconductor.

(Embodiment 1)
<Configuration Example 1 of Semiconductor Device>
An example of a semiconductor device including the transistor 1000 according to one embodiment of the present invention is described below.

  FIG. 1A is a top view of a semiconductor device including a transistor 1000. FIG. FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A and is a cross-sectional view in the channel length direction of the transistor 1000. 1C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 1A and is a cross-sectional view in the channel width direction of the transistor 1000. FIG. In the top view of FIG. 1A, some elements are omitted for clarity.

  As shown in FIGS. 1A to 1C, the transistor 1000 includes an insulator 402 disposed over a substrate 400, an oxide 406a disposed over the insulator 402, and an upper surface of the oxide 406a. An oxide 406b disposed in contact with at least a portion of the oxide, an insulator 412 disposed over the oxide 406b, a conductor 404a disposed over the insulator 412, and a conductor 404a. Conductor 404b, insulator 412, conductor 404a, and sidewall insulator 418 disposed in contact with the side surface of conductor 404b, and in contact with the top surface of oxide 406b and side surface of sidewall insulator 418 And an insulator 409 disposed in contact with the substrate. Here, as shown in FIG. 1B, it is preferable that the upper surface of the sidewall insulator 418 and the uppermost surface of the insulator 409 substantially coincide with the uppermost surface of the conductor 404b.

  Hereinafter, the oxide 406a and the oxide 406b may be collectively referred to as an oxide 406. Note that although the transistor 1000 has a structure in which the oxide 406a and the oxide 406b are stacked, the present invention is not limited to this. For example, only the oxide 406b may be provided. The conductor 404a and the conductor 404b may be collectively referred to as the conductor 404. Note that although the transistor 1000 has a structure in which the conductor 404a and the conductor 404b are stacked, the present invention is not limited to this. For example, only the conductor 404b may be provided.

  The transistor 1000 may have a structure in which the insulator 401 is provided over the substrate 400. Further, the structure may include the insulator 301 disposed on the insulator 401 and the conductor 310 disposed so as to be embedded in the insulator 301. The conductor 310 is preferably arranged so as to overlap with the oxide 406 and the conductor 404. In addition, the semiconductor device includes the insulator 301 and the insulator 302 disposed over the conductor 310 and the insulator 303 disposed over the insulator 302, and the insulator 402 is disposed over the insulator 303. It may be configured.

  In the conductor 310, a conductor 310a is formed in contact with the inner wall of the opening of the insulator 301, and a conductor 310b is formed further inside. Here, the heights of the upper surfaces of the conductors 310a and 310b and the height of the upper surface of the insulator 301 can be approximately the same. Note that although the transistor 1000 has a structure in which the conductor 310a and the conductor 310b are stacked, the present invention is not limited to this. For example, only the conductor 310b may be provided.

  The conductor 404 can function as a top gate, and the conductor 310 can function as a back gate. The potential of the back gate may be the same as that of the top gate, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the top gate.

Here, the conductor 310a is a conductive material having a function of suppressing the transmission of impurities such as water or hydrogen (difficult to transmit) (a conductive material having a function of suppressing the transmission of impurities such as water or hydrogen). Can also be used). For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or a stacked layer may be used. Thus, impurities such as hydrogen and water from the lower layer than the insulator 401 can be prevented from diffusing to the upper layer through the conductor 310. Note that the conductor 310a includes impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, an oxygen atom, an oxygen molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _{2, and the} like), a copper atom, It preferably has a function of suppressing permeation of at least one of oxygen (for example, oxygen atoms and oxygen molecules). The same applies to the case where a conductive material having a function of suppressing the permeation of impurities is described below. When the conductor 310a has a function of suppressing the permeation of oxygen, the conductor 310b can be prevented from being oxidized to lower the conductivity.

  The conductor 310b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Although not illustrated, the conductor 310b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

The insulator 401 can function as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor from below. For the insulator 401, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used. For example, aluminum oxide or the like is preferably used. Thus, impurities such as hydrogen and water can be prevented from diffusing into the upper layer than the insulator 401. Note that the insulator 401 suppresses at least one permeation of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (such as N ₂ O, NO, and NO ₂ ), and a copper atom. It preferably has a function. The same applies to the case where an insulating material having a function of suppressing the permeation of impurities is described below.

  The insulator 401 is preferably formed using an insulating material having a function of suppressing permeation of oxygen (eg, oxygen atoms or oxygen molecules). Thus, downward diffusion of oxygen contained in the insulator 402 and the like can be suppressed.

  The insulator 303 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, for example, aluminum oxide or hafnium oxide. Thus, impurities such as hydrogen and water from a lower layer than the insulator 303 can be prevented from diffusing from the insulator 303 to an upper layer. Furthermore, downward diffusion of oxygen contained in the insulator 402 and the like can be suppressed.

In addition, the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 402 is preferably reduced. For example, the amount of hydrogen desorbed from the insulator 402 is determined according to the temperature programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)) in the range of 50 ° C. to 500 ° C. It may be 2 × 10 ¹⁵ molecules / cm ² or less, preferably 1 × 10 ¹⁵ molecules / cm ² or less, more preferably 5 × 10 ¹⁴ molecules / cm ² or less in terms of the area of the body 402. The insulator 402 is preferably formed using an insulator from which oxygen is released by heating.

  The insulator 412 can function as a first gate insulating film, and the insulator 302, the insulator 303, and the insulator 402 can function as a second gate insulating film. Note that although the transistor 1000 has a structure in which the insulator 302, the insulator 303, and the insulator 402 are stacked, the present invention is not limited to this. For example, any two layers of the insulator 302, the insulator 303, and the insulator 402 may be stacked, or any one layer may be used.

  As the oxide 406, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. As the metal oxide, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

  Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

  The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the oxide semiconductor is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Here, in the metal oxide used for the oxide 406a, the atomic ratio of the element M in the constituent element is preferably larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 406b. . In the metal oxide used for the oxide 406a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 406b.

  When the metal oxide as described above is used as the oxide 406a, the energy at the lower end of the conduction band of the oxide 406a may be higher than the energy at the lower end of the conduction band in the region where the energy at the lower end of the conduction band of the oxide 406b is low. preferable. In other words, the electron affinity of the oxide 406a is preferably smaller than the electron affinity in a region where the energy at the lower end of the conduction band of the oxide 406b is low.

  Here, in the oxide 406a and the oxide 406b, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to achieve this, the density of defect states in the mixed layer formed at the interface between the oxide 406a and the oxide 406b is preferably reduced.

  Specifically, when the oxide 406a and the oxide 406b have a common element (main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide 406b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 406a.

  At this time, the main path of carriers is a narrow gap portion formed in the oxide 406b. Since the density of defect states at the interface between the oxide 406a and the oxide 406b can be reduced, influence on carrier conduction due to interface scattering is small, and a high on-state current can be obtained.

  The oxide 406 includes a region 426a, a region 426b, and a region 426c. As illustrated in FIG. 1B, the region 426a is sandwiched between the region 426b and the region 426c. The region 426b and the region 426c are regions whose resistance is reduced by the formation of the insulator 409, and are regions having higher conductivity than the region 426a. The region 426b and the region 426c are added with an impurity element such as hydrogen or nitrogen included in the deposition atmosphere of the insulator 409. Accordingly, oxygen vacancies are formed by the added impurity element around the region overlapping with the insulator 409 of the oxide 406b, and the impurity element further enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. Is done.

  Therefore, the region 426b and the region 426c preferably have a higher concentration of at least one of hydrogen and nitrogen than the region 426a. The concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like. Here, the concentration of hydrogen or nitrogen in the region 426a is approximately equal to the center of the region overlapping with the insulator 412 of the oxide 406b (for example, the distance from both side surfaces in the channel length direction of the insulator 412 of the oxide 406b). The concentration of hydrogen or nitrogen in (part) may be measured.

  Note that the resistance of the region 426b and the region 426c is reduced by adding an element that forms oxygen vacancies or an element that combines with oxygen vacancies. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Thus, the region 426b and the region 426c may include one or more of the above elements.

  An enlarged view of the vicinity of the region 426a illustrated in FIG. 1B is illustrated in FIG. As shown in FIG. 2A, the region 426b and the region 426c are formed in a region overlapping with at least the insulator 409 of the oxide 406. Here, one of the region 426b and the region 426c of the oxide 406b can function as a source region, and the other can function as a drain region. The region 426a of the oxide 406b can function as a channel formation region.

  Note that in FIGS. 1B and 2A, the region 426a, the region 426b, and the region 426c are formed in the oxide 406b and the oxide 406a, but these regions are formed in at least the oxide 406b. It only has to be done. In FIG. 1B and the like, the boundary between the region 426a and the region 426b and the boundary between the region 426a and the region 426c are displayed substantially perpendicular to the top surface of the oxide 406. It is not limited to. For example, the region 426b and the region 426c may protrude to the conductor 404 side near the surface of the oxide 406b and recede to the insulator 409 side near the lower surface of the oxide 406a.

  In the transistor 1000, as illustrated in FIG. 2A, the region 426b and the region 426c are formed in a region overlapping with the insulator 409 and the sidewall insulator 418 of the oxide 406. However, the semiconductor device described in this embodiment is not limited to this.

  For example, as illustrated in FIG. 2B, the region 426b and the region 426c are formed in regions overlapping with the vicinity of both ends of the insulator 409, the sidewall insulator 418, and the insulator 412 of the oxide 406. May be. At this time, a portion of the region 426b and the region 426c overlapping with the conductor 404 functions as a so-called overlap region (also referred to as a Lov region). With the structure having the Lov region, a high-resistance region is not formed between the channel formation region of the oxide 406 and the source and drain regions, so that the on-state current of the transistor can be increased.

  For example, as illustrated in FIG. 2C, the region 426 b and the region 426 c may be formed in a region overlapping with the insulator 409 of the oxide 406. At this time, a portion of the region 426a that does not overlap with the conductor 404 functions as a so-called offset region (also referred to as a Loff region). With the structure having the Loff region, a high-resistance region is formed between the channel formation region of the oxide 406 and the source and drain regions; thus, the off-state current of the transistor can be reduced.

  In this manner, by appropriately selecting the range of the region 426b and the region 426c, a transistor having electrical characteristics that meet requirements can be easily provided in accordance with circuit design.

  The insulator 412 is preferably provided in contact with the upper surface of the oxide 406b. The insulator 412 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 412 in contact with the top surface of the oxide 406b, oxygen can be effectively supplied to the oxide 406b. Similarly to the insulator 402, the concentration of impurities such as water or hydrogen in the insulator 412 is preferably reduced. The thickness of the insulator 412 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, and may be, for example, about 1 nm.

The insulator 412 preferably contains oxygen. For example, in the temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 412 is within the range of the surface temperature of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. 1 × 10 ¹⁴ molecules / cm ² or more, preferably 2 × 10 ¹⁴ molecules / cm ² or more, more preferably 4 × 10 ¹⁴ molecules / cm ² or more.

  The insulator 412 and the conductor 404 have a region overlapping with the oxide 406b. The side surfaces of the insulator 412, the conductor 404a, and the conductor 404b are preferably substantially matched.

  As the conductor 404a, a conductive oxide is preferably used. For example, a metal oxide that can be used as the oxide 406a or the oxide 406b can be used. In particular, among In—Ga—Zn-based oxides, the metal atomic ratio is high from [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, and the vicinity thereof. It is preferable to use those. By providing such a conductor 404a, permeation of oxygen to the conductor 404b can be suppressed, and an increase in the electrical resistance value of the conductor 404b due to oxidation can be prevented.

  Further, by forming such a conductive oxide by a sputtering method, oxygen can be added to the insulator 412 and oxygen can be supplied to the oxide 406b. Accordingly, oxygen vacancies in the region 426a of the oxide 406 can be reduced.

  For the conductor 404b, a metal such as tungsten can be used, for example. Alternatively, a conductor that can improve conductivity of the conductor 404a by adding an impurity such as nitrogen to the conductor 404a may be used as the conductor 404b. For example, the conductor 404b is preferably formed using titanium nitride or the like. Alternatively, the conductor 404b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are stacked thereover.

  Here, the conductor 404 functioning as a gate electrode is provided so as to cover the upper surface and the side surface in the channel width direction of the oxide 406b in the vicinity of the region 426a with the insulator 412 interposed therebetween. Therefore, the upper surface of the oxide 406b in the vicinity of the region 426a and the side surface in the channel width direction can be electrically surrounded by the electric field of the conductor 404 functioning as a gate electrode. A structure of a transistor that electrically surrounds a channel formation region with an electric field of the conductor 404 is referred to as a surrounded channel (s-channel) structure. Therefore, a channel can be formed on the top surface in the vicinity of the region 426a and the side surface in the channel width direction of the oxide 406b, so that a large current can flow between the source and the drain, and the current during conduction (on current) is increased. can do. In addition, since the upper surface of the oxide 406b in the vicinity of the region 426a and the side surface in the channel width direction are surrounded by the electric field of the conductor 404, leakage current (off-state current) during non-conduction can be reduced.

  The sidewall insulator 418 is provided in contact with the side surfaces of the insulator 412 and the conductor 404. The sidewall insulator 418 is preferably formed using an atomic layer deposition (ALD) method. As a result, the sidewall insulator can be formed to a thickness of about 1 nm to 20 nm, for example, 1 nm. Many precursors used in the ALD method contain impurities such as carbon. Therefore, the sidewall insulator 418 may contain an impurity such as carbon. For example, even when the sidewall insulator 418 and the insulator 401 are formed using aluminum oxide, the sidewall insulator 418 may contain more impurities such as carbon than the insulator 401. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

  As described above, the region 426 b and the region 426 c of the oxide 406 are formed using the impurity element added in the formation of the insulator 409. In the case where the transistor is miniaturized and the channel length is formed to be about 10 nm to 30 nm, an impurity element contained in the source region or the drain region may diffuse and the source region and the drain region may be electrically connected. On the other hand, as shown in this embodiment, by forming the sidewall insulator 418, the distance between the regions in contact with the insulator 409 of the oxide 406 can be increased, so that the source region And the drain region can be prevented from conducting electrically. Further, by forming the sidewall insulator 418 by using the ALD method, the film thickness is approximately equal to or smaller than the miniaturized channel length, the distance between the source region and the drain region is increased more than necessary, and resistance is increased. Can be increased.

  In addition, the range of the region 426b and the region 426c can be selected by adjusting the film thickness of the sidewall insulator 418 by using the ALD method. By increasing the thickness of the sidewall insulator 418, the off-state current can be reduced by preventing the conductor 404 from overlapping with the region 426 b and the region 426 c as illustrated in FIG. 2A and the like. . Further, by reducing the thickness of the sidewall insulator 418, as shown in FIG. 2B and the like, the conductor 404 overlaps with the region 426b and the region 426c, so that the on-state current can be increased. it can.

  The sidewall insulator 418 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, for example, aluminum oxide or hafnium oxide. Thereby, oxygen in the insulator 412 can be prevented from diffusing outside. In addition, entry of impurities such as hydrogen and water into the oxide 406 from an end portion of the insulator 412 can be suppressed.

  The sidewall insulator 418 is formed by forming an insulating film using the ALD method and then performing anisotropic etching so that portions of the insulating film in contact with the insulator 412 and the conductor 404 remain. To do. At this time, by providing an insulator or a layer of a conductor over the conductor 404, a portion in contact with the insulator 412 and the conductor 404 can be formed even if the insulating film is partially removed by the anisotropic etching. Sufficiently remain. Hereinafter, in this specification and the like, a layer provided over the conductor 404 in order to form the sidewall insulator 418 is referred to as a buffer layer. The upper portion of the buffer layer is preferably removed using a chemical mechanical polishing (CMP) process or the like in accordance with the height of the conductor 404.

  A part of the remaining buffer layer may be formed over at least a part of the conductor 404b like a buffer layer 405 illustrated in FIG. As illustrated in FIG. 1C, the buffer layer 405 does not overlap with the conductor 404b in at least part of a region overlapping with the oxide 406b. In addition, the upper surface of the buffer layer 405 is preferably substantially coincident with the uppermost surface of the conductor 404b. Here, the uppermost surface of the conductor 404b refers to the upper surface of the conductor 404b having the largest distance from the substrate 400. Further, the side surface of the buffer layer 405 is in contact with the sidewall insulator 418.

  The buffer layer 405 may use an insulator or a conductor. As the insulator used for the buffer layer 405, an insulator that can be used for the insulator 301, such as silicon oxynitride or silicon nitride, may be used, for example. As the buffer layer 405, an organic resin such as polyimide or acrylic, or a photosensitive resin that can be used as a photoresist may be used. As a conductor used for the buffer layer 405, for example, a material that can be used for the conductor 310 may be used. Note that the buffer layer 405 is preferably formed using a material different from that of the conductor 404b.

  The insulator 409 is provided so as to cover the oxide 406 and the insulator 402. The insulator 409 is provided in contact with the side surface of the sidewall insulator 418. As described above, the insulator 409 is formed by adding an impurity such as hydrogen or nitrogen to the oxide 406 to form the region 426b and the region 426c. Therefore, the insulator 409 preferably includes at least one of hydrogen and nitrogen.

  The insulator 409 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, the insulator 409 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like. By forming such an insulator 409, oxygen can penetrate through the insulator 409 and oxygen can be supplied to oxygen vacancies in the regions 426b and 426c, so that the carrier density can be prevented from decreasing. . Further, impurities such as water or hydrogen can permeate through the insulator 409 and the region 426b and the region 426c can be prevented from being excessively expanded toward the region 426a.

  An insulator 410 is preferably provided over the insulator 409. The insulator 410, the insulator 409, the sidewall insulator 418, the buffer layer 405, and the conductor 404b are polished in the same process (for example, CMP treatment) to planarize the upper surface, so that their uppermost surfaces are substantially omitted. Match. Further, the insulator 415 is preferably provided over the insulator 410. The insulator 410 and the insulator 415 preferably have a reduced concentration of impurities such as water or hydrogen in the film, like the insulator 402 and the like.

  Further, the insulator 420 is preferably provided over the insulator 415. The insulator 420 can function as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor or the like from an upper layer. The insulator 420 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, for example, aluminum oxide, like the insulator 301.

  Alternatively, an oxide insulator formed using an ALD method, which is similar to the sidewall insulator 418, may be provided over or below the insulator 420.

  Next, constituent materials of the transistor 1000 are described.

<Board>
As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

  Further, a flexible substrate may be used as the substrate 400. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 400 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 400. Further, the substrate 400 may have elasticity. Further, the substrate 400 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate 400 has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 400 is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate 400 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 400 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 400 which is a flexible substrate, for example, a metal, an alloy, a resin, glass, or fiber thereof can be used. The substrate 400, which is a flexible substrate, is preferable as the linear expansion coefficient is lower because deformation due to the environment is suppressed. For example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used as the substrate 400 that is a flexible substrate. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as the substrate 400 that is a flexible substrate.

<Insulator>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

  By surrounding the transistor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized. For example, as the insulator 303, the insulator 401, and the insulator 420, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used.

  Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

  For example, the insulator 303, the insulator 401, and the insulator 420 include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Metal oxide, silicon nitride oxide, silicon nitride, or the like may be used. Note that the insulator 303, the insulator 401, and the insulator 420 preferably include aluminum oxide, hafnium oxide, or the like.

  Further, for example, when the insulator 420 is formed by a sputtering method using plasma containing oxygen, oxygen can be added to the insulator serving as a base layer of the oxide.

  Examples of the insulator 301, the insulator 302, the insulator 402, and the insulator 412 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. For example, the insulator 301, the insulator 302, the insulator 402, and the insulator 412 preferably include silicon oxide, silicon oxynitride, or silicon nitride.

  The insulator 302, the insulator 303, the insulator 402, and / or the insulator 412 preferably includes an insulator with a high relative dielectric constant. For example, the insulator 302, the insulator 303, the insulator 402, and / or the insulator 412 include gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, silicon, and It is preferable to include an oxide containing hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. Alternatively, the insulator 302, the insulator 303, the insulator 402, and / or the insulator 412 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant. For example, when the insulator 402 and the insulator 412 have a structure in which aluminum oxide, gallium oxide, or hafnium oxide is in contact with the oxide 406, silicon contained in silicon oxide or silicon oxynitride is mixed into the oxide 406. Can be suppressed. For example, in the insulator 402 and the insulator 412, by using silicon oxide or silicon oxynitride in contact with the oxide 406, aluminum oxide, gallium oxide, or hafnium oxide, and silicon oxide or silicon oxynitride can be used. A trap center may be formed at the interface. In some cases, the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.

  The insulator 410 and the insulator 415 preferably include an insulator with a low relative dielectric constant. For example, the insulator 410 and the insulator 415 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and holes It is preferable to have silicon oxide or resin having Alternatively, the insulator 410 and the insulator 415 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or holes It is preferable to have a laminated structure of a silicon oxide having a resin and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

  As the sidewall insulator 418, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. As the sidewall insulator 418, for example, aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, or the like, silicon nitride oxide, or nitride Silicon or the like may be used.

<Conductor>
As the conductor 404a, the conductor 404b, the conductor 310a, and the conductor 310b, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium A material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

  Alternatively, a conductive material containing oxygen and a metal element contained in a metal oxide that can be used for the oxide 406 may be used as the conductor, particularly the conductor 404a and the conductor 310a. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. In some cases, hydrogen contained in the oxide 406 can be captured by using such a material. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

  A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

  Note that in the case where an oxide is used for a channel formation region of the transistor, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined as the gate electrode is preferably used. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

<Metal oxide applicable to oxide 406>
Hereinafter, the oxide 406 according to the present invention will be described. As the oxide 406, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.

  The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the oxide semiconductor is InMZnO containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Here, a case where the metal oxide includes indium, the element M, and zinc is considered. Note that the terms of the atomic ratio of indium, element M, and zinc of the metal oxide are [In], [M], and [Zn].

  The atoms of indium, element M, and zinc included in the metal oxide that can be used for the oxide 406a and the oxide 406b are described below with reference to FIGS. 19A, 19B, and 19C. A preferable range of the number ratio will be described. Note that FIG. 19A, FIG. 19B, and FIG. 19C do not describe the atomic ratio of oxygen. The terms of the atomic ratio of indium, element M, and zinc of the metal oxide are [In], [M], and [Zn].

  In FIG. 19A, FIG. 19B, and FIG. 19C, a broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line that satisfies (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1-α): line that has an atomic ratio of 2 [In]: [M] : [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): number of atoms of 4 A line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1−α): 5.

  The one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), and [In]: [M]: [Zn] = 2: A line with an atomic ratio of 1: β, [In]: [M]: [Zn] = 1: 1: a line with an atomic ratio of β, [In]: [M]: [Zn] = 1 2: Line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 1 : 4: represents a line having an atomic ratio of β.

  Further, the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 shown in FIG. 19 (A), FIG. 19 (B), and FIG. Metal oxides tend to have a spinel crystal structure.

  In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is a value close to [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure tend to coexist. Further, when the atomic ratio is a value close to [In]: [M]: [Zn] = 1: 0: 0, two phases of a bixbite type crystal structure and a layered crystal structure tend to coexist. When a plurality of phases coexist in a metal oxide, a crystal grain boundary may be formed between different crystal structures.

  A region A illustrated in FIG. 19A illustrates an example of a preferable range of the atomic ratio of indium, the element M, and zinc included in the metal oxide.

  The metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the indium content. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.

  On the other hand, when the content of indium and zinc in the metal oxide is lowered, the carrier mobility is lowered. Therefore, when the atomic ratio is [In]: [M]: [Zn] = 0: 1: 0 and its vicinity (for example, the region C shown in FIG. 19C), the insulating property becomes high. .

  For example, the metal oxide used for the oxide 406b preferably has a high carrier mobility and an atomic ratio represented by the region A in FIG. On the other hand, the metal oxide used for the oxide 406a preferably has an atomic ratio, which is relatively high, which is represented by a region C in FIG.

  In particular, in the region B illustrated in FIG. 19B, an excellent metal oxide with high carrier mobility and high reliability can be obtained among the regions A.

  Note that the region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and the vicinity thereof. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. The region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7, and Includes neighborhood values.

  In the case where an In-M-Zn oxide is used as the metal oxide, a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target. Note that the atomic ratio of the metal oxide film to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the metal oxide formed is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic ratio]. In addition, when the composition of the sputtering target used for the metal oxide is In: Ga: Zn = 5: 1: 7 [atomic ratio], the composition of the metal oxide formed is In: Ga: Zn = 5: It may be in the vicinity of 1: 6 [atomic ratio].

  Note that the properties of metal oxides are not uniquely determined by the atomic ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide film is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. Further, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.

<Composition of metal oxide>
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

  Note that in this specification and the like, they may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

  Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

  Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

  The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

  The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

  The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

  Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<Transistor with oxide semiconductor>
Next, the case where the above oxide semiconductor is used for a transistor is described.

  Note that by using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

In the transistor, the carrier density in the region 426a of the oxide 406b is preferably low. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the carrier density in the region 426a of the oxide 406b is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^{− It} may be ⁹ / cm ³ or more.

  In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.

  In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the region 426a of the oxide 406b. In order to reduce the impurity concentration in the region 426a of the oxide 406b, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

<Impurity>
Here, the influence of each impurity in the oxide semiconductor is described.

In the oxide semiconductor, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon (concentration obtained by SIMS) in the region 426a of the oxide 406b is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the region 426a of the oxide 406b. Specifically, the concentration of alkali metal or alkaline earth metal in the region 426a of the oxide 406b obtained by SIMS is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To do.

In addition, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density is increased, and the oxide semiconductor is likely to be n-type. As a result, a transistor in which nitrogen is contained in the region 426a of the oxide 406b is likely to be normally on. Therefore, it is preferable that nitrogen is reduced as much as possible in the region 426a of the oxide 406b. For example, the nitrogen concentration in the region 426a of the oxide 406b is less than 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS, preferably Is 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a large amount of hydrogen is contained in the region 426a of the oxide 406b is likely to be normally on. Therefore, hydrogen in the region 426a of the oxide 406b is preferably reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

  By sufficiently reducing impurities in the region 426a of the oxide 406b, stable electrical characteristics can be given to the transistor.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including the transistor 1000 according to the present invention will be described with reference to FIGS. Further, in FIGS. 1 and 3 to 10, (A) in each figure is a top view. (B) of each figure is a cross-sectional view of a portion indicated by a one-dot chain line of A1-A2 in (A) of each figure. Moreover, (C) of each figure is sectional drawing of the site | part shown with the dashed-dotted line of A3-A4 in (A) of each figure.

  First, the substrate 400 is prepared.

  Next, the insulator 401 is formed. The insulator 401 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD method. Etc. can be used.

  The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

  In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

  The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.

  The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

  In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

  The insulator 401 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, a structure in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide by a sputtering method may be employed.

  Next, the insulator 301 is formed over the insulator 401. The insulator 301 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a groove reaching the insulator 401 is formed in the insulator 301. The groove includes, for example, a hole and an opening. The groove may be formed by wet etching, but dry etching is preferable for fine processing. As the insulator 401, an insulator that functions as an etching stopper film when the insulator 301 is etched to form a groove is preferably selected. For example, in the case where a silicon oxide film is used for the insulator 301 that forms the groove, the insulator 401 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

  In this embodiment, an aluminum oxide film is formed as the insulator 401 by a sputtering method, and an aluminum oxide film is formed over the aluminum oxide by an ALD method. Further, a silicon oxide film is formed as the insulator 301 by a CVD method.

  After forming the groove, a conductor to be the conductor 310a is formed. The conductor serving as the conductor 310a preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 310 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, tantalum nitride is formed by a sputtering method as the conductor to be the conductor 310a.

  Next, a conductor to be the conductor 310b is formed over the conductor to be the conductor 310a. The conductor to be the conductor 310b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, as a conductor to be the conductor 310b, titanium nitride is formed by a CVD method, and tungsten is formed over the titanium nitride by a CVD method.

  Next, by performing CMP treatment, the conductor to be the conductor 310a and the conductor to be the conductor 310b on the insulator 301 are removed. As a result, the conductor 310a and the conductor 310b including the conductor 310b having a flat upper surface can be formed by leaving the conductor to be the conductor 310a and the conductor to be the conductor 310b remaining only in the groove portion ( (See FIGS. 3A, 3B, and 3C.)

  Next, the insulator 302 is formed over the insulator 301 and the conductor 310. The insulator 302 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 303 is formed over the insulator 302. The insulator 303 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 402 is formed over the insulator 303. The insulator 402 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, it is preferable to perform a first heat treatment. The first heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. The first heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed in a reduced pressure state. Alternatively, in the first heat treatment, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be. By the first heat treatment, impurities such as hydrogen and water contained in the insulator 402 can be removed. Alternatively, in the first heat treatment, plasma treatment containing oxygen may be performed in a reduced pressure state. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example. Alternatively, a power supply for applying RF (Radio Frequency) may be provided on the substrate side. High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 402 by applying RF to the substrate side. Alternatively, plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that the first heat treatment may not be performed.

  The heat treatment can also be performed after the insulator 302 is formed, after the insulator 303 is formed, and after the insulator 402 is formed. Although the first heat treatment condition can be used for the heat treatment, the heat treatment after the formation of the insulator 302 is preferably performed in an atmosphere containing nitrogen.

  In this embodiment, as the first heat treatment, after the insulator 402 is formed, a treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, and then continuously in an oxygen atmosphere at a temperature of 400 ° C. Do time processing.

  Next, an oxide film 406aA and an oxide film 406bA are formed in this order over the insulator 402 (see FIGS. 3A, 3B, and 3C). Note that the oxide film 406aA and the oxide film 406bA are preferably formed successively without being exposed to the air environment. By forming the film in this manner, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 406aA, and the vicinity of the interface between the oxide film 406aA and the oxide film 406bA can be kept clean. it can.

  The oxide film 406aA and the oxide film 406bA can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  For example, when the oxide film 406aA and the oxide film 406bA are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the oxide film 406aA and the oxide film 406bA are formed by a sputtering method, the above-described In-M-Zn oxide target can be used.

  In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 402 when the oxide film 406aA is formed.

  Note that the ratio of oxygen contained in the sputtering gas of the oxide film 406aA is 70% or more, preferably 80% or more, and more preferably 100%.

  Subsequently, an oxide film 406bA is formed by a sputtering method. At this time, when the film is formed so that the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%, an oxygen-deficient oxide semiconductor is formed. A transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.

  In the case where an oxygen-deficient oxide semiconductor is used for the oxide film 406bA, an oxide film containing excess oxygen is preferably used for the oxide film 406aA. Alternatively, oxygen doping treatment may be performed after the oxide film 406bA is formed.

  In this embodiment, the oxide film 406aA is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic ratio], and the oxide film 406bA is formed by an sputtering method using In. : Ga: Zn = 4: 2: 4.1 [atomic ratio] Target is used for film formation.

  Next, second heat treatment may be performed. For the second heat treatment, first heat treatment conditions can be used. By the second heat treatment, impurities such as hydrogen and water in the oxide film 406aA and the oxide film 406bA can be removed. In this embodiment mode, after processing for one hour at a temperature of 400 ° C. in a nitrogen atmosphere, the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.

  Next, the oxide film 406aA and the oxide film 406bA are processed into island shapes, so that the oxide 406a and the oxide 406b are formed (see FIGS. 4A, 4B, and 4C). Here, the oxide 406 a and the oxide 406 b are formed so that at least part of them overlaps with the conductor 310. The oxide film 406aA and the oxide film 406bA may be processed using a lithography method. In the processing, it is preferable that the cross-sectional shapes of the oxide 406a and the oxide 406b have a tapered shape. The taper angle is 30 degrees or more and less than 75 degrees, preferably 30 degrees or more and less than 70 degrees with respect to a plane parallel to the bottom surface of the substrate. By having such a taper angle, the coverage of the film in the subsequent film formation process is improved. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing and the above-described tapered processing.

  In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that a mask is not necessary when an electron beam or an ion beam is used. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.

  Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the oxide film 406bA, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do. The etching of the oxide film 406aA and the oxide film 406bA may be performed after the resist mask is removed, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the oxide film 406aA and the oxide film 406bA are etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

  As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

  By performing a process such as conventional dry etching, impurities due to an etching gas or the like may adhere or diffuse to the surface or inside of the oxide 406a and the oxide 406b. Examples of impurities include fluorine and chlorine.

  Cleaning is performed in order to remove the impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.

  As the wet cleaning, a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

  Next, third heat treatment may be performed. The first heat treatment condition described above can be used as the heat treatment condition. Note that the third heat treatment may not be performed. In this embodiment, the third heat treatment is not performed.

  Next, the insulating film 412A, the conductive film 404aA, the conductive film 404bA, and the buffer layer 405A are sequentially formed over the insulator 402 and the oxide 406 (FIGS. 5A, 5B, and 5C). reference.).

  The insulating film 412A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Here, fourth heat treatment can be performed. The first heat treatment condition can be used for the heat treatment. By the heat treatment, the moisture concentration and the hydrogen concentration in the insulating film 412A can be reduced. Note that the fourth heat treatment may not be performed.

  The conductive film 404aA can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A conductive oxide that can be used as the above-described conductor 404a is formed as the conductive film 404aA in an atmosphere containing oxygen by a sputtering method, so that oxygen is added to the insulator 412 and oxygen is added to the oxide 406b. Can be supplied.

  The conductive film 404bA can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. When the conductive film 404bA is formed by a sputtering method, the electrical resistance value of the conductive film 404aA can be reduced to obtain a conductor. This can be called an OC (Oxide Conductor) electrode. A conductor may be further formed on the conductor on the OC electrode by sputtering or the like.

  The buffer layer 405A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As described above, the buffer layer 405A may use a conductor or an insulator. Here, the thickness of the buffer layer 405 </ b> A is preferably larger than the thickness of the oxide 406. For example, the thickness of the buffer layer 405A is preferably 10 nm to 100 nm. Accordingly, when the sidewall insulator 418 is formed in a later process, the sidewall insulator 418 is easily left.

  Here, fifth heat treatment can be performed. The first heat treatment condition can be used for the heat treatment. Note that the fifth heat treatment may not be performed.

  Next, the insulating film 412A, the conductive film 404aA, the conductive film 404bA, and the buffer layer 405A are etched to form the insulator 412, the conductor 404a, the conductor 404b, and the buffer layer 405B (FIG. 6A). (See (B) and (C).) The insulator 412, the conductor 404a, the conductor 404b, and the buffer layer 405B are formed so that at least a part thereof overlaps with the conductor 310 and the oxide 406.

  Here, it is preferable that the cross-sectional shapes of the insulator 412, the conductor 404a, the conductor 404b, and the buffer layer 405B have a tapered shape as much as possible. Accordingly, when the sidewall insulator 418 is formed in a later process, the sidewall insulator 418 is easily left.

  In addition, the etching may etch an upper portion of a region of the oxide 406b that does not overlap with the insulator 412. In this case, the thickness of the region overlapping with the insulator 412 of the oxide 406b is larger than the thickness of the region not overlapping with the insulator 412.

  Next, the insulating film 418A is formed by an ALD method so as to cover the insulator 402, the oxide 406, the insulator 412, the conductor 404, and the buffer layer 405B (FIGS. 7A and 7B). And (C).) By forming the insulating film 418A using the ALD method, the thickness can be set to about 1 nm to 20 nm, for example, about 1 nm. Further, even when the structure including the insulator 412, the conductor 404, and the buffer layer 405B has a very high aspect ratio, the structure has a uniform film thickness with few pinholes on the top and side surfaces of the structure. can do. In this embodiment, aluminum oxide is formed by an ALD method as the insulating film 418A.

  Next, anisotropic etching is performed on the insulating film 418A to form sidewall insulators 418B in contact with the side surfaces of the insulator 412, the conductor 404, and the buffer layer 405B (FIG. 8A). (See (B) and (C).) As an anisotropic etching process, it is preferable to perform a dry etching process. Thus, the insulating film 418A formed on the surface substantially parallel to the substrate 400 can be removed, and the sidewall insulator 418B can be formed in a self-aligning manner.

  Here, by setting the thickness of the buffer layer 405B to be larger than that of the oxide 406, for example, 10 nm or more and 100 nm or less, even if the upper portion of the sidewall insulator 418B is removed by the etching treatment, The portions of the wall insulator 418B that are in contact with the insulator 412 and the conductor 404 can remain. Further, by forming the end portion of the oxide 406 in a tapered shape, the time for removing the insulating film 418A formed in contact with the side surface of the oxide 406 is shortened, and the sidewall insulator 418B can be more easily formed. Can be formed.

  In some cases, the sidewall insulator remains in contact with the side surface of the oxide 406. By providing the sidewall insulator in contact with the side surface of the oxide 406, impurities such as water or hydrogen mixed in the oxide 406 can be reduced and oxygen can be prevented from diffusing outward from the oxide 406. There is a case.

  Next, an insulating film 409A is formed to cover the insulator 402, the oxide 406, the sidewall insulator 418B, and the buffer layer 405B (see FIGS. 9A, 9B, and 9C). The insulating film 409A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a PECVD method is preferably used.

  The insulating film 409A is preferably formed in an atmosphere containing at least one of nitrogen and hydrogen. By performing deposition in such an atmosphere, oxygen vacancies are formed around a region of the oxide 406b that does not overlap with the insulator 412 and the oxygen vacancies are bonded to an impurity element such as nitrogen or hydrogen, so that carriers The density can be increased. In this manner, the region 426b and the region 426c with reduced resistance can be formed. As the insulating film 409A, for example, silicon nitride, silicon nitride oxide, or silicon oxynitride can be used by a CVD method. In this embodiment, silicon nitride oxide is used as the insulating film 409A.

  As described above, in the method for manufacturing the semiconductor device described in this embodiment, the source region and the drain region are formed in a self-aligned manner by forming the insulating film 409A even in a transistor whose channel length is reduced to about 10 nm to 30 nm. Can be formed. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.

  Alternatively, plasma treatment may be performed before the insulating film 409A is formed. The plasma treatment may be performed in an atmosphere containing an element that forms oxygen vacancies or an element that combines with oxygen vacancies, for example.

  Note that the region 426b and the region 426 may be formed in the oxide 406 only by plasma treatment. Note that after the regions 426b and 426c are formed in the oxide 406, it is preferable to use an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen, which is similar to the insulator 409 and the like. . By providing such an insulator over the region 426b and the region 426c, it is possible to prevent impurities such as water or hydrogen and oxygen from entering the region 426b and the region 426c and changing the carrier density.

  Next, an insulating film to be the insulator 410 is formed over the insulating film 409A. The insulating film to be the insulator 410 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulating film to be the insulator 410, the buffer layer 405B, the sidewall insulator 418B, and a part of the insulating film 409A are removed until part of the conductor 404b is exposed. 405, a sidewall insulator 418, and an insulator 409 are formed (see FIGS. 10A, 10B, and 10C). A CMP treatment is preferably used for forming the insulator 410, the buffer layer 405, the sidewall insulator 418, and the insulator 409.

  As shown in FIGS. 10B and 10C, the top surface of the conductor 404b, the sidewall insulator 418, the insulator 409, and the insulator 410 are subjected to CMP until the upper portion of the conductor 404b is exposed. , And the uppermost surface of the buffer layer 405 substantially coincide.

  Next, an insulator 415 is formed. The insulator 415 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.

  The insulator 415 may be formed so that an upper surface thereof is flat. For example, the insulator 415 may have a flat upper surface immediately after film formation. Alternatively, for example, the insulator 415 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. However, the top surface of the insulator 415 may not have flatness.

  next. An insulator 420 is formed over the insulator 415. The insulator 420 is preferably formed using a metal oxide, and can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  As the insulator 420, oxygen can be added to the insulator 410 by forming an aluminum oxide film by a sputtering method using oxygen plasma. The added oxygen becomes excess oxygen in the insulator 410.

  The insulator 420 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, a structure in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide by a sputtering method may be employed.

  Here, sixth heat treatment can be performed. The first heat treatment condition can be used for the heat treatment. Note that the sixth heat treatment may not be performed.

  Through the above steps, a semiconductor device including the transistor 1000 can be manufactured (see FIG. 1).

  In the above manufacturing method of the semiconductor device, the region 426b and the region 426c are formed by forming the insulating film 409A in contact with the oxide 406. However, the manufacturing method of the semiconductor device according to this embodiment is not limited thereto. It is not limited. For example, as illustrated in FIG. 11A, the region 426b and the region 426c may be formed by adding a dopant.

  The step shown in FIG. 11A is performed after the formation of the sidewall insulator 418B shown in FIG. As shown in FIG. 11A, a dopant 422 is added to the oxide 406 using the insulator 412, the conductor 404, the buffer layer 405B, and the sidewall insulator 418B as masks.

  As a method for adding the dopant 422, an ion implantation method in which an ionized source gas is added by mass separation, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. be able to. When mass separation is performed, the ionic species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.

  As the dopant 422, an element that forms oxygen vacancies or an element that combines with oxygen vacancies may be used.

  In FIG. 11A, the dopant 422 is added substantially perpendicularly to the top surface of the substrate 400; however, the present invention is not limited to this, and the dopant 422 may be added while being inclined with respect to the top surface of the substrate 400. .

  In this manner, after the region 426b and the region 426c are formed in the oxide 406, an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen, which is similar to the insulator 409 and the like, is used. It is preferable. By providing such an insulator over the region 426b and the region 426c, it is possible to prevent impurities such as water or hydrogen and oxygen from entering the region 426b and the region 426c and changing the carrier density.

  Alternatively, after the insulating film 409A illustrated in FIG. 9 is formed, a dopant 422 may be further added as illustrated in FIG. 11B.

  In the above method for manufacturing a semiconductor device, the upper portion of the buffer layer 405B is removed after forming the region 426b and the region 426c. However, the method for manufacturing the semiconductor device according to this embodiment is limited to this. is not. For example, as illustrated in FIGS. 12A to 12C, the region 426b and the region 426c may be formed after the buffer layer 405B is removed.

  The step shown in FIG. 12A is performed after the formation of the sidewall insulator shown in FIG. At this time, the sidewall insulator is preferably thicker than the finally formed sidewall insulator 418 (hereinafter referred to as a sidewall insulator 418C).

  First, the buffer layer 405B inside the sidewall insulator 418C is removed (see FIG. 12A). The removal of the buffer layer 405B may be performed using, for example, dry etching or wet etching. At this time, the etching rate of the conductor 404, the sidewall insulator 418C, the oxide 406, the insulator 412, and the like is set lower than the etching rate of the buffer layer 405B.

  Next, isotropic etching is performed to remove part of the sidewall insulator 418C, so that the sidewall insulator 418 is formed (see FIG. 12B). Here, wet etching may be used as the isotropic etching process. At this time, the etching rate of the conductor 404, the oxide 406, the insulator 412, and the like is set lower than the etching rate of the sidewall insulator 418C.

  Here, the portion of the sidewall insulator 418C above the conductor 404b is etched from both sides, while the portion of the sidewall insulator 418C below 404b is etched from only one side. . Accordingly, the sidewall insulator 418 can be formed by removing part of the sidewall insulator 418C.

  Next, the insulator 409 is formed so as to cover the insulator 402, the oxide 406, the sidewall insulator 418, and the conductor 404 (see FIG. 12C). Accordingly, the region 426b and the region 426c can be formed.

<Modification>
The semiconductor device described in this embodiment is not limited to that illustrated in FIG. Hereinafter, modified examples of the transistor described in this embodiment will be described with reference to FIGS.

  First, the transistor 1000a illustrated in FIG. 13 is described. FIG. 13A is a top view of a semiconductor device including a transistor 1000a. FIG. 13B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 13A and also a cross-sectional view in the channel length direction of the transistor 1000a. FIG. 13C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 13A and also a cross-sectional view in the channel width direction of the transistor 1000a. In the top view of FIG. 13A, some elements are omitted for clarity. Hereinafter, similarly, FIGS. 14 to 18 are a top view and a cross-sectional view.

  The transistor 1000a differs from the transistor 1000 in that the oxide 406c is disposed over the oxide 406b. The description of the transistor 1000 can be referred to for other structures. An insulator 412 is provided over the oxide 406c, and a side surface of the oxide 406c is in contact with the sidewall insulator 418. The oxide 406 c is formed so as to overlap with the insulator 412 and the conductor 404, and the side surface of the oxide 406 c substantially matches the side surface of the insulator 412 and the conductor 404. Here, the insulator 409 is in contact with the upper surface of the oxide 406b and is not in contact with the oxide 406c. Note that in the following, the oxide 406a, the oxide 406b, and the oxide 406c may be collectively referred to as an oxide 406.

  As the oxide 406c, a metal oxide that can be used for the oxide 406a or the oxide 406b can be used.

  When a metal oxide that can be used for the oxide 406a is used as the oxide 406c, the energy at the lower end of the conduction band of the oxide 406c is lower than the energy at the lower end of the conduction band in the region where the energy at the lower end of the conduction band of the oxide 406b is low. It is preferable to be high. In other words, the electron affinity of the oxide 406c is preferably smaller than the electron affinity in a region where the energy at the lower end of the conduction band of the oxide 406b is low.

  Here, in the oxide 406a, the oxide 406b, and the oxide 406c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to achieve this, the density of defect states in the mixed layer formed at the interface between the oxide 406a and the oxide 406b or the interface between the oxide 406b and the oxide 406c is preferably low.

  Specifically, the oxide 406a and the oxide 406b and the oxide 406b and the oxide 406c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed. be able to. For example, in the case where the oxide 406b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 406a and the oxide 406c.

  At this time, the main path of carriers is a narrow gap portion formed in the oxide 406b. Since the density of defect states at the interface between the oxide 406a and the oxide 406b and the interface between the oxide 406b and the oxide 406c can be reduced, the influence on the carrier conduction due to interface scattering is small, and a high on-current is obtained. can get.

  In the case of manufacturing the transistor 1000a, an oxide film to be the oxide 406c may be formed before the step of forming the insulating film 412A illustrated in FIGS. In the subsequent steps, the oxide film may be patterned similarly to the insulating film 412A.

  Next, the transistor 1000b illustrated in FIGS. 14A, 14B, and 14C is described. Transistor 1000b differs from transistor 1000 in that oxide 406c is disposed over oxide 406b. The description of the transistor 1000 can be referred to for other structures. An oxide 406b is disposed under the oxide 406c, and a side surface of the oxide 406c substantially matches a side surface of the oxide 406b. The oxide 406c is formed so as to overlap with the oxide 406a and the oxide 406b. Here, since the insulator 409 is in contact with the top surface of the oxide 406c, a region 426a, a region 426b, and a region 426c are formed in the oxide 406c similarly to the oxide 406b. Note that in the following, the oxide 406a, the oxide 406b, and the oxide 406c may be collectively referred to as an oxide 406.

  As in the transistor 1000a, the oxide 406c of the transistor 1000b can be formed using a metal oxide that can be used for the oxide 406a or the oxide 406b.

  In the case of manufacturing the transistor 1000b, an oxide film to be the oxide 406c may be formed after the step of forming the oxide film 406bA illustrated in FIGS. In the subsequent steps, the oxide film may be patterned similarly to the oxide film 406bA.

  Next, the transistor 1000c illustrated in FIGS. 15A, 15B, and 15C is described. The transistor 1000c is different from the transistor 1000 in that an insulator 419 is provided over the conductor 404b. The description of the transistor 1000 can be referred to for other structures. Here, like the sidewall insulator 418, the insulator 419 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, for example, aluminum oxide or hafnium oxide. Etc. are preferably used.

  By providing such an insulator 419, the upper surface and the side surface of the conductor 404 can be covered with the insulator 419 having a function of suppressing permeation of oxygen and the sidewall insulator 418. Thereby, surrounding excess oxygen can be prevented from being used for the oxidation of the conductor 404. As described above, the sidewall insulator 418 and the insulator 419 function as a gate cap for protecting the gate.

  In the case of manufacturing the transistor 1000c, an insulating film serving as the insulator 419 may be formed after the step of forming the conductive film 404bA illustrated in FIGS. In the subsequent steps, the insulating film may be patterned similarly to the conductive film 404bA. Note that in the case where the CMP process is performed in the step of removing the upper portion of the buffer layer 405B illustrated in FIG. 10, the CMP process may be performed until the insulator 419 is exposed.

  Next, the transistor 1000d illustrated in FIGS. 16A, 16B, and 16C will be described. The transistor 1000 d is different from the transistor 1000 in the shape of the buffer layer 405. The description of the transistor 1000 can be referred to for other structures.

  As shown in FIGS. 16B and 16C, in the transistor 1000d, the buffer layer 405 overlaps with the conductor 404 even in a region overlapping with the oxide 406. The upper surface of the buffer layer 405 substantially coincides with the uppermost surfaces of the sidewall insulator 418, the insulator 409, and the insulator 410. In addition, since the conductor 404b is covered with the buffer layer 405, the position of the uppermost surface of the conductor 404 is lower than the uppermost surfaces of the buffer layer 405, the sidewall insulator 418, the insulator 409, and the insulator 410. .

  In the case of manufacturing the transistor 1000d, the conductor 404 is formed into the buffer layer 405 in the step of removing part of the insulating film to be the insulator 410 illustrated in FIG. 10, the buffer layer 405B, the sidewall insulator 418B, and the insulating film 409A. The CMP process or the like may be terminated in a covered state, that is, before the conductor 404 is exposed.

  Next, the transistor 2000 illustrated in FIGS. 17A to 17C will be described. The transistor 2000 is a transistor that can be manufactured in parallel with the transistor 1000, the transistor 1000a, the transistor 1000b, the transistor 1000c, and the like. In particular, when the transistor 2000 is manufactured in parallel with the transistor 1000a, the transistor 2000 can be manufactured without increasing unnecessary steps.

  The transistor 2000 includes an insulator 401 disposed on the substrate 400, an insulator 301 disposed on the insulator 401, the conductors 310a and 310b embedded in the openings of the insulator 301, An insulator 302 disposed over the body 301 and the conductor 310; an insulator 303 disposed over the insulator 302; an insulator 402 disposed over the insulator 303; The oxide 406a1 and the oxide 406a2 that are spaced apart from each other, the oxide 406b1 that is disposed in contact with the top surface of the oxide 406a1, and the oxide 406b2 that is disposed in contact with the top surface of the oxide 406a2. The upper surface of the body 402, the side surfaces of the oxide 406a1 and the oxide 406a2, and the side surface and the upper surface of the oxide 406b1 and the oxide 406b2. Oxide 406c, insulator 412 disposed over oxide 406c, conductor 404a disposed over insulator 412; conductor 404b disposed over conductor 404a; 406c, insulator 412, conductor 404a, and sidewall insulator 418 disposed in contact with the side surfaces of conductor 404b, and in contact with the top and side surfaces of oxide 406b1 and oxide 406b2, and sidewall insulator 418 And an insulator 409 which is disposed in contact with the side surface.

  As illustrated in FIG. 17B, part of the oxide 406c, the insulator 412, and the conductor 404 overlaps with the oxide 406a1 and the oxide 406a2 or the oxide 406b1 and the oxide 406b2. Thus, in the transistor 2000, the top surface of the conductor 404b is a portion overlapping with the oxide 406a1 and the oxide 406a2 or the oxide 406b1 and the oxide 406b2. Therefore, the buffer layer 405 may be formed over the conductor 404b in a region that does not overlap with the oxide 406a1 and the oxide 406a2 or the oxide 406b1 and the oxide 406b2.

  The insulator 410 is preferably provided over the insulator 409, the insulator 415 is provided over the insulator 410, and the insulator 420 is preferably provided over the insulator 415.

  Note that the description of the transistor 1000a can be referred to for structures having the same reference numerals as those of the transistor 1000a.

  The oxide 406a1 and the oxide 406a2, and the oxide 406b1 and the oxide 406b2 can be formed using materials similar to the oxide 406a and the oxide 406b of the transistor 1000a, respectively. The oxide 406a1 and the oxide 406b1, the oxide 406a2, and the oxide 406b2 are formed to face each other with the conductor 310, the oxide 406c, the insulator 412, and the conductor 404 interposed therebetween.

  The oxide 406a1 and the oxide 406b1, and the oxide 406a2 and the oxide 406b2 each have a region overlapping with the insulator 409, and the region and its vicinity have a low resistance as in the region 426b and the region 426c of the transistor 1000a. Has been. Thus, the oxide 406a1 and the oxide 406b1 or the oxide 406a2 and the oxide 406b2 can function as either the source region or the drain region of the transistor 2000.

  The oxide 406c of the transistor 2000 can be formed using a material similar to that of the oxide 406c of the transistor 1000a. A region between the oxide 406a1 and the oxide 406a2 and the oxide 406b1 and the oxide 406b2 in the oxide 406c functions as a channel formation region.

  As in the oxide 406c of the transistor 1000a, the oxide 406c functioning as the active layer of the transistor 2000 has reduced oxygen vacancies and impurities such as hydrogen or water. Accordingly, the threshold voltage of the transistor 2000 can be made higher than 0 V, the off current can be reduced, and Icut can be made extremely small. Here, Icut refers to the drain current when the back gate voltage and the top gate voltage are 0V.

  The transistor 2000 can control the back gate voltage of the transistor 1000a and the like. For example, the top gate and the back gate of the transistor 2000 are diode-connected to the source, and the source of the transistor 2000 and the back gate of the transistor 1000a are connected. In this configuration, when the negative potential of the back gate of the transistor 1000a is held, the voltage between the top gate and the source of the transistor 2000 and the voltage between the back gate and the source are 0V. Since Icut of the transistor 2000 is very small, this structure allows the negative potential of the back gate of the transistor 1000a to be maintained for a long time without supplying power to the transistor 1000a and the transistor 2000.

  Next, the transistor 2000a illustrated in FIGS. 18A, 18B, and 18C will be described. In the transistor 2000a, the conductor 308 and the conductor 309 are provided in the same layer as the conductor 310, and the oxide 406c is formed in the conductor through the openings formed in the insulator 302, the insulator 303, and the insulator 402. 308 and the conductor 309 are different from the transistor 2000 in that the oxide 406a1, the oxide 406a2, the oxide 406b1, and the oxide 406b2 are not provided. The description of the transistor 2000 can be referred to for other structures.

  The conductor 308 and the conductor 309 are provided to face each other with the conductor 310 interposed therebetween. The conductor 308 or the conductor 309 can function as either a source electrode or a drain electrode.

  As in the case of the conductor 310, the conductor 308 is in contact with the inner wall of the opening of the insulator 301, a conductor 308a is formed, and a conductor 308b is further formed inside. The conductor 309 is also formed with a conductor 309a and a conductor 309b, similarly to the conductor 310 and the conductor 308. The oxide 406c is preferably in contact with the conductor 308b and the conductor 309b. The conductor 308a and the conductor 309a can be the same conductor as the conductor 310a, and the conductor 308b and the conductor 309b can be the same conductor as the conductor 310b.

  As in the oxide 406c of the transistor 1000a, the oxide 406c functioning as the active layer of the transistor 2000a has reduced oxygen vacancies and impurities such as hydrogen or water. Accordingly, the threshold voltage of the transistor 2000a can be made higher than 0V, the off current can be reduced, and Icut can be made extremely small.

  Similar to the transistor 2000, the transistor 2000a can control the back gate voltage of the transistor 1000a and the like. For example, the top gate and the back gate of the transistor 2000a are diode-connected to the source, and the source of the transistor 2000a and the back gate of the transistor 1000a are connected. When the negative potential of the back gate of the transistor 1000a is held with this configuration, the voltage between the top gate and the source of the transistor 2000a and the voltage between the back gate and the source are 0V. Since the Icut of the transistor 2000a is very small, this structure allows the negative potential of the back gate of the transistor 1000a to be maintained for a long time without supplying power to the transistor 1000a and the transistor 2000a.

  Similarly to the transistor 2000, the transistor 2000a can be manufactured almost in parallel with the transistor 1000a.

  As described above, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

[Storage device 1]
The semiconductor device illustrated in FIGS. 20 and 21 includes a transistor 300, a transistor 200, and a capacitor 100.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

  20 and 21, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the first gate of the transistor 200, and the wiring 3006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The semiconductor device illustrated in FIGS. 20 and 21 has the characteristic that the potential of the gate of the transistor 300 can be held, so that data can be written, held, and read as described below.

  Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).

  When the off-state current of the transistor 200 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is _supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

<Structure of Semiconductor Device 1>
The semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.

  The transistor 300 may be either a p-channel type or an n-channel type.

  The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

  The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

  Note that the transistor 300 illustrated in FIGS. 20A and 20B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.

  As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

  The insulator 322 may function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.

  As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

  Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

  A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 20, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 20, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 20, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

  For example, the insulator 210 and the insulator 214 are each formed using a film having a barrier property such that hydrogen or an impurity does not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  As the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  For example, the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. .

  A transistor 200 is provided above the insulator 216. Note that as the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. For example, as the transistor 200, a transistor 1000, a transistor 1000a, a transistor 1000b, or the like can be used. 20 illustrates an example in which a transistor 1000a is used as the transistor 200. In addition, the transistor 200 illustrated in FIGS. 20A and 20B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 280 is provided above the transistor 200. It is preferable that an excess oxygen region be formed in the insulator 280. In particular, in the case where an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region is provided in an interlayer film or the like in the vicinity of the transistor 200, so that oxygen vacancies in the oxide 230 included in the transistor 200 are reduced. Can be improved. Further, the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 200. Note that the insulator 280 is provided in contact with the insulator 281 and the insulator 225 which are formed over the transistor 200.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  An insulator 282 is provided over the insulator 280. The insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214. For example, the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  Note that in the case where the transistor 1000a is provided as the transistor 200, the insulator 214 is the insulator 301, the conductor 218 is the conductor 310, the insulator 216 is the insulator 301, the insulator 220 is the insulator 302, and the insulator 222. Is the insulator 303, the insulator 224 is the insulator 402, the insulator 225 is the insulator 409, the insulator 281 is the insulator 410, the insulator 280 is the insulator 415, and the insulator 282 is the insulator 420. Correspond. Therefore, description of a corresponding structure shown in the above embodiment can be referred to.

  An insulator 286 is provided over the insulator 282. The insulator 286 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  A conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 280, the insulator 282, and the insulator 286.

  The conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Subsequently, the capacitor element 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.

  Further, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 functions as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

  The conductor 112 and the conductor 110 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  In FIG. 20, the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  An insulator 130 is provided over the conductor 112 and the conductor 110 as a dielectric of the capacitor 100. Examples of the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination | stacking or single layer.

  For example, the insulator 130 may be formed using a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor 100 includes the insulator 130, whereby the dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

  A conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. Note that the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

  The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Variation 1 of Storage Device 1>
An example of a modification of the present embodiment is shown in FIG. FIG. 21 is different from FIG. 20 in the configuration of the transistor 300.

  In the transistor 300 illustrated in FIG. 9, a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

  The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Modification 2 of storage device 1>
An example of a modification of the present embodiment is shown in FIG. FIG. 22 is different from FIG. 20 in the configuration of the capacitive element 100.

  In the memory device illustrated in FIG. 22, the insulator 287 is provided over the insulator 286, the conductor 112 is embedded in the insulator 287, the insulator 155 is provided over the insulator 287, and the insulator 155 is formed. The conductor 110 is provided in the plurality of openings, the insulator 130 is provided on the conductor 110, and the conductor 120 is provided on the insulator 130 so as to overlap the conductor 110. The conductor 112 is provided so as to connect the conductor 248 electrically connected to the transistor 200 and the conductor 248 electrically connected to the transistor 300, and the conductor 112 is in contact with the conductor 112. 110 may be provided. The insulator 287 and the insulator 155 can be formed using a material similar to that of the insulator 320.

  In the capacitor 100 illustrated in FIG. 22, the conductor 110, the insulator 130, and the conductor 120 overlap in the opening formed in the insulator 155, so that the conductor 110, the insulator 130, and the conductor 120 are overlapped. Is preferably a film having good coverage. Therefore, the conductor 110, the insulator 130, and the conductor 120 are preferably formed using a film formation method having good step coverage such as a CVD method or an ALD method.

  Since the capacitor 100 is formed along the shape of the opening provided in the insulator 155, the capacitance can be increased as the opening is formed deeper. Further, the capacitance can be increased as the number of the openings is increased. By forming such a capacitive element 100, the capacitance can be increased without increasing the upper area of the capacitive element 100.

  The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>
An example of the memory cell array of this embodiment is illustrated in FIG. A memory cell array can be formed by arranging the memory devices shown in FIGS. 20 and 21 as memory cells in a matrix. FIG. 23 is a cross-sectional view of a part of a row extracted from the storage device shown in FIG. 20 arranged in a matrix.

  In the memory device illustrated in FIG. 23, the memory cell 600a and the memory cell 600b are arranged adjacent to each other. Similarly to the memory device illustrated in FIG. 20, the memory cell 600a and the memory cell 600b each include the transistor 300, the transistor 200, and the capacitor 100, and include the wiring 3001, the wiring 3002, the wiring 3003, the wiring 3004, the wiring 3005, and the wiring 3006 is electrically connected. Similarly, in the memory cell 600a and the memory cell 600b, a node where the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is a node FG. Note that the wiring 3002 is a wiring common to the adjacent memory cells 600a and 600b.

When memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, when the memory cell array has a NOR structure, only information on a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a fifth wiring which is connected to a memory cell from which information is not read with a potential at which the transistor 300 becomes “non-conductive” regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H.} It may be given to 3005. Alternatively, for example, when the memory cell array has a NAND configuration, information on a desired memory cell can be read only by turning on the transistor 300 of the memory cell from which information is not read. In this case, a fifth wiring 3005 connected to a memory cell from which information is not read with a potential at which the transistor 300 is in a “conducting state” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L.} To give.

[Storage device 2]
FIG. 24 illustrates an example of a memory device using the semiconductor device which is one embodiment of the present invention.

  A memory device illustrated in FIG. 24 includes a transistor 345 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.

  As the transistor 345, a transistor included in the semiconductor device described in the above embodiment may be used. For example, the transistor 345 can be the transistor 2000, the transistor 2000a, or the like. FIG. 24 illustrates an example in which a transistor 2000 is used as the transistor 200. In addition, the transistor 345 illustrated in FIG. 24 is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  By using the transistor 2000 or the transistor 2000a as the transistor 345, the transistor 345 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 345 are diode-connected to the source, and the source of the transistor 345 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held with this structure, the voltage between the first gate and the source of the transistor 345 and the voltage between the second gate and the source are 0V. In the transistor 345, since the drain current when the second gate voltage and the first gate voltage are 0 V is very small, the power supply to the transistor 200 and the transistor 345 is not supplied, so that the second gate voltage of the transistor 200 Negative potential can be maintained for a long time. Thus, the memory device including the transistor 200 and the transistor 345 can hold stored data for a long time.

  Accordingly, in FIG. 24, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the gate of the transistor 200, and the wiring 3006 is electrically connected to the back gate of the transistor 200. . The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. . The wiring 3007 is electrically connected to the source of the transistor 345, the wiring 3008 is electrically connected to the gate of the transistor 345, the wiring 3009 is electrically connected to the back gate of the transistor 345, and the wiring 3010 is connected to the drain of the transistor 345. And are electrically connected. Here, the wiring 3006, the wiring 3007, the wiring 3008, and the wiring 3009 are electrically connected.

  The memory device illustrated in FIG. 24 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described above.

  In addition, the memory device illustrated in FIG. 24 can form a memory cell array by being arranged in a matrix like the memory device illustrated in FIG. Note that one transistor 345 can control the second gate voltage of the plurality of transistors 200. Therefore, the transistor 345 may be provided in a smaller number than the transistor 200.

<Structure of storage device 2>
The transistor 345 is formed in the same layer as the transistor 200 and can be manufactured in parallel. For example, in the case where the transistor 2000 is used as the transistor 345 and the transistor 1000a is used as the transistor 200, as illustrated in FIG. 24, the same reference numerals of the transistor 1000a illustrated in FIG. 13 and the transistor 2000 illustrated in FIG. Can be formed. Note that the oxide 406a1 and the oxide 406a2 of the transistor 2000 are arranged in the same layer as the oxide 406a of the transistor 1000a, and the oxide 406b1 and the oxide 406b2 of the transistor 2000 are arranged in the same layer as the oxide 406b of the transistor 1000a. .

  A dicing line (which may be referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing the large-area substrate into semiconductor elements will be described. As a dividing method, for example, a groove (dicing line) for dividing a semiconductor element may first be formed on a substrate, and then cut in the dicing line to be divided (divided) into a plurality of semiconductor devices. For example, the structure 500 shown in FIG. 24 shows a cross-sectional view near the dicing line.

  For example, as illustrated in the structure 500, an insulator 280, an insulator 281, an insulator 225, an insulator 224, an insulator in the vicinity of a region overlapping with a dicing line provided on the outer edge of the memory cell including the transistor 200 or the transistor 345 222, the insulator 220, and the insulator 216 are provided with openings. The insulator 282 is provided so as to cover the side surfaces of the insulator 280, the insulator 281, the insulator 225, the insulator 224, the insulator 222, the insulator 220, and the insulator 216.

  That is, the insulator 222, the insulator 214, and the insulator 282 are in contact with each other in the opening. At this time, adhesion can be improved by forming at least one of the insulator 222 and the insulator 214 and the insulator 282 using the same material and the same method. For example, aluminum oxide can be used.

  With this structure, the insulator 214, the insulator 222, and the insulator 282 can enclose the insulator 280, the transistor 200, and the transistor 345. Since the insulator 210, the insulator 222, and the insulator 282 have a function of suppressing diffusion of oxygen, hydrogen, and water, a circuit region including a plurality of substrates over which the semiconductor element described in this embodiment is formed By dividing each of them, even when processed into a plurality of chips, impurities such as hydrogen or water can be prevented from being mixed into the transistor 200 or the transistor 345 from the side surface direction of the divided substrate. .

  Further, with this structure, excess oxygen in the insulator 280 can be prevented from diffusing outside the insulator 282 and the insulator 222. Accordingly, excess oxygen in the insulator 280 is efficiently supplied to the oxide in which the channel in the transistor 200 or the transistor 345 is formed. With the oxygen, oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 345 is formed can be reduced. Accordingly, an oxide in which a channel is formed in the transistor 200 or the transistor 345 can be an oxide semiconductor having a low defect level density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 or the transistor 345 can be suppressed and reliability can be improved.

  As illustrated in FIG. 25, the transistor 345 described in the above embodiment may be provided as the transistor 345.

  In addition, as illustrated in FIG. 25, the conductor 120 that functions as the upper electrode of the capacitor 100 may be provided so as to go around to the side surface of the conductor 112 that functions as the lower electrode of the capacitor 100. Accordingly, the side surface of the conductor 112 also functions as a capacitor element, so that the capacitance of the capacitor element 100 can be increased. Alternatively, the dielectric film forming the capacitor element 100 may be a stacked film of the insulator 130a and the insulator 130b. For example, aluminum oxide can be used as the insulator 130a, and silicon oxynitride or the like can be used as the insulator 130b.

  The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Semiconductor wafer, chip>
FIG. 14A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711. The circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.

  Each of the plurality of circuit regions 712 is surrounded by the isolation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 26B shows an enlarged view of the chip 715.

  Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented. In general, the dicing step is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, and preventing charging. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, productivity of the semiconductor device can be increased.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIGS. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.

  Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

  The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711 in the previous step, a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). . By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.

  Next, a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.

  Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.

  The chip 715 that has been wire bonded is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and deterioration of characteristics due to moisture, dust, etc. (reliability Reduction) can be reduced.

  Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).

  Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection process” (step S729) for checking whether the external shape is good or not, and whether there is a malfunction.

  FIG. 27B shows a schematic perspective view of the completed electronic component. FIG. 27B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 27B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

  An electronic component 750 illustrated in FIG. 27B is mounted on a printed board 752, for example. A plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for an electronic device or the like.

(Embodiment 4)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 28 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.

  FIG. 28A is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.

  An information terminal 2910 illustrated in FIG. 28B includes a housing 2911 including a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

  A laptop personal computer 2920 illustrated in FIG. 28C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

  A video camera 2940 illustrated in FIG. 28D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

  FIG. 28E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

  FIG. 28F illustrates an example of a wristwatch type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

  The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

  In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

  For example, a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

100 Capacitor Element 110 Conductor 112 Conductor 120 Conductor 130 Insulator 130a Insulator 130b Insulator 150 Insulator 155 Insulator 200 Transistor 205 Conductor 210 Insulator 212 Insulator 214 Insulator 216 Insulator 218 Conductor 220 Insulator 222 insulator 224 insulator 225 insulator 230 oxide 246 conductor 248 conductor 280 insulator 281 insulator 282 insulator 286 insulator 287 insulator 300 transistor 301 insulator 302 insulator 303 insulator 308 conductor 308a conductor 308b conductor 309 conductor 309a conductor 309b conductor 310 conductor 310a conductor 310b conductor 311 substrate 313 semiconductor region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 3 24 insulator 326 insulator 328 conductor 330 conductor 345 transistor 350 insulator 352 insulator 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 374 insulator 376 conductor 380 insulator 382 insulator 384 insulator 386 conductor 400 substrate 401 insulator 402 insulator 404 conductor 404a conductor 404aA conductor 404b conductor 404bA conductor 405 buffer layer 405A buffer layer 405B buffer layer 406 oxide 406a oxide 406a1 Oxide 406a2 Oxide 406aA Oxide film 406b Oxide 406b1 Oxide 406b2 Oxide film 406bA Oxide film 406c Oxide 409 Insulator 409A Insulator film 410 Insulator 412 Insulator 412A Insulator film 415 Edge body 418 Side wall insulator 418A Insulating film 418B Side wall insulator 418C Side wall insulator 419 Insulator 420 Insulator 422 Dopant 426 Region 426a Region 426b Region 426c Region 500 Structure 711 Substrate 712 Circuit region 713 Separation region 714 Separation line 715 Chip 750 Electronic component 752 Printed circuit board 754 Mounting board 755 Lead 1000 Transistor 1000a Transistor 1000b Transistor 1000c Transistor 1000d Transistor 2000 Transistor 2000a Transistor 2910 Information terminal 2911 Housing 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Operation switch 2916 External connection unit 2917 Microphone 2920 Notebook type personal computer 2921 Body 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Case 2294 Case 2944 Display unit 2944 Operation switch 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Case 2952 Display unit 2960 Information terminal 2961 Case 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 Icon 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring 3007 Wiring 3008 Wiring 3009 Wiring 3010 Wiring

Claims (22)

A first insulator disposed on the substrate;
A first oxide disposed on the first insulator;
A second oxide disposed in contact with at least a portion of the top surface of the first oxide;
A second insulator disposed on the second oxide;
A first conductor disposed on the second insulator;
A second conductor disposed on the first conductor;
A sidewall insulator disposed in contact with a side surface of the second insulator, the first conductor, and the second conductor;
A third insulator disposed in contact with an upper surface of the second oxide and in contact with a side surface of the sidewall insulator;
The semiconductor device according to claim 1, wherein an upper surface of the sidewall insulator and an uppermost surface of the third insulator substantially coincide with an uppermost surface of the second conductor. In claim 1,
The first oxide and the second oxide each include In, an element M (M is Al, Ga, Y, or Sn), and Zn. A first insulator disposed on the substrate;
A first oxide disposed on the first insulator;
A second oxide disposed in contact with at least a portion of the top surface of the first oxide;
A third oxide disposed on the second oxide;
A second insulator disposed on the third oxide;
A first conductor disposed on the second insulator;
A second conductor disposed on the first conductor;
A sidewall insulator disposed in contact with a side surface of the second insulator, the first conductor, and the second conductor;
A third insulator positioned on the second oxide and disposed in contact with a side surface of the sidewall insulator;
The semiconductor device according to claim 1, wherein an upper surface of the sidewall insulator and an uppermost surface of the third insulator substantially coincide with an uppermost surface of the second conductor. In claim 3,
A side surface of the third oxide is in contact with a sidewall insulator;
The semiconductor device, wherein the third insulator is in contact with an upper surface of the second oxide. In claim 3,
A side surface of the third oxide substantially coincides with a side surface of the second oxide;
The semiconductor device, wherein the third insulator is in contact with an upper surface of the third oxide. In any one of Claim 3 thru | or 5,
Each of the first oxide to the third oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. In any one of Claims 1 thru | or 6,
The region of the second oxide overlapping the third insulator has a concentration of at least one of hydrogen and nitrogen higher than the vicinity of the center of the region of the second oxide overlapping the second insulator. A semiconductor device. In any one of Claims 1 thru | or 6,
The region of the second oxide that overlaps the third insulator and the sidewall insulator has at least hydrogen and nitrogen from the vicinity of the center of the region of the second oxide that overlaps the second insulator. A semiconductor device characterized in that one of the concentrations is high. In any one of Claims 1 thru | or 6,
The region of the third insulator of the second oxide, the sidewall insulator, and the vicinity of both ends of the second insulator overlap with the second insulator of the second oxide. A semiconductor device characterized in that the concentration of at least one of hydrogen and nitrogen is higher than the vicinity of the center of the overlapping region. In any one of Claims 1 thru | or 9,
The semiconductor device according to claim 1, wherein the sidewall insulator is formed using an ALD method. In any one of Claims 1 to 10,
The semiconductor device according to claim 1, wherein the sidewall insulator includes either aluminum oxide or hafnium oxide. In any one of Claims 1 to 11,
The semiconductor device, wherein the first conductor includes a conductive oxide. In any one of Claims 1 to 12,
The semiconductor device, wherein the third insulator includes one or both of hydrogen and nitrogen. In any one of Claims 1 thru / or Claim 13,
A third conductor disposed under the first insulator so as to have a region overlapping the second oxide, the first conductor, and the second conductor; A semiconductor device characterized by the above. In any one of Claims 1 thru | or 14,
A buffer layer disposed on at least a portion of the second conductor;
The buffer layer does not overlap the second conductor in at least a part of the region overlapping the second oxide,
The side surface of the buffer layer is in contact with the sidewall insulator,
The semiconductor device according to claim 1, wherein an upper surface of the buffer layer substantially coincides with an uppermost surface of the second conductor. In any one of Claims 1 to 15,
The semiconductor device, wherein the buffer layer includes an insulator. In any one of Claims 1 to 15,
The semiconductor device, wherein the buffer layer has a conductor. Depositing a first insulator on the substrate;
A first oxide film and a second oxide film are sequentially formed on the first insulator,
Processing the first oxide film and the second oxide film into an island shape to form a first oxide and a second oxide;
A first insulating film, a first conductive film, a second conductive film, and a first buffer layer are sequentially formed on the second oxide;
Etching the first insulating film, the first conductive film, the second conductive film, and the first buffer layer to form a second insulator, a first conductor, and a second conductor And a second buffer layer;
The first insulator, the first oxide, the second oxide, the second insulator, the first conductor, the second conductor, and the second buffer layer. Covering, forming a third insulating film using the ALD method,
A dry etching process is performed on the third insulating film to contact the side surfaces of the second insulator, the first conductor, the second conductor, and the second buffer layer. Forming sidewall insulators,
Covering the first insulator, the first oxide, the second oxide, the first sidewall insulator, and the second buffer layer, a fourth insulation is performed using a PECVD method. Deposit a film,
Forming a fifth insulating film on the fourth insulating film;
Part of the second buffer layer, the first sidewall insulator, the fourth insulating film, and the fifth insulating film is removed until a part of the second conductor is exposed. And forming a third buffer layer, a second sidewall insulator, a third insulator, and a fourth insulator. In claim 18,
A method for manufacturing a semiconductor device, wherein the thickness of the first buffer layer is greater than or equal to 10 nm and less than or equal to 100 nm. In claim 18 or claim 19,
A method for manufacturing a semiconductor device, characterized in that the fourth insulating film is formed in an atmosphere containing nitrogen. In any one of claims 18 to 20,
A method for manufacturing a semiconductor device, wherein the third buffer layer, the second sidewall insulator, the third insulator, and the fourth insulator are formed by CMP treatment. In any one of Claims 18 to 21,
A method for manufacturing a semiconductor device is characterized in that the first conductive film is formed by sputtering in an atmosphere containing oxygen.