JP2017139270A - Method for manufacturing semiconductor light-emitting device, and semiconductor light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor light-emitting device with high brightness inexpensively.SOLUTION: A method for manufacturing a semiconductor light-emitting device comprises the steps of: (a) preparing a growth substrate 25 having a GaN layer 28 as a layer over a base substrate 26, provided that the GaN layer has defect-concentrated portions 41 formed in a plurality of regions disposed distributedly and the defect-concentrated portions are higher, in defect density, than regions other than the plurality of distributedly disposed regions; (b) forming, as a layer on the growth substrate, a semiconductor layer 5 including a n- or p-type first semiconductor layer 7, an active layer 9 and a second semiconductor layer 11 of a conductivity type different from the first conductivity type; and (c) forming an insulator layer as a top layer of a semiconductor layer located in particular regions 42 opposed to the defect-concentrated portions in a direction orthogonal to a plane of the growth substrate at the completion of the step (b).SELECTED DRAWING: Figure 5B

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device and a semiconductor light emitting device.

  Conventionally, a method of manufacturing a semiconductor light emitting device by epitaxially growing a buffer layer made of GaN on an upper surface of a crystal substrate made of sapphire and then forming various nitride semiconductor layers is known. However, since sapphire has a lattice constant difference with GaN, it is unavoidable that a semiconductor layer is formed with crystal defects and dislocations. When the density of such defects and the like is high, the light emitting efficiency of the semiconductor light emitting device is lowered and the life characteristics are lowered.

  On the other hand, a high-quality semiconductor layer can be realized by growing a semiconductor layer on the upper surface of a free-standing GaN substrate made of GaN with high crystal quality, but the free-standing GaN substrate is extremely expensive and manufactured for the purpose of distributing it to the market. It is a great obstacle to use as a growth substrate for LEDs.

  Patent Document 1 discloses a technique in which a substrate in which a high-quality GaN layer is formed on the top surface of a sapphire substrate is used as a growth substrate in place of a self-standing GaN substrate, and a semiconductor layer is regrown on the top surface of the substrate. ing. Such a substrate is sometimes referred to as a “GaN template substrate”.

JP 2001-44126 A

  An object of the present invention is to increase the light emission efficiency as compared with the prior art when manufacturing a semiconductor light emitting device using the so-called “GaN template substrate” as described above.

  As described above, when a sapphire substrate is used as a growth substrate and a nitride semiconductor layer is grown after a GaN buffer layer is grown on the upper surface of the sapphire substrate, it is inevitable that defects due to a difference in lattice constants will appear. It is. On the other hand, when a substrate (GaN template substrate) on which a high-quality GaN film is previously formed on the uppermost surface is used as a growth substrate and a semiconductor layer is grown on the upper surface of this growth substrate, the GaN layer and the growth thereon are grown. Since the difference in lattice constant between the nitride semiconductor layer and the nitride semiconductor layer is small, the occurrence frequency of defects is suppressed, and it is considered that a high-quality semiconductor layer can be formed.

  In recent years, low-cost and high-luminance light-emitting elements are required from the market. Therefore, as described above, if a GaN template substrate with high crystal quality can be used, it is possible to meet such market demands.

  By the way, among GaN template substrates, there are substrates that have improved crystal quality by concentrating defects in specific regions within the substrate and reducing the defect density in other regions. This type of substrate can be manufactured at a relatively low cost in a template substrate having a GaN layer with high crystal quality. Therefore, if such a substrate can be used as a growth substrate for a light-emitting element, it is possible to realize a light-emitting element that is inexpensive and has high luminance, and can meet market demands.

  However, according to the earnest study of the present inventor, even when a semiconductor layer including an active layer is grown on the upper layer of this type of GaN template substrate, a sufficiently high luminance cannot be realized. It was. This is because, as described above, there is a region having a high defect density in a predetermined region in the substrate, and thus the light emission efficiency in the active layer formed in the upper layer of this region cannot be sufficiently ensured. It is assumed that there is.

Therefore, a method for manufacturing a semiconductor light emitting device according to the present invention is as follows.
A step of preparing a growth substrate, in which a GaN layer having a defect concentration portion having a defect density higher than that of a region other than the plurality of regions is formed in an upper layer of a base substrate in a plurality of regions arranged in a dispersed manner ( a) and
Forming a semiconductor layer including an n-type or p-type first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type different from the first conductivity type, on the growth substrate (b) When,
When the step (b) is completed, an insulating layer is formed on the semiconductor layer located in a specific region, which is a region facing the defect concentration portion in a direction orthogonal to the plane of the growth substrate. And (c).

  When a semiconductor layer is grown on a growth substrate including a GaN layer having defect concentration portions in a plurality of dispersed regions, a region having a high defect density is formed above the defect concentration portion in the semiconductor layer. Will be. This region is a region facing the defect concentration portion in the direction orthogonal to the surface of the growth substrate, and corresponds to the “specific region” described above.

  In the above method, an insulating layer is provided on the upper layer of the semiconductor layer located in the “specific region” in the semiconductor layer. This insulating layer serves as a barrier against current flowing through a region in the semiconductor layer having a high defect density. That is, when a voltage is applied to the light-emitting element, current hardly flows in a region having a high defect density in the semiconductor layer, and current flows preferentially in a region formed of a high-quality semiconductor layer. . As a result, an inexpensive and high luminance light emitting element is realized.

  In the above, the semiconductor layer may be made of a nitride semiconductor. The base substrate may be made of mullite.

The step (c) is a step of forming the insulating layer on the second semiconductor layer located in the specific region,
After the step (c), a step (d) of attaching a support substrate different from the growth substrate to the upper layer of the second semiconductor layer;
After the step (d), the step (e) of peeling the growth substrate and exposing the first semiconductor layer;
The semiconductor layer located in the specific region remains by etching from the first semiconductor layer side until the insulating layer is exposed with respect to the semiconductor layer located in the specific region. The step (f1) for performing element isolation may be included.

  According to this configuration, since the semiconductor layer located in the “specific region” is removed by etching, the semiconductor layer remaining after the element isolation is configured with a high quality layer. Therefore, an element with high luminous efficiency is realized.

A plurality of the defect concentration portions are arranged along a predetermined first direction when viewed from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction,
The step (f1) may be a step of performing element isolation along the first direction.

  The defect concentration portion formed on the growth substrate may be arranged in a certain direction (first direction) in some cases. When a semiconductor layer is grown on the upper layer of such a growth substrate, a “specific region” facing the defect concentration portion is also arranged in alignment with the first direction in the direction orthogonal to the surface of the substrate.

  By the way, when the defect concentration portion is arranged on the growth substrate in alignment in the first direction, not only in the region where the defect concentration portion exists, but also on the line connecting adjacent defect concentration portions, The defect density tends to be higher than that. This means that the defect density is likely to be higher in the semiconductor layer than between the plurality of “specific regions” formed in alignment in the first direction.

  According to the above method, since element isolation is performed along the first direction formed by the “specific region”, the defect density formed between adjacent “specific regions” is relatively high. The region of the semiconductor layer is also etched. As a result, the semiconductor layer remaining after element isolation is composed of a semiconductor layer with high crystal quality, and thus a light-emitting element exhibiting high light emission efficiency is realized.

In the above method, a plurality of the defect concentration portions are disposed along a predetermined second direction different from the first direction as seen from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction and the second direction,
The step (f1) may be a step of performing element isolation along the first direction and the second direction.

  For example, it is assumed that a plurality of defect concentration portions are arranged vertically and horizontally on the growth substrate. In such a case, in the step (f1), element isolation is performed along the vertical direction and the horizontal direction, whereby the semiconductor layer in a region having a relatively high defect density is etched. As a result, the semiconductor layer remaining after element isolation is composed of a semiconductor layer with high crystal quality, and thus a light-emitting element exhibiting high light emission efficiency is realized.

The step (c) is a step of forming the insulating layer on the second semiconductor layer located in the specific region,
After the step (c), a step (d) of attaching a support substrate different from the growth substrate to the upper layer of the second semiconductor layer;
After the step (d), the step (e) of peeling the growth substrate and exposing the first semiconductor layer;
(F2) performing element isolation so that at least a part of the semiconductor layer located in the specific region remains by etching the semiconductor layer from the first semiconductor layer side. Have
After the execution of the step (f2), the insulating layer may be formed in contact with the semiconductor layer located in the specific region among the remaining semiconductor layers.

  According to the above method, even after the element isolation, even if the semiconductor layer located in the “specific region” remains, the semiconductor layer located in the “specific region” An insulating layer is formed in contact with As a result, a configuration in which current does not easily flow through the region is realized. That is, since a current flows in the semiconductor layer exhibiting high crystal quality, high luminous efficiency is realized.

A plurality of the defect concentration portions are arranged along a predetermined first direction when viewed from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction,
After the execution of the step (f2), the insulating layer is in contact with the semiconductor layer located in the specific region among the remaining semiconductor layers and continuously along the first direction. It may be formed either intermittently or intermittently.

  As described above, the defect concentration portion formed on the growth substrate may be arranged in a predetermined first direction. When a semiconductor layer is grown on the upper layer of such a growth substrate, and the semiconductor layer in the “specific region” remains after element isolation, the semiconductor located in the “specific region” There will be a plurality of layers along the first direction. In the above method, the insulating layer is formed continuously or intermittently so as to be in contact with the semiconductor layers in the plurality of “specific regions” formed along the first direction. A configuration in which current does not flow easily in a low-quality semiconductor layer is realized. As a result, since a current flows in the semiconductor layer exhibiting high crystal quality, high luminous efficiency is realized.

A plurality of the defect concentration portions are disposed along a predetermined second direction different from the first direction as seen from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction and the second direction,
After execution of the step (f2), the insulating layer is in contact with the semiconductor layer located in the specific region among the remaining semiconductor layers, and in the first direction and the second direction. It may be formed continuously or intermittently along the direction.

The step (f2) is a step of etching from the side of the first semiconductor layer until the insulating layer is exposed to a part of the semiconductor layer located in the specific region,
After the execution of the step (f2), the semiconductor layer may remain in a region sandwiched between the insulating layers when viewed from a direction orthogonal to the surface of the support substrate.

In addition, after the step (b), at least the first semiconductor from the second semiconductor layer side in the region facing the defect concentration portion in the direction perpendicular to the surface of the growth substrate in the semiconductor layer. Etching to form a first groove (g) until the layer is exposed;
The step (c) may be performed after the step (g) and is a step of forming the insulating layer so as to cover at least the inner surface of the first groove portion.

  According to the above method, at least the second semiconductor layer and the active layer are etched in the semiconductor layer located in the “specific region”. For this reason, the effect of preventing the current from flowing through the semiconductor layer with low crystal quality located in the “specific region” is further enhanced. As a result, since a current flows in the semiconductor layer exhibiting high crystal quality, high luminous efficiency is realized.

  A step (h) of forming a reflective electrode material so as to cover the upper surfaces of the second semiconductor layer and the insulating layer may be provided after the step (c) and before the step (d).

  Since no current flows in the region where the insulating layer is formed, the reflective electrode material formed in such a region does not function as an electrode. However, by forming the reflective electrode material also in such a region, high reflectivity is ensured, so that high light extraction efficiency is realized.

After the step (d), the step (e) of peeling the growth substrate and exposing the first semiconductor layer;
Etching the first semiconductor layer located in the specific region to form a second groove (i),
The step (c) may be performed after the step (i), and the insulating layer may be formed so as to cover at least the inner surface of the second groove portion.

  Also in the above method, the semiconductor layer in the “specific region” is configured such that at least the second semiconductor layer is etched and the insulating layer is in contact with each other, so that current does not easily flow through the region. Is realized. Therefore, since a current flows in the semiconductor layer exhibiting high crystal quality, high luminous efficiency is realized.

The semiconductor light emitting device according to the present invention is
A support substrate;
A semiconductor layer including an n-type or p-type first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type different from the first conductivity type, formed on an upper layer of the support substrate;
The semiconductor layer includes an insulating layer formed in contact with the first semiconductor layer or the second semiconductor layer in a specific region having a defect density higher than that of the surroundings.

The semiconductor light emitting element has a first groove portion provided in the specific region, from the second semiconductor layer side toward the first semiconductor layer side,
The insulating layer may be formed in contact with the inner surface of the first groove portion.

  The semiconductor light emitting element may have a reflective electrode formed on the second semiconductor layer and the insulating layer.

The semiconductor light emitting element has a second groove portion provided in the specific region, from the first semiconductor layer side toward the second semiconductor layer side,
The insulating layer may be formed in contact with the inner surface of the second groove portion.

  The insulating layer may be disposed continuously or intermittently along a predetermined first direction when viewed from a direction orthogonal to the surface of the support substrate. The insulating layer may be disposed continuously or intermittently along a predetermined second direction different from the first direction when viewed from a direction orthogonal to the surface of the support substrate. Absent.

  According to the present invention, an inexpensive and high-brightness semiconductor light emitting device is realized.

It is a top view which shows typically the structure of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is a top view which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is a top view which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 1st embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is a top view which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is a top view which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically another structure of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of 2nd embodiment of a semiconductor light-emitting device.

  A method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to the drawings. In each drawing, the dimensional ratio of the drawings does not necessarily match the actual dimensional ratio. The manufacturing conditions and film thickness dimensions described below are merely examples, and are not limited to these numerical values.

In the following, the description “AlGaN” is synonymous with the description Al _m Ga _1-m N (0 <m <1), and the description of the composition ratio of Al and Ga is simply omitted. And it is not the meaning limited to the case where the composition ratio of Al and Ga is 1: 1. The same applies to descriptions such as “InGaN”.

[First embodiment]
A first embodiment of the present invention will be described with reference to the drawings.

<Construction>
1A to 1B are drawings schematically showing a configuration of an embodiment of a semiconductor light emitting device of the present invention. FIG. 1A corresponds to a plan view when viewed from the light extraction direction. FIG. 1B corresponds to a cross-sectional view taken along line X1-X1 in FIG. 1A. Hereinafter, the light extraction surface is defined as an XY plane, and a direction orthogonal to the XY plane is defined as a Z direction.

  As shown in FIG. 1B, the semiconductor light emitting device 1 of the present embodiment includes a support substrate 3, a semiconductor layer 5 formed on the support substrate 3, a first electrode 15, a second electrode 13, and an insulating layer 24. With. Hereinafter, the semiconductor light emitting element 1 may be simply abbreviated as “light emitting element 1” as appropriate.

(Support substrate 3)
The support substrate 3 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Semiconductor layer 5)
In this embodiment, the semiconductor layer 5 is formed by sequentially stacking a p-type semiconductor layer 11, an active layer 9, and an n-type semiconductor layer 7 from the side close to the support substrate 3. In the present embodiment, the n-type semiconductor layer 7 corresponds to a “first semiconductor layer”, and the p-type semiconductor layer 11 corresponds to a “second semiconductor layer”.

  The p-type semiconductor layer 11 is composed of a nitride semiconductor layer doped with a p-type impurity such as Mg, Be, Zn, or C, for example. As the nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN, or the like can be used.

The active layer 9 is formed of a semiconductor layer in which, for example, a light emitting layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated. These layers may be undoped or p-type or n-type doped. The active layer 9 only needs to be configured by laminating layers made of at least two kinds of materials having different energy band gaps. The constituent material of the active layer 9 is appropriately selected according to the wavelength of light to be generated. In the light emitting device 1 of the present embodiment, the wavelength of light generated in the active layer 9 can be 410 nm or less. For example, when the emission wavelength is 365 nm, the active layer 9 is configured by repeatedly laminating In _0.05 Ga _0.95 N and Al _0.09 Ga _0.91 N.

The n-type semiconductor layer 7 is composed of a nitride semiconductor layer doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te. As this nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN or the like can be used. The n-type impurity concentration of the n-type semiconductor layer 7 is set to about 3 × 10 ¹⁹ / cm ³ , for example. The n-type impurity concentration of the n-type semiconductor layer 7 is preferably 1 × 10 ¹⁸ / cm ³ or more, and more preferably 1 × 10 ¹⁹ / cm ³ or more.

  The n-type semiconductor layer 7 may be made of a material having a composition different from that of the p-type semiconductor layer 11.

(First electrode 15)
The first electrode 15 is formed on the surface of the first semiconductor layer 7 opposite to the active layer 9. In the present embodiment, the first electrode 15 constitutes an n-side electrode. The first electrode 15 is made of, for example, a Ni / Al / Ni / Ti / Au multilayer structure, Cr / Au, Ti / Pt / Au, Ti / Pt / Cr / Au / Cr / Pt / Au, or the like. be able to.

  As shown in FIG. 1A, the first electrode 15 exhibits a frame shape when viewed in the Z direction. More specifically, the outer edge portion of the first electrode 15 has a frame shape along the outer edge portion of the semiconductor layer 5 (first semiconductor layer 7). In addition, the light emitting element 1 shown to FIG. 1A is the two 1st extended | stretched to the Y direction in the two places inside the outer edge part of the 1st electrode 15 which shows frame shape, and the position spaced apart from the outer edge part to the X direction. An electrode 15 is provided. However, the number of the first electrodes 15 to be extended inside the region indicating the frame shape is not limited to two, and may be one or three or more. The shape of the first electrode 15 shown in FIG. 1A is merely an example, and can be arbitrarily changed according to the design.

  The first electrode 15 is configured to include a current supply unit 15a to which the current supply line 14 is connected in some places. The current supply unit 15 a has a wider area than other areas of the first electrode 15. The current supply line 14 is made of, for example, Au or Cu. The end of the current supply line 14 opposite to the end connected to the current supply unit 15a is connected to, for example, a power supply pattern of a package substrate.

(Second electrode 13)
The second electrode 13 is formed in contact with the p-type semiconductor layer 11, and an ohmic contact is formed with the p-type semiconductor layer 11. In the present embodiment, the second electrode 13 constitutes a p-side electrode.

  When a voltage is applied between the first electrode 15 and the second electrode 13, a current flows through the active layer 9, and the active layer 9 emits light.

  The second electrode 13 is preferably made of a conductive material exhibiting a high reflectance (for example, 80% or more, more preferably 90% or more) with respect to light emitted from the active layer 9. More specifically, the second electrode 13 is made of a material containing, for example, Ag, Al, or Rh. As described above, the light emitting element 1 shown in FIG. 1A is assumed to extract light emitted from the active layer 9 to the n-type semiconductor layer 7 side. By configuring the second electrode 13 with a material exhibiting a high reflectance, light emitted from the active layer 9 toward the support substrate 3 is reflected toward the n-type semiconductor layer 7, so that the light extraction efficiency Is increased.

(Conductive layer 20)
The conductive layer 20 is formed in the upper layer of the support substrate 3. In the present embodiment, the conductive layer 20 has a multilayer structure of a protective layer 23, a bonding layer 21, a bonding layer 19, and a protective layer 17.

  The bonding layer 19 and the bonding layer 21 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the bonding layer 19 and the bonding layer 21 make the bonding layer 21 formed on the support substrate 3 and the bonding layer 19 formed on another substrate (a growth substrate 25 described later) face each other. Then, the two are bonded together. The bonding layer 19 and the bonding layer 21 may be integrated as a single layer.

  The protective layer 17 has a multilayer structure such as Ni / Ti / Pt, TiW / Pt, etc., and the material constituting the bonding layer (19, 21) diffuses to the second electrode 13 side, and the second electrode 13 is provided for the purpose of suppressing a decrease in reflectance. However, whether or not the light emitting element 1 includes the protective layer 17 is arbitrary.

  The protective layer 23 is made of the same material as that of the protective layer 17, for example, and is provided for the purpose of suppressing the material constituting the bonding layers (19, 21) from diffusing to the substrate 3 side. However, whether or not the light emitting element 1 includes the protective layer 23 is arbitrary.

(Insulating layer 24)
Insulating layer 24 is composed for example _{SiO 2, SiN, Zr 2 O} 3, AlN, etc. Al ₂ O _3. The insulating layer 24 is formed at a position outside the semiconductor layer 5 and functions as an etching stopper layer at the time of element isolation, as will be described later in the description of the manufacturing method (step S11).

  In the present embodiment, the insulating layer 24 is formed at a position facing the first electrode 15 in the Z direction, but this is optional. The insulating layer 24 formed at this position plays a role of spreading the current flowing through the active layer 9 in a direction parallel to the XY plane.

<Production method>
Hereinafter, a method for manufacturing the semiconductor light emitting device 1 will be described with reference to FIGS. 2A to 2N.

(Step S1)
First, as shown in FIG. 2A, a growth substrate 25 is prepared. The growth substrate 25 is a substrate in which a high-quality thin GaN layer 28 is formed on an upper surface of a base substrate 26 via an intermediate layer 27. Note that whether or not the growth substrate 25 includes the intermediate layer 27 is arbitrary.

The base substrate 26 is made of, for example, mullite made of a polycrystal of Al ₂ O ₃ and SiO ₂ . In addition, it is good also as a structure (YSZ mullite) containing a yttria stabilization zirconia.

The intermediate layer 27 is made of, for example, SiO ₂ . The intermediate layer 27 may be made of an inorganic oxide such as Al ₂ O ₃ , TiO ₂ , or ZrO ₂ in addition to SiO ₂ .

  The GaN layer 28 has defect concentration portions 41 having a defect density higher than that of the surrounding areas in a plurality of regions arranged in a dispersed manner. FIG. 2B is a plan view schematically showing the growth substrate 25. In the example shown in FIG. 2B, a plurality of defect concentration portions 41 are formed in the GaN layer 28 so as to be separated from each other in the X direction and the Y direction. The defect concentration portion 41 is provided for the purpose of improving the crystal quality of the GaN layer 28 in a region where the defect concentration portion 41 is not provided.

  This step S1 corresponds to the step (a).

(Step S2)
On the growth substrate 25, an n-type semiconductor layer 7, an active layer 9, and a p-type semiconductor layer 11 are sequentially formed. This step S2 is performed by the following procedure, for example.

The growth substrate 25 is installed in a processing furnace of the МОCVD apparatus, and the furnace temperature is raised to a predetermined temperature (for example, 1150 ° C.). The furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.013 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 7 having a composition of Al _0.06 Ga _0.94 N and a thickness of 2 μm is formed in the upper layer of the growth substrate 25. When the n-type semiconductor layer 7 is made of GaN or AlGaN, the Al composition ratio is preferably 0% or more and 15% or less, more preferably 2% or more and 11% or less, and 5%. More preferably, it is 9% or less.

  After this, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, thereby having a protective layer made of n-type GaN having a thickness of about 5 nm on the n-type AlGaN layer. An n-type semiconductor layer 7 may be realized. As described above, the thickness of the n-type semiconductor layer 7 is preferably 4.5 μm or less, more preferably 4 μm or less, and even more preferably 3.5 μm or less.

  In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 7 has been described. However, Ge, S, Se, Sn, Te, or the like can be used as the n-type impurity in addition to Si. .

  Next, an active layer 9 is formed on the n-type semiconductor layer 7. A specific method for forming the active layer 9 is, for example, as follows.

  First, the furnace pressure of the MOCVD apparatus is 100 kPa, and the furnace temperature is 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, an active layer 9 in which a light-emitting layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm are stacked for 15 periods is formed into an n-type semiconductor layer. 7 is formed on the upper layer.

  When the wavelength of light emitted from the active layer 9 is 410 nm or less, the In composition ratio of InGaN constituting the light emitting layer is preferably 10% or less. In this case, the Al composition ratio of GaN or AlGaN constituting the barrier layer is preferably 0% to 15%, more preferably 2% to 13%, and more preferably 5% to 10%. Is even more preferred.

  Next, the p-type semiconductor layer 11 is formed on the active layer 9. A specific method for forming the p-type semiconductor layer 11 is, for example, as follows.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (Cp ₂ Mg) is fed into the processing furnace for 60 seconds. Thereby, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 33. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 11 is formed by these hole supply layers.

After this step, the supply of TMA is stopped, the flow rate of Cp ₂ Mg is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds, so that the thickness is about 5 nm and the p-type impurity concentration is increased. However, a p-type semiconductor layer 11 having a p-type GaN layer of about 1 × 10 ²⁰ / cm ³ may be realized.

  In the above description, the case where Mg is used as the p-type impurity contained in the p-type semiconductor layer 11 has been described. However, Be, Zn, C, or the like can be used in addition to Mg as the p-type impurity.

  Step S2 corresponds to step (b). In the step S2, in the region having the defect concentration portion 41 as a base, a crystal grows with a defect. That is, after the completion of the step (b), the semiconductor layer 5 (7, 9) located in a region facing the defect concentration portion 41 (hereinafter referred to as “specific region 42”) in the direction orthogonal to the surface of the growth substrate 25. 11) has a lower crystal quality than the other regions.

  As shown in FIG. 2B, when a plurality of defect concentration portions 41 are discretely arranged in the X direction and the Y direction, after the completion of the step (b), the inside of the semiconductor layer 5 (7, 9, 11). Similarly, a plurality of semiconductor layers 5 (7, 9, 11) located in the “specific region 42” are discretely formed in the X direction and the Y direction.

(Step S3)
An activation process is performed on the wafer obtained in step S2. As a specific example, an activation process is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) apparatus.

(Step S4)
Next, as shown in FIG. 2D, the second electrode 13 is formed at a predetermined location on the upper surface of the p-type semiconductor layer 11. A specific method for forming the second electrode 13 is, for example, as follows.

  Using a sputtering apparatus, a 0.7 nm thick Ni film and a 150 nm thick Ag film are formed on the upper surface of a predetermined region of the p-type semiconductor layer 11. Thereafter, contact annealing is performed at 400 ° C. for 2 minutes in a dry air atmosphere using an RTA apparatus. In addition, as a material of the 2nd electrode 13, the 2nd electrode 13 can also be formed with Al, Rh, an alloy of Ag, Pd, and Cu other than the alloy of Ni and Ag.

  Here, in the present embodiment, the second electrode 13 is formed on the upper surface of the p-type semiconductor layer 11 excluding at least the specific region 42.

(Step S5)
As shown in FIG. 2E, an insulating layer 24 is formed in a predetermined region of the exposed upper surface of the p-type semiconductor layer 11 and the upper surface of the second electrode 13. The insulating layer 24 is formed, for example, by depositing SiO ₂ , SiN, Zr ₂ O ₃ , AlN, Al ₂ O ₃ or the like by a sputtering method or the like.

  By this step S5, the insulating layer 24 is formed on the upper surface of the p-type semiconductor layer 11 in at least the specific region 42. The insulating layer 24 is formed in a region to be etched for element isolation at least in the subsequent step S11.

  In the example of the present embodiment, the insulating layer 24 is formed at a position facing the Z direction with respect to a region where the first electrode 15 is to be formed in the subsequent step S12. However, this aspect is arbitrary.

  Step S5 corresponds to step (c).

(Step S6)
As shown in FIG. 2F, the protective layer 17 is formed on the entire upper surface of the second electrode 13 and the insulating layer 24, and the bonding layer 19 is formed on the upper surface of the protective layer 17. Whether or not the protective layer 17 is provided is arbitrary.

  The protective layer 17 is formed, for example, by depositing Ni with a thickness of 80 nm, Ti with a thickness of 100 nm, and Pt with a thickness of 200 nm using an electron beam evaporation apparatus (EB apparatus). In addition to Ti / Ti / Pt, TiW / Pt or the like can be used as the material for the protective layer 17.

  Thereafter, Ti having a film thickness of 10 nm is vapor-deposited on the upper surface of the protective layer 17, and Au—Sn solder composed of Au 80% Sn 20% is vapor-deposited with a film thickness of 3 μm, thereby forming the bonding layer 19. As the bonding layer 19, in addition to Au—Sn solder, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like can be used.

(Step S7)
As shown in FIG. 2G, the protective layer 23 and the bonding layer 21 are formed on the upper surface of the support substrate 3 prepared separately from the growth substrate 25. As the support substrate 3, as described above, a conductive substrate such as CuW, W, and Mo, or a semiconductor substrate such as Si can be used. The protective layer 23 can be formed in the same manner as the protective layer 17, and the bonding layer 21 can be formed in the same manner as the bonding layer 19. Whether or not the protective layer 23 is provided is arbitrary.

(Step S8)
As shown in FIG. 2H, the bonding layer 19 formed on the growth substrate 25 and the bonding layer 21 formed on the support substrate 3 are bonded together to bond the growth substrate 25 and the support substrate 3 together. Do. As a specific example, the bonding process is performed at a temperature of 280 ° C. and a pressure of 0.2 MPa.

  By this step, the bonding layer 19 and the bonding layer 21 are melted and bonded to form a structure in which the support substrate 3 and the growth substrate 25 are bonded to the front and back surfaces. That is, the bonding layer 19 and the bonding layer 21 may be integrated after this step. And since the protective layer 23 and the protective layer 17 are formed in the stage before execution of this step S8, the spreading | diffusion of the constituent material of a joining layer (19, 21) is suppressed.

  This step S8 corresponds to the step (d).

(Step S9)
As shown in FIG. 2I, the wafer on which step S8 has been completed is immersed in a predetermined solution 50. In this embodiment, the solution 50 may be any material that can dissolve SiO ₂ contained in the base substrate 26 and the intermediate layer 27, and for example, hydrofluoric acid can be used.

  By this step S9, the solution 50 permeates into the intermediate layer 27 and the base substrate 26 and dissolves a part thereof, whereby the base substrate 26 is separated from the support substrate 3 side. Note that a part of the GaN layer 28 remains on the upper surface of the n-type semiconductor layer 7 when step S9 is completed.

  Note that the base substrate 26 may be polished to reduce the thickness of the base substrate 26 before the execution of step S9. As an example, the base substrate 26 may be polished by mechanical polishing using diamond slurry so that the thickness becomes 100 μm or less. Thereby, the base substrate 26 can be peeled off in a short time in step S9.

(Step S10)
As shown in FIG. 2J, the remaining GaN layer 28 is removed by dry etching using, for example, an ICP apparatus. Thereby, the n-type semiconductor layer 7 is exposed.

  Steps S9 to S10 correspond to the step (e).

(Step S11)
As shown in FIG. 2K, adjacent element portions 45 are separated from each other. Specifically, the semiconductor layer 5 is etched using the ICP device until the upper surface of the insulating layer 24 is exposed at the boundary region between the adjacent element portions 45. At this time, the insulating layer 24 functions as an etching stopper layer. In FIG. 2K, the side surface of the semiconductor layer 5 is illustrated so as to be inclined with respect to the vertical direction, but this is an example, and the present invention is not limited to such a shape.

  In this step S11, the semiconductor layer 5 located in the “specific region 42” is removed by etching. That is, each element portion 45 remaining after step S11 is completed includes only the semiconductor layer 5 having a high crystal quality.

  FIG. 2L is a plan view showing the image of step S11. As described above with reference to FIG. 2B, in the example of this embodiment, the plurality of crystal defect portions 41 are arranged separately in the X direction and the Y direction. For this reason, the “specific regions 42” located above the crystal defect portions 41 are also arranged at a plurality of locations separated in the X direction and the Y direction.

  In this step S11, the semiconductor layer 5 in the specific region 42 is removed by etching the semiconductor layer 5 along the X direction and the Y direction. At this time, the etching width d <b> 2 is made wider than the outer diameter of the specific region 42.

  Here, if the interval between adjacent “specific regions” 42 is d1, the side length of the element portion 45 is shorter than d1. An interval d1 between adjacent “specific regions” 42 is a value that is substantially close to the interval between adjacent defect concentration portions 41 provided in the growth substrate 25. That is, in the aspect of the present embodiment, the size of the element portion 45 depends on the interval between the defect concentration portions 41 provided in the growth substrate 25.

  This step S11 corresponds to the step (f1).

(Step S12)
As shown in FIG. 2M, the constituent material of the first electrode 15 is formed at a predetermined position on the upper surface of the n-type semiconductor layer 7. Specifically, a conductive material made of, for example, Ni / Al / Ni / Ti / Au is deposited by an electron beam deposition apparatus, for example, with a film thickness of about 3 μm.

  In the example of this embodiment, the first electrode 15 is formed at a position facing the insulating layer 24 in the Z direction.

(Step S13)
As shown in FIG. 2N, the wafer is divided into chips. As a specific example, each element is separated by, for example, a laser dicing apparatus.

  Thereafter, the back surface of the support substrate 3 is joined to the package with, for example, Ag paste, and the current supply line 14 is connected to the current supply unit 15a. For example, wire bonding is performed by connecting a current supply line 14 made of Au to a current supply unit 15a having a diameter of 100 μm with a load of 50 g. Thereby, the light emitting element 1 shown to FIG. 1A-FIG. 1B is formed.

  According to the above method, the semiconductor layer 5 in the specific region 42 having a crystal quality lower than that of the surrounding area is removed at the time of element isolation according to step S11. As a result, each element portion 45 is formed of the semiconductor layer 5 with high crystal quality, and thus the light emitting element 1 exhibiting high light emission efficiency is realized. Further, since it can be manufactured using the growth substrate 25 having the defect concentration portion 41 in a plurality of regions arranged in a dispersed manner, an extremely high quality GaN substrate having no such defect concentration portion 41 is used as the growth substrate. The light-emitting element 1 can be manufactured at a lower cost than in the case of.

<Another Example>
In step S5, the insulating layer 24 may be formed as shown in FIG. 3A. In this example, the insulating layer 24 is formed only in a region to be subjected to element isolation in step S11. FIG. 3A shows an example in which the second electrode 13 is formed in a region other than the region where the first electrode 15 is scheduled to be formed in the subsequent step S12 in step S4.

  Thereafter, as shown in FIG. 3B, a current blocking layer 13 a is formed on the exposed upper surface of the p-type semiconductor layer 11 and the upper surface of the second electrode 13. As an example, the current blocking layer 13 a is made of a highly reflective metal material similar to that of the second electrode 13. However, unlike step S4, the annealing process is not performed, or the annealing process is performed at an extremely low temperature as compared with step S4. Thereby, ohmic contact is not realized at the interface between the current blocking layer 13a and the p-type semiconductor layer 11, and the same action as that of the insulating layer is exhibited. This performs the same function as the insulating layer 24 formed at a position facing the first electrode 15 in the Z direction in the light emitting element 1 shown in FIG. However, the second electrode 13 may be formed on the entire upper surface of the exposed p-type semiconductor layer 11 without providing the current blocking layer 13a.

[Second Embodiment]
The second embodiment of the present invention will be described with reference to the drawings, with respect to differences from the first embodiment.

(First example)
A first example of the second embodiment will be described.

<Construction>
In the second embodiment, unlike the first embodiment, the semiconductor layer 5 included in the light emitting element 1 includes the semiconductor layer 5 located in the specific region 42. FIG. 4 is a cross-sectional view schematically showing the configuration of the light-emitting element 1 of the first example of the second embodiment. In FIG. 4, for the convenience of illustration, the number of first electrodes 15 formed is reduced, but the first electrode 15 may be formed in the same manner as in the embodiment shown in FIGS. 2A and 2B. Absent.

  As shown in FIG. 4, the light emitting element 1 after being separated as the element unit 45 includes the semiconductor layer 5 including a specific region 42 whose crystal quality is lower than that of the surrounding area. However, the insulating layer 24 is formed so as to be in contact with the p-type semiconductor layer 11 located in the specific region 42. As a result, even if a voltage is applied between the first electrode 15 and the second electrode 13, the presence of the insulating layer 24 makes it difficult for current to flow in the specific region 42, and the semiconductor layer excluding the specific region 42 An electric current flows through 5. As a result, since a current flows in the semiconductor layer 5 with high crystal quality, the light emitting element 1 with high luminous efficiency in the active layer 9 and high luminance is realized.

<Production method>
Hereinafter, the manufacturing method of the light emitting element 1 of the first example of the second embodiment will be described.

(Steps S1 to S3)
Similar to the first embodiment, the steps S1 to S3 are executed (see FIG. 5A). As a result, the semiconductor layer 5 (7, 9, 11) is formed on the growth substrate 25 with the specific region 42 having a crystal quality lower than that of the surrounding area.

(Step S21)
As shown in FIG. 5B, the insulating layer 24 is formed on the upper surface of the p-type semiconductor layer 11 located at least in the specific region 42 among the upper surface of the p-type semiconductor layer 11. This step S21 corresponds to the step (c).

(Step S22)
As shown in FIG. 5C, the second electrode 13 is formed on the exposed upper surface of the p-type semiconductor layer 11. As described above in the first embodiment, the insulating layer 24 or the current blocking layer 13a is formed at a position facing the Z direction with respect to a region where the first electrode 15 is to be formed in the subsequent step S12. It doesn't matter.

(Steps S6 to S10)
Steps S6 to S10 are executed as in the first embodiment (see FIG. 5D).

(Step S23)
Similar to step S11, adjacent element portions 45 are separated from each other. Specifically, the semiconductor layer 5 is etched using the ICP device until the upper surface of the insulating layer 24 is exposed at the boundary region between the adjacent element portions 45. At this time, as shown in FIG. 5E, the insulating layer 24 located at the end of the element portion 45 functions as an etching stopper layer.

  FIG. 5F shows the image of step S23 in a plan view following FIG. 2L. FIG. 5F also illustrates the case where “specific regions 42” located above the crystal defect portion 41 are arranged at a plurality of locations apart in the X direction and the Y direction.

  In the aspect of FIG. 5E, the semiconductor layer 5 in a part of the specific region 42 is removed in the element isolation step according to step S23, but the semiconductor layer in the specific region 42 even after the end of step S23. It is shown that 5 remains. That is, each element unit 45 includes the semiconductor layer 5 located in the “specific region 42”.

  This step S23 corresponds to the step (f2).

(Steps S12 to S13)
Then, the light emitting element 1 is implement | achieved through steps S12-S13.

  As described above, since the insulating layer 24 is formed in contact with the p-type semiconductor layer 13 in the specific region 42, current does not easily flow through the semiconductor layer 5 in the specific region 42. Therefore, a current flowing in the semiconductor layer 5 having a high crystal quality contributes to most of light emission, so that a light emitting element with high light emission efficiency is realized.

  According to the present embodiment, the size of the side of the element unit 45 is set to be larger than the interval d1 between two adjacent specific regions 42, that is, the interval between adjacent defect concentration portions 41 provided in the growth substrate 25. Can be bigger. That is, in the aspect of this embodiment, the light-emitting element 1 having a larger chip size can be realized as compared with the case of the first embodiment, and an element with high luminance is realized.

(Second example)
A second example of the second embodiment will be described. The following examples can be appropriately combined with each other.

  Also in the configuration of the second embodiment, as in FIG. 2B, the plurality of defect concentration portions 41 are arranged in alignment in the X direction and the Y direction. In this case, the defect density is likely to be higher than the surrounding area not only in the region where the defect concentration portion 41 exists but also on the line connecting the adjacent defect concentration portions 41.

  That is, in the example of FIG. 5D, a linear region connecting a plurality of “specific regions 42” arranged in the X direction and a linear region connecting a plurality of “specific regions 42” arranged in the Y direction. In, the crystal quality of the semiconductor layer 5 tends to be lower than in the surrounding region.

  Therefore, the p-type semiconductor layer 24 formed in contact with the p-type semiconductor layer 11 in the specific region 42 remaining in the element portion 45 is continuously or intermittently along the arrangement direction of the specific region 42. It does not matter as a structure which extends | stretches. FIG. 6 corresponds to a cross-sectional view taken along line X2-X2 or Y2-Y2 in FIG. 5F at the end of step S23 under such a configuration. The X2-X2 line is a line segment that passes through the specific region 42 and is parallel to the X axis. The Y2-Y2 line is a line segment that passes through the specific region 42 and is parallel to the Y axis. Under this configuration, FIG. 5E corresponds to a cross-sectional view taken along line X3-X3 or Y3-Y3 in FIG. 5F. The X3-X3 line is a line segment that does not pass through the specific region 42 and is parallel to the X axis. The Y3-Y3 line is a line segment that does not pass through the specific region 42 and is parallel to the Y axis.

  (Third Example) In the second embodiment, the light emitting device 1 can be manufactured by the following method.

(Step S31)
After execution of steps S1 to S3, as shown in FIG. 7A, a part of the semiconductor layer 5 in the specific region 42 is etched from the p-type semiconductor layer 11 side to form the first groove 61. At this time, it is preferable to perform etching until at least the upper surface of the n-type semiconductor layer 7 located in the specific region 42 is exposed.

  Of the specific region 42, the region to be etched in the element isolation step according to step S23 may not be etched in step S31.

  This step S31 corresponds to the step (g).

(Step S21)
Next, the insulating layer 24 is formed similarly to step S21 mentioned above (refer FIG. 7B). At this time, the insulating layer 24 is formed so as to cover at least the inner surface of the first groove 61. By this step S21, the insulating layer 24 is formed so as to be in contact with the semiconductor layer 5 in the specific region 42.

(Step S22)
Next, as in step S22 described above, the second electrode 13 is formed on the exposed upper surface of the p-type semiconductor layer 11 (see FIG. 7C). At this time, it is preferable to form the second electrode 13 also on the upper surface of the insulating layer 24 formed in the first groove 61 as shown in FIG. 7C. Thereby, a high reflectance can be further ensured.

(Subsequent steps)
Hereinafter, as described above, the light-emitting element 1 is realized through steps S6 to S10, step S23, and steps S12 to S13. FIG. 7D is a schematic cross-sectional view of the light-emitting element 1 at the time when the element isolation process according to Step S23 is completed.

  Note that the third example may be combined with the second example.

  (Fourth Example) In the second embodiment, in the element isolation step according to step S23, all of the semiconductor layer 5 located in the specific region 42 may not be etched. FIG. 8 is a plan view of the image of step S23 in the fourth example, following FIG. 2L.

  Even in such a mode, as described above, the semiconductor layer 5 in the specific region 42 is in contact with the insulating layer 24, so that the current hardly flows through the semiconductor layer 5 in the specific region 42. It has been realized.

  (Fifth Example) A fifth example of the second embodiment will be described with reference to the drawings, centering on points different from the contents described above.

<Construction>
In the fifth example, as in the first example to the fourth example, the specific region 42 remains in the semiconductor layer 5 included in the light emitting element 1. FIG. 9 is a cross-sectional view schematically showing the configuration of the light-emitting element 1 of the fifth example. In FIG. 9, as in FIG. 4, the number of first electrodes 15 is reduced for the sake of illustration, but the first electrode 15 is formed in the same manner as in the embodiment shown in FIGS. 2A and 2B. It doesn't matter as it is.

  As shown in FIG. 9, the light emitting element 1 after being separated as the element unit 45 includes the semiconductor layer 5 including a specific region 42 whose crystal quality is lower than that of the surrounding area. However, the insulating layer 24 is formed so as to be in contact with the n-type semiconductor layer 7 located in the specific region 42. As a result, even if a voltage is applied between the first electrode 15 and the second electrode 13, the presence of the insulating layer 24 makes it difficult for current to flow in the specific region 42, and most current is specified. Flows in the semiconductor layer 5 except for the region 42. As a result, since a current flows in the semiconductor layer 5 with high crystal quality, the light emitting element 1 with high luminous efficiency in the active layer 9 and high luminance is realized.

<Production method>
Hereinafter, the manufacturing method of the light emitting element of the 5th example of 2nd embodiment is demonstrated.

(Steps S1 to S3)
Similar to the first embodiment, the steps S1 to S3 are executed. As a result, the semiconductor layer 5 (7, 9, 11) is formed on the growth substrate 25 with the specific region 42 having a crystal quality lower than that of the surrounding area.

(Steps S4 to S5)
Similarly to the first embodiment, the processes of steps S4 to S5 are executed (see FIG. 10A). In step S5, the insulating layer 24 may be formed only in the etching target region for performing element isolation in at least the subsequent step S11 on the upper surface of the p-type semiconductor layer 11. As described above in the first embodiment, the insulating layer 24 or the current blocking layer 13a is formed at a position facing the Z direction with respect to a region where the first electrode 15 is to be formed in the subsequent step S12. It doesn't matter.

(Steps S6 to S10)
Similar to the first embodiment, the processes of steps S6 to S10 are executed (see FIG. 10B). After execution of step S10, the upper surface of the n-type semiconductor layer 7 including the specific region 42 is exposed.

(Step S31)
As shown in FIG. 10C, adjacent element portions 45 are separated from each other. Specifically, the semiconductor layer 5 is etched using the ICP device until the upper surface of the insulating layer 24 is exposed at the boundary region between the adjacent element portions 45. At this time, the insulating layer 24 functions as an etching stopper layer.

  In step S31, a part of the semiconductor layer 5 including the specific region 42 is etched to form the second groove 62. At this time, at least the n-type semiconductor layer 7 located in the specific region 42 is etched.

  This step S31 corresponds to the step (i) and the step (f2). In addition, although the case where the process of forming the 2nd groove part 62 and the process of element isolation were performed simultaneously was demonstrated here, you may carry out separately.

(Step S32)
As shown in FIG. 10D, the insulating layer 24 is formed on the upper surface of the n-type semiconductor layer 7 so as to cover at least the inner surface of the second groove 62. By this step S32, the insulating layer 24 is formed so as to be in contact with the semiconductor layer 5 in the specific region 42. This step S32 corresponds to the step (c).

(Steps S12 to S13)
Similarly to the first embodiment, the light emitting element 1 shown in FIG. 9 is realized by executing the steps S12 to S13.

  As described above, since the insulating layer 24 is formed in contact with the n-type semiconductor layer 7 in the specific region 42, current does not easily flow through the semiconductor layer 5 in the specific region 42. Therefore, a current flowing in the semiconductor layer 5 having a high crystal quality contributes to most of light emission, so that a light emitting element with high light emission efficiency is realized.

  According to the fifth example, as in the first example, the size of the side of the element portion 45 is set to the distance d1 between two adjacent specific regions 42, that is, adjacent to the growth substrate 25. It is possible to make it larger than the interval between the defect concentration portions 41 to be made. That is, in the aspect of the second embodiment, the light-emitting element 1 having a large chip size can be realized as compared with the case of the first embodiment, and an element with high luminance is realized.

  The light emitting element 1 may be manufactured by combining the fifth example described above and the first to fourth examples. That is, the insulating layer 24 that contacts the p-type semiconductor layer 13 may be provided in the specific region 42, and the insulating layer 24 formed so as to cover the inner surface of the second groove portion 62 may be provided.

  In the fifth example, in step S31, the second groove 62 may be formed to extend in one or both of the X direction and the Y direction.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> In the embodiment described above, the side close to the substrate 3 among the layers constituting the semiconductor layer 5 is described as the p-type semiconductor layer 11 and the side far from the substrate 3 is described as the n-type semiconductor layer 7. The conductivity type may be reversed.

<2> In the above embodiment, the growth substrate 25 is described as having the GaN layer 28 formed on the upper surface of the base substrate 26 made of mullite via the intermediate layer 27 made of SiO ₂ . However, in the present invention, regardless of the material of the base substrate 26 and the intermediate layer 27, the GaN layer 28 that is generally cut out from the free-standing GaN substrate and has a good film quality in a region excluding the defect concentration portion 41 is formed on the outermost surface. This includes contents for manufacturing a semiconductor light emitting device by growing a semiconductor layer on the upper surface of the substrate (GaN template substrate).

1: Semiconductor light emitting element 3: Support substrate 5: Semiconductor layer 7: n-type semiconductor layer 9: active layer 11: p-type semiconductor layer 13: second electrode 13 a: current blocking layer 14: current supply line 15: first electrode 15 a : Current supply unit 17: Protection layer 19: Bonding layer 20: Conductive layer 21: Bonding layer 23: Protection layer 24: Insulating layer 25: Growth substrate 26: Underlying substrate 27: Intermediate layer 28: GaN layer 41: Defect concentration portion 42 : Specific area 45: Element part 50: Solution 61: First groove part 62: Second groove part

Claims (18)

A step of preparing a growth substrate, in which a GaN layer having a defect concentration portion having a defect density higher than that of a region other than the plurality of regions is formed in an upper layer of a base substrate in a plurality of regions arranged in a dispersed manner ( a) and
Forming a semiconductor layer including an n-type or p-type first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type different from the first conductivity type, on the growth substrate (b) When,
When the step (b) is completed, an insulating layer is formed on the semiconductor layer located in a specific region, which is a region facing the defect concentration portion in a direction orthogonal to the plane of the growth substrate. A method for manufacturing a semiconductor light emitting device, comprising the step (c). The step (c) is a step of forming the insulating layer on the second semiconductor layer located in the specific region,
After the step (c), a step (d) of attaching a support substrate different from the growth substrate to the upper layer of the second semiconductor layer;
After the step (d), the step (e) of peeling the growth substrate and exposing the first semiconductor layer;
The semiconductor layer located in the specific region remains by etching from the first semiconductor layer side until the insulating layer is exposed with respect to the semiconductor layer located in the specific region. 2. The method of manufacturing a semiconductor light-emitting element according to claim 1, further comprising a step (f <b> 1) of performing element isolation so as not to occur. A plurality of the defect concentration portions are arranged along a predetermined first direction when viewed from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction,
The method of manufacturing a semiconductor light emitting element according to claim 2, wherein the step (f1) is a step of performing element isolation along the first direction. A plurality of the defect concentration portions are disposed along a predetermined second direction different from the first direction as seen from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction and the second direction,
4. The method of manufacturing a semiconductor light emitting element according to claim 3, wherein the step (f1) is a step of performing element isolation along the first direction and the second direction. The step (c) is a step of forming the insulating layer on the second semiconductor layer located in the specific region,
After the step (c), a step (d) of attaching a support substrate different from the growth substrate to the upper layer of the second semiconductor layer;
After the step (d), the step (e) of peeling the growth substrate and exposing the first semiconductor layer;
(F2) performing element isolation so that at least a part of the semiconductor layer located in the specific region remains by etching the semiconductor layer from the first semiconductor layer side. Have
The insulating layer is formed in contact with the semiconductor layer located in the specific region among the remaining semiconductor layers after the step (f2) is performed. Item 12. A method for manufacturing a semiconductor light emitting device according to Item 1. A plurality of the defect concentration portions are arranged along a predetermined first direction when viewed from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction,
After the execution of the step (f2), the insulating layer is in contact with the semiconductor layer located in the specific region among the remaining semiconductor layers and continuously along the first direction. 6. The method of manufacturing a semiconductor light emitting device according to claim 5, wherein the method is formed intermittently or intermittently. A plurality of the defect concentration portions are disposed along a predetermined second direction different from the first direction as seen from a direction orthogonal to the surface of the growth substrate,
The step (c) is a step of forming the insulating layer continuously or intermittently along the first direction and the second direction,
After execution of the step (f2), the insulating layer is in contact with the semiconductor layer located in the specific region among the remaining semiconductor layers, and in the first direction and the second direction. The method of manufacturing a semiconductor light emitting element according to claim 6, wherein the semiconductor light emitting element is formed continuously or intermittently along the direction. The step (f2) is a step of etching from the first semiconductor layer side until the insulating layer is exposed to a part of the semiconductor layer located in the specific region,
8. The semiconductor layer according to claim 5, wherein the semiconductor layer remains in a region sandwiched between the insulating layers when viewed from a direction orthogonal to the surface of the support substrate after the execution of the step (f2). The manufacturing method of the semiconductor light-emitting device of any one of Claims 1. After the step (b), at least the first semiconductor layer from the second semiconductor layer side in the region facing the defect concentration portion in the direction perpendicular to the surface of the growth substrate in the semiconductor layer. Etching until exposed to form a first groove (g),
The step (c) is performed after the step (g), and is a step of forming the insulating layer so as to cover at least the inner surface of the first groove portion. A method for producing a semiconductor light-emitting device according to claim 1.   The method further comprises a step (h) of forming a reflective electrode material so as to cover the upper surfaces of the second semiconductor layer and the insulating layer after the step (c) and before the step (d). Item 10. A method for producing a semiconductor light-emitting device according to Item 9. After the step (d), the step (e) of peeling the growth substrate and exposing the first semiconductor layer;
Etching the first semiconductor layer located in the specific region to form a second groove (i),
The said process (c) is a process performed after the said process (i), and is a process of forming the said insulating layer so that at least the inner surface of a said 2nd groove part may be covered. A method for producing a semiconductor light-emitting device according to claim 1.   The method for manufacturing a semiconductor light-emitting element according to claim 1, wherein the base substrate is made of mullite. A support substrate;
A semiconductor layer including an n-type or p-type first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type different from the first conductivity type, formed on an upper layer of the support substrate;
A semiconductor light emitting device comprising: an insulating layer formed in contact with the first semiconductor layer or the second semiconductor layer in a specific region having a defect density higher than that of the semiconductor layer. element. A first groove provided in the specific region, from the second semiconductor layer side toward the first semiconductor layer side;
The semiconductor light emitting device according to claim 13, wherein the insulating layer is formed in contact with an inner surface of the first groove portion.   The semiconductor light emitting device according to claim 14, further comprising a reflective electrode formed on an upper layer of the second semiconductor layer and the insulating layer. A second groove provided in the specific region from the first semiconductor layer side toward the second semiconductor layer side;
The semiconductor light emitting element according to claim 13, wherein the insulating layer is formed in contact with an inner surface of the second groove portion.   The said insulating layer is arrange | positioned continuously or intermittently along predetermined | prescribed 1st direction seeing from the direction orthogonal to the surface of the said support substrate, The any one of Claims 13-16 characterized by the above-mentioned. 2. The semiconductor light emitting device according to item 1.   The said insulating layer is arrange | positioned continuously or intermittently along predetermined | prescribed 2nd direction different from said 1st direction seeing from the direction orthogonal to the surface of the said support substrate. Item 18. The semiconductor light emitting device according to Item 17.

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