JP2017104420A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of achieving an appropriate control.SOLUTION: A game machine has a main control board on which a game control computer is mounted. The game control computer includes a WDT 61 and a WDT clear circuit 62 for clearing timekeeping operation of the WDT 61. The WDT 61, when once started, then continues to execute the timekeeping operation without stopping. Start of the WDT 61 is performed immediately before the end of the initial setting. Then, the timing operation of the WDT 61 is cleared not only within the timer interrupt processing but also in a predetermined timing during initial setting.SELECTED DRAWING: Figure 5B

Description

  The present invention relates to a gaming machine having a watchdog timer as a main control means. This gaming machine includes, for example, a ball game machine, a revolving game machine, and the like.

2. Description of the Related Art Conventionally, a gaming machine including a watchdog timer is known to monitor the operation state of a main control CPU of a main control board that controls game control in an integrated manner (see, for example, Patent Document 1 below).
The watchdog timer performs a timekeeping operation. If a clear operation is performed during the timekeeping operation, the timekeeping value returns to the initial value, and the main control CPU is reset when the time-out period elapses without performing the clear operation.

  Once started, the watchdog timer mounted on the gaming machine described in Patent Document 1 continues to perform the timing operation as long as power supply continues. The watchdog timer is started at a predetermined timing after the execution of the program by the main control CPU and after the completion of a predetermined setting operation or the like.

JP 2014-87407 A

  In a gaming machine, the main control CPU may be reset due to the occurrence of noise or the like. When such a reset due to the occurrence of noise occurs after activation of the watchdog timer, the main control CPU executes the program again from the beginning. As described above, once the watchdog timer is started, the watchdog timer continues to execute the timing operation as long as the power supply continues. continuing. Therefore, after restarting the program execution, the time count by the watchdog timer times out and the watchdog timer resets the main control CPU. Even after resetting the main control CPU, the watchdog timer time-out and the reset of the main control CPU are repeated, and as a result, the gaming machine may not normally shift to normal operation, that is, appropriate control of the gaming machine. May not be possible.

  Therefore, an object of the present invention is to provide a gaming machine that can realize appropriate control.

  In order to achieve the above object, the invention according to claim 1 is a gaming machine comprising main control means for comprehensively controlling the progress of a game, wherein the main control means executes main control for executing a program. A CPU and a watchdog timer that starts a clocking operation upon activation and resets the main control CPU when the clocked value reaches a predetermined time-out value without being cleared, and after the main control CPU starts executing a program Further includes a watchdog timer starting means for starting the watchdog timer at a predetermined start timing, and a clearing means for clearing the timekeeping value of the watchdog timer, wherein the clearing means is a program executed by the main control CPU. At the timing before the start timing after the start of execution, the watchdog timer Including activation before clearing means for clearing the said counting value, to provide a gaming machine.

  The invention according to claim 2 further includes a timeout value setting means for setting the timeout value, and the watchdog timer starting means is realized by setting a predetermined timeout value in the timeout value setting means. The game machine according to claim 1, wherein the watchdog timer is not started when a specific value is set as the timeout value in the timeout value setting means.

The invention according to claim 3 is the gaming machine according to claim 2, wherein the timeout value is a predetermined value excluding zero, and the specific value is zero. .
The invention according to claim 4 further includes a timeout value setting means for setting the timeout value, and the timeout value setting means changes the set timeout value after activation of the watchdog timer. It is a gaming machine as described in any one of Claims 1-3 which cannot be performed.

  A fifth aspect of the present invention is the gaming machine according to any one of the first to fourth aspects, wherein the watchdog timer is configured to continue to be executed without being stopped after the watchdog timer is started once. It is.

  According to the present invention, a gaming machine capable of realizing appropriate control can be provided.

1 is a perspective view of a gaming machine according to an embodiment of the present invention. It is a front view which shows the structure of the game board contained in the said gaming machine. It is a block diagram which shows the electrical structure of the said gaming machine. It is a block diagram which shows the circuit structure of the game control microcomputer shown in FIG. It is a figure which shows the memory map of the game control microcomputer shown in FIG. FIG. 5 is a block diagram showing a configuration of a watchdog timer circuit shown in FIG. 4. It is a block diagram which shows the more detailed structure of the said watchdog timer circuit. FIG. 5B is a block diagram showing a more detailed configuration of the watchdog timer clear circuit shown in FIG. 5B. It is a figure which shows the content of the WDT control register shown in FIG. 5B, and the content of the WDT mode setting register. FIG. 4 is a flowchart showing the contents of a system reset process in the main control board shown in FIG. 3 (No. 1). It is a flowchart which shows the content of the system reset process in the said main control board (the 2). It is a flowchart which shows the flow of the timer interruption process by the said main control board. 10 is a flowchart showing a flow of a power supply abnormality check process shown in FIG. 9.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view of a gaming machine 1 according to an embodiment of the present invention. Hereinafter, the ball game machine (pachinko machine) will be described as an example of the game machine 1, but the present invention is not limited to the ball game machine, and other types such as a revolving type game machine represented by a pachislot machine. It can also be applied to gaming machines.
The gaming machine 1 includes a substantially square frame-shaped outer frame 2 for mounting (installation) on a game island arranged in a game store, and an inner frame 3 attached to the outer frame 2 so as to be able to be opened one by one. ing. A hinge 4 is attached to one of the left and right sides of the outer frame 2, for example, the left side, and the inner frame 3 is held so as to be rotatable around a rotation axis of the hinge 4.

  A game board 5 (see FIG. 2) is accommodated and held in the upper part of the inner frame 3. A launching device (not shown) is accommodated and held in the lower part of the inner frame 3. A safe ball recovery unit (not shown) is disposed below the game board 5 in the inner frame 3. A front door 6 is provided on the front side of the inner frame 3 so as to be openable and closable. A lower opening / closing plate 7 is provided on the front side of the inner frame 3 below the front door 6 so as to be opened and closed. The front door 6 is formed with a substantially circular opening 8 at a position facing the game board 5. A transparent plate 9 such as a glass plate is fitted in the opening 8 so that the game board 5 on the back side of the transparent plate 9 can be visually recognized through the transparent plate 9 with the front door 6 closed. Yes. A pair of left and right speakers 12 are disposed on the upper portion of the front door 6. In addition, a pair of left and right game lamps 13 is disposed at the lower part of the front door 6.

  On the lower opening / closing plate 7, an upper plate 10 for storing game balls used for a game and a lower plate 11 for receiving game balls overflowing from the upper plate 10 through an overflow path (not shown) are arranged vertically. Is provided. On the right side of the lower plate 11, a handle 14 that is operated when a game ball is launched into the game board 5 is disposed. A player can launch a game ball from the launching device toward the board surface of the game board 5 by gripping and rotating the handle 14, and by adjusting the rotation angle of the handle 14, It is possible to adjust the momentum of the game ball that is launched toward the surface of the game board 5.

FIG. 2 is a front view showing the configuration of the game board 5 included in the gaming machine 1.
On the board surface (front surface) of the game board 5, a substantially circular circular region R is set at the center. On the periphery of the circular region R, a substantially arc-shaped guide rail 15 for guiding a game ball fired from the launching device to the upper part (left upper part) of the circular region R, and an inner rail 16 extending opposite to the guide rail 15 And are arranged. A liquid crystal display unit 17 is disposed in the center of the circular region R. The liquid crystal display unit 17 displays a stopped effect symbol, a changing effect symbol, a predetermined message, or the like in a game on the gaming machine 1.

The tip of the inner rail 16 extends to the upper part of the circular area R, and the game ball launched by the launching device passes between the guide rail 15 and the inner rail 16 to the upper part of the circular area R (game area S). It is guided. A large number of obstacle nails 18 (only part of which are shown in FIG. 2) are planted in the game area S.
In the game area S, a first special symbol start port 19 is disposed below the liquid crystal display unit 17 (lower part of the game area S). The first special symbol starting port 19 is provided so that a game ball flowing down the circular region R can enter. The first special symbol starting port 19 is a non-variable winning port (a so-called navel winning port) having no opening / closing means. In accordance with the winning of one game ball in the first special symbol starting port 19, a predetermined number (for example, three balls) of winning balls are paid out from the winning ball payout device 20 (see FIG. 3). A special symbol lottery for determining whether or not the special profit state is a big hit is executed in accordance with the winning of the game ball in the first special symbol start port 19.

  Below the first special symbol start port 19, a second special symbol start port 21 is arranged side by side with the first special symbol start port 19. The second special symbol start opening 21 is a variable winning opening having an opening / closing means 22 such as an electric tulip accessory. In accordance with the winning of one game ball in the second special symbol starting port 21, a predetermined number (for example, five balls) of prize balls are paid out from the prize ball payout device 20 (see FIG. 3). A special symbol lottery for determining whether or not the special profit state is a big hit is executed in accordance with the winning of the game ball to the second special symbol start opening 21.

  In the game area S, a variable winning device 23 is arranged in the lower right part of the game board 5. The variable winning device 23 is disposed, for example, on the right side of the first and second special symbol start ports 19 and 21. The variable prize-winning device 23 includes a special prize-winning port 24 that is arranged in the lower right portion of the game area S and has a rectangular shape in plan view that is long on the left and right sides, and a special prize-winning opening / closing accessory 25 for opening and closing the special prize-winning port 24. Prepare. In other words, the special winning opening 24 is a variable winning opening, and is provided in a size that allows a plurality of (for example, 3 to 4) game balls to enter simultaneously in the left-right direction.

In the game area S, a normal symbol gate 26 through which a game ball flowing down along the surface of the game board 5 can pass is arranged on the right side of the liquid crystal display unit 17 (right part of the game area S). When the game ball passes through the normal symbol gate 26, a normal symbol lottery for determining whether to open the second special symbol start port 21 (whether to open / close the opening / closing means 22) is executed.
In the special profit state, the special prize opening 24 is kept until a predetermined time (for example, 30 (sec)) elapses or until a predetermined number of game balls (for example, 10 balls) enter the special prize opening 24 in advance. Such an opening operation such as opening is performed as one round game, and such an opening operation is performed up to the upper limit of the number of rounds (for example, a maximum of 13 rounds) across the interval.

A first special symbol display means 27, a second special symbol display means 28, and a normal symbol display means 29 are arranged in a predetermined area (for example, the upper right corner) outside the guide rail 15 on the board surface of the game board 5.
The 1st special symbol display means 27 is comprised by the 7 segment type display etc. which can carry out the variable operation | movement of one or several special symbols. The first special symbol display means 27 moves the first special symbol for a predetermined time to enter the first special symbol start port 19 on condition that a game ball enters the first special symbol start port 19. When the big hit determination random number acquired at the time of sphere coincides with a predetermined big hit value, it stops at a predetermined special symbol for big hit, and in other cases it stops with a special symbol for losing.

  The second special symbol display means 28 is composed of a seven-segment display or the like that can perform variable operation of one or more special symbols. The second special symbol display means 28 moves the second special symbol for a predetermined time on the condition that a game ball enters the second special symbol start port 21 and enters the second special symbol start port 21. When the jackpot determination random number acquired at the time of sphere coincides with a predetermined jackpot value, it stops with a special symbol for a predetermined jackpot, otherwise it stops with a special symbol for losing.

In addition, special symbol hold display means (not shown) for displaying the number of reserved balls of the first special symbol and / or the number of reserved balls of the second special symbol in the predetermined area (for example, the upper right corner), respectively. It may be provided.
The normal symbol display means 29 is for changing the normal symbol. The normal symbol display means 29 is provided as small as possible by using a 7-segment display or the like so that the game ball passes through the normal symbol gate 26. If the random number for hit determination obtained when the game ball passes through the normal symbol gate 26 matches the predetermined hit value when the normal symbol fluctuates for a predetermined time according to the condition, it does not match in a predetermined hit mode. In some cases, it is stopped in a predetermined disengagement mode. This normal symbol is preferably assigned a symbol that does not have a special meaning so that the player cannot easily determine the type of this normal symbol.

The result of the big hit lottery is displayed on the special symbol display means 27 and 28 as described above, but is displayed not only on the special symbol display means 27 and 28 but also on the liquid crystal display unit 17.
Specifically, during the special symbol changing operation of the special symbol display means 27 and 28, the liquid crystal display unit 17 performs the symbol changing operation of the effect symbol. Further, when the probability variation symbol is stopped and displayed on the first or second special symbol display means 27, 28, the jackpot effect symbol corresponding to the probability variation symbol is stopped and displayed. 2 When the non-stochastic variation symbol is stopped and displayed on the special symbol display means 27, 28, the jackpot effect symbol corresponding to the non-probability variation symbol is stopped and displayed.

  A game ball launched at a moderate momentum from a launching device (not shown) by a player's handle operation is released from the upper left part of the circular area R to the game area S diagonally upward to the right. Further, the target of the game ball can be shot between the upper left part of the game area S and the upper right part of the game area S by operating the handle. The game balls released to the game area S flow down between the obstacle nails 18 implanted in the game area S. Of the game balls flowing down along the board surface of the game board 5, any of the first and second special symbol starting ports 19 and 21, the variable winning device 23 (special winning port 24), and other winning ports (not shown) A game ball (out ball) that has not entered the ball enters the machine through an out port 30 formed in the lower part of the game area S and is collected by a ball collection unit (not shown).

The board surface configuration of the game board 5 shown in FIG. 2 is an example, and is not limited to this board surface, and various board surface configurations can be adopted.
FIG. 3 is a block diagram showing an electrical configuration of the gaming machine 1. The gaming machine 1 receives an AC voltage of 24V AC and outputs various DC voltages, a system reset signal SYS, and the like, a main control board (main control means) 32 that performs overall control of the game, and main control An effect control board 33 that performs effect control based on a control command CMD from the board 32, a liquid crystal control board 34 that drives the liquid crystal display unit 17 based on a control command CMD ′ from the effect control board 33, and a main control board 32 Based on the control command CMD ″ received from the payout control board 35 for driving the prize ball payout device 20 to pay out the game ball, and according to the turning operation of the player's handle 14 (see FIG. 1), And a firing control board 36 that drives a launching device (not shown) to launch a game ball. Each control board 32, 33, 34, 35, 36 is mounted with a one-chip microcomputer including, for example, a CPU, RAM and ROM.

  A power supply board 31 and a payout control board 35 are connected to the main control board 32 via a main board relay board 37. The main control board 32 is connected to the effect control board 33 and the liquid crystal control board 34 via the command relay board 38 and the effect interface board 39. The effect control board 33 and the liquid crystal control board 34 are connected to each other via an effect interface board 39. In addition, the power supply board 31 is connected to the effect interface board 39 via the power supply relay board 40.

  The main control board 32 is connected to various game components of the game board 5 (see FIG. 2) via the game board relay board 41. Then, the game board relay board 41 has a prize detection switch (for example, a big prize opening prize detection switch) for detecting the entrance of a game ball to various prize openings on the game board 5 (for example, the special prize opening 24 (see FIG. 2)). ), The driving mechanism (for example, solenoids) of the opening / closing means 22 (see FIG. 2) and the special prize opening opening / closing accessory 25 (see FIG. 2) is driven. The switch signal (start port switch signal) of the detection switch built in the special symbol start ports 19 and 21 is directly input to the main control board 32 without going through the game board relay board 41.

  A speaker 12 (see FIG. 1) and a game lamp 13 (see FIG. 1) are connected to the effect interface board 39 via a first frame relay board 43 and a second frame relay board 44. Further, a lamp board 45 for driving the lamp unit 50 arranged on the board surface of the game board 5 is connected to the effect interface board 39. A system reset signal SYS and a power supply voltage from the power supply board 31 are input to the liquid crystal control board 34 and the lamp board 45 via the effect interface board 39.

The payout control board 35 is connected to an external terminal board 46 for outputting a signal to the outside of the gaming machine 1. The external terminal board 46 is communicably connected to, for example, a hall computer (hall computer) in an amusement store.
Among the boards shown in FIG. 3, the payout control board 35, the launch control board 36, the power supply board 31, the second frame relay board 44 and the external terminal board 46 are frame side members attached to the inner frame 3 (FIG. 3). In FIG.

On the other hand, the main control board 32, the production control board 33, the liquid crystal control board 34, the production interface board 39, the lamp board 45, the main board relay board 37, the command relay board 38, the power relay board 40, and the first frame relay board 43. The game board relay board 41 is a board side member attached to the back of the game board 5.
The control command CMD output from the main control board 32 is given to the effect control board 33 via the command relay board 38 and the effect interface board 39. Based on the control command CMD from the main control board 32, the effect control board 33 turns on / off the game lamp 13 and the speaker 12 via the first frame relay board 43 and the second frame relay board 44 (see FIG. 2). Are further controlled, the specific contents of the effect of the liquid crystal display unit 17 are determined, and a control command CMD ′ describing the contents of the effect is transmitted to the liquid crystal control board 34.

The control command CMD ′ output from the effect control board 33 is given to the liquid crystal control board 34 via the effect interface board 39, and based on the control command CMD ′ (in this case, a command for liquid crystal control), the liquid crystal control board 34 controls the display of the liquid crystal display unit 17.
The control command CMD ″ output from the main control board 32 is given to the payout control board 35 via the main board relay board 37. The payout control board 35 controls the payout operation of the prize ball payout device 20 based on the control command CMD ″.

  The power supply board 31 is connected to the main board relay board 37 and the power supply relay board 40, respectively. The main board relay board 37 performs main control of the system reset signal SYS, the RAM clear signal DEL, the voltage abnormality signal ARM, the voltage drop signal DWN, the power supply voltage (DC12V, DC32V), and the backup power supply voltage BAK from the power supply board 31 as they are. Output to the substrate 32. Similarly, the power relay board 40 also outputs the system reset signal SYS received from the power board 31 and the AC and DC power supply voltages to the effect interface board 39 as they are. The effect interface board 39 gives the power supply voltage from the power supply board 31 and the system reset signal SYS to the effect control board 33.

The system reset signal SYS is a power reset signal indicating that the supply of AC power 24V to the power supply board 31 is started, and the microcomputer of each control board is reset by the system reset signal SYS.
The RAM clear signal DEL is a signal for determining whether to initialize the contents stored in the RAM of the microcomputer of the main control board 32 and the payout control board 35, respectively.

On the other hand, the payout control board 35 is directly connected to the power supply board 31 without a relay board. The payout control board 35 receives the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal DWN, and the backup power supply voltage BAK together with other power supply voltages on the power supply board 31.
The RAM clear signal DEL is a signal for determining whether or not to initialize all areas of a RAM (main control RAM 53 (see FIG. 4) described later) of the main control board 32 and a RAM of the payout control board 35. Each of the predetermined values is indicated in correspondence with on / off of a RAM clear switch (not shown) operated by a store clerk of the game shop.

  The voltage drop signal DWN is a signal indicating that the AC power supply 24V has started to drop, and is provided to the microcomputer input ports of the main control board 32 and the payout control board 35. Based on the input of the voltage drop signal DWN, in the main control board 32 and the payout control board 35, necessary data is saved in the RAM of the main control board 32 and the RAM of the payout control board 35, respectively.

  The microcomputer of the main control board 32 and the payout control board 35 is supplied with a backup power supply voltage BAK of DC 5V from the power supply board 31. Therefore, even after the AC power supply 24V is shut off due to a business end or power failure, the data in the RAM of the main control board 32 and the RAM of the payout control board 35 are retained. In the present embodiment, the storage contents of these RAMs are designed to be retained for at least several days.

  In response to receiving the voltage drop signal DWN, the main control board 32 and the payout control board 35 start necessary termination processing prior to a power failure or business termination. As a result, coupled with the effect of the power supply by the backup power supply voltage BAK described above, the main control board 32 and the payout control board 35 can be played immediately before the start of business or after the recovery from the power failure (or the game state before the power cut-off (or Operation).

  On the other hand, the effect control board 33 and the liquid crystal control board 34 are not provided with a power backup function. The system control signal SYS is commonly supplied to the effect control board 33 and the liquid crystal control board 34 via the power relay board 40 and the effect interface board 39. The power reset operation is realized at a timing substantially synchronized with the control board 32 and the payout control board 35.

FIG. 4 is a block diagram showing a circuit configuration of the main control board 32.
A game control microcomputer MC composed of a one-chip microcomputer is mounted on the main control board 32. The game control microcomputer MC includes a main control CPU 51 for executing a program in which a game procedure is written, a main control ROM 52 storing the program, and a main control RAM 53 functioning as a work area or a buffer memory. . The game control microcomputer MC has a built-in clock circuit 54. The clock circuit 54 divides an external clock to generate a system clock MCKL to be used inside the game control microcomputer MC. Further, the game control microcomputer MC has a built-in reset controller 55 for controlling the reset signal RST. The reset controller 55 includes a watchdog timer circuit (hereinafter referred to as “WDT circuit”) 56 that detects a runaway of the main control CPU 51 and generates a watchdog timer reset signal (WDT reset signal) WDTR. . The reset signal RST controlled in the reset controller 55 includes not only the WDT reset signal WDTR generated in the WDT circuit 56 but also the system reset signal SYS generated in the power supply board 31 (see FIG. 3).

  The main control board 32 further includes a CTC (Counter Timer Circuit) 57 that generates a timer interrupt signal for each predetermined timer interrupt time that is set, and an interrupt controller 58 that controls the timer interrupt signal generated in the CTC 57. And a random number generation circuit 59 for generating random numbers used for random drawing of special symbols and the like, and a serial communication circuit 60 for communicating with other boards and the like. The main control CPU 51, main control ROM 52, main control RAM 53, clock circuit 54, reset controller 55, WDT circuit 56, CTC 57, interrupt controller 58, random number generation circuit 59 and serial communication circuit 60 communicate with each other via an internal bus 71. It is possible.

  The reset controller 55 is a circuit that controls various resets and internal resets. When the system reset signal SYS is given to the reset controller 55, the reset controller 55 initializes all the internal circuits of the game control microcomputer MC except for some circuits such as the WDT circuit 56. On the other hand, when the WDT reset signal WDTR is given to the reset controller 55, the reset controller 55 resets the main control CPU 51, the CTC 57, the interrupt controller 58 and the serial communication circuit 60 in the game control microcomputer MC.

After the main control CPU 51 (its operation and internal functions) is reset, access to the main control RAM 53 is partially prohibited. Specifically, the read operation of the main control RAM 53 is allowed, while the write operation of the main control RAM 53 is prohibited.
FIG. 5A is a diagram showing a memory map of the game control microcomputer MC. The memory map of FIG. 5A shows a memory circuit (configuration including both the main control ROM 52 and the main control RAM 53) and various function registers RT. As shown in FIG. 5A, the control program created by the gaming machine manufacturer and the fixed value data referred to by the control program are stored, for example, after address 8000H. The main control ROM 52 has not only fixed value data but also a parameter area. This parameter area is an area in which operation parameters transferred to the function register RT when the main control CPU 51 is reset can be stored. The operating parameter includes, for example, a set value that defines a waiting time until the control program starts to function.

FIG. 5B is a block diagram showing a configuration of the WDT circuit 56. FIG. 6 is a block diagram showing a more detailed configuration of the WDT circuit 56. FIG. 7A is a block diagram showing a more detailed configuration of a watchdog timer clear circuit (hereinafter referred to as “WDT clear circuit”, clearing means) 63.
As shown in FIG. 5B, the WDT circuit 56 includes a watchdog timer (hereinafter referred to as “WDT”) 61 that performs a counting operation (timekeeping operation) within a predetermined range, and a timeout value (indicated value of timeout time) of the WDT 61. A watchdog timer control register (hereinafter referred to as “WDT control register”) 62 for setting, and a WDT clear circuit 63 that resets the time value of WDT 61 to an initial value (clears the time value). .

  The WDT 61 sends a WDT reset signal WDTR to the reset controller 55 every time the measured value goes round the numerical range from the initial value to the final value. When the WDT reset signal WDTR is given to the reset controller 55, the reset controller 55 forcibly resets the main control CPU 51 and the like. That is, the main control CPU 51 is repeatedly reset every output cycle of the WDT reset signal WDTR. In this embodiment, for example, a decimal counter is employed as the WDT 61, the initial value is “0”, and the final value is “99”.

  As shown in FIG. 5B, the WDT clear circuit 63 is provided so as to be able to generate a clear signal CLRWDT. The clear signal CLRWDT is output from the WDT clear circuit 63 and given to the WDT 61. When the clear signal CLRWDT is given to the WDT 61, the timing value of the WDT 61 is returned to the initial value (“0”) (the timing operation of the WDT 61 is cleared), and the timing operation of the WDT 61 is restarted from the initial value (“0”). The That is, before the WDT 61 reaches the final value, the WDT clear circuit 63 gives the clear signal CLRWDT to the WDT 61 to return the time value of the WDT 61 to the initial value, thereby preventing the output of the WDT reset signal WDTR.

  As shown in FIG. 6, the WDT clear circuit 63 includes a WDT clear register (watchdog timer starting means) 64 for receiving and storing clear data from the main control CPU 51, and a keyword register for permanently storing a clear processing keyword. 65, an operation sequence control circuit 66 that controls the operation sequence of the WDT clear register 64, and a clear match determination that determines whether the stored value of the WDT clear register 64 matches the stored value of the keyword register 65 Circuit (watchdog timer starting means) 67. The WDT clear register 64, the keyword register 65, and the like are realized by function registers RT (see FIG. 5A).

In the WDT clear circuit 63, when the stored value of the WDT clear register 64 and the stored value of the keyword register 65 match, the clear match determination circuit 67 outputs an “L” level clear signal CLRWDT, which is sent to the WDT 61. By being given, the time value of WDT 61 is returned to the initial value.
As shown in FIG. 7A, the WDT clear register 64 includes, for example, four input registers 71A, 72A, 73A, and 74A. Each of the input registers 71A to 74A is configured by an 8-bit register. Addresses (port numbers) N1, N2, N3, and N4 are assigned to the input registers 71A to 74A. Each input terminal of the input registers 71A to 74A is connected to the data bus of the main control CPU 51. Each input terminal stores and outputs clear data output from the main control CPU 51 on condition that it receives a chip select signal CS1, CS2, CS3, CS4 for selecting itself. The chip select signals CS1 to CS4 are “L” active unique signals generated based on the addresses N1 to N4.

  The keyword register 65 includes, for example, four keyword registers 71B, 72B, 73B, and 74B. The keyword registers 71B to 74B are provided in a one-to-one correspondence with the input registers 71A to 74A. Each of the keyword registers 71B to 74B is configured by an 8-bit register. The keyword registers 71B to 74B are assigned the same addresses N1 to N4 as the corresponding input registers 71A to 74A. Each input terminal of the keyword registers 71B to 74B is fixedly set to either “H” level or “L” level. Each of the keyword registers 71B to 74B stores and outputs a unique keyword on condition that it receives chip select signals CS1 to CS4 for selecting itself. In this embodiment, the keyword registers 71B, 72B, 73B, and 74B store “5AH”, “33H”, “55H”, and “AAH”, respectively.

  In the WDT clear circuit 63 of the gaming machine 1 according to this embodiment, a simple clear mode for clearing the time measured value of the WDT 61 using one register pair (first register pair 71A, 71B) and three register pairs ( A cyclic clear mode is provided in which the time value of the WDT 61 is cleared using the second register pair 72A, 72B, the third register pair 73A, 73B, and the fourth register pair 74A, 74B). The circulation clear mode has a higher security level than the simple clear mode. As described above, the WDT circuit 56 is provided with the operation sequence control circuit 66, and the operation of the operation sequence control circuit 66 realizes the circulation clear mode.

  The clear match determination circuit 67 receives the output values from the four pairs of registers (register pair 71A, 71B, register pair 72A, 72B, register pair 73A, 73B and register pair 74A, 74B) and performs subtraction processing. A circuit 75, a NOR gate 76 that receives an output bit (8 bits in this embodiment) of the subtraction circuit 75 and executes an OR operation, and a NAND gate 77 that receives each chip select signal CS1 to CS4 and performs an AND operation NAND gate 78 which receives the output of NAND gate 77 and the output of NOR gate 76 and performs an AND operation. The output of the NAND gate 78 is an L active clear signal CLRWDT applied to the WDT 61.

  The subtraction circuit 75 compares the output values of input registers and keyword registers (register pair 71A, 71B, register pair 72A, 72B, register pair 73A, 73B and register pair 74A, 74B) corresponding to each other, and the subtraction results thereof. Is output. When the output values of the corresponding input register and keyword register match each other, zero is output as the subtraction result.

The NOR gate 76 indicates an “H” level output when the input value is zero. When the input value is other than zero, an “L” level output is indicated. Therefore, the output value of NOR gate 76 normally indicates “L” level, and the output value of NOR gate 76 indicates “H” level only when the output values of the corresponding input register and keyword register match each other.
In the NAND gate 77, if any of the four input chip select signals CS1 to CS4 is at "L" level, the output of the NAND gate 77 indicates "H" level. When any of the four input chip select signals CS1 to CS4 becomes “H” level, the output of the NAND gate 77 changes to “L” level.

  Therefore, the output of the NAND gate 78 is the timing at which the output values from the corresponding input registers and keyword registers (register pair 71A, 71B, register pair 72A, 72B, register pair 73A, 73B, and register pair 74A, 74B) match. Only indicates the “L” level which is an active level, and the output of this “L” level functions as a clear signal CLRWDT for returning the time measured value of the WDT 61 to the initial value.

  In the simple clear mode, “5AH” is written to the input register 71A as clear data. As a result of the match between the clear data written in the input register 71A and the clear data ("5AH") stored in the keyword register 71B, zero as the match data is output from the subtraction circuit 75 (see FIG. 7A). As a result, an active level clear signal CLRWDT is output from the NAND gate 78. When the clear signal CLRWDT is given to the WDT 61, the time measured value of the WDT 61 is returned to the initial value, thereby preventing the main control CPU 51 from being reset.

  On the other hand, in the cyclic clear mode, “33H” is written to the input register 72A to clear the time measured value of the WDT 61, and “55H” is written to the input register 73A to clear the time measured value of the WDT 61. And the three clear processes of writing “AAH” to the input register 74A and clearing the time measured value of the WDT 61 are repeated cyclically.

  Specifically, in the first clear process, “33H” is written as clear data in the input register 72A. In this case, as a result of the clear data written to the input register 72A and the clear data ("33H") stored in the keyword register 72B being coincident, zero, which is coincident data, is obtained from the subtraction circuit 75 (see FIG. 7A). Is output. Subsequent writing of clear data to the WDT clear register 64 is allowed only to the input register 73A.

  In the second clear process, “55H” is written as clear data in the input register 73A. In this case, as a result of the clear data written to the input register 73A and the clear data (“55H”) stored in the keyword register 73B being coincident, zero, which is coincident data, is obtained from the subtraction circuit 75 (see FIG. 7A). Is output. Subsequent writing of clear data to the WDT clear register 64 is allowed only to the input register 74A.

  In the third clear process, “AAH” is written as clear data in the input register 74A. In this case, as a result of the clear data written in the input register 74A and the clear data (“AAH”) stored in the keyword register 74B being coincident, the subtraction circuit 75 (see FIG. 7A) outputs zero as the coincidence data. Is output. Subsequent writing of clear data to the WDT clear register 64 is permitted only to the input register 72A.

  As shown in FIG. 5B, the WDT circuit 56 further includes a prescaler 81 that divides the pulse period of the system clock MCKL divided from the clock generation circuit 54 into a predetermined division ratio, and an output clock of the prescaler 81. And a postscaler (programmable postscaler) 82 that divides the pulse period by a set division ratio and outputs the result to the WDT 61. The WDT control register 62 includes a frequency division ratio setting register 83 that stores the frequency division ratio of the postscaler 82 and other operation parameters. The frequency division ratio setting register 83 is realized by a function register RT (see FIG. 5A).

  In this embodiment, the frequency division ratio setting register 83 is provided so that an arbitrary frequency division ratio can be set between “10” and “1270”. That is, it is possible for the gaming machine manufacturer to set the pulse period of the clock given to the WDT 61. As a result, the output period (that is, the timeout time) of the WDT reset signal WDTR can be set on the gaming machine manufacturer side. A predetermined default value (for example, a frequency division ratio “50”) is set in the frequency division ratio setting register 83, and the value of the frequency division ratio setting register 83 is set to the default value immediately after reset at power-on. Is set. Thereafter, when frequency division ratio data is written to the setting input register 84 by the main control CPU 51, the frequency division ratio corresponding to the frequency division ratio data is set in the frequency division ratio setting register 83.

  In this embodiment, the system clock MCKL input to the prescaler 81 is 20 MHz, for example. Further, the frequency division ratio by the prescaler 81 is 2000, for example. Therefore, the pulse period of the clock given from the prescaler 81 to the postscaler 82 is, for example, 100 μsec. The pulse period of the input clock is divided by the postscaler 82, and a clock having a pulse period of 1 msec to 127 msec is output from the postscaler 82. Therefore, one round cycle of the WDT 61 composed of a decimal counter is in the range of 0.1 sec to 12.7 sec. Therefore, the output period (that is, the timeout period) of the WDT reset signal WDTR is in the range of 0.1 sec to 12.7 sec.

  As shown in FIG. 6, the WDT control register 62 further stores a setting input register 84 (see also FIG. 5B) for the main control CPU 51 to write frequency division ratio data, and an output value of the setting input register 84. The frequency division ratio control register 85, the input coincidence determination circuit 86 for comparing the output value of the frequency division ratio control register 85 and the input value to the setting input register 84, and the output value of the input coincidence determination circuit 86 as S RS flip-flop 87 received at the input terminal. The setting input register 84 and the frequency division ratio control register 85 are realized by a function register RT (see FIG. 5A).

  The output of the division ratio control register 85 is supplied to the input coincidence determination circuit 86 and the division ratio setting register 83, respectively. When the frequency division ratio setting register 83 receives an “L” level signal at the clock terminal CK, it latches the signal at the input terminal. Therefore, in the frequency division ratio setting register 83, the output value of the frequency division ratio control register 85 is stored at the timing when the output value of the frequency division ratio control register 85 matches the input value of the setting input register 84.

  When the output value of the division ratio control register 85 matches the input value of the setting input register 84, the input match determination circuit 86 sets the control terminal OE (output enable) of the input match determination circuit 86 to “H”. "L" level judgment value is output on condition that it is "" level, and "H" level judgment value is output at other timings. The determination output of the input coincidence determination circuit 86 is given to the clock terminal CK of the frequency division ratio setting register 83.

The R input terminal of the RS flip-flop 87 is fixed to the “H” level. The Q-bar output terminal of the RS flip-flop 87 is connected to the first input terminal of the AND gate 88 via a delay circuit using a NOT gate. When the power is turned on, the RS flip-flop 87 receives the system reset signal SYS at the clear terminal CLR, and the power is reset. After the power is turned on, the Q bar output terminal of the RS flip-flop 87 indicates the “H” level. That is, after the power is turned on, the first input terminal of the AND gate 88 maintains the “H” level. The setting input register 84 and the frequency division ratio control register 85 are connected to the chip select signal CS output from the main control CPU 51. Based on this, the division ratio data of the data bus is latched. Specifically, the setting input register 84 latches the frequency division ratio data at the falling edge of the chip select signal CS. Further, the frequency division ratio control register 85 latches the frequency division ratio data at the rising edge of the chip select signal CS ″ that is appropriately delayed.

On the other hand, the logically inverted chip select signal CS ′ is applied to the second input terminal of the AND gate 88. As described above, since the first input terminal of the AND gate 88 maintains the “H” level after the power reset, the logic-inverted chip select signal CS ′ remains at that level and the input match determination circuit 86 It is given to the control terminal OE.
The control terminal OE of the input coincidence determination circuit 86 has a function of controlling the output operation of the input coincidence determination circuit 86, and at the timing when the chip select signal CS returns to the steady level (“H” level). It returns to the “L” level together with the logically inverted chip select signal CS ′. That is, the output of the input coincidence determination circuit 86 returns to the steady level (“H” level) in accordance with the change of the logically inverted chip select signal CS ′.

FIG. 7B is a diagram showing the contents of the WDT control register 62. Hereinafter, a description will be given with reference to FIGS. 6 and 7B.
The bit of the WDT control register 62 is a bit for setting a timeout value, in other words, the setting input register 84 (see FIGS. 5B and 6) for writing the frequency division ratio data. In the bits of the WDT control register 62, frequency division ratio data from “00H (ie,“ 0 ”) to“ 7FH (ie, “127”) ”can be written as a timeout value. In this embodiment, a value obtained by multiplying the value (timeout value) of the frequency division ratio data written in the WDT control register 62 (setting input register 84) by 10 is set in the frequency division ratio setting register 83 as the frequency division ratio. The Therefore, in this embodiment, the time obtained by multiplying the value of the frequency division ratio data (timeout value) written in the WDT control register 62 by 0.1 sec is the output period (that is, the time-out time) of the WDT reset signal WDTR. . Therefore, for example, when 0.1 sec is set as the time-out time (when the frequency division ratio “10” is set), the main control CPU 51 writes “01H” as the frequency division ratio data and 12.7 sec as the time-out time. When setting (when setting the frequency division ratio “1270”), the main control CPU 51 writes “7FH” as the frequency division ratio data.

  FIG. 7C is a diagram showing the contents of the WDT mode setting register 70. The bits of the WDT mode setting register 70 are bits for setting the clear mode and constitute a part of the operation sequence control circuit 66. When “00H (ie,“ 0 ”)” is set in the bit of the WDT mode setting register 70, the above-described simple clear mode is executed. On the other hand, when “01H (ie,“ 1 ”)” is set in the bit of the WDT mode setting register 70, the above-described circulation clear mode is set.

In the simple clear mode, the main control CPU 51 writes “5AH” as the clear data to the symbol “WTCLR0” of the WDT clear register 64 within the set time of the WDT 61, whereby the time measured value of the WDT 61 is returned to the initial value.
In the cyclic clear mode, the main control CPU 51 writes “33H” as the clear data in the symbol “WTCLR1” of the WDT clear register 64 within the set time of the WDT 61, whereby the time measured value of the WDT 61 is returned to the initial value, and the next setting is performed. The main control CPU 51 writes “55H” as the clear data in the symbol “WTCLR2” of the WDT clear register 64 within the set time of the WDT 61 within the time, so that the time measured value of the WDT 61 is returned to the initial value, and within the next set time When the main control CPU 51 writes “AAH” as the clear data in the symbol “WTCLR3” of the WDT clear register 64 within the set time of the WDT 61, the time measured value of the WDT 61 is returned to the initial value.

Next, the division ratio data writing operation by the main control CPU 51 will be described.
The main control CPU 51 writes the same frequency division ratio data in the setting input register 84 twice in succession within a predetermined time. Thus, the input frequency division ratio data is stored in the frequency division ratio setting register 83, and the frequency division ratio of the postscaler 82 corresponding to the frequency division ratio data is set in the frequency division ratio setting register 83.

  Specifically, in each write operation, the division ratio data is latched in the setting input register 84 (WDT clear register 64) at the falling edge of the chip select signal CS. The latched division ratio data is latched in the division ratio control register 85 (WDT clear register 64) at the rising edge of the delayed chip select signal CS ″. The frequency division ratio data is sent to the clear match determination circuit 67 of the WDT clear circuit 63.

  When the same division ratio data is continuously given, the clear match determination circuit 67 assumes that the same division ratio data has been written twice in the WDT clear register 64 (a normal setting process is performed). As an execution), the output of the clear match determination circuit 67 changes to the “L” level. The frequency division ratio data output for the first time is stored in the frequency division ratio setting register 83 in synchronization with the falling edge of the output of the clear match determination circuit 67.

  The main control CPU 51 stores “00H” (that is, “0”) in the setting input register 84. By writing the same frequency division ratio data (“01H (ie,“ 1 ”)) to“ 7FH (ie, “127”) excluding the “specific value” twice in a predetermined time, the frequency division ratio setting register 83 is written. A frequency division ratio (time-out value) is set, and a frequency division ratio other than zero is set in the frequency division ratio setting register 83, whereby the WDT 61 is activated, that is, the watchdog timer activation means sets zero. This is realized by setting a frequency division ratio (timeout value) to be excluded in the frequency division ratio setting register 83.

On the other hand, “00H” (that is, “0”) is set as frequency division ratio data (timeout value) in the setting input register 84. By writing “specific value” twice within a predetermined time, zero is set as the frequency division ratio in the frequency division ratio setting register 83. In this case, the WDT 61 will not start.
The RS flip-flop 87 is set to perform a set operation based on the S terminal input at the “L” level when the output of the clear match determination circuit 67 changes to the “L” level. Therefore, after the same division ratio data (division ratio data other than “0”) is continuously given, the output of the clear match determination circuit 67 changes to the “L” level. The Q bar output of 87 changes to “L” level, and this change is transmitted to the AND gate 74, whereby the control terminal OE of the clear match determination circuit 67 becomes “L” level. Along with this, the output of the clear match determination circuit 67 returns to the “H” level. On the other hand, the Q bar output of the RS flip-flop 87 is maintained at the “L” level thereafter, and the clear match determination circuit 67 does not function thereafter.

  Therefore, the frequency division ratio (time-out value) set in the frequency division ratio setting register 83 cannot be changed after the start of timing of WDT 61 (after activation of WDT 61). Therefore, even after the WDT 61 is activated, even if the division ratio data corresponding to the division ratio different from the division ratio set in the division ratio setting register 83 is written to the setting input register 84, the division ratio setting register 83 The set division ratio cannot be changed.

  Since the frequency division ratio set in the frequency division ratio setting register 83 cannot be changed after the WDT 61 is activated, “00H” (that is, “0”) after the WDT 61 is activated. Even if the “specific value” is written twice in the WDT control register 62, the timing operation of the WDT 61 is not stopped. That is, the timing operation cannot be stopped after the WDT 61 is activated. In other words, once the WDT 61 is activated, the clocking operation is continued as long as power supply continues thereafter.

FIG. 8A and FIG. 8B are flowcharts showing the contents of the system reset process in the main control board 32. The system reset process will be described with reference to FIGS. 3, 4, 8A and 8B.
The execution of the system reset process is started based on the input of the system reset signal SYS and the WDT reset signal WDTR to the reset controller 55 of the main control board 32.

  When the system reset signal SYS or the WDT reset signal WDTR is input to the reset controller 55, the main control CPU 51 first sets itself to an interrupt disabled state (step S1), and then proceeds to each process of step S2. . In step S2, the following processes are performed. That is, the main control CPU 51 sets an interrupt mode (interrupt mode setting). Also, register values and the like in the main control CPU 51 are initialized (various initial settings). Further, the value of the stack pointer in the main control CPU 51 is set to the final address (for example, 8000H) of the stack area (stack pointer setting). Further, the main control CPU 51 activates an internal hard random number circuit (internal hard random number setting).

When the main control board 32 receives the RAM clear signal DEL from the power supply board 31, the main control CPU 51 reads the RAM clear signal DEL and checks the level of the RAM clear signal DEL (step S3). ).
Next, the main control CPU 51 sets a start waiting time for the sub control boards 33 and 34 (step S4). Then, 1 is subtracted from the set activation waiting time (step S5), and the WDT clear circuit 63 gives the clear signal CLRWDT to the WDT 61 to clear the time value of the WDT 61 (step S6), and the set activation waiting time becomes zero. Each process of step S5 and step S6 is repeated until it becomes (step S7). In other words, it waits for the set activation waiting time to elapse while clearing the time measured value of the WDT 61.

When the WDT 61 has already been activated, the clear value CLRWDT is given to the WDT 61, whereby the time value of the WDT 61 is returned to the initial value.
When the set activation waiting time becomes zero (YES in step S7), the main control CPU 51 then reads the voltage abnormality signal ARM transmitted from the power supply board 31 (see FIG. 3) twice (step S8). Then, whether or not the level of the voltage abnormality signal ARM read twice is matched (step S9), and if these levels do not match (NO in step S9), the process returns to step S8, If these levels match (YES in step S9), the voltage abnormality signal ARM is stored in an internal register (not shown), and the level of the voltage abnormality signal ARM is referred to (step S10). If the level of the voltage abnormality signal ARM is “H” level (YES in step S10), the process returns to step S8. In other words, the main control CPU 51 repeats the same processing until the voltage abnormality signal ARM changes to a normal level (ie, “L” level) (steps S8 to S10).

When the level of the voltage abnormality signal ARM becomes “L” level (NO in step S10), the main control CPU 51 validates the protection of the main control RAM 53 and invalidates the prohibited area of the main control RAM 53 (step S11). . Thereby, data writing to the main control RAM 53 is prohibited in the subsequent processing.
Next, the WDT clear circuit 63 gives a clear signal CLRWDT to the WDT 61 to clear the time value of the WDT 61 (step S12), and the main control CPU 51 refers to the power-on signal transmitted from the payout control board 35 (step S13). ) If the power-on signal is off (NO in step S13), the processes in steps S12 and S13 are repeated until the power-on signal is turned on. In other words, it waits for the dispensing control board 35 to start up while clearing the time value of the WDT 61. When the WDT 61 has already been activated, the clear value CLRWDT is given to the WDT 61, whereby the time value of the WDT 61 is returned to the initial value.

  When the dispensing control board 35 is activated and the power-on signal is turned on as a result (YES in step S13), the main control CPU 51 then refers to the level of the RAM clear signal transmitted from the power board 31 (step S13). If the RAM clear signal is on (YES in step S14), the main control CPU 51 performs a RAM clear process for clearing all the areas in the main control RAM 53 (step S18).

  On the other hand, when the RAM clear signal transmitted from the power supply board 31 is OFF (NO in step S14), the main control CPU 51 determines the contents of the backup flag (step S15). The backup flag is data indicating whether or not the operation of the abnormal power supply check process (step T1 in FIG. 9) has been executed. If the backup flag is off (NO in step S15), the main control CPU 51 performs a RAM clear process in step S18.

  On the other hand, if the backup flag is on (YES in step S15), the main control CPU 51 performs a checksum calculation for calculating the checksum value (8-bit addition operation for the work area of the main control RAM 53). The calculation result (check sum value) is compared with the stored value at the SUM address in the main control RAM 53 (step S16). The stored calculation result is maintained by the backup voltage generated in the power supply board 31 together with other data stored in the main control RAM 53.

If the stored value at the SUM address does not match the checksum value calculated in step S13 (NO in step S16), the main control CPU 51 performs RAM clear processing in step S18.
On the other hand, when the checksum values match (YES in step S16), the main control CPU 51 returns to the game operation at the time of power-off based on the data stored in the main control RAM 53. Processing is performed (step S17).

After the process of step S17 or step S18, the main control CPU 51 invalidates the protection of the main control RAM 53 and validates the prohibited area of the main control RAM 53 (step S19). Thereby, data writing to the main control RAM 53 is allowed in the subsequent processing.
Next, the main control CPU 51 sets a predetermined time in the CTC 57 (see FIG. 4) so that a timer interrupt is periodically generated every 4 ms (step S20), and “00H” (ie, “0”) is set in the WDT control register 62. The frequency division ratio data (10 to 1270) corresponding to the frequency division ratio data (“01H (ie,“ 1 ”)” to “7FH (ie,“ 127 ”)) is set in the frequency division ratio setting register 83. In the non-activated state, the WDT 61 is activated by setting the frequency division ratio (10 to 1270) (step S20).

Further, when reset for some reason such as noise, the WDT 61 is already activated, but even if a value is set in the WDT control register 62, the operation of the WDT 61 cannot be changed. Does not affect the operation.
Next, the main control CPU 51 performs update processing of various random number counters (step S22) in a state where the interruption to itself is set to a prohibited state (step S21). In this various random number update processing, the initial value random number for normal symbol determination used to change the initial value of the random number for normal symbol determination used for the normal symbol success / failure lottery and the special symbol variation pattern command are determined. Update of random numbers for variation patterns used for the lottery of the above.

After completion of the update process, the main control CPU 51 is returned to the interrupt enabled state (step S23), and the process returns to step S18. And the process of step S21-S23 is repeated.
Next, a timer interrupt processing program that is started every 4 msec after interrupting the main processing will be described. In this specification, a series of processing (processing of steps S1 to S20) before entering the processing of steps S21 to S23 in the system reset processing may be referred to as “initial setting”.

FIG. 9 is a flowchart showing the flow of timer interrupt processing by the main control board 32. The flow of the timer interrupt process will be described with reference to FIG. 2, FIG. 3, FIG. 4, and FIG.
When the timer interrupt process is started, the abnormal power supply check process is promptly executed without saving the register of the main control CPU 51 (step T1). In the abnormal power check process, the level of the voltage drop signal DWN supplied to the main control board 32 from the power supply board 31 connected to the main control board 32 is determined. If it is detected that the level of the voltage drop signal DWN is a level indicating power-off, over one or a plurality of timer interrupt processes, the process proceeds to a backup process (described later).

  On the other hand, when it is determined that the voltage drop signal DWN is at a level that does not indicate power-off, the timer is subtracted (updated) for each timer that manages the game operation time (T2: timer management). processing). The timer subtracted here is a timer used for managing the opening time of the special winning opening 24, the normal symbol variation time, the game effect time such as the special symbol variation time, the fraud information timer, and the like.

Next, an input management process is executed (step T3). The input management process stores the contents of the detection outputs of various sensors provided in the gaming machine 1 (for example, when various detection sensors output an on / off signal, the on / off state or the rising state thereof) This is a process of periodically updating data based on the.
Next, the value of the random number counter for normal hit determination used in the normal symbol determination process in the normal symbol management process (step T7) to be described later, or the big hit determination random number determination process in the special symbol management process (step T9). The value of the big hit determination random number counter is updated (T4: random number management process in timer interruption).

Next, an error management process is performed to determine whether or not the supply of game balls to the ball supply mechanism (not shown) for supplying game balls to the prize ball payout device 20 is stopped or whether or not the game balls are clogged (step T5). . In this error management process, it is also determined whether or not an abnormality has occurred inside the gaming machine 1.
Next, a winning ball management process for confirming winning information and creating command signal data is performed with respect to winning in a winning opening (special symbol starting openings 19, 21, special winning opening 24, etc.) (step T6). In the winning ball management process, when a detection output of a ball detecting sensor or the like provided in association with each winning opening 19, 21, 24 or the like is input to the main control board 32, the main control of the main control board 32 is performed. Based on these detection outputs, the CPU 51 creates command signal data for instructing the winning ball payout device 20 on the number of payouts.

  Next, normal symbol management processing is performed (step T7). In the normal symbol management process, the value of the normal symbol determination random number acquired from the random number for normal hit determination updated by the random number management process in timer interruption at step T4 is compared with the normal hit value. If it is determined that the opening / closing means 22 is open, a process for opening the opening / closing means 22 is executed, and thereafter, a process for realizing the opening operation of the opening / closing means 22 is executed (T8: normal electric drive). Property management processing).

After the end of the ordinary electric accessory management process, a special symbol management process is then performed (step T9). In this special symbol management process, a series of lottery processes associated with winning a prize to the first special symbol start opening 19 and a series of lottery processes accompanying winning a prize to the second special symbol start opening 21 are sequentially executed.
Next, when it is determined that the jackpot determination random number determination process included in the special symbol management process is a big hit, a process for opening the special winning opening 24 is executed, and then the special winning opening 24 Processing for realizing the opening operation is executed (T10: special electric accessory management processing).

Next, a right-handed notification information management process is performed (step T11). In this right-handed notification information management process, for example, when the special winning opening 24 is opened or when the opening / closing means 22 is opened (during the open extended state), the right-handed game is advantageous in the right-handed situation. Processing for causing a “right-handed notification effect” to be made is made.
Next, a lamp management process for causing a predetermined lamp (game lamp 13 or the like) managed by the main control board 32 to perform a lighting operation or an extinguishing operation is executed (step T12).

Next, a solenoid management process for managing the solenoid that drives the opening / closing means 22, the special prize opening opening / closing accessory 25, etc. is executed (step T13).
Next, the WDT clear circuit 63 clears the time value of the WDT 61 (step T14). As a result, the timing operation of the WDT 61 is reset. Specifically, the clear signal CLRWDT generated in the WDT clear circuit 63 is given to the WDT 61, and thereby the time value of the WDT 61 is returned to the initial value.

Next, after returning the main control CPU 51 to the interrupt enabled state (step T15), the timer interrupt process is finished. As a result, the routine of the timer interrupt process is exited and the main process of an infinite loop is executed. In this main process, various random number counter update processes are performed.
FIG. 10 is a flowchart showing the flow of the power supply abnormality check process. The flow of the power supply abnormality check process will be described with reference to FIG. 3, FIG. 4, and FIG.

  In the power supply abnormality check process, the main control CPU 51 first reads the voltage abnormality signal ARM transmitted from the power supply board 31 (see FIG. 3) twice (step E1). Then, it is determined whether or not the levels of the voltage abnormality signal ARM read twice are matched (step E2). If these levels do not match (NO in step E2), the process returns to step E1. Are equal (YES in step E2), the voltage abnormality signal ARM is stored in an internal register (not shown), and the level of the voltage abnormality signal ARM is confirmed (step E3).

When the level of the voltage abnormality signal ARM stored in the internal register (not shown) is “L” level (NO in step E3), the main control CPU 51 clears the value of the power supply abnormality confirmation counter (step E5). ) And the backup flag is turned on (step E6). Thereafter, the power supply abnormality check process of FIG. 10 is returned.
On the other hand, when the level of the voltage abnormality signal ARM stored in the internal register (not shown) is “H” level (YES in step E3), the main control CPU 51 increments the value of the power supply abnormality confirmation counter (+1) (Step E4), and then it is determined whether or not the value of the power supply abnormality confirmation counter has reached 2 (Step E7). When the value of the power supply abnormality confirmation counter is less than 2 (NO in step E7), the power supply abnormality check process of FIG. 10 is returned as it is, and when the value of the power supply abnormality confirmation counter reaches “2”. The main control CPU 51 performs backup processing of data stored in the main control RAM 53 (step E8 to step E10).

  Specifically, processing for clearing the value of the power supply abnormality confirmation counter is executed (step E8), and the backup flag is turned on (step E9). Then, the main control CPU 51 calculates a checksum by continuously performing 8-bit addition on the work area of the main control RAM 53 (step E10). The main control CPU 51 stores the calculation result (SUM address) as a checksum value in the SUM storage area of the main control RAM 53 (step E10). After the backup process, the main control CPU 51 sends a power-off command for notifying that the power has been cut off to the effect interface board 39 (step E11).

  Next, the main control CPU 51 validates the protection of the main control RAM 53 and invalidates the prohibited area of the main control RAM 53 (step E12). Thereby, data writing to the main control RAM 53 is prohibited in the subsequent processing. Further, the main control CPU 51 clears the output data of all output ports (step E13). Then, the main control CPU 51 prohibits timer interruption by setting processing for the CTC 57 (step E14). Thereafter, the infinite loop process is repeated to wait for the power supply voltage to drop and the main control CPU 51 to become inoperative.

At this time, the WDT 61 may time out before the main control CPU 51 becomes inactive. In this case, the main control CPU 51 is reset and starts the initial setting operation again (steps S1 to S20 in FIGS. 8A and 8B). However, when the power supply voltage sufficiently drops, the main control CPU 51 is in the non-operating state. become.
In this embodiment, the time measured value of WDT 61 is cleared during the initial setting (steps S1 to S20 in FIGS. 8A and 8B). Temporarily, the WDT clear (steps S6 and S12) during the initial setting (steps S1 to S20 in FIGS. 8A and 8B) is not provided, and the time measured value of the WDT 61 is cleared within the timer interrupt process (see FIG. 9) (step T4). ) Will cause the following problems.

  That is, when the system reset signal SYS is given to the reset controller 55 of the game control microcomputer MC due to the occurrence of noise or the like after the start of the WDT 61, the operation of the main control CPU 51 is reset. Are executed again from the initial setting (steps S1 to S20 in FIGS. 8A and 8B). On the other hand, as described above, once the WDT 61 is started, the clocking operation is continued as long as the power supply continues, so that the program to be executed can return to the initial setting (steps S1 to S20 in FIGS. 8A and 8B). Regardless, the WDT 61 remains activated and continues to perform the timing operation. For this reason, during the initial setting (steps S1 to S20 in FIGS. 8A and 8B), the time measurement by the WDT 61 times out, and the main control CPU 51 is reset by the WDT 61. Thereafter, the timeout of the WDT 61 and the reset of the main control CPU 51 resulting from the timeout are repeated, and the initial setting (steps S1 to S20 in FIG. 8A and FIG. 8B) cannot be escaped. As a result, the gaming machine 1 operates normally. There is a possibility that it cannot be restored.

  In particular, since the activation waiting time of the sub control boards 33 and 34 is set to be relatively long, the WDT 61 may time out while waiting for activation of the sub control boards 33 and 34 (NO in step S7 in FIG. 8A). . Further, since the waiting time for receiving the power-on signal from the payout control board 35 is relatively long, the WDT 61 may time out during the waiting time for receiving the power-on signal (NO in step S13 in FIG. 8B). There is.

  On the other hand, according to this embodiment, the time measured value of WDT 61 is cleared during the initial setting (steps S1 to S20 in FIGS. 8A and 8B). Thereby, during the initial setting (steps S1 to S20 in FIG. 8A and FIG. 8B), it is possible to prevent a situation in which the timeout of the WDT 61 and the reset of the main control CPU 51 resulting from the time-out are repeated. It can be recovered satisfactorily.

In particular, in this embodiment, while the sub-control boards 33 and 34 are waiting to be activated (NO in step S7 in FIG. 8A), the time measured value of the WDT 61 is cleared (step S6 in FIG. 8A). Therefore, it is possible to prevent the WDT 61 from timing out while waiting for activation of the effect control board 33, which takes a relatively long time.
Also, during the waiting time for receiving the power-on signal (NO in step S13 in FIG. 8B), the time measured value of the WDT 61 is cleared (step S12 in FIG. 8B). Therefore, it is possible to prevent the WDT 61 from timing out during a waiting time for receiving a power-on signal that requires a relatively long time. Accordingly, it is possible to more effectively prevent the WDT 61 from timing out during the initial setting (steps S1 to S20 in FIGS. 8A and 8B).

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form.
For example, the time measured value of the WDT 61 is cleared during processing setting, waiting for activation of the sub control boards 33 and 34 (NO in step S7 in FIG. 8A), and waiting time for receiving a power-on signal (step S13 in FIG. 8B). And NO), but only one of them may be performed.

  In addition, various modifications can be made within the scope of the matters described in the claims.

32: Main control board (main control means)
51: Main control CPU
55: Reset controller 56: WDT circuit 61: WDT
63: WDT clear circuit (clearing means)
64: WDT clear register (watchdog timer starting means)
67: Clear match judgment circuit (watchdog timer starting means)

The invention according to claim 2 further includes an effect control means for controlling an effect relating to a game in the gaming machine, wherein the pre-start clearing means starts the effect control means after the initial setting of the main control CPU. The gaming machine according to claim 1, wherein the timekeeping value of the watchdog timer is cleared while waiting.

The invention according to claim 3 further includes payout control means for controlling payout of game balls in the gaming machine, wherein the pre-start-up clearing means is configured such that after the initial setting of the main control CPU, the payout control means The gaming machine according to claim 1 or 2, wherein the time count value of the watchdog timer is cleared while waiting for activation.

The board surface configuration of the game board 5 shown in FIG. 2 is an example, and is not limited to this board surface, and various board surface configurations can be adopted.
FIG. 3 is a block diagram showing an electrical configuration of the gaming machine 1. The gaming machine 1 receives an AC voltage of 24V AC and outputs various DC voltages, a system reset signal SYS, and the like, a main control board (main control means) 32 that performs overall control of the game, and main control An effect control board (effect control means) 33 that performs effect control based on the control command CMD from the board 32, and a liquid crystal control board 34 that drives the liquid crystal display unit 17 based on the control command CMD ′ from the effect control board 33 Based on a control command CMD ″ received from the main control board 32, a payout control board (payout control means) 35 for driving the prize ball payout device 20 to pay out game balls, and a player's handle 14 (FIG. 1). And a launch control board 36 that drives a launching device (not shown) to launch a game ball in response to the turning operation of (see). Each control board 32, 33, 34, 35, 36 is mounted with a one-chip microcomputer including, for example, a CPU, RAM and ROM.

Claims (5)

A gaming machine with main control means for overall control of the progress of the game,
The main control means includes: a main control CPU that executes a program; and a watchdog timer that starts a time counting operation upon activation and resets the main control CPU when the time measured value reaches a predetermined time-out value without being cleared. Including
Watchdog timer activation means for activating the watchdog timer at a predetermined activation timing after the execution of the program by the main control CPU;
Clear means for clearing the timekeeping value of the watchdog timer,
The clearing means includes a pre-startup clearing means for clearing the timekeeping value of the watchdog timer at a timing before the start timing after the execution of the program by the main control CPU. A time-out value setting means for setting the time-out value;
The watchdog timer starting means is realized by setting a predetermined timeout value in the timeout value setting means,
The gaming machine according to claim 1, wherein the watchdog timer is not started when a specific value is set as the timeout value in the timeout value setting means.   The gaming machine according to claim 2, wherein the timeout value is a predetermined value excluding zero, and the specific value is zero. A time-out value setting means for setting the time-out value;
The gaming machine according to any one of claims 1 to 3, wherein the timeout value setting means cannot change the set timeout value after the watchdog timer is activated.   The gaming machine according to any one of claims 1 to 4, wherein the watchdog timer is configured to continue to be executed without stopping after the timer operation is started once.

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