JP2017198993A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device that suppresses the number of masks of an element substrate to efficiently hide disclination, makes optical leakage inconspicuous for a pixel that displays a green color with a high relative luminosity, and secures a good black level.SOLUTION: Source wiring, a gate electrode, a capacitance electrode, and an electrically floating light shielding film of an element substrate are arranged at an edge of a pixel electrode or an area where optical leakage is likely to occur due to disclination, the optical leakage due to disclination is efficiently hidden even when the number of masks for wiring are two, and an overlapped area of a drain electrode and a light transmissive conductive film in a pixel facing a green color filter is enlarged.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to a semiconductor device typified by a liquid crystal display panel and an electronic apparatus in which such a semiconductor device is mounted as a component.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and a semiconductor device, a semiconductor circuit, and an electronic device are all semiconductor devices.

In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and semiconductor devices, and development of switching devices for liquid crystal display devices is urgently required.

Liquid crystal display devices are roughly classified into two types, an active matrix type and a passive matrix type.

An active matrix liquid crystal display device uses a TFT as a switching element and can obtain a high-quality image. A notebook personal computer is generally used as an active matrix type application, but it is also expected to be used as a television for home use and a portable terminal.

However, the active matrix type has more masks than the passive matrix type,
There are many processes. Therefore, in order to make an active matrix liquid crystal display device versatile, it is essential to reduce the number of masks and to reduce costs and to improve yield.

The element substrate of the active matrix type liquid crystal display device causes line defects and point defects due to fine dust. As the number of processes increases, the probability of occurrence of defects increases. Yield improvement
It depends on how to reduce the number of processes on the element substrate side.

By the way, in an active matrix type liquid crystal display device, liquid crystal disclination can be performed by line inversion driving and a step due to an element. In order to obtain a high-quality black level, a light-shielding film that hides light leakage due to disclination is necessary.

However, when the light shielding film is patterned on the element substrate side of the active matrix type liquid crystal display device, not only the number of steps and masks for forming the light shielding film itself are increased, but an interlayer insulating film is provided between the light shielding film and the wiring. It will be necessary to insulate. The cost also increases due to the formation of the interlayer insulating film. Of course, an increase in the number of processes leads to a decrease in yield.

If a light-shielding film is formed only on the counter substrate, an increase in the number of processes on the element substrate side can be suppressed and yield can be improved. However, if the light shielding film is formed only on the counter substrate, depending on the alignment accuracy when the substrates are bonded together, the light leakage may not be completely hidden due to the positional deviation of the light shielding film, and a high-quality black level cannot be secured. As shown in FIG. 23, the light shielding film 701 formed on the counter substrate is misaligned and bonded to the element substrate, and light leakage 703 due to disclination can be seen. In particular, light leakage near the edge of disclination is visible. For this reason, light leakage is mixed in the black display 702 and the black level is deteriorated. If the light shielding area is increased in order to prevent light leakage due to misalignment of the alignment, the aperture ratio decreases, and conversely the brightness is impaired.

In other words, in order to increase the aperture ratio and contrast and ensure a good black level, it is natural to form a light shielding film on the element substrate side. However, in order to perform this common practice while suppressing an increase in the number of processes on the element substrate side, it is necessary to efficiently lay out the pixel wiring pattern.

In order to secure a high-quality black level and to reduce the cost of an active matrix type liquid crystal display device, a completely new pixel configuration which is not conventionally required is required.

The present invention responds to such a demand, and provides an active matrix liquid crystal display device that ensures a high-quality black level without increasing the number of masks and steps on the element substrate side by forming a light shielding film. This is the issue.

In order to solve the above-mentioned problems of the prior art, the following measures were taken.

First, an element substrate was manufactured with six masks. The structure of the element substrate will be described with reference to FIGS. FIG. 21 shows a cross-sectional view of the top view of FIG. 19 taken along the chain line KK ′ and the chain line LL ′. In FIG. 19 and FIG. 21, the same elements are denoted by the same reference numerals.

The first semiconductor layer 613 and the second semiconductor layer 614 are patterned with one mask. The source wiring 601 and the gate electrode 600 are patterned with a single mask. A first interlayer insulating film 615 and a second interlayer insulating film 616 (not shown in FIG. 19) are formed. The gate wiring 602, the connection electrode 603, the drain electrode 604, and the capacitor connection electrode 605 are patterned with a single mask so as to be in contact with the second interlayer insulating film 616.

Further, the transparent pixel electrode 606 is formed so as to overlap the drain electrode 604 and the capacitor connection electrode 605. The transparent pixel electrode 606 has a margin so as not to be short-circuited with the gate wiring 602 and the connection electrode 603.

A color filter, an overcoat material, and a transparent pixel electrode were formed on the counter substrate, the element substrate and the counter substrate were assembled into a cell, and the orientation of the liquid crystal was observed. The orientation was observed from the back surface of the element substrate. The orientation is TN, and the mixed chiral material is left-handed. In order to analyze the region where the liquid crystal disclination appears, the counter substrate has no light shielding film.

A direct view type liquid crystal display device is driven by a gate line. In a pixel whose length in the gate direction is shorter than that in the source direction, the gate line inversion driving can reduce the rate of light leakage due to disclination in the pixel compared to the source line inversion driving. The disclination at this time is shown in FIGS.

In one pixel, strong light leakages 607 to 609 due to disclination are seen in the source wiring on the side of the element substrate that is rubbed ahead. Since the sensitivity of the human eye is high in green, light leakage is strongly recognized in green with high specific vision sensitivity.

As can be seen from the cross-sectional view of FIG. 21, a capacitor connection electrode 605, a drain electrode 604, and a connection electrode 603 are formed under the transparent pixel electrode 606. Since the capacitor connection electrode 605, the drain electrode 604, and the connection electrode 603 are not flattened by the insulating film, the film thickness of the electrode itself induces a step in the liquid crystal alignment surface. As a result, weak light leaks 610 to 612 were observed around the steps. Such a weak light leakage 610 to 612 is not a big problem in a direct-view type liquid crystal display device, but in a projection type liquid crystal display device, in order to secure a good black level, light leakage due to a step may be caused in some cases. It is necessary to shield the light.

Although it is not so noticeable because the light leakage is blocked, the gate line inversion drive allows light leakage due to disclination along the gate line.

Overall, light leakage due to disclination was observed near the edge of the transparent pixel electrode 606.

Therefore, based on the above analysis, a pixel layout was created that efficiently masked light leakage due to disclination while the number of masks on the element substrate remained six. It should be noted that a wiring pattern or the like is formed with only two masks for a light-shielding conductive film, and the disclination is hidden in the element substrate.

However, since a wiring pattern or the like is formed with two masks for a light-shielding conductive film, an area where the disclination cannot be completely hidden is formed. However, if the region where strong light leakage is possible and the edge portion of the disclination can be surely hidden in the element substrate, the light shielding film on the counter substrate can be made smaller than the light shielding pattern on the element substrate. Even if there is a slight misalignment when the element substrates are bonded together, the disclination can be hidden together with the light shielding film of the counter substrate.

In the present invention, a gate wiring and a capacitor electrode made of a first light-shielding conductive film, a source wiring and a drain electrode made of a second light-shielding conductive film, and the drain electrode are electrically connected The present invention is characterized by being applied to a semiconductor device having a light-transmitting conductive film.

The present invention includes an island-shaped gate electrode and a source wiring made of a conductive film having a first light-shielding property,
A gate wiring electrically connected to the island-shaped gate electrode made of the second light-shielding conductive film, a drain electrode made of the second light-shielding conductive film, and the drain electrode electrically The present invention is characterized by being applied to a semiconductor device having a connected light-transmitting conductive film.

For example, part of the capacitor electrode overlaps with the gap between the source wiring and the light-transmitting conductive film and overlaps with the edge of the source wiring and the light-transmitting conductive film, so that the light-transmitting property is achieved. It is characterized by hiding light leakage due to disclination formed at the edge of the conductive film.

Alternatively, an electrically isolated island-shaped pattern made of the first light-shielding conductive film or the second light-shielding conductive film may be formed to hide light leakage due to disclination.

A part of the drain electrode may be placed over the edge of the light-transmitting conductive film and the edge of the source wiring to hide light leakage due to disclination that can be formed at the edge of the light-transmitting conductive film.

When the color filter is green, light leakage due to disclination tends to be more conspicuous than other colors. Therefore, the area of the light shielding region may be changed according to the color of the color filter.

Light leakage due to disclination by placing a part of the island-shaped gate electrode in the gap between the light-transmitting conductive film and the gate wiring and overlapping the edge of the light-transmitting conductive film and the gate wiring May be hidden.

A part of the source wiring may be twice or more, preferably 2 to 4 times thicker than other parts, so that the light-shielding film of the light-transmitting conductive film may be used.

The present invention can be widely used not only as a TN system but also as a means for hiding liquid crystal disclination. For example, R-TN mode, liquid crystal display device using smectic liquid crystal, IPS
In the (In Plane Switching) method, a region where display is discontinuous may be hidden and used as a means for keeping the luminance in the pixel constant.

The present invention is widely used as a method for shielding a region where there is a discontinuous display in a pixel in an electro-optical device that modulates a voltage or an electric field with a semiconductor element and optically modulates a light control layer. it can. For example, the present invention can be applied when forming a switching element of an EL display device.

According to the present invention, a liquid crystal display device having a pixel structure that realizes a high aperture ratio and a high-quality black level can be realized without increasing the number of masks and the number of steps of an element substrate.

The figure which shows the pixel part top view of this invention. Example 1 The figure which shows the pixel part top view of this invention. Example 1 The figure which shows the relationship between a rubbing direction and a light shielding area. Example 1 The figure which shows the cross-section figure of an active matrix substrate. Example 1 10A and 10B illustrate a manufacturing process of an active matrix substrate. (Example 2) 10A and 10B illustrate a manufacturing process of an active matrix substrate. (Example 2) 10A and 10B illustrate a manufacturing process of an active matrix substrate. (Example 2) The figure which shows the cross-section figure of a transmissive liquid crystal display device. (Example 3) The figure which shows the pixel part top view of this invention. Example 4 The figure which shows the relationship between a rubbing direction and a light shielding area. Example 4 The figure which shows the cross-section figure of an active matrix substrate. Example 4 The figure which shows the pixel part top view of this invention. (Example 5) The figure which shows the pixel part top view of this invention. (Example 5) The figure which shows the relationship between a rubbing direction and a light shielding area. (Example 5) The figure which shows the cross-section figure of an active matrix substrate. (Example 5) FIG. 14 illustrates an example of an electronic device. (Example 7) FIG. 14 illustrates an example of an electronic device. (Example 7) FIG. 14 illustrates an example of an electronic device. (Example 7) The figure which shows the light leakage by the disclination of a liquid crystal. The figure which shows the light leakage by the disclination of a liquid crystal. The figure which shows the cross-section figure of an active matrix substrate. The figure which shows the light leakage by the disclination of a liquid crystal. The figure which shows the light leakage by the disclination of the liquid crystal by the alignment shift | offset | difference of a counter substrate. The figure which shows the wavelength dependence of specific luminous efficiency.

In this embodiment, a direct-view transmissive liquid crystal display device is manufactured. There are only two masks for the wiring pattern using metal electrodes. Hides light leakage due to disclination with two wiring pattern masks.

As shown in FIG. 22, in one pixel 804, the light from the disclination 803 is applied to the side of the counter substrate that is rubbed first in the rubbing direction 802, the side that is rubbed first in the rubbing direction 801 of the element substrate, and the edge of the pixel electrode. A leak comes out. A layout that can hide light leakage due to disclination. This embodiment will be described with reference to FIGS. The orientation is the TN system, and the driving is the source line inversion driving. FIG. 3 shows the relationship between the rubbing direction and the light shielding area. The one cut along the chain line AA ′ and the chain line BB ′ in the top view of FIG. 1 corresponds to the cross section indicated by the line AA ′ and the chain line BB ′ in FIG.

As shown in FIG. 1, the element substrate includes a gate wiring 104 arranged in the row direction, a source wiring 108 arranged in the column direction, and a pixel portion having a pixel TFT in the vicinity of the intersection of the gate wiring and the source wiring. And a driving circuit having an n-channel TFT and a p-channel TFT.

The first semiconductor layer 100 and the second semiconductor layer 101 are patterned. The first semiconductor layer 100 is an active layer of the TFT element. The second semiconductor layer 101 functions as a capacitor electrode of a storage capacitor described later.

The light shielding film 102 and the capacitive electrode 1 serving as the light shielding film so as to be in contact with the gate insulating film (not shown)
03, the gate wiring 104 is formed. The capacitor electrode 103 also serving as a light shielding film is short-circuited in the display area.

After forming a first interlayer insulating film and a second interlayer insulating film (not shown), contact hole 1
Open 05-107. Next, a source wiring 108, a drain electrode 109 that also serves as a light shielding film, and a light shielding electrode 110 are formed by patterning.

The first semiconductor layer 100 and the source wiring 108 are electrically connected through the contact hole 105.

Through the contact hole 106, the drain electrode 1 serving as the first semiconductor layer 100 and the light shielding film.
09 is electrically connected.

Through the contact hole 107, the drain electrode 1 serving as the second semiconductor layer 101 and the light-shielding film
09 is electrically connected.

Further, the transparent pixel electrode 111 is formed without using an insulating film. At this time, the transparent pixel electrode 1
11 overlaps with the light shielding electrode 110 and the drain electrode 109 which also serves as a light shielding film.

With the above structure, the gate wiring 104, the source wiring 108, the drain electrode 109 serving also as a light shielding film, and the light shielding electrode 110 protect the first semiconductor layer 100 that is an active layer of the TFT element from external light.

By providing the light shielding electrode 110, light leakage due to the active layer and disclination formed in the vicinity of the active layer can be shielded.

The liquid crystal disclination that can be formed on the first rubbed side of the four corners of the transparent pixel electrode 111 can be shielded by the drain electrode 107 that also serves as a light shielding film.

Further, when the drain electrode 109 also serving as the light shielding film directly below the transparent pixel electrode 111 and the light shielding electrode 110 are as thick as 0.5 to 0.75 μm or more, the alignment of the liquid crystal is disturbed by the step, and fine light leakage occurs. There is a time. Such light leakage can be shielded by the light shielding film 102.

When the gate line is inverted, the gate wiring 104 and the source wiring 1 are caused by a lateral electric field or the like.
Disclination along 08. Although this light leakage greatly affects visibility, the disclination can be hidden because the capacitor electrode 103 that also serves as a light shielding film is formed at a position where disclination can be performed. With the capacitor electrode 103 that also serves as a light shielding film, the area of the storage capacitor can be increased.

For the storage capacitor, the second semiconductor layer 101 provided for each pixel and the capacitor electrode 103 serving as a light-shielding film short-circuited in the display region are used as electrodes. The capacitor electrode 103 is a contact hole 107.
Thus, the drain electrode 109 and the pixel electrode 111 have the same potential.
The gate insulating film functions as an insulating film for the capacitor electrode.

4A of the cross-sectional view, the light shielding electrode 115 and the transparent pixel electrode 116, the transparent pixel electrode 118 and the semiconductor layer 117 in FIG. 4B, and the light shielding film 123 and the transparent pixel electrode 122 in FIG. And the light shielding electrode 121 are those of adjacent pixels.

The structure of the above pixel portion can be manufactured with five masks. FIG. 3 shows a light shielding region 112 of the element substrate by the wiring pattern of FIG. Since light is shielded by only two wiring pattern masks, there are regions 123 to 126 through which light passes, but the edges of the regions where disclination appears are hidden. If the light shielding film on the counter substrate is made wider, light leakage can be hidden even if there is a slight misalignment. Even if the light shielding film of the counter substrate is widened, the aperture ratio does not decrease due to the misalignment of bonding because the light shielding film of the element substrate overlaps.

As will be described later, when low-temperature polysilicon is used for the active layer of the TFT element, the drive circuit TFT and the pixel TFT can be manufactured on one substrate. At this time, an n-channel TFT and a p-channel TFT are necessary to manufacture a CMOS driving circuit.

Depending on the manufacturing process of the element substrate, one additional mask is required as a mask for doping with an impurity element imparting p-type conductivity. Nevertheless, the number of masks necessary for forming an element substrate having a pixel portion having a pixel structure shown in FIG. 1 and a driver circuit can be six.

That is, one sheet is a mask for patterning the first semiconductor layer 100 and the second semiconductor layer 101, and one sheet is a mask for patterning the capacitor electrode 103 that also serves as the gate wiring 104 and the light shielding film, and the light shielding film 102. One is a mask for forming a contact hole, one is a source wiring 108
And a mask for patterning the drain electrode 109, which also serves as a light shielding film, and the light shielding electrode 110;
One sheet is a mask for patterning the transparent pixel electrode 111, and one sheet is a mask for doping.

Accordingly, a driver circuit portion including an n-channel TFT, a p-channel TFT, and an n-channel TFT, and a pixel portion including the pixel TFT 114 and the storage capacitor 113 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

As described above, in the case of the pixel structure shown in FIG. 1, a transmissive liquid crystal display device with high contrast can be realized without increasing the number of masks in the element substrate.

In this embodiment, as an example of a manufacturing method when the first embodiment is applied to an active matrix liquid crystal display device, a pixel TFT which is a switching element of a pixel portion and a drive circuit (signal line drive circuit) provided around the pixel portion A method for manufacturing a TFT of a scanning line driving circuit or the like over the same substrate will be described in accordance with steps. However, in order to simplify the description, a CMOS circuit which is a basic configuration circuit is illustrated in the drive circuit portion, and an n-channel TFT is illustrated in a cross section along a certain path in the pixel TFT of the pixel portion. To do.

First, as shown in FIG. 5A, a silicon oxide film on a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass, A base film 401 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, SiH _{4 by} plasma CVD,
A silicon oxynitride film 401a made of NH ₃ and N ₂ O is formed to 10 to 200 nm (preferably 50 to 100 nm), and a silicon oxynitride silicon film 401b made of SiH ₄ and N ₂ O is similarly formed to 50 The layers are stacked to a thickness of ˜200 nm (preferably 100 to 150 nm).
Although the base film 401 is shown as a two-layer structure in this embodiment, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are stacked.

The island-shaped semiconductor layers 402 to 406 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. These island-like semiconductor layers 402 to
The thickness of 406 is 25-80 nm (preferably 30-60 nm)
The thickness is formed. There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to manufacture a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are selected by the practitioner.
When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ² ). In the case of using a YAG laser, the second harmonic is used and the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ).
Then, a laser beam condensed in a linear shape with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80.
Perform as ~ 98%.

Next, a gate insulating film 407 is formed to cover the island-shaped semiconductor layers 402 to 406.
The gate insulating film 407 is formed by plasma CVD or sputtering, and has a thickness of 40 to 150 n.
m is an insulating film containing silicon. In this embodiment, a silicon oxynitride film having a thickness of 120 nm is formed. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ort) is formed by plasma CVD.
hosilicate) and O ₂ can be mixed to form a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and discharge at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, a first conductive film 408 and a second conductive film 409 for forming a gate electrode are formed over the gate insulating film 407. In this embodiment, the first conductive film 408 is made of 50 to 10 Ta.
The second conductive film 409 is formed to a thickness of 100 to 300 nm with W.

The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, A
When an appropriate amount of Xe or Kr is added to r, the internal stress of the Ta film can be relaxed to prevent the film from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm, so that an α-phase Ta film can be easily obtained. be able to.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is 20 μm.
It is desirable to make it Ωcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, the resistivity is obtained by using a W target with a purity of 99.9999% and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation. 9-20 μΩcm can be realized.

In this embodiment, the first conductive film 408 is Ta and the second conductive film 409 is W.
Any of them may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a combination other than the present embodiment, the first conductive film is formed of tantalum nitride (TaN), the second conductive film is formed of W, and the first conductive film is formed of tantalum nitride (TaN). The second conductive film is made of Al.
The first conductive film is formed of tantalum nitride (TaN) and the second conductive film is C.
There are combinations such as u.

Next, resist masks 410 to 417 are formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF ₄ and Cl ₂ are mixed in an etching gas, and 1 Pa
500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer have an angle of taper of 15 due to the effect of the bias voltage applied to the substrate side. It becomes a taper shape of ˜45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3),
By over-etching, the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm. Thus, the first etching process and the second conductive layer are performed by the first etching process.
First conductive layers 419 to 426 (first conductive layers 419a to 426a).
And second conductive layers 419b to 426b) are formed. Reference numeral 418 denotes a gate insulating film, and a region not covered with the first shape conductive layers 419 to 426 is etched and thinned by about 20 to 50 nm.

Then, a first doping process is performed, and an impurity element imparting n-type conductivity is added. (Fig. 5
(B)) The doping may be performed by ion doping or ion implantation. The conditions of the ion doping method are a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to
This is performed at 100 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 419 to 423 serve as a mask for the impurity element imparting n-type, and the first impurity regions 427 to 431 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 427 to 431 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ .

Next, as shown in FIG. 5C, a second etching process is performed. Similarly, using the ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed in the etching gas, and 500 W of RF power (13.56 MHz) is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. Do. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the W film is anisotropically etched, and
Ta, which is the first conductive layer, is anisotropically etched at a slower etching rate to form second-shaped conductive layers 433 to 440 (first conductive layers 433a to 440a and second conductive layers 433b to 433).
440b). Reference numeral 432 denotes a gate insulating film, which is the second shape conductive layers 433 to 43.
The region not covered with 7 is further etched by about 20 to 50 nm to form a thinned region.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF _6, which is a fluoride of W, is extremely high, and other WCl ₅
, TaF ₅ and TaCl ₅ are comparable. Therefore, in the mixed gas of CF ₄ and Cl ₂ , the W film and T
Both a films are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂
Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Also, Ta is more easily oxidized than W, so
The surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV, and the dose is 1 × 10 ¹³ / cm ^2. A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 5B. Form. Doping is performed using the second shape conductive layers 433 to 437 as masks for the impurity elements so that the impurity elements are also added to the lower regions of the first conductive layers 433 a to 437 a. Thus, the third impurity regions 441 to 445 overlapping with the first conductive layers 433a to 437a and the second impurity region between the first impurity region and the third impurity region are provided.
Impurity regions 446 to 450 are formed. The impurity element imparting n-type conductivity has a concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ in the second impurity region, and 1 in the third impurity region.
The concentration is set to × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ .

Then, as shown in FIG. 6B, an island-shaped semiconductor layer 403 forming a p-channel TFT is formed.
In addition, fourth impurity regions 454 to 456 having a conductivity type opposite to the one conductivity type are formed. Using the second shape conductive layer 434 as a mask for the impurity element, an impurity region is formed in a self-aligning manner. At this time, the island-shaped semiconductor layers 402, 404, 405, and 4 that form the n-channel TFT are formed.
06 covers the entire surface with resist masks 451 to 453. Impurity regions 454 to 456
Phosphorus is added at different concentrations, but the impurity concentration is 2 × 10 ²⁰ to 2 × 10 ²¹ atom in any region by ion doping using diborane (B ₂ H ₆ ).
made to be s / cm ^3.

Through the above steps, an impurity region is formed in each island-shaped semiconductor layer. Conductive layers 433 to 436 overlapping with the island-like semiconductor layers function as TFT gate electrodes.
Reference numeral 439 denotes a signal line, 440 denotes a scanning line, 437 denotes a capacity wiring, and 438 functions as a wiring in the driver circuit.

Thus, for the purpose of controlling the conductivity type, as shown in FIG. 6C, a step of activating the impurity element added to each island-like semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 400 ppm to 700 ° C., typically 500 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
In this embodiment, heat treatment is performed at 500 ° C. for 4 hours. However, 4
When the wiring material used for 33-440 is weak against heat, an interlayer insulating film (
The activation is preferably performed after the formation of silicon).

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, the first interlayer insulating film 457 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 458 made of an organic insulating material is formed thereon. Next, an etching process for forming a contact hole is performed.

In the driver circuit portion, source wirings 459 to 461 that form contacts with the source region of the island-shaped semiconductor layer, and drain wirings 462 to 464 that form contacts with the drain region.
Form. In the pixel portion, source electrodes 465 and drain electrodes 466 to 467 and 468 that also serve as a light shielding film are formed. The drain electrode 468 that also serves as a light shielding film is formed in an adjacent pixel (FIG. 7). In FIG. 7, the same elements as those in FIG. 1 indicate the corresponding numerals in parentheses. The chain lines AA ′ and BB ′ in FIG. 7 are the chain lines AA of the cut line in the top view of FIG.
Corresponds to ', BB'.

The drain electrode 466 that also serves as a light-shielding film is an island-shaped semiconductor layer 467 corresponding to the active layer of the pixel TFT.
In addition, the drain electrode 467 that also serves as a light-shielding film is an island-shaped semiconductor layer 431 that forms the storage capacitor 505.
And an electrical connection is formed. Note that the drain electrode 468 which also serves as a light shielding film is for an adjacent pixel.

Thereafter, a transparent conductive film is formed on the entire surface, and transparent pixel electrodes 469 to 471 are formed by patterning processing and etching processing using a photomask. The transparent pixel electrode 470 is formed so as to overlap the drain electrode 466 that also serves as a light shielding film.
Further, a portion overlapping with the drain electrode 467 that also serves as a light-shielding film of the pixel TFT 504 is provided, and a potential is applied to the island-shaped semiconductor film 406 that functions as an electrode of the storage capacitor 505.

The material of the transparent conductive film is indium oxide (In ₂ O ₃ ) or indium oxide tin oxide alloy (I
n ₂ O ₃ -SnO _2; ITO film) can be used as formed by using a sputtering or a vacuum evaporation method. Etching treatment of such a material is performed with a hydrochloric acid based solution. But,
In particular, since etching of the ITO film tends to generate residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to the ITO film, even if Al is used for the drain electrodes 466 to 468 which also serve as the capacitive electrode, Corrosion reaction can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.

As described above, the driver circuit portion including the n-channel TFT 501, the p-channel TFT 502, and the n-channel TFT 503, and the pixel portion including the pixel TFT 504 and the storage capacitor 505 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 501 in the driver circuit portion includes a channel formation region 468, a third impurity region 441 (GOLD region) overlapping with the conductive layer 433 forming the gate electrode, and a second impurity region 446 (outside of the gate electrode). LDD region) and a first impurity region 427 functioning as a source region or a drain region.
The p-channel TFT 502 includes a channel formation region 469 and a conductive layer 4 for forming a gate electrode.
34, a fourth impurity region 455 formed outside the gate electrode, and a fourth impurity region 454 functioning as a source region or a drain region. The n-channel TFT 503 includes a channel formation region 470, a third impurity region 443 (GOLD region) overlapping with the conductive layer 435 forming the gate electrode, and a second impurity region 448 (LDD region) formed outside the gate electrode. And a first impurity region 429 functioning as a source region or a drain region.

The pixel TFT 504 in the pixel portion includes a channel formation region 471, a third impurity region 444 (GOLD region) overlapping with the conductive layer 436 forming the gate electrode, and a second impurity region 449 (LDD region) formed outside the gate electrode. ) And a first impurity region 430 functioning as a source region or a drain region. The semiconductor layer 431 functioning as one electrode of the storage capacitor 505 has the same concentration as the first impurity region, the semiconductor layer 445 has the same concentration as the third impurity region, and the semiconductor layer 450 has the second concentration. An impurity element imparting n-type conductivity is added at the same concentration as the impurity region, and a storage capacitor is formed by the capacitor wiring 437 and an insulating layer therebetween (the same layer as the gate insulating film).

In this embodiment, the end portions of the pixel electrodes are arranged so as to overlap with the capacitor electrodes that also serve as gate lines and light shielding films so that the gaps between the pixel electrodes can be shielded from light without using a black matrix. . Further, a light-shielding electrode is formed in contact with the pixel electrode.

Further, according to the steps shown in this embodiment, the number of photomasks necessary for the production of the active matrix substrate is six (an island-shaped semiconductor layer pattern, a first wiring pattern (source line, gate wiring,
A capacitor electrode also serving as a light shielding film, a light shielding film), a second wiring pattern (source wiring, drain electrode, light shielding film), a contact hole pattern, a transparent pixel electrode pattern, and an n channel region mask pattern). As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

In this embodiment, a process for manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 2 will be described below. FIG. 8 is used for the description. A chain line AA ′ and a chain line BB ′ in FIG. 8 correspond to a cross section obtained by cutting the top view of FIG. 1 with a chain line AA ′ and a chain line BB ′.

First, after obtaining the active matrix substrate in the state of FIG. 7 according to Example 2, spacers 515 are formed on the active matrix substrate of FIG. 8 using a photosensitive resin.

The arrangement of the spacers may be arbitrarily determined. For example, as shown in FIG. 8, the spacers may be arranged on the counter substrate so as to be positioned on the drain electrode (466) that also serves as a light shielding film. In addition, a spacer may be arranged on the counter substrate with its position aligned on the TFT of the driver circuit portion. This spacer may be disposed over the entire surface of the drive circuit portion, or may be disposed so as to cover the source wiring and the drain wiring.

After the formation of the spacers 515, an alignment film 506 is formed and a rubbing process is performed.

On the other hand, a counter substrate 507 is prepared. A light shielding film is formed over the counter substrate 507. When the substrate of FIGS. 1 and 2 of Example 1 is used, it is necessary to shield at least the light transmitting regions 123 to 126 of FIG. 2, so that the light shielding film is wider by 1 to 1.5 μm than the light shielding regions 123 to 126. Form.

Further, color filter layers 508 and 509 and an overcoat layer 510 are formed. Of the three primary color filter layers, two colors are shown. The color filter layer for each color is formed by mixing a pigment with an acrylic resin and has a thickness of 1 to 3 μm. This can be formed in a predetermined pattern using a photosensitive material and a mask. The overcoat layer 510 is formed of a photocurable or thermosetting organic resin material, and for example, polyimide or acrylic resin is used.

After forming the overcoat layer 510, the counter electrode 512 is formed by patterning,
After the alignment film 513 is formed, a rubbing process is performed.

Then, the active matrix substrate on which the pixel portion and the driver circuit portion are formed and the counter substrate are attached to each other with a sealant 513. By bonding the active matrix substrate and the counter substrate so that the rubbing directions are orthogonal to each other, the alignment of the liquid crystal becomes the TN system. A filler is mixed in the sealant 513, and the two substrates are bonded to each other with a uniform interval by the filler and the spacer 515. Thereafter, liquid crystal 514 is injected between both substrates, and a sealing agent (
Seal completely with (not shown). A known liquid crystal material may be used for the liquid crystal 514. Thus, the active matrix type liquid crystal display device shown in FIG. 8 is completed.

Note that the TFT formed by the above process has a top gate structure, but the present invention can be applied to a TFT having a bottom gate structure and other structures.

Also, instead of liquid crystal material, EL (Electro Luminescence)
The present invention can also be applied to an EL display device that is a self-luminous image display device using a material.

An example of the present invention will be described with reference to a top view of the pixel TFT in FIG. Compared with the layout of the pixel portion of Embodiment 1, the transparent pixel electrode 316 can be overlapped above the source wiring 302, so that the aperture ratio can be increased.

Example 4 is a direct-view transmissive liquid crystal display device. Red, blue and green color filters are formed. In a pixel in which a green color filter with high specific visibility is formed, light leakage due to disclination is clearly seen compared to red and blue pixels. For this reason, the area of the light shielding region is changed in accordance with the relative visibility of the pixel.

In Example 1, since the capacitor electrode is a light shielding film, the area of the light shielding region has to be the same in each pixel. In Example 4, since the drain electrode that is in direct contact with the transparent pixel electrode is used as the light shielding film, the area of the light shielding region can be changed according to the display color of the pixel.

As in the first embodiment, the layout is such that the disclination is efficiently hidden by using only two metal film wiring pattern masks.

The rubbing direction is set to an angle of 45 ° with respect to one side of the substrate in order to obtain a symmetrical viewing angle characteristic. The orientation is a TN system. The light shielding area is set from the relationship between the rubbing direction and the disclination. The relationship between the rubbing direction and the light shielding area is shown in FIG.

As shown in FIG. 9, the element substrate includes a gate wiring 311 arranged in the row direction, a source wiring 302 arranged in the column direction, and a pixel portion having a pixel TFT near the intersection of the gate wiring and the source wiring. And a driving circuit having an n-channel TFT and a p-channel TFT.

However, the gate wiring in FIG. 9 indicates a connection with the gate electrode 303 arranged in the row direction. The gate wiring 311 is provided in contact with the second interlayer insulating film.

The first semiconductor layer 300 and the second semiconductor layer 301 are patterned. The first semiconductor layer 300 is an active layer of the TFT element. The second semiconductor layer 301 functions as a capacitor electrode of a storage capacitor described later.

A source wiring 302 and a gate electrode 303 are formed so as to be in contact with a gate insulating film (not shown).

After forming the first interlayer insulating film and the second interlayer insulating film (not shown), the first semiconductor layer 30
0, contact holes 304 to 308 reaching the second semiconductor layer 301 and the source wiring 302
317 is opened. Next, a connection electrode 309, a drain electrode 310, a gate wiring 311, a capacitor connection electrode 312, drain electrodes 313 to 314 that also serve as a light shielding film, and a light shielding film 315 for blue display pixels are formed by patterning.

Via the connection electrode 309 by the contact hole 304 and the contact hole 305,
The first semiconductor layer 300 and the source wiring 302 are electrically connected.

Through the contact hole 306, the drain electrode 3 serving as the first semiconductor layer 300 and the light-shielding film
13-314 are electrically connected. Contact hole 317 and drain electrodes 313 to 31
4 is electrically connected.

Through the contact hole 307, the second semiconductor layer 301 and the capacitor connection electrode 312 are electrically connected.

Through the contact hole 308, the gate electrode 303 and the gate wiring 311 are electrically connected.

Further, the transparent pixel electrode 316 is replaced by the drain electrode 310 and the capacitor contact side electrode 3 without using an insulating film.
12, the drain electrodes 313 to 314 that also serve as a light shielding film and the light shielding film 315 of the blue display pixel are formed so as to overlap.

Accordingly, the capacitor connection electrode 312 is electrically connected to the transparent pixel electrode 315 and applies a potential to the second semiconductor layer 301 that functions as an electrode of the storage capacitor. A storage capacitor is formed by the gate electrode 303 and the island-shaped semiconductor layer 301. The gate insulating film functions as an insulating film for the storage capacitor.

The gate wiring 311, the connection electrode 309, the drain electrode 310, and the drain electrodes 313 to 314 that also serve as a light shielding film protect the first semiconductor layer 300 that is an active layer of the TFT element from external light. It is possible to prevent deterioration of the device due to light and potential fluctuation due to photocurrent.

The drain electrode 310 and the drain electrodes 313 to 314 that also serve as a light shielding film are formed above the source wiring 302 with the first interlayer insulating film and the second interlayer insulating film interposed therebetween. Thereby, the disclination which can be made on the side rubbed ahead of the element substrate can be hidden.

Further, in the present embodiment, the drain electrode 3 that also serves as a light shielding film according to the display color of each pixel.
The area of 13-314 is changed.

Assuming that the relative visibility of green (wavelength 555 nm) is 1, the relative visibility of red (wavelength 650 nm) is 0.11, and the relative visibility of blue (wavelength 450 nm) is 0.04. Compared with a single wavelength,
Red is about 3 times brighter than blue, and green is about 25 times brighter. FIG. 24 shows the wavelength dependence of specific luminous efficiency.
Shown in

In other words, light leakage is conspicuous for pixels displaying green with high relative visibility. Therefore, priority is given to contrast, and the area of the drain electrode 313 also serving as a light-shielding film is widened so that disclination can be reliably shielded. . For pixels displaying red, a light shielding electrode 314 that also serves as a light shielding film is provided with a narrow width. For the blue color, priority is given to the brightness, so that only a part of the light shielding film 315 of the blue display pixel is formed.

In this embodiment, the area of the light-shielding electrode for each color is determined in consideration of only the specific luminous efficiency. However, the area of the light-shielding electrode may be determined in consideration of both the specific luminous efficiency and the transmittance of the color filter. The area of the light shielding electrode may be determined in consideration of both the specific visibility and the wavelength distribution of the light source.

With the pixel layout described above, light leakage due to liquid crystal disclination can be effectively concealed by using only two wiring pattern masks.

FIG. 10 shows a light shielding region 318 of the element substrate. Since the light is shielded by only two wiring pattern masks, there is an area where light passes, but the edge of the area where the disclination appears is hidden, so even if the alignment of the light shielding film on the counter substrate is slightly misaligned, light leakage Can hide. Even if the light shielding film on the counter substrate is widened, the area of the light shielding region is smaller than that of the light shielding region of the element substrate. Does not drop.

In order not to make the light leakage due to disclination inconspicuous and not to impair the brightness, the aperture ratio of the red display pixel 328 and the green display pixel 32 according to the relative visibility.
The aperture ratio of 9 and the aperture ratio of the blue display pixel 330 are changed.

A cross-sectional view of the element substrate of FIG. 9 is shown in FIG. The chain line EE ′, the chain line FF ′ in FIG.
A chain line GG ′ indicates that FIG. 9 is cut by a chain line EE ′, a chain line FF ′, and a chain line GG ′. FIG. 11 is produced by adding the following steps to the substrate shown in FIG. This will be described with reference to FIG.

First, a first interlayer insulating film 323 is formed with a thickness of 100 to 200 nm using a silicon oxynitride film. A second interlayer insulating film 324 made of an organic insulating material is formed thereon. Next, an etching process for forming a contact hole is performed.

In the driver circuit portion, source wirings 328 to 330 that form contacts with the source region of the island-shaped semiconductor layer, and drain wirings 331 to 333 that form contacts with the drain region.
Form.

In the pixel portion, a connection electrode 309, a drain electrode 310, a gate wiring 311, a capacitor connection electrode 312, and drain electrodes 313 to 314 that also serve as a light shielding film are formed. The film thickness is 0.
3 μm to 0.75 μm is desirable.

The connection electrode 309 is electrically connected to the source wiring 302 and the first semiconductor layer 300. Although not shown, the gate wiring 311 is electrically connected to the gate electrode 303 through a contact hole. The capacitor connection electrode 312 is electrically connected to the second semiconductor layer 301.

Thereafter, a transparent conductive film is formed on the entire surface, and a transparent pixel electrode 316 is formed by patterning processing and etching processing using a photomask. The film thickness is desirably 100 nm to 1400 nm. The transparent pixel electrode 316 is formed so as to overlap the drain electrode 310 of the pixel TFT 321. A potential is applied to the island-shaped semiconductor film 301 functioning as an electrode of the storage capacitor 322 by the transparent pixel electrode 316.

The material of the transparent conductive film is indium oxide (In ₂ O ₃ ) or indium oxide tin oxide alloy (I
n ₂ O ₃ -SnO _2; ITO film) can be used as formed by using a sputtering or a vacuum evaporation method. Etching treatment of such a material is performed with a hydrochloric acid based solution. But,
In particular, since etching of the ITO film tends to generate residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and thermal stability with respect to the ITO film, even if Al is used for the drain electrode 316, corrosion reaction with Al in contact with the surface can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.

11B, the present embodiment is characterized in that the areas of the drain electrodes 313 to 314 that also serve as a light shielding film are changed according to the display color of the pixel. Source wiring 3
In order to conceal light leakage due to disclination that can occur in the vicinity of 25 to 327, a drain electrode 313 that also serves as a light-shielding film with a large area is used in green with high relative visibility of the display color. In the case of red in which the relative luminous sensitivity of the display color is lower than that of green, the drain electrode 314 that also serves as a light-shielding film having a slightly narrow area is used. In the blue display pixel, priority is given to the aperture ratio, and a light shielding film is formed only in a portion where light leakage is strongly recognized.

As described above, a driver circuit portion including an n-channel TFT, a p-channel TFT, and an n-channel TFT and a pixel portion including the pixel TFT 321 and the storage capacitor 322 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

When low-temperature polysilicon is used for the active layer of the TFT element, the drive circuit TFT and the pixel TFT are
It can be manufactured on a single substrate. At this time, an n-channel TFT and a p-channel TFT are necessary to manufacture a CMOS driving circuit.

According to the manufacturing process of the element substrate of Example 2 and this example, the number of masks necessary for forming the element substrate having the pixel portion having the pixel structure shown in FIGS. Good.

That is, the first sheet is a mask for patterning the first semiconductor layer 300 and the second semiconductor layer 301, and the second sheet is a mask for patterning the source wiring 302 and the gate electrode 303.
The first is a doping mask of an impurity imparting p-type, and the fourth is the first semiconductor layer 300 and the second
A mask for forming contact holes reaching the semiconductor layer 301, the source wiring 302, and the gate electrode 303, respectively, and the fifth layer also serves as a connection electrode 309, a drain electrode 310, a gate wiring 311, a capacitor connection electrode 312, and a light shielding film Drain electrodes 313 to 314, light shielding film 31
5 is a mask for patterning, and the sixth is a mask for patterning the transparent pixel electrode 316.

As described above, in the case of the pixel structure shown in FIGS. 9 to 11, a transmissive liquid crystal display device with good contrast can be realized without increasing the number of masks of the element substrate in order to form the light shielding film. . Since it is sufficient to form a light-shielding film on the counter substrate as a supplement, light leakage due to misalignment of bonding and a decrease in aperture ratio do not occur so much.

Furthermore, since the pixel electrode can be formed so as to overlap the source wiring as compared with the first embodiment, the aperture ratio can be increased. In addition, since the light shielding region is determined according to the relative luminous sensitivity of the display color, it is possible to suppress the decrease in the aperture ratio and secure the contrast.

Example 5 shows another embodiment of the present invention. An example in which the present invention is applied to a projection-type transmissive liquid crystal display device will be described.

As in the fourth embodiment, since the transparent pixel electrode overlaps the source wiring, the aperture ratio is higher than that in the first embodiment.

The rubbing direction is set at an angle of 45 ° with respect to one side of the substrate in order to facilitate the optical axis alignment of the optical system of the projection type apparatus. For this reason, the light shielding area is set in accordance with the disclination that appears when rubbing in the 45 ° direction.

As shown in FIGS. 12 and 13, the element substrate includes a gate wiring 211 arranged in the row direction, a source wiring 202 serving as a light shielding film arranged in the column direction, and the vicinity of the intersection of the gate wiring and the source wiring. A pixel portion having a pixel TFT and a driving circuit having an n-channel TFT or a p-channel TFT.

However, the gate wirings in FIGS. 12 and 13 indicate those connected to the gate electrode 203 also serving as a light shielding film arranged in the row direction. The gate wiring is provided on and in contact with the second interlayer insulating film.

The first semiconductor layer 200 and the second semiconductor layer 201 are patterned. The first semiconductor layer 200 is an active layer of the TFT element. The second semiconductor layer 201 functions as a capacitor electrode of a storage capacitor described later.

A source wiring 202 also serving as a light shielding film and a gate electrode 203 also serving as a light shielding film are formed so as to be in contact with a gate insulating film (not shown). The disclination of the liquid crystal tends to appear strongly near the edge of the transparent pixel electrode 214 described later and on the side of the four corners of the transparent pixel electrode 214 that is rubbed ahead of the element substrate. Therefore, the source wiring 202 that also serves as a light shielding film and the gate electrode 203 that also serves as a light shielding film cover the edge of the transparent pixel electrode, and the shape of the four corners of the transparent pixel electrode can be shielded from light. To do.

After forming a first interlayer insulating film and a second interlayer insulating film (not shown), contact hole 2
04 to 208 are opened, and a connection electrode 209, a drain electrode 210, a gate wiring 211, a capacitor connection electrode 212, and a light shielding electrode 213 are formed.

Via the connection electrode 209 by the contact hole 204 and the contact hole 205,
The first semiconductor layer 200 and the source wiring 202 are electrically connected.

The first semiconductor layer 200 and the drain electrode 210 are electrically connected through the contact hole 206.

Through the contact hole 207, the second semiconductor layer 201 and the capacitor connection electrode 212 are electrically connected.

Through the contact hole 208, the gate electrode 203, which also serves as a light shielding film, and the gate wiring 211 are electrically connected.

Further, the transparent pixel electrode 214, the light-shielding electrode 213, and the capacitor connection electrode 21 are not provided without an insulating film.
2. It is formed so as to overlap the drain electrode 120.

Accordingly, the capacitor connection electrode 212 is electrically connected to the transparent pixel electrode 214 and applies a potential to the second semiconductor layer 201 functioning as an electrode of the storage capacitor. Gate electrode 2 also serving as a light-shielding film
03 and the second semiconductor layer 201 form a storage capacitor. The gate insulating film functions as an insulating film for the storage capacitor.

The gate wiring 211, the connection electrode 209, and the drain electrode 210 protect the first semiconductor layer 200, which is the active layer of the TFT element, from external light. It is possible to prevent deterioration of the device due to light and potential fluctuation due to photocurrent.

The shape of the source wiring 202 that also functions as a light shielding film and the shape of the gate electrode 203 that also functions as a light shielding film can be characterized to reliably hide light leakage that strongly occurs on the side that is rubbed first among the four corners of the transparent pixel electrode 214. it can. Hide disclinations that have a significant impact on visibility. In other words, in addition to the wiring shape extending in the column direction, the source wiring 202 that also serves as a light shielding film is formed into a triangular projection shape to shield the position where the disclination appears. In addition, the gate electrode 203 also serving as a light shielding film
A part of the triangle is shaped like a triangle to shield the disclination. Further, a part of the gate electrode 203 also serving as a light shielding film is formed in a gap between the gate wiring 211 and the transparent pixel electrode 214 to shield light leakage due to disclination.

Since the source wiring 202 and the gate electrode 203 are formed in the same layer, there is a gap for preventing a short circuit. This gap is an area where strong disclination occurs due to source line inversion driving. For this reason, the light shielding electrode 213 is formed through the insulating film.

With the pixel layout described above, light leakage due to liquid crystal disclination can be effectively concealed by using only two wiring pattern masks.

FIG. 14 shows a light shielding region 215 of the element substrate of FIG. Since the light is shielded by only two wiring pattern masks, there is an area where light passes, but the edge of the area where the disclination appears is hidden, so even if the alignment of the light shielding film on the counter substrate is slightly misaligned, light leakage Can hide. In addition, even if the light shielding film of the counter substrate is widened, the light shielding region of the counter substrate exists inside the light shielding region of the element substrate. A reduction in the aperture ratio can be prevented.

A cross-sectional view of the element substrate of FIGS. 12 and 13 is shown in FIG. Chain line HH ′, chain line I— in FIG.
I ′ and chain line JJ ′ are the same as those in FIGS. 12 and 13, the chain line HH ′, chain line II ′, and chain line JJ ′.
Shown after cutting. FIG. 15 is produced by adding the following steps to the substrate shown in FIG. This will be described with reference to FIG.

First, the first interlayer insulating film 215 is formed using a silicon oxynitride film with a thickness of 100 to 200 nm. A second interlayer insulating film 216 made of an organic insulating material is formed thereon. Next, an etching process for forming a contact hole is performed.

In the driver circuit portion, source wirings 217 to 219 that form contacts with the source region of the island-shaped semiconductor layer, and drain wirings 220 to 222 that form contacts with the drain region.
Form.

In the pixel portion, a connection electrode 209, a drain electrode 210, a gate wiring 211, and a capacitor connection electrode 212 are formed. The film thickness is desirably 0.3 μm to 0.75 μm.

The connection electrode 209 is electrically connected to the source wiring 202 serving also as a light shielding film and the first semiconductor layer 200. Although not shown, the gate wiring 211 is a gate electrode 203 that also serves as a light shielding film.
Are electrically connected to each other through a contact hole. The capacitor connection electrode 212 is the second semiconductor layer 20.
1 is electrically connected.

Thereafter, a transparent conductive film is formed on the entire surface, and a transparent pixel electrode 214 is formed by patterning processing and etching processing using a photomask. The film thickness is desirably 100 nm to 1400 nm. The transparent pixel electrode 214 is formed so as to overlap the drain electrode 210 of the pixel TFT 222. In addition, a potential is applied to the island-shaped semiconductor film 201 that functions as an electrode of the storage capacitor 223.

The material of the transparent conductive film is indium oxide (In ₂ O ₃ ) or indium oxide tin oxide alloy (I
n ₂ O ₃ -SnO _2; ITO film) can be used as formed by using a sputtering or a vacuum evaporation method. Etching treatment of such a material is performed with a hydrochloric acid based solution. But,
In particular, since etching of the ITO film tends to generate residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to the ITO film, even when Al is used for the drain electrode 210, corrosion reaction with Al in contact with the surface can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.

15B, in this embodiment, the gate electrode 203 is formed in the gap between the gate wiring 211 and the transparent pixel electrode 214, and the gate electrode 203 is used as a film that blocks light leakage due to disclination. Yes. A first interlayer insulating film 215 and a second interlayer insulating film 216 are between the transparent pixel electrode 214 and the gate electrode 203.

As described above, a driver circuit portion including an n-channel TFT, a p-channel TFT, and an n-channel TFT and a pixel portion including the pixel TFT 222 and the storage capacitor 223 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

When low-temperature polysilicon is used for the active layer of the TFT element, the drive circuit TFT and the pixel TFT are 1
It can be manufactured on a single substrate. At this time, an n-channel TFT and a p-channel TFT are necessary to manufacture a CMOS driving circuit.

According to the manufacturing process of the element substrate of Example 2 and this example, the number of masks necessary for forming the element substrate having the pixel portion having the pixel structure shown in FIGS. Good. Furthermore, since the pixel electrode can be formed so as to overlap the source wiring as compared with the first embodiment, the aperture ratio can be increased.

That is, the first sheet is a mask for patterning the first semiconductor layer 200 and the second semiconductor layer 201, and the second sheet is a source wiring 202 that also serves as a light shielding film and a gate electrode 203 that also serves as a light shielding film.
The third mask is a p-type impurity doping mask, the fourth mask is a contact hole-forming mask, the fifth mask is a connection electrode 209, the drain electrode 210,
A mask for patterning the gate wiring 211, the capacitor connection electrode 212, and the light shielding electrode 213;
The first sheet is a mask for patterning the transparent pixel electrode 214.

As described above, when the pixel structure shown in FIGS. 12 to 15 is used, a transmissive liquid crystal display device with good contrast can be realized without increasing the number of masks of the element substrate in order to form the light shielding film. . Since a light-shielding film may be supplementarily formed on the counter substrate, light leakage due to misalignment of bonding and a decrease in aperture ratio can be prevented.

In this embodiment, another manufacturing method of a crystalline semiconductor layer for forming a TFT semiconductor layer of the active matrix substrate shown in Embodiment 2 will be described. In this embodiment, Japanese Patent Laid-Open No. 7-130652.
A crystallization method using a catalyst element disclosed in Japanese Patent Publication No. H11 can also be applied. An example in that case will be described below.

In the same manner as in Example 2, a base film and an amorphous semiconductor layer are formed on a glass substrate with a thickness of 25 to 80 nm. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, an aqueous solution containing 10 ppm of the catalyst element in terms of weight is applied by a spin coating method to form a layer containing the catalyst element. Catalyst elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu
), Gold (Au), and the like. For the layer 170 containing the catalyst element, the layer of the catalyst element may be formed to a thickness of 1 to 5 nm by a sputtering method or a vacuum deposition method in addition to the spin coating method.

In the crystallization step, first, heat treatment is performed at 400 to 500 ° C. for about 1 hour, so that the hydrogen content of the amorphous silicon film is 5 atom% or less. Then, using a furnace annealing furnace, thermal annealing is performed at 550 to 600 ° C. for 1 to 8 hours in a nitrogen atmosphere. Through the above steps, a crystalline semiconductor layer made of a crystalline silicon film can be obtained.

If an island-shaped semiconductor layer is produced from the crystalline semiconductor layer produced in this manner, Example 2 is obtained.
The active matrix substrate can be completed in the same manner as described above. However, when a catalyst element that promotes crystallization of silicon is used in the crystallization process, a small amount (about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ) of the catalyst element remains in the island-like semiconductor layer. To do. Of course, it is possible to complete the TFT even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region. One means for removing this catalytic element is a means that utilizes the gettering action of phosphorus (P).

The gettering process using phosphorus (P) for this purpose can be performed simultaneously in the activation step described with reference to FIG. The concentration of phosphorus (P) necessary for gettering may be approximately the same as the impurity concentration in the high-concentration n-type impurity region, and the n-channel T
Phosphorus (P) at the concentration of the catalyst element from the channel formation region of FT and p-channel TFT
It is possible to segregate into an impurity region that contains. As a result, the impurity region is 1 × 10
A catalytic element of about ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ was segregated. The TFT manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 5.

The CMOS circuit and the pixel portion formed by implementing the present invention can be used for various semiconductor devices (active matrix liquid crystal display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these semiconductor devices are incorporated in the display portion. Sensors may be incorporated in the following devices to detect the external brightness and reduce the brightness in dark places to reduce power consumption.

FIG. 18A illustrates a mobile phone, which includes a main body 9001, an audio output unit 9002, and an audio input unit 90.
03, a display device 9004, an operation switch 9005, and an antenna 9006. The present invention can be applied to a display device 9004 including an audio output unit 9002, an audio input unit 9003, and an active matrix substrate.

FIG. 18B shows a video camera, which includes a main body 9101, a display device 9102, and an audio input unit 9.
103, an operation switch 9104, a battery 9105, and an image receiving unit 9106.
The present invention relates to a display device 910 including a voice input unit 9103 and an active matrix substrate.
2. It can be applied to the image receiving unit 9106.

FIG. 18C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention relates to a display device 9 having an image receiving portion 9203 and an active matrix substrate.
205 can be applied.

FIG. 18D illustrates a head mounted display which includes a main body 9301 and a display device 9302.
The arm portion 9303 is configured. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.

FIG. 18E illustrates a television which includes a main body 9401, speakers 9402, and a display device 9403.
, Receiving device 9404, amplifying device 9405 and the like. The liquid crystal display device shown in Embodiment 5 and the EL display device shown in Embodiment 6 or 7 can be applied to the display device 9403.

FIG. 18F illustrates a portable book, which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, operation switches 9505, and an antenna 9506, and data stored on a minidisc (MD) or DVD, The data received by the antenna is displayed. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to them.

FIG. 18A illustrates a personal computer, which includes a main body 9601, an image input portion 9602,
A display device 9603 and a keyboard 9604 are included.

FIG. 18B shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded. The main body 9701, a display device 9702, a speaker portion 9703, and a recording medium 970 are shown.
4 and operation switch 9705. This apparatus uses a DVD (Di as a recording medium).
gial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games, and the Internet.

FIG. 18C illustrates a digital camera, which includes a main body 9801, a display device 9802, and an eyepiece unit 98.
03, an operation switch 9804, and an image receiving unit (not shown).

FIG. 18A illustrates a front projector, which includes a display device 9901 and a screen 99.
02. The present invention can be applied to display devices and other signal control circuits.

FIG. 18B shows a rear projector, which includes a main body 10001, a projection device 10002,
A mirror 10003 and a screen 10004 are included. The present invention can be applied to display devices and other signal control circuits.

Note that FIG. 18C illustrates a projection device 9901 in FIGS. 18A and 18B.
It is the figure which showed an example of the structure of 10002. The projection devices 9901 and 10002 include a light source optical system 10101, mirrors 10102, 10104 to 10106, and dichroic mirror 10.
103, a prism 10107, a liquid crystal display device 10108, a retardation plate 10109, and a projection optical system 10110. The projection optical system 10110 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

FIG. 18D illustrates an example of the structure of the light source optical system 10201 in FIG. In this embodiment, the light source optical system 10201 includes a reflector 10211, a light source 10212, lens arrays 10213 and 10214, a polarization conversion element 10215, and a condenser lens 10216. Note that the light source optical system illustrated in FIG. 18D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

Claims (2)

A first transistor, a second transistor, a first color filter, and a second color filter;
The first transistor includes:
A first gate electrode; a first semiconductor layer; a first gate insulating layer between the first gate electrode and the first semiconductor layer; a first source electrode; and a first drain. An electrode, and
The first drain electrode is electrically connected to the first pixel electrode;
The second transistor is
A second gate electrode; a second semiconductor layer; a second gate insulating layer between the second gate electrode and the second semiconductor layer; a second source electrode; and a second drain. An electrode, and
The second drain electrode is electrically connected to the second pixel electrode;
The first color filter has a function of transmitting green light;
The second color filter has a function of transmitting red light,
The first pixel electrode has a region overlapping with the first color filter,
The second pixel electrode has a region overlapping with the second color filter,
The width of the first drain electrode is larger than the width of the second drain electrode. In claim 1,
The semiconductor device, wherein the first drain electrode and the second drain electrode have a light shielding property.

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