JP2017175360A - Clock generator circuit and clock generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generator circuit which can be suitably used as a clock source in an LSI for an OA device such as a laser printer.SOLUTION: A clock generator circuit 1 comprises: a PLL circuit 10 which divides, by a divider, one output clock of output clocks of multiple phases in frequency to generate feedback clocks, and which generates output clocks of multiple phases as a result of multiplication of reference clocks based on a result of detection of the phase difference between the reference clocks and the feedback clocks; a control part which determines a frequency division number of the feedback clocks, required for frequency modulation; an SDM which instructs the divider of a division ratio to realize the frequency division number determined by the control part; and a clock selector circuit which selects the output clock for the divider to divide in frequency. When it is decided that a predetermined internal value of the SDM satisfies a predetermined requirement before and after a predetermined period to perform a frequency modulation in, the clock selector circuit changes the output clock for the divider to divide in frequency.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a clock generation circuit and a clock generation method, and more particularly to a clock generation circuit and a clock generation method used in a laser printer or the like.

  The clock generation circuit is a circuit that generates a clock signal (hereinafter referred to as “clock”) necessary for the operation of an electronic device including a logic circuit such as a microprocessor, and typically includes a PLL (Phase Locked Loop) circuit. It is configured. Some clock generation circuits can generate a modulated clock.

  For example, the following Patent Document 1 discloses a multi-phase clock generator, a multi-carrier random selection module that generates a control signal corresponding to each clock generated by the multi-phase clock generator, and the multi-phase clock generator based on the control signal. A clock selector that selects any one of a plurality of clocks generated by phase clocks, the clock selector selecting the control signals in order and then selecting the control signals in the reverse order; Disclosed is a clock generation circuit which is supposed to perform clock modulation.

  Further, Patent Document 2 below describes an edge of a phase shift clock signal that is selected so that the phase controller changes its period from the period of the output clock signal by a predetermined first phase shift amount. Determining and selecting a phase of the second phase shift amount, periodically generating a second phase shift amount and adding the second phase shift amount to the first phase shift amount, determining a phase of an edge of the selected phase shift clock signal, Disclosed is a clock generation circuit that performs spread spectrum modulation on an output clock signal with a phase shift amount of 2, and changes the phase data selected immediately after the phase data update signal is updated.

  Incidentally, the clock generation circuit as described above is also used as a clock source in an LSI (Large-Scale Integration) such as a laser printer.

  The laser printer has a configuration in which light emitted from the semiconductor laser device is scanned in the main scanning direction using a polygon mirror and an fθ lens to expose the photosensitive member. For this reason, distortions such as polygon mirrors and fθ lenses, and other manufacturing errors can affect the image quality of printed matter. As a method for solving such a problem, it is conceivable to process a polygon mirror, an fθ lens, or the like with high accuracy. However, such processing leads to an increase in cost. Therefore, in laser printers, attempts have been made to correct distortion such as polygon mirrors and fθ lenses, other manufacturing errors, and the like by modulating the clock.

  For example, Patent Document 3 below proposes, as a correction method, changing the phase of a clock used for driving a polygon mirror or the like using phase shift amount data. Japanese Patent Application Laid-Open No. 2004-228620 proposes modulating a clock used for driving a semiconductor laser as a correction method. Further, Patent Document 5 below proposes, as a correction method, controlling light emission of the semiconductor laser by a modulation signal generated from a reference clock.

JP2013-258544A Japanese Patent Laying-Open No. 2015-122644 JP 2003-34051 A JP 2006-259444 A JP 2004-195827 A

  In the laser printer technology, there is a continuous demand for further improvement in image quality of printed matter. Therefore, in a laser printer that corrects distortions such as the polygon mirror and fθ lens described above and other manufacturing errors by modulating the clock, a clock generation circuit used as a clock source can provide a more accurate clock. Need to be modulated.

  For this reason, for example, the clock generation circuits disclosed in Patent Documents 1 and 2 described above may be used as the clock sources of the techniques disclosed in Patent Documents 3 to 5 described above. However, the clock generation circuits disclosed in Patent Documents 1 and 2 are not intended to be used as a clock source in a laser printer, and cannot deal with a specific problem that occurs in the laser printer.

  Therefore, an object of the present invention is to provide a clock generation circuit and a clock generation method that can be suitably used as a clock source in an OA LSI such as a laser printer.

  The present invention for solving the above-described problems is configured to include the following invention specific items or technical features.

  That is, the invention according to a certain aspect is a clock generation circuit that generates a multiphase output clock frequency-modulated from a reference clock. The clock generation circuit generates a feedback clock by dividing one output clock among the multiphase output clocks by a frequency divider, and based on a detection result of a phase difference between the reference clock and the feedback clock, A PLL circuit that generates the multi-phase output clock multiplied by a reference clock, a control unit that determines the frequency division number of the feedback clock required for the frequency modulation, and the frequency division number obtained by the control unit An SDM for instructing the frequency divider to achieve the frequency division, and a clock selection circuit for selecting the output clock to be frequency-divided by the frequency divider, the clock selection circuit comprising: When it is determined that a predetermined internal value satisfies a predetermined requirement before and after a predetermined period for performing the frequency modulation, the output clock to be frequency-divided by the frequency divider is changed.

  Here, the clock selection circuit satisfies the predetermined requirement based on an integration unit that integrates a fractional part of the division number obtained by the control unit within the predetermined period, and an integration result by the integration unit. And a determination unit that determines whether or not.

  The determination unit may determine that the predetermined requirement is satisfied when a result of integration by the integration unit is an integer value.

  The clock selection circuit further includes a selection unit that selects the output clock, and when the determination unit determines that the predetermined requirement is satisfied, the clock selection circuit selects the output clock selected by the selection unit. A frequency divider can be used.

  The selector may sequentially select one output clock from the multiphase output clocks.

  In addition, the selection unit may randomly select one output clock from the multiphase output clocks.

  The clock selection circuit further includes a signal generation unit that counts the feedback clock and generates a start signal and an end signal, and the clock selection circuit receives the start signal from the signal generation unit and then outputs the end signal. The period until receipt is the predetermined period.

  The clock selection circuit further includes a signal generation unit that counts the feedback clock and generates a start signal and an end signal, and the clock selection circuit receives a predetermined number of times of the start signal from the signal generation unit, The predetermined period may be a period until the predetermined number of end signals are received.

  The invention according to a certain aspect is a clock generation method for generating a multi-phase output clock frequency-modulated from a reference clock. In this clock generation method, one output clock among the multiphase output clocks is divided by a frequency divider to generate a feedback clock, and based on the detection result of the phase difference between the reference clock and the feedback clock, Generating a multi-phase output clock multiplied by a reference clock; obtaining a frequency division number of the feedback clock required for the frequency modulation; and dividing a frequency division ratio for realizing the frequency division by an SDM Instructing the frequency divider and determining that the predetermined internal value of the SDM satisfies a predetermined requirement before and after a predetermined period for performing the frequency modulation. Changing the output clock to be divided.

  Here, the determination as to whether or not the predetermined requirement is satisfied may be made based on a result of integrating the fractional part of the frequency division number obtained within the predetermined period.

  Further, when the integrated result is an integer value, it can be determined that the predetermined requirement is satisfied.

  According to the present invention, the clock generation circuit and the clock generation method can be suitably used as a clock source in an OA LSI such as a laser printer.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a block diagram for demonstrating the clock generation circuit which concerns on one Embodiment of this invention. It is a figure explaining the relationship between the setting signal in the clock generation circuit which concerns on one Embodiment of this invention, and the frequency of an output clock. 4 is a timing chart of various signals in the clock generation circuit according to the embodiment of the present invention. It is a block diagram for demonstrating SDM of the clock generation circuit which concerns on one Embodiment of this invention. 6 is a table for explaining the SDM operation of the clock generation circuit according to the embodiment of the present invention. It is a figure which shows the relationship between the output of SDM of the clock generation circuit which concerns on one Embodiment of this invention, and output clock CLK. It is a wave form diagram showing an example of output clock CLK of the clock generation circuit concerning one embodiment of the present invention. It is a wave form diagram which shows an example of output clock CLK of the clock generation circuit based on a prior art. It is a flowchart explaining the clock generation method which concerns on one embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and technical applications that are not explicitly described below. The present invention can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match actual dimensions and ratios. In some cases, the dimensional relationships and ratios may be different between the drawings.

  FIG. 1 is a block diagram for explaining a clock generation circuit according to an embodiment of the present invention. As shown in the figure, the clock generation circuit 1 includes a PLL circuit 10, a modulation control circuit 20, and a clock selection circuit 30.

  The PLL circuit 10 includes, for example, a phase detection circuit 11, a charge pump 12, a loop filter 13, an oscillation frequency control unit 14, a selector 15, and a frequency divider 16. The PLL circuit 10 is supplied with a reference clock REFCLK having a reference frequency from a transmission source (not shown), and outputs a multiphase output clock CLK.

  The phase detection circuit 11 compares the reference clock REFCLK received from the outside with the feedback clock FBCLK received from the frequency divider 16, detects the phase difference, and generates a phase difference signal corresponding to the phase difference. Specifically, when the phase of the feedback clock FBCLK is delayed with respect to the reference clock REFCLK, the phase detection circuit 11 outputs an up signal UP having a pulse width corresponding to the phase difference. On the other hand, when the phase of the feedback clock FBCLK is advanced with respect to the reference clock REFCLK, the phase detection circuit 11 outputs a down signal DN having a pulse width corresponding to the phase difference.

  The charge pump 12 receives the up signal UP and the down signal DN output from the phase detection circuit 11, and outputs a current corresponding to them. Specifically, when the charge pump 12 receives the up signal UP from the phase detection circuit 11, the charge pump 12 outputs a current that is larger by a unit current. On the other hand, when the charge pump 12 receives the down signal DN from the phase detection circuit 11, the charge pump 12 outputs a current smaller by a unit current.

  The loop filter 13 is, for example, a low-pass filter circuit, and the output voltage changes according to the current supplied from the charge pump 12.

  The oscillation frequency control unit 14 oscillates at a frequency corresponding to the output voltage of the loop filter 13, generates an output clock CLK, and outputs the output clock CLK to the outside and the selector 15. The oscillation frequency control unit 14 is designed so that, for example, the oscillation frequency increases as the output voltage of the loop filter 13 increases. The oscillation frequency control unit 14 is configured to output a multi-phase output clock CLK, and outputs, for example, an 8-phase output clock CLK. The oscillation frequency control unit 14 is, for example, a ring oscillator in which a plurality of stages of inverter elements are connected in a ring shape, but is not limited thereto.

  The selector 15 selects any one of the multiphase output clocks CLK received from the oscillation frequency control unit 14 and outputs the selected output clock CLK to the frequency divider 16. The selector 15 determines an output clock CLK to be selected based on an instruction received from the selector 35 of the clock selection circuit 30.

  The frequency divider 16 divides the output clock CLK received from the selector 15 by a frequency dividing ratio instructed from the modulation control circuit 20 to generate a feedback clock FBCLK and outputs it to the phase detection circuit 11. In addition, the frequency divider 16 outputs the feedback clock FBCLK to the signal generation unit 21, the control unit 23, the SDM (Sigma-Delta Modulator) 24 of the modulation control circuit 20, and the integration unit 33 of the clock selection circuit 30. .

  The modulation control circuit 20 includes, for example, a signal generation unit 21, a storage unit 22, a control unit 23, and an SDM 24.

  The signal generator 21 receives the feedback clock FBCLK, counts the number of clocks, generates a start signal START indicating the start of the predetermined period, and an end signal END indicating the end of the predetermined period, and the control unit 23 and The data is output to the integrating unit 33. Here, for example, when the clock generation circuit 1 is used as a clock source in a laser printer LSI, the predetermined period is a period during which the semiconductor laser scans the first line of an image to be printed.

  The storage unit 22 includes, for example, a RAM (Random Access Memory) and a register, and stores information indicating the modulation content of the output clock CLK performed by the clock generation circuit 1. The storage unit 22 reads out stored information in synchronization with the storage unit clock SCLK received from the control unit 23, and outputs it to the control unit 23 as a setting signal SET.

  The information included in the setting signal SET can be, for example, frequency increase / decrease when performing frequency modulation of the output clock CLK, unit frequency fluctuation amount, and the number of times of unit frequency fluctuation. For example, in order to perform frequency modulation of the output clock CLK as shown in FIG. 2, the setting signal SET includes information for increasing the frequency, information for setting the unit frequency fluctuation amount α, and information for performing the unit frequency fluctuation eight times. Including. In the figure, the vertical axis represents the frequency of the output clock CLK, and the horizontal axis represents the number of unit frequency fluctuations, which represents an example of frequency modulation of the output clock CLK.

  In addition to the information described above, the setting signal SET may include information related to the basic value of the fractional multiplication of the reference clock REFCLK performed in the clock generation circuit 1.

  The control unit 23 receives the start signal START, the end signal END, and the setting signal SET, generates an integer multiplication signal IM and a decimal multiplication signal FM, and outputs them to the SDM 24. Specifically, the control unit 23 receives the setting signal SET from the storage unit 22 based on the start signal START and the end signal END, interprets the setting signal SET, and generates the reference clock REFCLK performed by the clock generation circuit 1. An integer multiplication signal IM indicating the value of the integer part of the fractional multiplication and a fractional multiplication signal FM indicating the value of the decimal part are generated and output to the SDM 24. Note that the fractional multiplication value of the reference clock REFCLK is equal to the average value of the frequency division number of the feedback clock FBCLK.

  The SDM 24 receives the integer multiplication signal IM and the fractional multiplication signal FM, determines a frequency division ratio for realizing frequency multiplication of the reference clock REFCLK indicated in the signal, and instructs the frequency divider 16. Details of the SDM 24 will be described later.

  The clock selection circuit 30 includes, for example, a clock selection unit 31, a flip-flop 32, an integration unit 33, a determination unit 34, and a selector 35.

  The clock selection unit 31 selects the output clock CLK to be selected by the selector 15. For example, when the output clock CLK has eight phases, the clock selection unit 31 may sequentially select from the output clock CLK of the first phase. Further, the clock selection unit 31 may randomly select one output clock CLK from among the multiphase output clocks CLK. The clock selection unit 31 outputs the selection result as a signal to the flip-flop 32.

  The flip-flop 32 may be a so-called D-type flip-flop. The flip-flop 32 receives the signal from the clock selection unit 31 and the end signal END from the signal generation unit 21 of the modulation control circuit 20, latches the signal from the clock selection unit 31 according to the end signal END, and selects the selector 35. Output to.

  The integrating unit 33 receives the feedback clock FBCLK from the frequency divider 16 of the PLL circuit 10, the start signal START and end signal END from the signal generation unit 21 of the modulation control circuit 20, and the control unit 23 of the modulation control circuit 20. The fractional multiplication signal FM is received. The accumulator 33 operates in synchronization with the feedback clock FBCLK, accumulates the value indicated by the fractional multiplication signal FM, and subtracts the integer part from the start signal START until the end signal END is received. The number is reduced and output to the determination unit 34.

  The determining unit 34 performs a predetermined calculation on the integrated value obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM received from the integrating unit 33, and determines whether the result satisfies a predetermined determination criterion. to decide. The determination unit 34 instructs the selector 35 according to the determination result. The criteria for the determination performed by the determination unit 34 will be described later.

  The selector 35 receives a signal from the flip-flop 32, a zero signal 0, and an instruction from the determination unit 34. The selector 35 selects a signal from the flip-flop 32 and outputs it to the selector 15 when the determination unit 34 determines that the predetermined requirement is satisfied. Accordingly, the selector 15 selects the output clock CLK selected by the clock selection unit 31. On the other hand, if the determination unit 34 determines that the predetermined requirement is not satisfied, the selector 35 selects the zero signal 0 and outputs it to the selector 15. As a result, the selector 15 continues to select the output clock CLK that has been previously selected.

  FIG. 3 is a timing chart of various signals in the clock generation circuit according to the embodiment of the present invention. More specifically, this figure shows an example of frequency modulation of the output clock CLK based on reception of the setting signal SET by the control unit 23.

  As shown in the figure, the control unit 23 generates the internal clock ICLK after receiving the start signal START until receiving the end signal END, and further stores the storage unit clock SCLK from the start signal START and the internal clock ICLK. Is generated. The control unit 23 sequentially reads information necessary for performing one frequency modulation from the storage unit 22 in synchronization with the storage unit clock SCLK and receives it as a setting signal SET. The signals received as the setting signal SET by the control unit 23 are, for example, setting signals SET_F1, SET_F2, SET_F3, SET_F5, and SET_STAY as illustrated. Each setting signal SET is a value determined for the purpose of correcting distortion such as a polygon mirror and an fθ lens, and other manufacturing errors when the clock generation circuit 1 is used as a clock source in a laser printer LSI. Become.

  The control unit 23 generates an integer multiplied signal IM and a fraction multiplied signal FM shown in FIG. 1 based on each received setting signal SET, and outputs the generated signal to the SDM 24. Thereafter, processing is performed by the SDM 24 and the frequency division ratio of the frequency divider 16 is set, whereby the output clock CLK output from the oscillation frequency control unit 14 is modulated. That is, as shown in the figure, the frequency of the output clock CLK is modulated from the initial value F0 to F1 when the control unit 23 receives the setting signal SET_F1. Similarly, the frequency of the output clock CLK is modulated according to the setting signal SET received by the control unit 23. Further, when the control unit 23 receives the setting signal SET_STAY, the frequency of the output clock CLK is maintained as it is.

  FIG. 4 is a block diagram for explaining the SDM of the clock generation circuit according to the embodiment of the present invention. As shown in the figure, the SDM 24 includes, for example, an adder 241, an adder 242, a delay unit 243, a quantizer 244, and an adder 245. For the sake of explanation, the output from the adder 241 is output A, the output from the adder 242 is output B, the output from the delay unit 243 is output C, and the output from the quantizer 244 is output. Let D be the output from the adder 245.

  The adding unit 241 outputs a value obtained by subtracting the value of the output D received from the quantizing unit 244 from the value indicated by the decimal multiplication signal FM received from the control unit 23 as an output A to the adding unit 242.

  The adding unit 242 outputs a value obtained by adding the value of the output A received from the adding unit 241 and the value of the output C received from the delay unit 243 to the delay unit 243 as an output B.

  The delay unit 243 delays the output B received from the adder 242 by one clock of the feedback clock FBCLK, and outputs it as an output C to the adder 242 and the quantizer 244.

  When the value of the output C received from the delay unit 243 is 1 or more, the quantization unit 244 sets the value of the output D output to the adding unit 241 and the adding unit 245 to 1. On the other hand, when the value of the output C received from the delay unit 243 is less than 1, the quantization unit 244 sets the value of the output D output to the adding unit 241 and the adding unit 245 to 0.

  The adding unit 245 outputs a value obtained by adding the value indicated by the integer multiplied signal IM received from the control unit 23 and the value of the output D received from the quantizing unit 244 to the frequency divider 16 as an output E. To do. The value of the output E is the frequency division ratio of the output clock CLK performed by the frequency divider 16.

  FIG. 5 is a table for explaining the SDM operation of the clock generation circuit according to the embodiment of the present invention. This figure shows a state in which the multiplication number of the reference clock REFCLK performed by the clock generation circuit 1 is 8.2 times. Therefore, the value of the integer multiplication signal IM is 8, and the fractional multiplication signal FM The value of is 0.2. The SDM 24 starts from a predetermined state. Specifically, the output A start value is 0.2, the output B start value is 0.4, the output C start value is 0.2, and the output D start value is 0. The start value of output E is 8.

  As shown in the figure, the value of the output E is 8 during the period from the first clock to the third clock of the feedback clock FBCLK. Therefore, in this period, the frequency division ratio of the frequency divider 16 is set to 8.

  Further, at the fourth clock of the feedback clock FBCLK, the value of the output E is 9 based on the value of the output D being 1. Therefore, the frequency division ratio of the frequency divider 16 is set to 9 at the fourth clock of the feedback clock FBCLK. Then, at the fifth clock of the feedback clock FBCLK, the value of the output E returns to 8, and the frequency dividing ratio of the frequency divider 16 returns to the state set to 8.

  Thereafter, the value of the output E is set to 8 or 9 in the same cycle. That is, the output E takes 8 periods in the period of 4 clocks in the period of 5 clocks of the feedback clock FBCLK, and 9 in the period of 1 clock. As a result, since the average value of the value of the output E within one period is 8.2, the clock generation circuit 1 realizes multiplication of the reference clock REFCLK by 8.2 times.

  FIG. 6 is a diagram illustrating a relationship between the output of the SDM of the clock generation circuit according to the embodiment of the present invention and the output clock CLK. In the figure, the vertical axis represents the frequency of the output clock CLK, and the horizontal axis represents the number of feedback clocks FBCLK. In the figure, it is assumed that the value of the output E output from the SDM 24 to the frequency divider 16 changes as shown in FIG.

  As shown in the figure, the frequency of the output clock CLK is constant from the set frequency when the value of the output E output from the SDM 24 to the frequency divider 16 is switched from 8 to 9 and from 9 to 8. The time is significantly off. As a result, the fluctuation range ΔF of the frequency of the output clock CLK is locally increased. Even if the value of the output E is 8 and a certain period, the frequency of the output clock CLK slightly fluctuates with respect to the set frequency, but this inevitably occurs.

  Here, as described above, when the frequency of the output clock CLK greatly deviates locally from the set frequency, the jitter component of the output clock CLK increases. For example, when the clock generation circuit 1 is used as a clock source in a laser printer LSI, the increase in the jitter component described above appears as a local distortion in the printed image.

  Since the laser printer has a configuration in which the semiconductor laser scans for each line of the image to be printed, printing is performed when the above-described local increase in jitter components occurs at the same timing in each scan. It appears as continuous distortion in the sub-scan line direction of the image.

  In the present invention, as a countermeasure against this, the clock generation circuit 1 changes the output clock CLK selected by the selector 15 based on the determination result in the determination unit 34 shown in FIG.

  Specifically, the determination unit 34 first makes a determination based on whether or not the integrated value obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM obtained by the integrating unit 33 and subtracting the value is 0. . Then, when the determination unit 34 determines that the integrated value obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM obtained by the integration unit 33 and subtracting the value is 0, the determination unit 34 sends the selector 35 to the flip-flop 32. Let the signal be selected. Accordingly, the selector 35 outputs the selection result by the clock selection unit 31 to the selector 15, so that the selector 15 changes the output clock CLK to be selected to the output clock CLK having the phase selected by the clock selection unit 31.

  Here, the integrated value obtained by subtracting the integer part of the value indicated by the above-described decimal multiplication signal FM is a fractional multiplication during the period from when the integration unit 33 receives the start signal START until the end signal END is received. This is a value obtained by integrating the values indicated by the signal FM and subtracting the integer part thereof. For example, when the SDM 24 whose operation example is shown in FIG. 5 is adopted and the fractional multiplication signal is 0.2, the integration unit 33 obtains the integration value obtained by subtracting the integer part of the value indicated by the fractional multiplication signal FM and reducing it to the feedback clock. When the fractional multiplication signal FM from the 1st clock to the 5th clock of FBCLK is integrated, the integration value of the value indicated by the fractional multiplication signal FM becomes 1, so that it becomes 0 by subtracting the integer part therefrom.

The total number of values that the decimal multiplication signal FM can take is determined by the number of operations of the SDM 24 to be employed. For example, when the SDM 24 whose operation example is shown in FIG. 5 is adopted, the decimal multiplication signal FM can take values of 0, 0.2,..., 0.6, and 0.8. The total number of values that FM can take is 5. Similarly, when the SDM 24 having a calculation number of 16 bits is adopted, the total number of values that the decimal multiplication signal FM can take is 2 ¹⁶ .

  When the definition is made as described above, the integrated value of the value indicated by the fractional multiplication signal FM obtained by the integrating unit 33 becomes an integer value or 0 indicates that the output C of the SDM 24 has returned to the start value. means. For example, in the SDM 24 whose operation example is shown in FIG. 5, when the period during which the determination unit 34 integrates the fractional multiplication signal FM is from the first clock to the fifth clock of the feedback clock FBCLK, the fractional multiplication signal FM obtained by the integration unit 33. The integrated value of the values indicated by becomes zero when the integer part is subtracted. In this case, the value of the output C of the SDM 24 returns to the start value of 0.2.

  Thus, when the value of the output C of the SDM 24 returns to the start value, the value of the output E changes at the same timing. For example, in the SDM 24 whose operation example is shown in FIG. 5, the value of the output E changes to 9 after 4 clocks from the first clock, but the start value of the output C is the same as that of the first clock. Similarly, when starting from the eye, the value of the output E changes to 9 after 4 clocks. Therefore, the jitter component increases at the same timing as it is, and when the laser printer is used as the clock source, continuous distortion appears in the sub-scan line direction of the printed image.

  Therefore, as described above, in the clock generation circuit 1, the integrated value of the value indicated by the fractional multiplication signal FM obtained by the integrating unit 33 becomes 0 when the integer part is reduced, so that the determining unit 34 outputs the output of the SDM 24. It is determined that the value of C has returned to the start value, and the output clock CLK selected by the selector 15 is changed to the output clock CLK selected by the clock selector 31. As a result, the clock generation circuit 1 generates the output clock CLK based on the reference clock REFCLK and the feedback clock FBCLK obtained by frequency-dividing the output clock CLK having a different phase from the previous one by the frequency divider 16, so that the C value of the SDM 24 is Even in the state of returning to the start value, an increase in the jitter component occurs at different timings. Therefore, when the clock generation circuit 1 is used as a clock source for a laser printer, continuous distortion can be prevented from appearing in the sub-scan line direction of the printed image.

  FIG. 7A is a waveform diagram showing an example of the output clock CLK of the clock generation circuit according to the embodiment of the present invention. FIG. 7B is a waveform diagram showing an example of an output clock of the clock generation circuit according to the related art shown for comparison. In these figures, it is assumed that the clock generation circuit is used as a clock source in a laser printer LSI, and that one line scan of an image to be printed by a semiconductor laser is performed three times in succession. Yes. The output clock CLK has eight phases. Further, scanning of the first line of the image to be printed by the semiconductor laser is started from the time of START, and scanning of the first line of the image to be printed by the semiconductor laser is completed at the time of END, and then the next line It is assumed that a blanking period is reached until this scan is started. In the first line, the output clock CLK divided by the frequency divider 16 is assumed to be a first phase clock.

  As shown in FIG. 7A, in the clock generation circuit 1, the integration result obtained by subtracting the integer part of the value indicated by the fractional multiplication signal FM received by the determination unit 34 from the integration unit 33 at the end of the scan of the first line is When 0, the output clock CLK selected by the clock selection unit 31 is changed to be divided by the frequency divider 16. For example, when the clock selector 31 selects the fourth phase output clock, the frequency divider 16 divides the fourth phase output clock CLK.

  In the clock generation circuit 1, when the output clock CLK to be frequency-divided by the frequency divider 16 is switched during the blanking period, the output clock CLK is stabilized by the time the second line scan is started. . Therefore, the scan of the second line starts from the rise of the output clock CLK of the fourth phase. Based on the above, the clock generation circuit 1 can prevent the influence of switching of the output clock CLK divided by the frequency divider 16 on the image printed by the laser printer.

  In the clock generation circuit 1, when the integration result obtained by subtracting the integer part of the value indicated by the fractional multiplication signal FM received by the determination unit 34 from the integration unit 33 is 0 even at the end of scanning of the second line, the clock selection is performed. The output clock CLK selected by the unit 31 is changed to be divided by the frequency divider 16. For example, when the clock selection unit 31 selects the sixth phase output clock, the frequency divider 16 divides the sixth phase output clock CLK. As a result, the clock generation circuit 1 can prevent continuous distortion from appearing in the sub-scanning line direction of the printed image.

  On the other hand, as shown in FIG. 7B, the clock generation circuit according to the related art starts scanning in synchronization with the clock of the same first phase even in the scan of the second line when the setting is not particularly changed. Here, when the value of the output C of the SDM 24 is the same at the start of scanning of the first line and at the start of scanning of the second line, the timing at which the value of the output E of the SDM 24 changes is the same. Continuous distortion appears in the sub-scan line direction.

  FIG. 8 is a flowchart for explaining a clock generation method according to an embodiment of the present invention. Such a clock generation method is a process executed in the clock generation circuit 1.

  As shown in the figure, the selector 15 selects one output clock CLK from the multiphase output clock CLK (S801). For example, the selector 15 may select the first phase output clock CLK from among the multiphase output clocks CLK. The output clock CLK selected by the selector 15 is divided by the frequency divider 16 in order to generate the feedback clock FBCLK. Subsequently, the oscillation frequency control unit 14 starts generating and outputting the output clock CLK at a frequency corresponding to the output voltage of the loop filter 13 (S802).

  Subsequently, the control unit 23 determines whether or not the start signal START is received from the signal generation unit 21 (S803). When the control unit 23 has received the start signal START (Yes in S803), the control unit 23 creates the integer multiplication signal IM and the fractional multiplication signal FM based on the setting signal SET signal received from the storage unit 22 ( S804). On the other hand, when the control unit 23 has not received the start signal START (No in S803), the control unit 23 stands by in that state.

  Subsequently, in the clock generation circuit 1, two processes are performed in parallel or in parallel. First, the SDM 24 receives the integer multiplication signal IM and the fractional multiplication signal FM from the control unit 23, determines a division ratio that needs to be performed by the frequency divider 16 based on them, and determines the division. The data is output to the device 16 (S805). As a result, the output clock CLK output from the oscillation frequency control unit 14 is frequency-modulated according to the setting signal SET. Next, as a second, the integrating unit 33 integrates the value indicated by the decimal multiplication signal FM received from the control unit 23 (S806).

  After the processes of S805 and S806, the control unit 23 determines whether or not the end signal END is received from the signal generation unit 21 (S807). When the control unit 23 has not received the end signal END (No in S807), the control unit 23 returns to S804 and continues the processing. On the other hand, when the control unit 23 receives the end signal END (Yes in S807), the integration unit 33 outputs the integration result obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM to the determination unit 34 (S808). .

  Subsequently, the determination unit 34 determines whether or not the integration result obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM received from the integration unit 33 is 0 (S809). When the determination unit 34 determines 0 (Yes in S809), the determination unit 34 causes the selector 15 to select the output clock CLK selected by the clock selection unit 31 via the selector 35, thereby dividing the frequency. The output clock CLK to be frequency-divided by the device 16 is changed (S810). Thereafter, the clock generation circuit 1 returns to S803 and continues the processing. If the determination unit 34 determines that it is not 0 (No in S809), the clock generation circuit 1 returns to S803 and continues the process.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, in the clock generation circuit 1, in S809 of FIG. 8, when the integration result obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM received from the integration unit 33 is 0, the subsequent operation of the decimal multiplication signal FM is performed thereafter. The output clock CLK divided by the frequency divider 16 may be changed to the output clock CLK selected by the clock selection unit 31 every time the end signal END is received without performing the integration.

  In S809 of FIG. 8, when the integration result obtained by subtracting the integer part of the value indicated by the decimal multiplication signal FM received from the integration unit 33 is not 0, the clock generation circuit 1 performs the subsequent integration of the decimal multiplication signal FM. Alternatively, the output clock CLK divided by the frequency divider 16 may not be changed.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  The present invention can be widely used in the field of electronic devices including a clock generation circuit.

DESCRIPTION OF SYMBOLS 1 ... Clock generation circuit 10 ... PLL circuit 11 ... Phase detection circuit 12 ... Charge pump 13 ... Loop filter 14 ... Oscillation frequency control part 15 ... Selector 16 ... Frequency divider 20 ... Modulation control circuit 21 ... Signal generation part 22 ... Memory | storage part 23 ... Control unit 24 ... SDM
241 ... Adder 242 ... Adder 243 ... Delay 244 ... Quantizer 245 ... Adder 30 ... Clock selector 31 ... Clock selector 32 ... Flip-flop 33 ... Integrator 34 ...: Determiner 35 ... Selector

Claims (11)

A clock generation circuit for generating a multi-phase output clock frequency-modulated from a reference clock,
The output clock of one of the multiphase output clocks is divided by a frequency divider to generate a feedback clock, and the reference clock is multiplied based on the detection result of the phase difference between the reference clock and the feedback clock. A PLL circuit that generates a multi-phase output clock;
A control unit for determining a frequency division number of the feedback clock necessary for the frequency modulation;
An SDM for instructing the frequency divider to realize a frequency division ratio determined by the control unit;
A clock selection circuit for selecting the output clock to be frequency-divided by the frequency divider;
With
The clock selection circuit changes the output clock to be divided by the frequency divider when it is determined that a predetermined internal value of the SDM satisfies a predetermined requirement before and after a predetermined period for performing the frequency modulation. To
Clock generation circuit. The clock selection circuit includes:
An accumulator for accumulating the decimal part of the multiplication number obtained by the control unit within the predetermined period;
A determination unit that determines whether or not the predetermined requirement is satisfied based on a result of integration by the integration unit;
The clock generation circuit according to claim 1, comprising:   The clock generation circuit according to claim 2, wherein the determination unit determines that the predetermined requirement is satisfied when a result of integration by the integration unit is an integer value. The clock selection circuit includes:
A selection unit for selecting the output clock;
4. The clock generation circuit according to claim 2, wherein the determination unit divides the output clock selected by the selection unit by the frequency divider when determining that the predetermined requirement is satisfied. 5.   The clock generation circuit according to claim 4, wherein the selection unit sequentially selects one output clock from the multiphase output clocks.   The clock generation circuit according to claim 4, wherein the selection unit randomly selects one output clock from the multiphase output clocks. A signal generator for counting the feedback clock and generating a start signal and an end signal;
2. The clock generation circuit according to claim 1, wherein the clock selection circuit sets the predetermined period after receiving the start signal from the signal generation unit until receiving the end signal. A signal generator for counting the feedback clock and generating a start signal and an end signal;
2. The clock selection circuit according to claim 1, wherein the period from when the predetermined number of start signals are received from the signal generation unit to when the predetermined number of end signals is received is the predetermined period. Clock generation circuit. A clock generation method for generating a multi-phase output clock frequency-modulated from a reference clock,
The output clock of one of the multiphase output clocks is divided by a frequency divider to generate a feedback clock, and the reference clock is multiplied based on the detection result of the phase difference between the reference clock and the feedback clock. Generating a polyphase output clock;
Obtaining a frequency division number of the feedback clock necessary for the frequency modulation;
Obtaining a frequency division ratio for realizing the frequency division number by SDM and instructing the frequency divider;
Changing the output clock to be divided by the frequency divider when it is determined that a predetermined internal value of the SDM satisfies a predetermined requirement before and after a predetermined period for performing the frequency modulation;
Including a clock generation method.   10. The clock generation method according to claim 9, wherein the determination as to whether or not the predetermined requirement is satisfied is performed based on a result obtained by integrating a fractional part of the frequency division number obtained within the predetermined period.   The clock generation method according to claim 10, wherein when the integrated result is an integer value, it is determined that the predetermined requirement is satisfied.