JP2017152647A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device suppressing an increase in circuit area, and suppressing malfunctions caused by a surge and the like.SOLUTION: A semiconductor device according to one embodiment comprises: a first transistor that has a drain connected with an input/output terminal and a source is connected with a first power supply line; a second transistor that has a drain connected with the first power supply line and a source connected with a second power supply line; a first diode that has an anode connected with the second power supply line; an N-type MOS transistor that has a drain connected with a gate of the second transistor and a source connected with a cathode of the first diode; and an inner circuit that has one end connected with the first power supply line, and the other end connected with the second power supply line.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

A protection circuit is known in which a transistor is arranged between a high-voltage power supply and a low-voltage power supply in order to protect the internal circuit from surges and the like.

JP 2013-197128 A

The problem to be solved by the present embodiment is to provide a semiconductor device that suppresses an increase in circuit area and suppresses malfunction due to a surge or the like.

In the semiconductor device of the present embodiment, the drain is connected to the input / output terminal, the source is connected to the first power supply line, the drain is connected to the first power supply line, and the source is connected to the second power supply line. A second transistor connected, a first diode having an anode connected to the second power supply line, a drain connected to the gate of the second transistor, and a source connected to the cathode of the first diode The MOS transistor includes an internal circuit having one end and the other end, one end connected to the first power supply line and the other end connected to the second power supply line.

1 is a circuit diagram showing a semiconductor device according to a first embodiment. Sectional drawing which shows the semiconductor device concerning 1st embodiment. Sectional drawing which shows the semiconductor device of a comparative example. A circuit diagram showing a semiconductor device concerning a second embodiment. A circuit diagram showing a semiconductor device concerning a third embodiment. Sectional drawing which shows the semiconductor device concerning 3rd embodiment.

(First embodiment)
A circuit of the semiconductor device according to the first embodiment will be described below with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, in the drawings, the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones and are schematic.

FIG. 1 is a circuit diagram of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device according to the present embodiment includes a high-voltage power supply line 20 connected to the high-voltage power supply 2 and a low-voltage power supply line 40 connected to the low-voltage power supply 4. P-type MOS transistor 3 and N-type MOS connected to at least one of the high-voltage power supply line 20 and the low-voltage power supply line 40
Transistor 5, diode 6, resistor 7, N-type MOS transistor 13, and internal circuit 18
And an N-type MOS transistor 8 connected to the diode 6. A power supply voltage Vdd is applied to the high-voltage power supply 2 and a ground voltage Vss is applied to the low-voltage power supply 4.

The P-type MOS transistor 3 has a drain connected to the input / output terminal 1 and a source and gate connected to the high-voltage power supply line 20. The N-type MOS transistor 5 has a drain connected to the high voltage side power supply line 20 and a source connected to the low voltage side power supply line 40. The diode 6 has an anode connected to the low-voltage power supply line 40 and a cathode connected to the source of the N-type MOS transistor 8. The drain and gate of N-type MOS transistor 8 are connected to the gate of N-type MOS transistor 5.

A resistor 7 is connected between the gate of the N-type MOS transistor 5 and the low-voltage power supply line 40. An N-type MOS transistor 1 having a drain connected to the input / output terminal 1 and a source and a gate connected to the low-voltage power supply line 40 between the input / output terminal 1 and the low-voltage power supply line 40.
3.

An internal circuit 18 is connected between the high-voltage power supply line 20 and the low-voltage power supply line 40. N so that no surge flows into the internal circuit 18 when a surge is applied to the high-voltage power line 20.
The type MOS transistor 5 becomes conductive, and a surge flows from the high voltage side power supply line 20 to the low voltage side power supply line 40.

As the N-type MOS transistor 5, it is desirable to use a high breakdown voltage transistor because the N-type MOS transistor 5 is turned on by flowing an overcurrent due to a surge.

The resistor 7 is inserted in order to suppress the destruction of the N-type MOS transistor 5 due to the increase in the voltage difference between the gate of the N-type MOS transistor 5 and the low-voltage side power supply line 40, but to obtain the effect of this embodiment. Is not always necessary.

  The diode 6 can be a Zener diode, but is not limited thereto.

The diode 6 is inserted in order to lower the gate voltage of the N-type MOS transistor 5 and suppress the spread of the voltage between the gate and the source of the N-type MOS transistor 5. When a voltage higher than the breakdown voltage of the diode 6 is applied to the cathode of the diode 6, the diode 6
Flows current and suppresses the voltage rise of the N-type MOS transistor 5. In the present embodiment, when a voltage equal to or higher than the breakdown voltage of the diode 6 is applied to the N-type MOS transistor 8, the N-type MOS transistor 8 becomes conductive, and a current flows through the diode 6.

The N-type MOS transistor 8 is provided to suppress a rise in the voltage of the gate of the N-type MOS transistor 5 when a positive surge is applied to the input / output terminal 1, and is not limited to the N-type MOS transistor.

Hereinafter, an operation when a positive surge is applied to the input / output terminal 1 in a state where a voltage is applied to the high-voltage power supply line 20 and the low-voltage power supply line 40 will be described with reference to FIG.

FIG. 2 is a cross-sectional view of the P-type MOS transistor 3, the N-type MOS transistor 5, the diode 6, the resistor 7, and the N-type MOS transistor 8 of the semiconductor device according to this embodiment.

N surrounding the drain 8a, source 8b and P-type region 8c of the N-type MOS transistor 8
A mold region 8 d is formed on the P-type substrate 9. This N-type region 8 d is connected to the high-voltage side power supply line 20. Between the N-type MOS transistor 8 and the P-type substrate 9, there is formed a parasitic diode 12 having the P-type substrate 9 as an anode and the N-type region 8d as a cathode.

The N-type region 3c of the P-type MOS transistor 3 is located around the drain 3a and the source 3b formed of P-type. Between the P-type MOS transistor 3 and the P-type substrate 9, there is formed a parasitic PNP transistor 10 having the N-type region 3c as a base, the P-type substrate 9 as a collector, and the drain 3a as an emitter.

N surrounding the drain 5a, source 5c and P-type region 5d of the N-type MOS transistor 5
A mold region 5 e is formed on the P-type substrate 9. The source 5c is connected to the low voltage side power line 40,
The drain 5 a is connected to the high voltage side power supply line 20.

In the diode 6, an N-type region 6 b surrounding the P-type region 6 a is formed on the P-type substrate 9. Between the diode 6 and the P-type substrate 9, there is formed a parasitic diode 11 having the P-type substrate 9 as an anode and the N-type region 6b as a cathode.

When a voltage is applied to the high-voltage power supply line 20 and the low-voltage power supply line 40, a parasitic PNP
A voltage is applied to the N-type region 3 c that is the base of the transistor 10. When a positive surge is applied to the input / output terminal 1 in a state where a voltage is applied to the N-type region 3c, a parasitic PNP
A voltage is also applied to the drain 3 a which is the emitter of the transistor 10. Therefore, the parasitic PNP transistor 10 is turned on, and a current flows through the P-type substrate 9. When the parasitic PNP transistor 10 is turned on and current flows, current also flows through the parasitic diode 11. However, in the parasitic diode 11, since the current path in the direction of the gate 5b of the N-type MOS transistor 5 is blocked by the N-type MOS transistor 8, the voltage of the gate 5b of the N-type MOS transistor 5 does not increase.

Similarly, when the parasitic PNP transistor 10 is turned on and current flows, current also flows through the parasitic diode 12. However, the N-type region 8d which is the cathode of the parasitic diode 12 is N
Since it surrounds the MOS transistor 8 and is connected to the high-voltage side power supply line 20, the N-type MO
No current flows through the drain 8 a and the source 8 b of the S transistor 8.

  Next, a comparative example of the semiconductor device according to the present embodiment will be described.

The comparative example is a case where the N-type MOS transistor 8 is not provided in the circuit diagram shown in FIG. The circuit diagram of the comparative example is the same as the configuration of FIG. 1 except that the N-type MOS transistor 8 is omitted.

3 shows a P-type MOS transistor 3, an N-type MOS transistor 5, and a semiconductor device of a comparative example.
A sectional view of a diode 6 and a resistor 7 is shown. Hereinafter, an operation when a positive surge is applied to the input / output terminal 1 while a voltage is applied to the high-voltage power supply line 20 and the low-voltage power supply line 40 in FIG. 3 will be described.

As shown in FIG. 3, a parasitic PNP transistor 10 and a parasitic PN diode 11 are also formed in the comparative example.

The input / output terminal 1 with voltage applied to the high-voltage power line 20 and the low-voltage power line 40
When a positive surge is applied to the parasitic PNP transistor 10, the parasitic PNP transistor 10 is turned on and current flows. When a current flows through the parasitic PNP transistor 10, a current also flows through the parasitic PN diode 11. Since the parasitic diode 11 is connected to the gate 5b of the N-type MOS transistor 5, the voltage of the gate 5b of the N-type MOS transistor 5 is increased.

When the voltage of the gate 5b of the N-type MOS transistor 5 rises, the N-type MO which is in the off state
The S transistor 5 is turned on. Due to this malfunction, for example, the high-voltage power line 20
Through current flows from the low-voltage side power supply line 40 to the N-type MOS transistor 5, there is a risk of destruction.

Further, the increased gate voltage may exceed the breakdown voltage of the gate insulating film of the N-type MOS transistor 5, so that the gate insulating film of the N-type MOS transistor 5 may be destroyed.

For these reasons, it is necessary to increase the distance between the P-type MOS transistor 3 and the diode 6 and the N-type MOS transistor 5. In this case, the problem is that the chip size increases.

In the semiconductor device according to the present embodiment, the N-type MOS transistor 8 is interposed between the gate of the N-type MOS transistor 5 and the diode 6. As a result, it is possible to cut off the current flowing toward the N-type MOS transistor 5 and suppress the voltage rise of the gate 5b of the N-type MOS transistor 5. As a result, malfunctions and destruction of the gate insulating film can be avoided.

In the comparative example, the effect cannot be obtained unless the distance between the P-type MOS transistor 3 and the N-type MOS transistor 5 is sufficiently larger than the size of the N-type MOS transistor 8. Therefore, the chip size of the semiconductor device of the present embodiment in which the N-type MOS transistor 8 is newly provided can be made smaller than the chip size of the comparative example.

(Second embodiment)
Next, FIG. 4 shows a circuit diagram of the semiconductor device according to the second embodiment.

FIG. 4 shows an application of the circuit shown in the first embodiment to an RCTMOS circuit. RCT
The MOS circuit includes an RC timer circuit composed of a resistor 14 and a capacitor 15 and an N-type MOS transistor 5. The configuration of the semiconductor device of FIG. 4 is the same as that of FIG. 1 except for the resistor 14, the capacitor 15, and the inverter 16.

As the resistor 14, a polysilicon resistor, a bulk resistor, a wiring resistor, a diffused resistor, or the like can be used. As the capacitor 15, for example, MIM (Metal-Insulato
r-Metal) structure or MOS structure is used.

One end of the resistor 14 is connected to the high voltage side power supply line 20, and one end is connected to the other end of the capacitor 15. The other end of the capacitor 15 is connected to the low-voltage power supply line 40. The connection between the resistor 14 and the capacitor 15 is connected to the input of the inverter 16.

  Next, the operation of the RCTMOS circuit will be described.

When a surge is applied to the high-voltage power supply line 20, charging of the capacitor 15 via the resistor 14 is started. As a result, a voltage drop occurs in the resistor 14 and the voltage at the connection between the resistor 14 and the capacitor 15 is lowered.

Next, since the connection portion of the resistor 14 and the capacitor 15 is connected to the input of the inverter 16, the lowered voltage is output as a high voltage via the inverter 16. The high voltage output from the inverter 16 is supplied to the N-type MOS transistor 5, and the N-type MOS transistor is turned on. At this time, the source of the N-type MOS transistor 5 has a high voltage and the drain has a low voltage.

The capacitor 15 continues to be charged at the connection portion between the resistor 14 and the capacitor 15, and the voltage at the connection portion increases. When this voltage exceeds the threshold voltage of the inverter 16, the high voltage is
6 to output a low voltage. Therefore, the gate 5b of the N-type MOS transistor 5
Is supplied with a low voltage, and the N-type MOS transistor 5 is turned off.

Thus, while the capacitor 15 is charged, the N-type MOS transistor 5 is turned on, so that noise from the high-voltage side power line 20 can be released to the low-voltage side power line 40.

In this RCTMOS circuit, when the N-type MOS transistor 5, the diode 6 and the P-type MOS transistor 3 are arranged close to each other as shown in FIG. 4, the parasitic PNP transistor uses a current similar to the circuit shown in the comparative example of FIG. N-type MOS transistor 5 by flowing
This raises the voltage of the gate 5b. Therefore, the cathode of the diode 6 and the N-type MO
By interposing an N-type MOS transistor 8 between the gate 5b of the S transistor 5,
Similar to the circuit of the present embodiment shown in FIGS. 1 and 2, it is possible to prevent a current from flowing to the N-type MOS transistor 5 and to suppress a voltage rise of the gate 5b of the N-type MOS transistor 5. For this reason, it is possible to avoid a malfunction that the N-type MOS transistor 5 is turned on due to an increase in the voltage of the gate 5b of the N-type MOS transistor 5, and a breakdown of the gate insulating film. As a result, the N-type MOS transistor 5, the diode 6 and the P-type MOS transistor 3 can be arranged close to each other.

The semiconductor device according to the present embodiment needs to increase the distance between the P-type MOS transistor 3 and the N-type MOS transistor 5 by interposing the N-type MOS transistor 8 between the N-type MOS transistor 5 and the diode 6 in the RCTMOS circuit. As a result, the chip size can be reduced.

In this embodiment, the RCTMOS circuit is shown. However, in other circuits, an N-type MOS is used.
The present invention can also be applied when the distance between the transistor 5 and the P-type MOS transistor 3 is short.

(Third embodiment)
Next, a third embodiment will be described with reference to FIGS.

In the third embodiment, a diode is arranged in place of the N-type MOS transistor in the circuit of the semiconductor device shown in the first embodiment. In the following description of the semiconductor device, parts different from the first embodiment will be described, and similar parts will be omitted.

FIG. 5 is a circuit diagram of the semiconductor device according to the present embodiment. As shown in FIG. 5, the anode of the diode 17 is connected to the gate of the N-type MOS transistor 5, and the cathode of the diode 17 is connected to the cathode of the diode 6.

6 shows a cross-sectional view of the P-type MOS transistor 3, the N-type MOS transistor 5, the diode 6, the resistor 7, and the diode 17 of the semiconductor device shown in FIG. Hereinafter, FIG.
An operation when a positive surge is applied to the input / output terminal 1 in a state where a voltage is applied to the high-voltage power supply line 20 and the low-voltage power supply line 40 will be described.

As shown in FIG. 6, the diode 17 is composed of a PN junction between an N-type region 17b formed on the P-type substrate 9 and a P-type region 17a formed on the N-type region 17b. Between the diode 17 and the P-type substrate 9, the N-type region 17 of the diode 17 with the P-type substrate 9 as an anode.
A parasitic PN diode 19 having b as a cathode is formed.

When a voltage is applied to the high-voltage power supply line 20 and the low-voltage power supply line 40, a voltage is applied to the N-type region 3c serving as the base of the parasitic PNP transistor 10 as in the first embodiment. When a positive surge is applied to the input / output terminal 1 while a voltage is applied to the N-type region 3c, the parasitic PNP transistor 10 is turned on and a current flows.

When a current flows through the PNP transistor 10, a current also flows through the parasitic diode 19. However, the N-type region 17b of the parasitic diode 19 has no current path to the gate 5b of the N-type MOS transistor 5. Therefore, the voltage of the gate 5b of the N-type MOS transistor 5 does not rise, and N
The malfunction of the type MOS transistor 5 and the breakdown of the gate insulating film can be suppressed.

According to the semiconductor device according to the present embodiment, the diode 17 is interposed between the N-type MOS transistor 5 and the diode 6 to increase the voltage of the gate 5b of the N-type MOS transistor 5 as in the first embodiment. Can be suppressed. Therefore, unlike the comparative example shown in FIG. 3, it is not necessary to increase the distance between the N-type MOS transistor 5 and the P-type MOS transistor 3. As a result, the P-type MOS transistor 3 and the N-type MOS transistor 5 can be arranged close to each other, and the chip size can be reduced.

  The diode 17 may be a Zener diode, but is not limited to this.

The circuit of this embodiment can also be applied to other circuits including the RCTMOS circuit shown in the second embodiment.

Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Input / output terminal 2 High voltage side power supply 3 P-type MOS transistors 5, 8, 13 N-type MOS transistor
3a, 5a, 8a Drain
3b, 5c, 8b source
6b, 8d, 17b, 5e, 3c N-type region 4 Low voltage side power supply 5b Gate 6, 17 Diodes 6a, 17a, 5d, 8c P-type region 7, 14 Resistance 9 P-type substrate 10 Parasitic PNP transistors 11, 12, 19 Parasitic Diode 15 Capacitor 16 Inverter 18 Internal circuit

Claims (7)

A first transistor having a drain connected to the input / output terminal and a source connected to the first power supply line;
A second transistor having a drain connected to the first power supply line and a source connected to a second power supply line;
A first diode having an anode connected to the second power line;
An N-type MOS transistor having a drain connected to the gate of the second transistor and a source connected to the cathode of the first diode;
An internal circuit having one end and the other end, one end connected to the first power supply line and the other end connected to the second power supply line;
A semiconductor device. A first transistor having a drain connected to the input / output terminal and a source connected to the first power supply line;
A second transistor having a drain connected to the first power supply line and a source connected to a second power supply line;
A first diode having an anode connected to the second power line;
A second diode having an anode connected to the gate of the second transistor and a cathode connected to the cathode of the first diode;
An internal circuit having one end and the other end, one end connected to the first power supply line and the other end connected to the second power supply line;
A semiconductor device. A first transistor having a drain connected to the input / output terminal and a source connected to the first power supply line;
A second transistor having a drain connected to the first power supply line and a source connected to a second power supply line;
A first diode having an anode connected to the second power line;
An internal circuit having one end and the other end, one end connected to the first power supply line and the other end connected to the second power supply line;
A first circuit having one end and the other end, one end connected to the gate of the second transistor, the other end connected to the cathode of the first diode, and conducting at least when the breakdown voltage of the first diode is higher When,
A semiconductor device comprising: 4. The semiconductor device according to claim 3, wherein the first circuit is a diode or an N-type MOS transistor. The semiconductor device according to claim 1, wherein the first diode is a Zener diode. The first transistor is a P-type MOS transistor, and the second transistor is an N-type MOS
6. The semiconductor device according to claim 1, further comprising a transistor. An inverter having one end of the first circuit and the gate of the second transistor connected to the output;
A resistor having one end and the other end, one end connected to the first power supply line and the other end connected to the capacitor;
A capacitor having one end and the other end, one end connected to the second power supply line and the other end connected to a resistor;
With
The semiconductor device according to claim 3, wherein a connection portion between the resistor and the capacitor is connected to an input portion of the inverter.

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