JP2017028406A - Gate drive circuit for voltage-driven switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit of a voltage-driven switching device, capable of preventing, when providing an auxiliary power circuit in order to obtain the high speed charge and discharge of a gate capacitor, the insulation breakdown thereof even if a relatively low cost auxiliary power circuit having a low withstand voltage is used.SOLUTION: A gate drive circuit 10 includes a first drive circuit 18 and a second drive circuit 22. The first drive circuit 18 includes a constant voltage source 16, first ground GND1, a first switching device S1 and a second switching device S2. The second drive circuit 22 includes an auxiliary power 20 outputting a lower voltage than the constant voltage source 16, second ground GND2, a third switching device S3 and a fourth switching device S4. The second drive circuit is connected to the gate terminal 14 of the switching device 12 through a capacitor 26 having a withstand voltage characteristic of the voltage of the constant voltage source 16 or higher. The second drive circuit and the capacitor are connected to the gate terminal 14 in parallel with the first drive circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a gate drive circuit that drives the gate of a voltage-driven switching element.

  A gate drive circuit (gate driver) for controlling the gate terminal voltage is connected to the gate terminal of a voltage-driven switching element such as a MOSFET or IGBT. Through the control of the gate terminal voltage, on / off of the gate, that is, turn-on and turn-off of the switching element are controlled.

  In the switching element, parasitic capacitance is generated between each of the three terminals of the gate, the source, and the drain through the depletion layer. A gate capacitance Cg composed of a combined capacitance of a gate-source capacitance Cgs and a gate-drain capacitance Cgd is generated at the gate terminal.

  In order to switch the gate from off to on, that is, to raise the gate terminal voltage from a predetermined gate off voltage (for example, ground voltage) to the gate on voltage, it is necessary to charge the gate capacitance Cg. Similarly, in order to switch the gate from on to off, that is, to lower the gate terminal voltage from the gate on voltage to the gate off voltage, it is necessary to discharge the gate capacitance Cg. The gate driving circuit charges the gate capacitance Cg when the switching element is turned on, and discharges the gate capacitance Cg when the switching element is turned off.

  The period until the gate capacitance Cg is charged from the gate-off voltage to the gate-on voltage at the turn-on time, and the period until the gate capacitance Cg is discharged from the gate-on voltage to the gate-off voltage at the turn-off time are the on and off switching periods. Become. The longer the switching period, the lower the switching speed and the higher the switching loss.

  In order to increase the switching speed and reduce the switching loss, a technique for speeding up charging / discharging of the gate capacitance has been proposed. For example, in Patent Document 1, when an inductance component is formed on the source terminal side due to wiring being stranded, etc., a circuit including a gate capacitance and a capacitor for charging the gate capacitance is avoided. Forming. In Patent Document 2, when the gate capacitance is discharged, the gate capacitance is accelerated by applying a reverse bias to the gate capacitance by a charged capacitor. Patent Document 3 discloses a gate drive circuit in which a constant voltage circuit and a constant current circuit are connected in parallel to a gate terminal.

JP 2004-336533 A JP 2009-200891 A JP 2013-34382 A

  By the way, as in Patent Document 3 described above, an auxiliary power supply circuit such as a constant current circuit is connected in addition to the constant voltage circuit, and current is supplied simultaneously to the gate capacitance from the constant voltage circuit and the auxiliary power supply circuit. It is conceivable to shorten the charging period. Further, in the case where a ground path is provided in both the constant voltage circuit and the auxiliary power supply circuit, it is conceivable that the charge of the gate capacitance is discharged through both to shorten the discharge period of the gate capacitance.

  However, in such a configuration, in order to prevent dielectric breakdown, it is necessary for the auxiliary power supply circuit to have a withstand voltage characteristic higher than that of the constant voltage source during charging, and when discharging, the auxiliary power supply circuit is applied from a fully charged gate capacity. It is necessary to have a withstand voltage characteristic higher than the gate-on voltage. As a result, another problem arises in that the cost is increased, for example, the constituent elements of the auxiliary power supply circuit are composed of high withstand voltage elements. Therefore, the present invention provides a gate drive circuit for a voltage-driven switching element that can prevent dielectric breakdown even when an auxiliary power supply circuit with a relatively low cost and a low withstand voltage is used.

  The present invention relates to a gate drive circuit for a voltage-driven switching element. The drive circuit includes a first drive circuit and a second drive circuit. The first driving circuit is connected to the voltage source, the first ground, and the gate terminal of the voltage-driven switching element, and electrically connects the voltage source and the gate terminal when charging the gate capacitance of the voltage-driven switching element. A first switching element that is connected to the gate terminal, and a second switching element that conducts the gate terminal and the first ground when the gate capacitance is discharged. A second switching circuit configured to connect an auxiliary power source having a lower voltage than the voltage source; a second ground; and a gate terminal connected to the gate terminal to electrically connect the auxiliary power source and the gate terminal. And a fourth switching element connected to the gate terminal and conducting the gate terminal and the second ground when the gate capacitance is discharged. The second driving circuit is connected to the gate terminal via a capacitor having a withstand voltage characteristic equal to or higher than the voltage of the voltage source, and the second driving circuit and the capacitor are connected to the gate in parallel with the first driving circuit. Connected to the terminal.

  It is known that a capacitor conducts current (I = C × dV / dt) in a transient state where the voltage across the capacitor changes. Taking advantage of this characteristic, when the voltage fluctuates immediately after the start of charging / discharging of the gate capacitance, it is possible to quickly charge / discharge the gate capacitance using the second driving circuit via a capacitor in addition to the first driving circuit.

  In addition, by providing a capacitor, dielectric breakdown of the second drive circuit is prevented. For example, it is known that a capacitor has a potential difference (q = CV) between its both end electrodes according to the electric charge accumulated at both end electrodes. In other words, even if a high voltage is applied to the electrode on the first drive circuit side among the both end electrodes of the capacitor, the electrode potential on the second drive circuit side is reduced by the amount of accumulated charge in the capacitor. Thereby, application of a high voltage to the second drive circuit is avoided.

  In the above invention, a first diode having a forward direction from the auxiliary power source toward the gate terminal may be provided. The first diode may be disposed between a connection point connecting the capacitor and the third and fourth switching elements and the third switching element.

  With such a configuration, it becomes possible to cut off the flow of current from the first drive circuit to the second drive circuit when the gate capacitance is charged, and the current of the first drive circuit is supplied exclusively to the gate terminal. be able to.

  In the above invention, a second diode having a forward direction from the gate terminal toward the second ground may be provided. The second diode may be disposed between a connection point connecting the capacitor and the third and fourth switching elements and the fourth switching element.

  By providing such a configuration, it becomes possible to cut off the discharge current from the capacitor flowing from the second ground to the capacitor and from the capacitor through the first ground when the gate capacitance is discharged. As a result, interruption of the discharge current of the capacitor to the discharge path from the gate capacitance to the first ground can be prevented.

  In the above invention, the voltage Vcc2 of the auxiliary power source and the capacitance C1 of the capacitor are obtained by using the gate terminal voltage Vmrr (mirror voltage) in the mirror period when charging and discharging the gate capacitance Cg and the gate capacitance Cg. It may be determined so as to satisfy C1 × Vcc2 / (C1 + Cg) <Vmrr.

  As will be described later, the gate capacitance in the mirror period is larger than that in other periods. With the above configuration, current supply from the auxiliary power supply to the gate capacitance is stopped before the gate terminal voltage reaches the mirror voltage Vmrr, and a large current supply (surge) from the auxiliary power supply to the gate capacitance can be avoided.

  According to the present invention, even when an auxiliary power supply circuit having a low withstand voltage, which is relatively low in cost, is used, the dielectric breakdown can be prevented.

It is a figure which illustrates the gate drive circuit concerning this embodiment. It is a figure explaining the RC series circuit contained in the gate drive circuit which concerns on this embodiment. It is a time chart explaining the operation | movement at the time of turn-on of the switching element by the gate drive circuit which concerns on this embodiment. It is the figure which represented typically the flow of the electric current in the time t1-t2 of FIG. It is the figure which represented typically the flow of the electric current in the time t2-t3 and t4-t5 of FIG. It is the figure which represented typically the flow of the electric current in the time t3-t4 of FIG. It is a time chart explaining the operation | movement at the time of the turn-off of the switching element by the gate drive circuit which concerns on this embodiment. It is the figure which represented typically the flow of the electric current in the time t11-t12 of FIG. It is the figure which represented typically the flow of the electric current in the time t12-t13 of FIG. 7, and t14-t15. It is the figure which represented typically the flow of the electric current in the time t13-t14 of FIG. It is a time chart explaining the operation | movement at the time of turn-on of a switching element when making high side resistance small relatively. It is a time chart explaining the operation | movement at the time of turn-off of a switching element when low side resistance is made relatively small. It is a figure which illustrates the gate drive circuit which concerns on another example of this embodiment. It is a figure explaining a mode that the electric current which flows into a 2nd drive circuit from a 1st drive circuit at the time of gate capacity charge is interrupted | blocked by a diode. It is a figure explaining a mode that the electric current which flows into 1st earth | ground from a capacitor | condenser at the time of gate capacity discharge is interrupted | blocked by a diode. It is a time chart explaining the operation | movement at the time of the turn-on of the switching element by the gate drive circuit which concerns on another example of this embodiment. It is a time chart explaining the operation | movement at the time of the turn-off of the switching element by the gate drive circuit which concerns on another example of this embodiment.

<Overall configuration>
A gate drive circuit 10 according to this embodiment is illustrated in FIG. The gate drive circuit 10 is connected to the gate terminal 14 of the voltage driven switching element 12. In FIG. 1, an IGBT (insulated gate bipolar transistor) is shown as an example of the voltage-driven switching element 12 to which the gate drive circuit 10 is connected.

  The gate drive circuit 10 includes a first drive circuit 18 having a constant voltage source 16, a second drive circuit 22 having an auxiliary power supply 20, and a control circuit 24. The second drive circuit 22 is connected to the gate terminal 14 in parallel with the first drive circuit 18 via a capacitor 26. The first drive circuit 18 and the second drive circuit 22 shown in FIG. 1 include a so-called low-side drive circuit that discharges the gate capacitor 30 in addition to a so-called high-side drive circuit that charges the gate capacitor 30. It has become.

  When the switching element 12 is turned on, the gate drive circuit 10 charges the gate capacitance 30 generated at the gate terminal 14 to raise the gate terminal voltage Vgs to the gate-on voltage Vgon. In this charging, the control circuit 24 turns on the high-side switching element S1 of the first drive circuit 18 via the high-side drive circuit 34. At this time, a current flows from the constant voltage source 16 into the gate capacitor 30 via the high side switching element S1 and the high side resistor 28.

  Further, the control circuit 24 turns on the high side switching element S3 of the second drive circuit 22 simultaneously with turning on the high side switching element S1. At this time, the potential of the auxiliary power supply side electrode 26B of the capacitor 26 quickly rises from the ground voltage to the voltage of the auxiliary power supply 20. This potential change causes a current to flow through the capacitor 26 (I = C × dV / dt). That is, a current is also supplied from the second drive circuit 22 to the gate capacitor 30 (gate terminal 14) via the capacitor 26. When current flows into the gate capacitor 30 from both the first and second drive circuits 18 and 22, the gate capacitor 30 is quickly charged.

  As the gate capacitor 30 is charged, the capacitor 26 connected in series with the gate capacitor 30 is also charged. By accumulating the charge q in the capacitor 26, a potential difference V is generated between both end electrodes of the capacitor 26 (q = CV). Specifically, in a steady state where the gate capacitance 30 has reached the gate-on voltage, the gate terminal side electrode 26A of the capacitor 26 is equipotential with the gate-on voltage, while the auxiliary power source side electrode 26B of the capacitor 26 is connected to the auxiliary power source 20. It remains the same potential as the voltage. By maintaining the auxiliary power supply side electrode 26B at a low potential, application of a high voltage to the second drive circuit 22 connected thereto is prevented, and dielectric breakdown is avoided.

  When the switching element 12 is turned off, the gate drive circuit 10 discharges the gate capacitor 30 to reduce the gate terminal voltage Vgs to a predetermined off voltage Vgoff. Upon this discharge, the control circuit 24 turns on the low-side switching element S2 of the first drive circuit 18 via the low-side drive circuit 36. At this time, a current flows from the gate capacitor 30 to the ground GND1 (first ground) via the low-side resistor 32 and the low-side switching element S2.

  In addition, the control circuit 24 turns on the low side switching element S4 of the second drive circuit 22 simultaneously with turning on the low side switching element S2. At this time, the potential of the auxiliary power supply side electrode 26B of the capacitor 26 decreases from the auxiliary power supply voltage to the ground voltage. As a result, the voltage across the capacitor 26 changes and a current flows. That is, a current flows from the gate capacitance 30 to the ground GND2 (second ground) via the capacitor 26 and the low-side switching element S4. As described above, the current flows from the gate capacitor 30 to the ground via both the first and second drive circuits 18 and 22, so that the gate capacitor 30 is quickly discharged.

<Details of each configuration>
The first drive circuit 18 is connected to the gate terminal 14 of the switching element 12. In FIG. 1, the first drive circuit 18 is indicated by a two-dot chain line. The first drive circuit 18 connects the constant voltage source 16 and the gate terminal 14 when the gate capacitor 30 is charged, and connects the gate terminal 14 and the ground GND 1 when the gate capacitor 30 is discharged, thereby charging the gate capacitor 30. Discharge. The first drive circuit 18 includes a constant voltage source 16, a high side switching element S 1, a low side switching element S 2, a high side drive circuit 34, a low side drive circuit 36, a high side resistor 28, and a low side resistor 32.

  The constant voltage source 16 is a voltage source that applies a voltage to the gate terminal 14, and for example, the voltage Vcc1 is determined to be a predetermined gate-on voltage Vgon (Vcc1 = Vgon). The gate-on voltage Vgon is set higher than the gate threshold voltage Vth in order to achieve complete turn-on of the switching element 12 (complete gate-on of the gate terminal 14). The gate threshold voltage Vth refers to a voltage when an n channel is formed in the p layer immediately below the gate terminal and becomes conductive. As an example, the gate-on voltage Vgon is set to 2 to 3 times the gate threshold voltage Vth.

  The high-side switching element S1 (first switching element) is provided between the constant voltage source 16 and the gate terminal 14, and switches between conduction / cutoff of both. The high-side switching element S1 is composed of a voltage-driven switching element such as a MOSFET. The MOSFET that constitutes the high-side switching element S1 is composed of, for example, a P-channel MOSFET that is turned on when a negative voltage (Lo) is applied to the gate terminal and turned off when a positive voltage (Hi) is applied. The gate terminal of the high side switching element S 1 is connected to the high side drive circuit 34, the source terminal is connected to the constant voltage source 16, and the drain terminal is connected to the gate terminal 14 via the high side resistor 28. A diode D1 is connected in antiparallel with the high side switching element S1.

  The high side drive circuit 34 is provided between the control circuit 24 and the gate terminal of the high side switching element S1. The high-side drive circuit 34 includes an arithmetic circuit such as a CPU, receives the signal (Lo / Hi) from the control circuit 24, and turns on the voltage (Lo) or off-voltage with respect to the gate terminal of the high-side switching element S1. Apply (Hi).

  The low-side switching element S2 (second switching element) is provided between the gate terminal 14 and the ground GND1, and switches between conduction / cutoff of both. The low-side switching element S2 is composed of a voltage-driven switching element such as a MOSFET. The MOSFET that constitutes the low-side switching element S2 is composed of, for example, an N-channel MOSFET that is turned on when a positive voltage (Hi) is applied to the gate terminal and turned off when a negative voltage (Lo) is applied. The gate terminal of the low-side switching element S2 is connected to the low-side drive circuit 36, the source terminal is connected to the first ground GND1, and the drain terminal is connected to the gate terminal 14 via the low-side resistor 32. A diode D2 is connected in antiparallel with the low-side switching element S2.

  The low side drive circuit 36 is provided between the control circuit 24 and the gate terminal of the low side switching element S2. The low-side drive circuit 36 includes an arithmetic circuit such as a CPU, receives a signal (Lo / Hi) from the control circuit 24, and turns on (Hi) or off-voltage (Hi) with respect to the gate terminal of the low-side switching element S2. Lo) is applied.

  The second drive circuit 22 is connected to the gate terminal 14 of the switching element 12 in parallel with the first drive circuit 18. In FIG. 1, the second drive circuit 22 is indicated by a two-dot chain line. The second drive circuit 22 makes the auxiliary power supply 20 and the gate terminal 14 conductive when the gate capacitor 30 is charged, and makes the gate terminal 14 and ground GND 2 conductive when the gate capacitor 30 is discharged, thereby charging and discharging the gate capacitor 30. I do. The second drive circuit 22 includes an auxiliary power supply 20, a high side switching element S3, and a low side switching element S4.

  The auxiliary power source 20 is a voltage source that applies a voltage to the gate terminal 14, and is constituted by, for example, a DC power source. The voltage Vcc2 is determined to be less than the voltage Vcc1 of the constant voltage source 16 and to be in a range that satisfies formulas (1) and (2) described later. Accordingly, the withstand voltage of the constituent elements of the second drive circuit 22 may be of a level that can withstand the voltage Vcc2 (<Vcc1) of the auxiliary power supply 20 (eg, withstand voltage upper limit value ≧ Vcc2).

  The high-side switching element S3 (third switching element) is provided between the auxiliary power supply 20 and the gate terminal 14 and switches between conduction / cutoff of both. The high side switching element S3 is composed of a P-channel type MOSFET, similarly to the high side switching element S1 of the first drive circuit 18. The gate terminal of the high-side switching element S3 is connected to the control circuit 24, the source terminal is connected to the auxiliary power supply 20, and the drain terminal is connected to the gate terminal 14 via the capacitor 26. The gate terminal of the high side switching element S3 is connected to the control circuit 24.

  The low-side switching element S4 (fourth switching element) is provided between the gate terminal 14 and the ground GND2 (second ground), and switches between conduction / cutoff of both. The low side switching element S4 is composed of an N-channel type MOSFET, similarly to the low side switching element S2 of the first drive circuit 18. The gate terminal of the low-side switching element S4 is connected to the control circuit 24, the source terminal is connected to the second ground GND2, and the drain terminal is connected to the gate terminal 14 via the capacitor 26. The gate terminal of the low side switching element S4 is connected to the control circuit 24.

  Both the high-side switching elements S1 and S3 and the low-side switching elements S2 and S4 are composed of voltage-driven switching elements similar to the switching element 12 such as an IGBT. Therefore, strictly speaking, these switching elements S1 to S4 also have gate capacitance. However, in practice, the switching elements S1 to S4 are selected so that the gate capacity is sufficiently smaller than the gate capacity 30 of the switching element 12 (IGBT). Therefore, when charging / discharging the gate capacitor 30, the delay time and the like related to charging / discharging of the gate capacitors of the switching elements S1 to S4 can be substantially ignored.

  The capacitor 26 is provided between the second drive circuit 22 and the gate terminal 14 and the first drive circuit 18. That is, the second drive circuit 22 and the capacitor 26 are connected to the gate terminal 14 in parallel with the first drive circuit 18. Specifically, the connection point 38 where the wirings of the high-side switching element S3 and the low-side switching element S4 of the second drive circuit 22 are connected, and the wiring extending from the second drive circuit 22 are connected to the first drive circuit 18. A capacitor 26 is provided between the connection points 40.

  The capacitor 26 has a withstand voltage characteristic equal to or higher than the gate-on voltage Vgon (= Vcc1) so as not to be broken down when a voltage is applied from the first drive circuit 18 and the gate terminal 14. For example, the capacitor 26 has a withstand voltage characteristic (withstand voltage upper limit value) twice to three times the gate-on voltage Vgon (= Vcc1). Further, the capacitance C1 of the capacitor 26 satisfies the following formula (1) using the capacitance Cg of the gate capacitance 30, the voltage Vcc2 of the auxiliary power supply 20, and the gate terminal voltage Vmrr (mirror voltage) in the mirror period described later. Determined.

  That is, the capacity C1 of the capacitor 26 (and the voltage Vcc2 of the auxiliary power supply 20) is determined so that the divided voltage applied from the auxiliary power supply 20 to the gate capacity 30 is lower than the gate terminal voltage Vmrr (mirror voltage) in the mirror period. . By doing so, current supply from the second drive circuit 22 to the gate capacitor 30 is prevented in the mirror period in which the amount of charge to the gate capacitor 30 is relatively large. That is, generation of a large current (surge) from the second drive circuit 22 to the gate capacitor 30 can be suppressed (a large current supply from the first drive circuit 18 to the gate capacitor 30 is caused by the high side resistor 28 and the low side resistor. 32).

  As will be described later, the second drive circuit 22 is provided to support charging / discharging of the gate capacitance 30 (Cg) by the first drive circuit 18. The longer the support period, the shorter the charge / discharge period of the gate capacitor 30. From this, the capacitance C1 (and the auxiliary power supply) of the capacitor 26 is set so that the divided voltage applied from the auxiliary power supply 20 to the gate capacitance 30 becomes higher than the gate threshold voltage Vth of the switching element 12 as shown in the following formula (2). A voltage of 20 (Vcc2) may be defined.

  As will be described later, in order to quickly increase the voltage value of the capacitor 26, it is preferable that the RC series circuit L2c (shown by a broken line in FIG. 2) including the capacitor 26 and the auxiliary power supply 20 has a smaller time constant RC. It is. Specifically, RC is set such that the time constant RC of RC series circuit L2c is smaller than the time constant RC of RC series circuit L1c (shown by a broken line in FIG. 2) including constant voltage source 16 and gate capacitance 30. The resistance value of the series circuit L2c may be determined. For example, it is not necessary to provide a resistance element in the wiring path of the RC series circuit L2c.

  Similarly, the time constant RC of the RC series circuit L2d (shown by a broken line in FIG. 2) including the capacitor 26 and the ground GND2 (second ground) determines the gate capacitance 30 and the ground GND1 (first ground). The resistance value of the RC series circuit L2d (shown by a broken line in FIG. 2) may be determined so as to be smaller than the time constant RC of the included RC series circuit L1d (shown by a broken line in FIG. 2). For example, it is not necessary to provide a resistance element in the wiring path of the RC series circuit L2d.

  Returning to FIG. 1, the control circuit 24 turns on / off the high-side switching element S1 and the low-side switching element S2 of the first drive circuit 18, and the high-side switching element S3 and the low-side switching element S4 of the second drive circuit 22. To control. The control circuit 24 includes an arithmetic circuit such as a CPU. For example, the control circuit 24 receives a control signal Sg1 from a higher-level control means such as an electronic control unit (ECU) and receives control signals (on / off signals) to the switching elements S1 to S4. Is output. These control signals are composed of voltage signals, for example.

  For example, the control circuit 24 sends a control signal Sg2 to the high side drive circuit 34, a control signal Sg3 to the low side drive circuit 36, and a control signal Sg4 to the high side switching element S3 and the low side switching element S4. Output each.

  For example, the control signal Sg2 includes a signal having the same pattern as the Lo / Hi pattern of Sg1. (Sg2 = Sg1). Further, for example, the control signals Sg3 and Sg4 are composed of inverted signals of Sg1. (Sg3 & Sg4 = / Sg1).

  The switching element 12 is mounted on a so-called power electronics device such as an inverter or a DC / DC converter of a hybrid vehicle or an electric vehicle, for example. The switching element 12 is composed of an element having a high withstand voltage and a large current capacity, and is composed of, for example, an IGBT (insulated gate bipolar transistor).

  A gate capacitance 30 is generated as a parasitic capacitance at the gate terminal 14 of the switching element 12. The gate capacitance 30 is composed of a combined capacitance of a gate-drain capacitance Cgd and a gate-source capacitance Cgs. When the gate terminal voltage is raised when the switching element 12 is turned on (the gate terminal 14 is turned on), the gate capacitor 30 is charged. When the gate terminal voltage is lowered when the switching element 12 is turned off (gate terminal 14 is turned off), the gate capacitance 30 is discharged.

<Operation at turn-on>
The operation when the switching element 12 is turned on will be described with reference to FIG. In FIG. 3, the control signal Sg1 (= Sg2) to the control circuit 24, the inverted signal / Sg1 (= Sg3, Sg4), the wiring 31 between the capacitor 26 and the second drive circuit 22 (capacitor wiring) are shown in order from the top of the drawing. The time change of the voltage (capacitor wiring voltage) Vsg5, the current IC1 flowing through the capacitor 26, the voltage VC1 across the capacitor 26, the gate terminal voltage Vgs, and the charge / discharge current Ig to the gate capacitor 30 is illustrated. Among these, the capacitor wiring voltage Vsg5 is substantially equal to the voltage applied to the second drive circuit 22 (if the wiring resistance or the like is ignored).

  For the capacitor current IC1, the direction in which the current flows through the gate capacitor 30 is the positive direction. Further, regarding the voltage VC1 across the capacitor, the case where the potential on the gate capacitance 30 side is relatively high is positive, and the case where the potential on the auxiliary power supply 20 side is relatively high is negative.

  Referring to FIG. 3, the period from time t0 to t1 is a turn-off period of switching element 12 (gate off period of gate terminal 14). At this time, the control circuit 24 outputs a control signal Sg2 (Lo) to the high-side drive circuit 34. Further, the control circuit 24 outputs a control signal Sg3 (Hi) to the low side drive circuit 36. Further, the control circuit 24 outputs a control signal Sg4 (Hi) to the high side switching element S3 and the low side switching element S4 of the second drive circuit 22.

  The high side drive circuit 34 receives Sg2 (Lo) and outputs an off signal (Hi) to the P-channel type high side switching element S1. The low side drive circuit 36 receives Sg3 (Hi) and outputs an ON signal (Hi) to the N-channel type low side switching element S2. Further, upon receiving Sg4 (Hi), the P-channel type high-side switching element S3 is turned off, and the N-channel type low-side switching element S4 is turned on. That is, the two low side switching elements S2 and S4 are turned on, and the gate terminal 14 is grounded. The potential of the gate capacitor 30 becomes the ground voltage Vgnd, and the switching element 12 is turned off.

  From time t1 to time t5 is a switching period of switching element 12 from on to off. When the control circuit 24 receives the control signal Sg1 (Hi) at time t1, the control circuit 24 outputs the control signals Sg2 (Hi), Sg3 (Lo), and Sg4 (Lo). In response to Sg2 (Hi), the high side drive circuit 34 outputs an on signal (Lo) to the high side switching element S1 to turn it on. In response to Sg3 (Lo), the low side drive circuit 36 outputs an off signal (Lo) to the low side switching element S2 to turn it off. Further, upon receiving Sg4 (Lo), the P-channel type high-side switching element S3 is turned on, and the N-channel type low-side switching element S4 is turned off. That is, the two high side switching elements S1 and S3 are switched from off to on, and the two low side switching elements S2 and S4 are switched from on to off.

  When the high-side switching element S1 is turned on, the constant voltage source 16 and the gate capacitor 30 are brought into conduction, and the gate capacitor 30 is charged. At this time, the charging of the gate capacitor 30 is performed according to a mathematical expression describing a transient phenomenon of a so-called RC series circuit. Generally, the capacitor voltage VC (t) during charging in the RC series circuit changes as shown in the following formula (3).

  In Equation (3), E represents the power supply voltage [V], e represents the base of the natural logarithm (Napier number), R represents the resistance [Ω], C represents the capacitance, and t represents time. In the RC series circuit including the high-side resistor 28 and the gate capacitor 30, the voltage of the gate capacitor 30 (gate terminal voltage Vgs) increases in accordance with the time constant RC according to Equation (3). At the initial time t1 (t = 0), the gate terminal voltage Vgs becomes the ground voltage Vgnd (VC (0) = 0). In response, the potential of the gate terminal side electrode 26A of the capacitor 26 also becomes Vgnd at time t1.

  Further, when the high side switching element S3 is turned on, the potential of the auxiliary power supply side electrode 26B of the capacitor 26 changes from the ground voltage Vgnd to the auxiliary power supply voltage Vcc2. If the wiring resistance between the auxiliary power supply 20 and the capacitor 26 and the internal resistance of the auxiliary power supply 20, the high-side switching element S3, and the capacitor 26 are ignored, R = 0 in the above equation (3) (time constant) Since RC becomes 0), at time t1, the potential of the auxiliary power supply side electrode 26B instantaneously changes from the ground voltage Vgnd to the auxiliary power supply voltage Vcc2.

  In response to such a difference between the gentle rise of the potential corresponding to the time constant RC of the gate terminal side electrode 26A and the rapid rise of the potential of the auxiliary power supply side electrode 26B, the voltage across the capacitor VC1 is 0 [ V] suddenly changes to -Vcc2. As a result, the current IC1 flows through the capacitor 26. That is, current is supplied from the auxiliary power source 20 to the gate capacitor 30 via the capacitor 26.

  After time t1, the potential of the auxiliary power supply side electrode 26B of the capacitor 26 maintains the auxiliary power supply voltage Vcc2. On the other hand, in the first drive circuit 18, the voltage applied to the gate capacitor 30 corresponding to the time constant RC gradually rises, and in response to this, the potential of the gate terminal side electrode 26A of the capacitor 26 gradually increases. In response to the voltage change of the capacitor 26, the current IC1 is supplied from the auxiliary power source 20 to the gate capacitor 30 via the capacitor 26 from time t1 to time t2.

  FIG. 4 shows a state of charging the gate capacitor 30 from time t1 to time t2. As indicated by the one-dot chain line arrow in FIG. 4, in addition to the current supplied from the constant voltage source 16 to the gate capacitor 30 in the first drive circuit 18, the capacitor 26 is connected from the auxiliary power supply 20 in the second drive circuit 22. The current IC1 is supplied to the gate capacitor 30 through the via. By supplying these currents, the gate capacitance 30 is quickly charged, as is apparent from the fact that the value of the gate charge / discharge current Ig protrudes from time t1 to t2 in FIG.

  From time t1 to time t2, the gate terminal voltage Vgs increases as the gate capacitance 30 is charged, and exceeds the gate threshold voltage Vth. As a result, an n channel is formed in the p layer immediately below the gate terminal of the switching element 12. Further, the rate of change of the voltage VC1 across the capacitor 26 gradually decreases, and as a result, the current IC1 flowing through the capacitor 26 gradually decreases.

  At time t2, the gate terminal voltage Vgs reaches C1 × Vcc2 / (C1 + Cg) as the voltage increases with the time constant RC of the first drive circuit 18. This voltage value is equal to the divided voltage applied from the auxiliary power supply 20 to the gate capacitance 30 in a steady state in a circuit in which the auxiliary power supply 20, the capacitor 26, and the gate capacitance 30 are connected in series. At this time, the electrodes 26A and 26B of the capacitor 26 are equipotential (VC1 = 0 [V]), and the current supply from the auxiliary power supply 20 to the gate capacitor 30 temporarily becomes zero.

  Further, after time t2, when the gate terminal voltage Vgs further increases, the potential of the gate terminal side electrode 26A of the capacitor 26 becomes higher than the potential of the auxiliary power source side electrode 26B (reverse bias). At this time, as indicated by an alternate long and short dash line arrow in FIG. 5, a part of the current supplied from the first drive circuit 18 flows to the auxiliary power supply 20 side via the capacitor 26. Further, charges are accumulated in the capacitor 26 through this current supply.

  Further, at time t3, the gate terminal voltage becomes the mirror voltage Vmrr, which is a so-called mirror period until time t4. Since the mirror period is known, it will be briefly described here. When the gate terminal voltage Vgs becomes equal to or higher than the gate threshold voltage Vth, current starts to flow from the drain to the source via the n-channel immediately below the gate. As a result, the drain terminal voltage starts to drop, and a potential difference is generated between the gate terminal 14 and the drain terminal. As a result, the capacity of the gate-drain capacity Cgd in the gate capacity 30 increases, and the current flowing into the gate capacity 30 is supplied exclusively to the gate-drain capacity Cgd.

  In the gate drive circuit 10 according to the present embodiment, the voltage Vcc2 of the auxiliary power supply 20 and the capacitance C1 of the capacitor 26 are determined so as to satisfy the above-described formula (1). In other words, before the gate terminal voltage becomes the mirror voltage Vmrr, the auxiliary power supply 20 has a reverse bias state in which the potential of the gate terminal side electrode 26A of the capacitor 26 becomes higher than the potential of the auxiliary power supply side electrode 26B. The voltage Vcc2 and the capacitance C1 of the capacitor 26 are determined. This prevents current from flowing from the auxiliary power source 20 to the gate capacitor 30. By avoiding current supply to the relatively large capacity gate-drain capacity Cgd during the mirror period, large current supply (surge) of the second drive circuit 22 can be avoided.

  Note that the charging of the gate capacitor 30 in the mirror period (time t3 to t4) is exclusively performed by the first drive circuit 18. Since the amount of current is reduced by the high side resistor 28 of the first drive circuit 18, the occurrence of surge in the first drive circuit 18 can be avoided.

  In the mirror period, the gate terminal voltage Vgs is kept (clamped) at the mirror voltage Vmrr until the gate-drain capacitance Cgd is charged to the same extent as the gate-source capacitance Cgs. At this time, the voltage VC1 across the capacitor 26 is maintained at Vmrr-Vcc2. Since no voltage change occurs in the voltage VC1 across the capacitor 26, no current flows through the capacitor 26. That is, at time t3 to t4, the gate capacitor 30 is charged only by the current supplied from the first drive circuit 18 as shown by the one-dot chain arrow in FIG.

  After time t4, the charging of the gate capacitor 30 further proceeds and the gate terminal voltage Vgs rises from the mirror voltage Vmrr to the gate-on voltage Vgon (= Vcc1). In response to this, the voltage VC1 across the capacitor 26 also changes in the reverse bias state, and a part of the current of the first drive circuit 18 is transferred to the auxiliary power supply 20 side via the capacitor 26, as shown in FIG. Flowing. As a result, charges are accumulated in the capacitor 26.

  When the gate terminal voltage Vgs reaches the gate-on voltage Vgon at time t5, the switching element 12 is turned on thereafter (the gate-on period of the gate terminal 14). Since the gate terminal voltage Vgs is fixed to the gate-on voltage Vgon during this ON period, the voltage VC1 across the capacitor 26 remains constant at Vcc1-Vcc2 (steady state). For this reason, no current flows through the capacitor 26, and therefore, current is prevented from flowing into the second drive circuit 22.

  Further, the electric charge is accumulated in the capacitor 26 through the period from time t1 to time t5, so that the voltage VC1 across the capacitor becomes Vcc1-Vcc2 (q = CV) at time t5. That is, the potential of the gate terminal side electrode 26A of the capacitor 26 is Vcc1, while the potential of the auxiliary power source side electrode 26B is Vcc2. Thereby, voltage application exceeding Vcc2 is avoided in the second drive circuit 22 connected to the auxiliary power supply side electrode 26B, and dielectric breakdown is prevented.

<Operation at turn-off>
The operation when the switching element 12 is turned off will be described with reference to FIG. Similar to FIG. 3, FIG. 7 shows a control signal Sg <b> 1 (= Sg <b> 2), an inverted signal / Sg <b> 1 (= Sg <b> 3, Sg <b> 4), a capacitor wiring voltage Vsg <b> 5, and a current flowing through the capacitor 26. The time change of IC1, the both-ends voltage VC1 of the capacitor | condenser 26, the gate terminal voltage Vgs, and the charging / discharging current Ig to the gate capacity | capacitance 30 is illustrated.

  First, a period from time t10 to t11 is a turn-on period of the switching element 12 (a gate-on period of the gate terminal 14). That is, the operation state is the same as after t5 in FIG. Specifically, the high side switching elements S1 and S3 are turned on, and the low side switching elements S2 and S4 are turned off.

  When the control circuit 24 receives the control signal Sg1 (Lo) at time t11, the control circuit 24 outputs the control signal Sg2 (Lo) to the high side drive circuit 34. The control circuit 24 outputs a control signal Sg3 (Hi) to the low side drive circuit 36. Further, the control circuit 24 outputs a control signal Sg4 (Hi) to the high side switching element S3 and the low side switching element S4 of the second drive circuit 22.

  The high side drive circuit 34 receives Sg2 (Lo) and outputs an off signal (Hi) to the P-channel type high side switching element S1. The low side drive circuit 36 receives Sg3 (Hi) and outputs an ON signal (Hi) to the N-channel type low side switching element S2. Further, upon receiving Sg4 (Hi), the P-channel type high-side switching element S3 is turned off, and the N-channel type low-side switching element S4 is turned on. That is, the two high-side switching elements S1 and S3 are turned off from on, the low-side switching elements S2 and S4 are turned on from off, and the gate terminal 14 is grounded.

  At this time, the low-side switching element S2 is turned on, whereby the gate capacitor 30 and the ground GND1 (first ground) are conducted, and the gate capacitor 30 is discharged. The discharge of the gate capacitor 30 is performed according to a mathematical expression describing the transient phenomenon of the RC series circuit, as in the case of charging. Generally, in the RC series circuit, the voltage VC (t) of the capacitor at the time of discharging changes as shown in the following formula (4).

  Further, the voltage (voltage drop) VR (t) across the resistor R (low-side resistor 32 in the present embodiment) in the RC series circuit changes as shown in the following formula (5).

  In the RC series circuit including the gate capacitor 30 and the low-side resistor 32, the voltage of the gate capacitor 30 (gate terminal voltage Vgs) decreases according to the time constant RC according to Equation (4). At the initial time t11 (t = 0), the gate terminal voltage Vgs becomes the gate-on voltage Vgon (= Vcc1) (VC (0) = E). In response, the potential of the gate terminal side electrode 26A of the capacitor 26 also becomes Vcc1 at time t11.

  Further, since no resistor is sandwiched between the capacitor 26 and the ground GND2 (second ground), there is no theoretical delay due to the time constant RC if the internal resistance and wiring resistance of the capacitor 26 and the like are ignored. Therefore, when the low side switching element S4 is turned on at time t11, the potential of the auxiliary power supply side electrode 26B of the capacitor 26 changes from the auxiliary power supply voltage Vcc2 to the ground voltage Vgnd.

  Due to the difference between the gradual decrease in potential according to the time constant RC of the gate terminal side electrode 26A and the rapid decrease in potential of the auxiliary power supply side electrode 26B, the voltage across the capacitor VC1 becomes Vcc1- It changes suddenly from Vcc2 to Vcc1. As a result, the current IC1 flows through the capacitor 26. That is, current is discharged (discarded) from the gate capacitance 30 to the ground GND2 (second ground) through the capacitor 26.

  After time t11, the gate terminal voltage Vgs decreases as the gate capacitance 30 is released. As the gate terminal voltage Vgs decreases, the potential of the gate terminal side electrode 26A of the capacitor 26 also starts to decrease, and accordingly, the capacitor both-end voltage VC1 also decreases. A current IC1 flows through the capacitor 26 due to a decrease in the voltage VC1 across the capacitor. That is, a current flows from the gate terminal 14 to the ground GND2 through the capacitor 26 and the low-side switching element S4.

  At this time, in addition to the current being discharged from the gate capacitor 30 to the ground GND1 in the first drive circuit 18 as indicated by the one-dot chain arrow in FIG. 8, the second capacitor 22 is connected to the ground GND2 in the second drive circuit 22. Current is released. Due to these discharges, the gate capacitance 30 is quickly discharged, as is apparent from the fact that the value of the gate charge / discharge current Ig protrudes at times t11 to t12 in FIG.

  From time t11 to t12, the gate terminal voltage Vgs decreases as the gate capacitance 30 is discharged. When the gate terminal voltage Vgs becomes equal to Vcc1- [C1 × Vcc2 / (C1 + Cg)] at time t12, both ends of the capacitor 26 are equipotential.

  After time t12, as the gate terminal voltage Vgs decreases, the flow of charging from the gate capacitance 30 to the capacitor 26 and charging the capacitor 26 switches to the flow of discharging the charged capacitor 26. That is, as indicated by the one-dot chain line arrow in FIG. 9, the charge of the capacitor 26 flows into the ground GND1 (first ground) via the low-side resistor 32 instead of the ground GND2. That is, in addition to the charge released from the gate capacitor 30, the charge of the capacitor 26 is released to the ground GND1 through the low side switching element S2.

  Further, at time t13, the gate terminal voltage Vgs becomes the mirror voltage Vmrr, and the mirror period is reached until time t14. In the mirror period, the gate terminal voltage Vgs is maintained at the mirror voltage Vmrr, and the voltage VC1 across the capacitor 26 is also constant. Therefore, the capacitor 26 does not pass current, and the gate capacitance 30 is discharged exclusively through the low-side switching element S2, as indicated by the dashed line arrow in FIG.

  After time t14, the gate capacitor 30 is further discharged, and the gate terminal voltage Vgs decreases to the ground voltage Vgnd. In response to this, the voltage VC1 across the capacitor 26 also changes, and a current flows from the capacitor 26 to the ground GND1 via the low-side switching element S2 in the same manner as shown in FIG. After time t15, similarly to the time between t0 and t1 in FIG. 3, the switching element 12 is turned off (turn-off period) (steady state).

  As described above, in the gate drive circuit 10 according to the present embodiment, the second drive circuit 22 in addition to the first drive circuit 18 in the initial period (time t11 to t12) of the switching element 12 from on to off. The gate capacitor 30 is discharged. As a result, the gate capacitor 30 is quickly discharged, and the switching period can be shortened.

  Further, in the time chart of FIG. 7, as indicated by the capacitor wiring voltage Vsg5 indicating the voltage applied to the second drive circuit 22, the switching period (t11 to t15) of the switching element 12 from on to off, The voltage applied to the second drive circuit 22 is maintained at the ground voltage Vgnd throughout the subsequent off period (t15-). In this way, by providing the capacitor 26, application of a high voltage such as the gate-on voltage Vgon (= Vcc1) to the second drive circuit 22 can be avoided, and dielectric breakdown of the second drive circuit 22 can be prevented.

  In the example shown in FIGS. 3 and 7, the capacitor current IC1 flows backward during the period from time t2 to t3 and t4 to t5 during charging and from time t12 to t13 and t14 to t15 during discharging. That is, during charging, the current from the first driving circuit 18 to be directed to the gate capacitor 30 flows to the second driving circuit 22 as shown in FIG. 5, and during discharging, the capacitor 26 passes through the discharge path of the gate capacitor 30 as shown in FIG. Discharge current interrupts. The pace of charging and discharging of the gate capacitor 30 is slowed with the backflow of the capacitor current IC1.

  In order to suppress the slowing of the charge / discharge pace of the gate capacitor 30, the charge amount and the discharge amount by the first drive circuit 18 are relatively high by making the high-side resistor 28 and the low-side resistor 32 relatively low resistance. It is preferable to do. Thereby, the influence of the backflow of the capacitor current IC1 becomes relatively small. For example, the influence of the backflow of the capacitor current IC1 can be suppressed as shown in FIG. 11 from the top to the bottom when charging the gate capacitor 30 and from the top to the bottom of FIG. 12 when discharging.

Second Embodiment
As a circuit capable of preventing the reverse flow of the capacitor current IC1 as described above, there is a gate drive circuit 10 as shown in FIG. The difference from the circuit of FIG. 1 is that diodes D3 and D4 are provided between the auxiliary power supply 20 and the gate terminal 14, and between the gate terminal 14 and the ground GND2.

  Specifically, the diode D3 (first diode) is provided between a connection point 38 that connects the capacitor 26 to the high-side switching element S3 and the low-side switching element S4 and the drain terminal of the high-side switching element S3. It is done. The diode D3 has a forward direction from the auxiliary power supply 20 to the gate terminal 14, and blocks a current flow from the gate terminal 14 to the auxiliary power supply 20. Specifically, by providing the diode D3, the current Ic flowing from the first drive circuit 18 to the auxiliary power supply 20 of the second drive circuit 22 can be cut off when the gate capacitor 30 is charged, as shown in FIG. it can.

  The diode D4 (second diode) is provided between the connection point 38 and the drain terminal of the low-side switching element S4. The diode D4 has a forward direction from the gate terminal 14 toward the ground GND2 (second ground), and blocks a current flow from the ground GND2 to the gate terminal 14. By providing the diode D4, the current Id flowing from the capacitor 26 to the ground GND1 can be cut off when the gate capacitor 30 is discharged, as shown in FIG.

  Both diodes D3 and D4 preferably have a withstand voltage characteristic equal to or higher than the gate-on voltage Vgon (= Vcc1) in order to avoid dielectric breakdown.

<Operation at turn-on>
The operation when the switching element 12 using the gate drive circuit 10 shown in FIG. 13 is turned on will be described with reference to FIG. In FIG. 16, the control signal Sg1 (= Sg2) to the control circuit 24, the inverted signal / Sg1 (= Sg3, Sg4), the voltage Vsg5 of the capacitor wiring 31, the current IC1 flowing through the capacitor 26, and the capacitor 26 are sequentially shown in FIG. The time change of the both-ends voltage VC1, the gate terminal voltage Vgs, and the charging / discharging current Ig to the gate capacitance 30 is illustrated.

  First, a period from time t0 'to t1' is a turn-off period of the switching element 12 (gate-off period of the gate terminal 14). The on / off states of the control signals Sg2 to Sg4 and the switching elements S1 to S4 output from the control circuit 24 are the same as the period from time t0 to time t1 in FIG. That is, the high side switching elements S1 and S3 are turned off and the low side switching elements S2 and S4 are turned on.

  At time t0 ', the voltage VC1 across the capacitor 26 becomes Vcc1-Vcc2. This will be described later. Since the potential of the gate terminal side electrode 26A of the capacitor 26 is the ground voltage Vgnd similarly to the gate terminal voltage, the potential of the auxiliary power supply side electrode 26B is (Vgnd− (Vcc1−Vcc2) =) Vcc2−Vcc1.

  From time t1 'to time t5' is a switching period of switching element 12 from on to off. At this time, similarly to FIG. 3, at time t1 ', the high side switching elements S1, S3 are switched from OFF to ON, and the low side switching elements S2, S4 are switched from ON to OFF.

  When the high-side switching element S1 is turned on, the constant voltage source 16 and the gate capacitor 30 are brought into conduction, and the gate capacitor 30 is charged based on the time constant RC. Further, since the high-side switching element S3 is turned on to conduct with the auxiliary power source 20, the capacitor wiring voltage Vsg5 is raised from −Vcc1 to Vcc2 at time t1 ′.

  Further, due to the increase in the gate terminal voltage Vgs accompanying the charging of the gate capacitance 30, the voltage VC1 across the capacitor 26 decreases (the potential difference across the capacitor decreases). As the voltage VC1 across the capacitor 26 changes as described above, the current IC1 flows through the capacitor 26. In this way, current is supplied from the auxiliary power supply 20 to the gate capacitor 30 through the capacitor 26 from time t1 'to t2'.

  At this time, in addition to the current supplied from the constant voltage source 16 to the gate capacitor 30 in the first drive circuit 18, the current is supplied from the auxiliary power supply 20 to the gate capacitor 30 in the second drive circuit 22. By supplying these currents, as can be seen from the fact that the gate charge / discharge current Ig protrudes at times t1 'to t2' in FIG. 16, the gate capacitor 30 is quickly charged.

  When the gate terminal voltage Vgs becomes equal to the divided voltage (C1 × Vcc2 / (C1 + Cg)) when the voltage is applied from the auxiliary power supply 20 at time t2 ′, both ends of the capacitor 26 are equipotential (VC1 = 0 [ V]).

  Further, after time t2 ', the gate terminal voltage Vgs further rises. That is, in the capacitor 26, the potential of the gate terminal side electrode 26A becomes higher than the potential of the auxiliary power source side electrode 26B (reverse bias). However, by providing the diode D3, the flow of the current IC from the gate terminal 14 to the auxiliary power source 20 is prevented as shown in FIG. That is, after the time t2 'at which the potential of the gate terminal side electrode 26A is higher than the potential of the auxiliary power supply side electrode 26B in the capacitor 26, the current flow from the constant voltage source 16 to the auxiliary power supply 20 is blocked by the diode D3. This interruption is continued until the switching element 12 is turned on (after time t5 '). By doing so, the current supplied from the constant voltage source 16 is theoretically all supplied to the gate capacitor 30.

  Since no current flows through the capacitor 26, the voltage VC1 across the capacitor 26 maintains 0 [V] at time t2 ′ (I = C × dV / dt, d = 0 / dt = I = 0). 0). As the gate capacitance 30 is charged, the potential of the gate terminal side electrode 26A of the capacitor 26 increases. Since the both-ends voltage VC1 of the capacitor 26 is maintained at 0 [V], the potential of the auxiliary power supply side electrode 26B is increased together with the gate terminal side electrode 26A. That is, the capacitor wiring voltage Vsg5 indicating the voltage applied to the second drive circuit 22 also increases.

  When the gate terminal voltage Vgs reaches the gate-on voltage Vgon (= Vcc1) at time t5 ′ (steady state), the potential of the gate terminal side electrode 26A of the capacitor 26, the potential of the auxiliary power source side electrode 26B, and the capacitor wiring voltage Vsg5 Also reaches the gate-on voltage Vgon.

  When the capacitor wiring voltage Vsg5 reaches the gate-on voltage Vgon, the gate-on voltage Vgon is applied to the second drive circuit 22. In the gate drive circuit 10 according to the present embodiment, the dielectric breakdown of the second drive circuit 22 is prevented by preventing the current from flowing into the second drive circuit 22 in such a case.

  Generally, dielectric breakdown refers to a state in which a voltage applied to an insulator exceeds a withstand voltage and a current flows through the insulator when the current flows in that state. Based on this definition, since the current flow is interrupted by the diode D3 after the time t2 'when the voltage applied to the second drive circuit 22 exceeds Vcc2, breakdown of the second drive circuit 22 is avoided. That is, if the upper limit of the withstand voltage of the second drive circuit 22 is set to at least Vcc2, the dielectric breakdown of the second drive circuit 22 is substantially avoided.

<Operation at turn-off>
The operation at the time of switching off of the switching element 12 will be described with reference to FIG. Similar to FIG. 16, FIG. 17 shows the control signal Sg1 (= Sg2) to the control circuit 24, the inverted signal / Sg1 (= Sg3, Sg4), the capacitor wiring voltage Vsg5, and the current flowing through the capacitor 26 in order from the page. The time change of IC1, the both-ends voltage VC1 of the capacitor | condenser 26, the gate terminal voltage Vgs, and the charging / discharging current Ig to the gate capacity | capacitance 30 is illustrated.

  First, a period from time t10 'to t11' is a turn-on period of the switching element 12 (gate on period of the gate terminal 14). That is, the operation state is the same as that after t5 'in FIG. Specifically, the high side switching elements S1 and S3 are turned on, and the low side switching elements S2 and S4 are turned off.

  At time t11 ', the high-side switching elements S1 and S3 are switched from on to off, and the low-side switching elements S2 and S4 are switched from off to on. When the low side switching element S2 is turned on, a current flows from the gate capacitor 30 to the ground GND1 (first ground) via the low side resistor 32 and the low side switching element S2. Accordingly, the gate terminal voltage Vgs gradually decreases from the gate-on voltage Vgon (= Vcc1). In response to this, the potential of the gate terminal side electrode 26A of the capacitor 26 gradually decreases from the gate-on voltage Vgon (= Vcc1).

  Further, when the low side switching element S4 is turned on at time t11 ', the potential of the auxiliary power supply side electrode 26B of the capacitor 26 is lowered from Vcc1 to the ground voltage Vgnd.

  With the change in the voltage VC1 across the capacitor 26 as described above (the potential change between the gate terminal side electrode 26A and the auxiliary power source side electrode 26B), the current IC1 flows through the capacitor 26. That is, a current flows from the gate terminal 14 to the ground GND2 (second ground) through the capacitor 26 and the low-side switching element S4.

  As described above, in the section from the time t11 'to the time t12', a current is discharged from the gate capacitor 30 to the ground GND1 in the first drive circuit 18 as in the time t11 to t12 in FIG. In addition, in the second drive circuit 22, a current is discharged from the gate capacitance 30 to the ground GND 2 via the capacitor 26. As a result, the gate capacitor 30 is quickly discharged.

  After time t12 ', as the gate terminal voltage Vgs decreases, the flow of charging from the gate capacitor 30 to the capacitor 26 and charging the capacitor 26 switches to the flow of discharging the charged capacitor 26. In the present embodiment, the charge discharge flow of the capacitor 26 is blocked by the diode D4. That is, the current loop from the ground GND2 to the ground GND1 through the capacitor 26 and the low-side switching element S2 is interrupted by the diode D4. As a result, the current Id flowing from the capacitor 26 to the ground GND1 is blocked by the diode D4 as shown in FIG. 15 until the switching element 12 is turned off (time t15 ') after the time t12'. As a result, since the discharge current from the capacitor 26 does not flow into the discharge path from the gate capacitor 30 to the ground GND1, a delay in the discharge period of the gate capacitor 30 can be avoided.

  Since the current does not flow to the capacitor 26 due to the action of the diode D4, the voltage VC1 across the capacitor 26 is maintained at Vcc1-Vcc2 at time t12 '. Further, the capacitor wiring voltage Vsg5 decreases while keeping the voltage difference between the gate terminal voltage Vgs and Vcc1-Vcc2, and reaches Vcc2-Vcc1 when the switching element 12 is turned off (time t15 '). This voltage state is the initial state at time t0 'in FIG.

  As described above, in the gate drive circuit 10 according to the present embodiment, since the discharge current of the capacitor 26 flows into the discharge path of the gate capacitor 30 during the discharge of the gate capacitor 30, the discharge time of the gate capacitor 30 is delayed. Can be suppressed.

  In the embodiment shown in FIG. 13, both the diode D3 and the diode D4 are provided in the gate drive circuit 10, but either one may be provided. For example, when the circuit configuration is such that only the diode D3 is provided out of both the diodes D3 and D4, the current Ic flowing from the first drive circuit 18 to the auxiliary power supply 20 of the second drive circuit 22 can be cut off when the gate capacitor 30 is charged. . Therefore, as compared with the gate drive circuit 10 shown in FIG. Further, when the circuit configuration is such that only the diode D4 is provided among the diodes D3 and D4, the current Id flowing from the capacitor 26 to the ground GND1 can be cut off when the gate capacitance 30 is discharged. Therefore, the gate capacitor 30 is quickly discharged as compared with the gate driving circuit 10 shown in FIG.

  DESCRIPTION OF SYMBOLS 10 Gate drive circuit, 12 Switching element, 14 Gate terminal, 16 Constant voltage source, 18 1st drive circuit, 20 Auxiliary power supply, 22 2nd drive circuit, 24 Control circuit, 26 Capacitor, 30 Gate capacity, 34 High side drive circuit 36, low side drive circuit, D1 to D4 diode, S1 high side switching element of the first drive circuit, S2 low side switching element of the first drive circuit, S3 high side switching element of the second drive circuit, S4 of the second drive circuit Low-side switching element.

Claims (4)

A gate drive circuit for a voltage driven switching element,
A voltage source; a first ground; and a first switching element connected to a gate terminal of the voltage-driven switching element and electrically connecting the voltage source and the gate terminal when the gate capacitance of the voltage-driven switching element is charged. A first switching circuit comprising: a second switching element connected to the gate terminal and conducting the gate terminal and the first ground when the gate capacitance is discharged;
An auxiliary power supply having a voltage lower than that of the voltage source; a second ground; a third switching element connected to the gate terminal and conducting the auxiliary power supply and the gate terminal when the gate capacitance is charged; and the gate terminal A second switching circuit comprising: a fourth switching element connected to the first switching element and electrically connecting the gate terminal and the second ground when the gate capacitance is discharged;
With
The second drive circuit is connected to the gate terminal via a capacitor having a withstand voltage characteristic equal to or higher than the voltage of the voltage source,
The gate drive circuit of a voltage drive type switching device, wherein the second drive circuit and the capacitor are connected to the gate terminal in parallel with the first drive circuit. It is a gate drive circuit of the voltage drive type switching element according to claim 1,
A first diode having a forward direction from the auxiliary power source toward the gate terminal;
The gate of the voltage-driven switching element, wherein the first diode is disposed between a connection point connecting the capacitor and the third and fourth switching elements and the third switching element. Driving circuit. It is a gate drive circuit of the voltage drive type switching element according to claim 1 or 2,
A second diode having a forward direction from the gate terminal toward the second ground,
The gate of the voltage-driven switching element, wherein the second diode is disposed between a connection point connecting the capacitor and the third and fourth switching elements and the fourth switching element. Driving circuit. It is a gate drive circuit of the voltage drive type switching element according to any one of claims 1 to 3,
The auxiliary power supply voltage Vcc2 and the capacitor capacitance C1 are set such that C1 × Vcc2 / (C1 + Cg) <Vmrr using the gate capacitance Cg and the gate terminal voltage Vmrr in the mirror period during charging and discharging of the gate capacitance Cg. A gate drive circuit for a voltage-driven switching element, characterized in that the gate drive circuit is defined so as to satisfy.

Images