JP2017019679A - Silicon carbide epitaxial substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide epitaxial substrate capable of improving a conversion ratio from a basal plane dislocation to a threading edge dislocation.SOLUTION: A silicon carbide epitaxial substrate 50 includes a silicon carbide single crystal substrate 30, a first silicon carbide layer 10 and a second silicon carbide layer 20. The first silicon carbide layer 10 is on the silicon carbide single crystal substrate, and the second silicon carbide layer 20 is on the first silicon carbide layer. The first silicon carbide layer 10 is formed by alternately laminating a first impurity layer 1 and a second impurity layer 2. When the first impurity layer 1 and the second impurity layer 2 are used as one period, the lamination period of the first impurity layer 1 and the second impurity layer 2 is two or more periods. The concentration of a n type impurity included in the first impurity layer 1 is higher than that of a n type impurity included in the second impurity layer 2. The first impurity layer 1 is contacted with the silicon carbide single crystal substrate 30.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a silicon carbide epitaxial substrate.

  2. Description of the Related Art In recent years, silicon carbide has been increasingly used as a material for semiconductor devices in order to enable higher breakdown voltages, lower losses, and use in high-temperature environments for semiconductor devices such as MOSFETs (Metal Oxide Field Effect Transistors). It is being

  For example, Japanese Patent Laid-Open No. 2002-329670 (Patent Document 1) discloses a method of epitaxially growing a silicon carbide thin film on a silicon carbide substrate by a CVD (Chemical Vapor Deposition) method.

JP 2002-329670 A

  An object of the present disclosure is to provide a silicon carbide epitaxial substrate capable of improving the conversion rate from basal plane dislocations to threading edge dislocations.

  A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide single crystal substrate, a first silicon carbide layer, and a second silicon carbide layer. The first silicon carbide layer is on the silicon carbide single crystal substrate. The second silicon carbide layer is on the first silicon carbide layer. The first silicon carbide layer is configured by alternately laminating first impurity layers and second impurity layers. When the first impurity layer and the second impurity layer have one period, the stacking period of the first impurity layer and the second impurity layer is two periods or more. The silicon carbide single crystal substrate, the first impurity layer, the second impurity layer, and the second silicon carbide layer have n-type impurities. The n-type impurity concentration in the first impurity layer is higher than the n-type impurity concentration in the second impurity layer. The first impurity layer is in contact with the silicon carbide single crystal substrate.

  According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate capable of improving the conversion rate from basal plane dislocations to threading edge dislocations.

It is a cross-sectional schematic diagram which shows the structure of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a figure which shows roughly the density distribution of the n-type impurity of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a figure which shows schematically the density distribution of the n-type impurity of the silicon carbide epitaxial substrate which concerns on the 1st modification of this embodiment. It is a figure which shows schematically the density distribution of the n-type impurity of the silicon carbide epitaxial substrate which concerns on the 2nd modification of this embodiment. It is a cross-sectional schematic diagram which shows the structure of the silicon carbide epitaxial substrate which concerns on the 3rd modification of this embodiment. It is a figure which shows schematically the density distribution of the n-type impurity of the silicon carbide epitaxial substrate which concerns on the 3rd modification of this embodiment. It is a figure which shows schematically the density distribution of the n-type impurity of the silicon carbide epitaxial substrate which concerns on the 4th modification of this embodiment. It is a figure which shows schematically the density distribution of the n-type impurity of the silicon carbide epitaxial substrate which concerns on the 5th modification of this embodiment. It is a partial cross section schematic diagram which shows the structure of the manufacturing apparatus of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 1st process of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 2nd process of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 3rd process of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 4th process of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 5th process of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 6th process of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment.

[Description of Embodiment]
(1) A silicon carbide epitaxial substrate 50 according to the present disclosure includes a silicon carbide single crystal substrate 30, a first silicon carbide layer 10, and a second silicon carbide layer 20. First silicon carbide layer 10 is on a silicon carbide single crystal substrate. Second silicon carbide layer 20 is on the first silicon carbide layer. The first silicon carbide layer 10 is configured by alternately stacking the first impurity layer 1 and the second impurity layer 2. When the first impurity layer 1 and the second impurity layer 2 have one period, the stacking period of the first impurity layer 1 and the second impurity layer 2 is two or more periods. Silicon carbide single crystal substrate 30, first impurity layer 1, second impurity layer 2, and second silicon carbide layer 20 have n-type impurities. The concentration of the n-type impurity included in the first impurity layer 1 is higher than the concentration of the n-type impurity included in the second impurity layer 2. First impurity layer 1 is in contact with silicon carbide single crystal substrate 30.

  Dislocations are usually present in silicon carbide single crystal substrate 30. Dislocations present in silicon carbide include basal plane dislocations in which the direction of dislocation lines is parallel to the {0001} plane, and threading edge dislocations and threading in which the direction of dislocation lines is substantially perpendicular to the {0001} plane. A screw dislocation is known. The threading screw dislocation and the basal plane dislocation have the same Burgers vector. Therefore, threading edge dislocations and basal plane dislocations can be distinguished by the direction of dislocation lines.

  If basal plane dislocations are present in the silicon carbide epitaxial substrate, the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate is reduced. Specifically, basal plane dislocations may extend to stacking faults at the interface between the P-type region and the N-type region, which may reduce the reliability of the gate insulating film. On the other hand, even though the threading edge dislocation exists in the silicon carbide epitaxial substrate, it hardly affects the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate. Therefore, it is desirable to convert the basal plane dislocations existing in the silicon carbide single crystal substrate into threading edge dislocations and reduce the number of basal plane dislocations.

  According to silicon carbide epitaxial substrate 50 according to (1) above, first silicon carbide layer 10 is configured by alternately stacking first impurity layer 1 and second impurity layer 2. When the first impurity layer 1 and the second impurity layer 2 have one period, the stacking period of the first impurity layer 1 and the second impurity layer 2 is two or more periods. The concentration of the n-type impurity included in the first impurity layer 1 is higher than the concentration of the n-type impurity included in the second impurity layer 2. Thereby, the conversion rate from a basal plane dislocation to a threading edge dislocation can be improved.

  The mechanism by which basal plane dislocations are converted to threading edge dislocations is considered as follows. First, nitrogen, which is an n-type impurity, functions as a donor by being replaced with carbon in silicon carbide. The covalent bond radius of nitrogen is smaller than the covalent bond radius of carbon. Therefore, the silicon carbide crystal doped with nitrogen is contracted more than the silicon carbide crystal not doped with nitrogen. That is, the silicon carbide crystal having a high nitrogen doping concentration is contracted more than the silicon carbide crystal having a low nitrogen doping concentration. When the second impurity layer 2 having a low nitrogen dopant concentration is disposed on the first impurity layer 1 having a high nitrogen dopant concentration, the first impurity layer 1 is contracted, so that the second impurity layer 2 is compressed. Stress is acting. The basal plane dislocation extending from the first impurity layer 1 to the second impurity layer 2 due to the compressive stress acting on the second impurity layer 2 causes the first impurity layer 1, the second impurity layer 2, It is thought that it becomes easy to be converted into a threading edge dislocation at the boundary surface.

  (2) In silicon carbide epitaxial substrate 50 according to (1) above, the value obtained by dividing the concentration of n-type impurities contained in silicon carbide single crystal substrate 30 by the concentration of n-type impurities contained in first impurity layer 1 is 0. It may be greater than 1 and less than 10. When the difference between the concentration of n-type impurity contained in silicon carbide single crystal substrate 30 and the concentration of n-type impurity contained in first impurity layer 1 is large, the interface between silicon carbide single crystal substrate 30 and first impurity layer 1 In this case, a new stacking fault may occur. The silicon carbide epitaxial substrate 50 according to the present embodiment has a small difference between the concentration of the n-type impurity contained in the silicon carbide single crystal substrate 30 and the concentration of the n-type impurity contained in the first impurity layer 1. It is possible to suppress the occurrence of a new stacking fault at the interface between the substrate 30 and the first impurity layer 1.

(3) Value obtained by dividing the concentration of n-type impurities contained in first impurity layer 1 by the concentration of n-type impurities contained in second impurity layer 2 in silicon carbide epitaxial substrate 50 according to (1) or (2) above. ^{May be} 10 ² or more and 10 ⁵ or less. Thereby, the difference between the nitrogen concentration contained in the second impurity layer 2 and the nitrogen concentration contained in the first impurity layer 1 is increased, and the compressive stress acting on the second impurity layer 2 is increased. Therefore, the conversion rate from the basal plane dislocation to the threading edge dislocation can be further improved.

(4) In silicon carbide epitaxial substrate 50 according to (3) above, the value obtained by dividing the concentration of n-type impurities contained in first impurity layer 1 by the concentration of n-type impurities contained in second impurity layer 2 is 10 ³ It may be 10 ⁴ or less.

  (5) In silicon carbide epitaxial substrate 50 according to any of (1) to (4) above, the thickness of first impurity layer 1 may be not less than 20 nm and not more than 500 nm.

  (6) In silicon carbide epitaxial substrate 50 according to any of (1) to (5) above, the thickness of second impurity layer 2 may be not less than 20 nm and not more than 500 nm.

(7) In silicon carbide epitaxial substrate 50 according to any of (1) to (6) above, the stacking period may be not less than 3 periods and not more than 50 periods. By setting the stacking period to 3 cycles or more, the opportunity to convert from basal plane dislocations to threading edge dislocations increases. Therefore, the conversion rate from the basal plane dislocation to the threading edge dislocation can be further improved. By setting the stacking cycle to 50 cycles or less, it is possible to suppress an increase in the lead time.
[Details of the embodiment]
Embodiments will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the present specification, individual planes are indicated by (), and aggregate planes are indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

First, the configuration of silicon carbide epitaxial substrate 50 according to the embodiment will be described.
As shown in FIG. 1, silicon carbide epitaxial substrate 50 according to the embodiment mainly includes a silicon carbide single crystal substrate 30, a first silicon carbide layer 10, and a second silicon carbide layer 20. Silicon carbide single crystal substrate 30 is, for example, a hexagonal silicon carbide single crystal having polytype 4H. First silicon carbide layer 10 is on silicon carbide single crystal substrate 30. First silicon carbide layer 10 is, for example, a buffer layer. First silicon carbide layer 10 is an epitaxial layer formed in contact with silicon carbide single crystal substrate 30 by epitaxial growth. Second silicon carbide layer 20 is on first silicon carbide layer 10. Second silicon carbide layer 20 is an epitaxial layer formed in contact with first silicon carbide layer 10 by epitaxial growth. Second silicon carbide layer 20 is, for example, a drift layer.

  The first silicon carbide layer 10 is configured by alternately stacking the first impurity layer 1 and the second impurity layer 2. As shown in FIG. 1, first impurity layer 1 is provided on a silicon carbide single crystal substrate 30. First impurity layer 1 is in contact with silicon carbide single crystal substrate 30. A second impurity layer 2 is provided on the first impurity layer 1. The first impurity layer 1 and the second impurity layer 2 constitute a first stacked film 11. A third impurity layer 3 (corresponding to the first impurity layer) is provided on the second impurity layer 2. A fourth impurity layer 4 (corresponding to the second impurity layer) is provided on the third impurity layer 3. The third impurity layer 3 and the fourth impurity layer 4 constitute a second stacked film 12. A second silicon carbide layer 20 is provided on fourth impurity layer 4. First impurity layer 1, second impurity layer 2, third impurity layer 3, and fourth impurity layer 4 constitute first silicon carbide layer 10. As shown in FIG. 1, when the first impurity layer 1 and the second impurity layer 2 have one period, the stacking period of the first impurity layer 1 and the second impurity layer 2 is two periods. The stacking period of the first impurity layer 1 and the second impurity layer 2 may be two or more.

  Silicon carbide single crystal substrate 30 is made of, for example, polytype 4H hexagonal silicon carbide. Surface S1 of silicon carbide single crystal substrate 30 is, for example, a surface inclined by an off angle from the basal plane. The basal plane is, for example, a {0001} plane, and specifically a (0001) plane. The off angle is, for example, not less than 2 ° and not more than 8 °. The off direction may be the <1-100> direction or the <11-20> direction. The maximum diameters of the front surface S1 and the back surface S2 are, for example, 100 mm or more, preferably 150 mm or more.

Silicon carbide single crystal substrate 30, first impurity layer 1, second impurity layer 2, third impurity layer 3, fourth impurity layer 4, and second silicon carbide layer 20 are made of n such as nitrogen, for example. Contains type impurities. The concentration of the n-type impurity included in the first impurity layer 1 is higher than the concentration of the n-type impurity included in the second impurity layer 2. The concentration of n-type impurities such as nitrogen included in the first impurity layer 1 is, for example, 5 × 10 ¹⁸ cm ⁻³ . The concentration of the n-type impurity such as nitrogen included in the first impurity layer 1 may be, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. The concentration of the n-type impurity such as nitrogen included in the second impurity layer 2 is, for example, 5 × 10 ¹⁵ cm ⁻³ . The concentration of the n-type impurity such as nitrogen contained in the second impurity layer 2 may be 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. A value obtained by dividing the concentration of the n-type impurity contained in the first impurity layer 1 by the concentration of the n-type impurity contained in the second impurity layer 2 is, for example, 10 ² or more and 10 ⁵ or less, preferably 10 ³ or more and 10 ⁴ or less. It is.

  The thickness T1 of the first impurity layer 1 is, for example, 100 nm. The thickness T1 may be not less than 20 nm and not more than 500 nm. The thickness T1 may be 50 nm or more, or 100 nm or less. Similarly, the thickness T2 of the second impurity layer 2 is, for example, 100 nm. The thickness T2 may be 20 nm or more and 500 nm or less. The thickness T2 may be 50 nm or more, or 100 nm or less. Silicon carbide single crystal substrate 30 has a thickness greater than that of first silicon carbide layer 10. Thickness T8 of silicon carbide single crystal substrate 30 is not less than 250 μm and not more than 700 μm, for example. The thickness T7 of the second silicon carbide layer 20 may be larger than the thickness of the first silicon carbide layer 10. The thickness T7 of the second silicon carbide layer 20 is, for example, 10 μm. The thickness T3 of the third impurity layer 3 is substantially the same as the thickness T1 of the first impurity layer 1. Similarly, the thickness T4 of the fourth impurity layer 4 is substantially the same as the thickness T2 of the second impurity layer 2.

  As shown in FIG. 2, first impurity layer 1 is in contact with silicon carbide single crystal substrate 30 at position a1. The concentration D3 of the n-type impurity included in the silicon carbide single crystal substrate 30 may be higher than the concentration D1 of the n-type impurity included in the first impurity layer 1. Conversely, the concentration D3 of the n-type impurity included in the silicon carbide single crystal substrate 30 may be lower than the concentration D1 of the n-type impurity included in the first impurity layer 1. Preferably, the value obtained by dividing the concentration of n-type impurities contained in silicon carbide single crystal substrate 30 by the concentration of n-type impurities contained in first impurity layer 1 is greater than 0.1 and less than 10. The value obtained by dividing the concentration of the n-type impurity contained in the silicon carbide single crystal substrate 30 by the concentration of the n-type impurity contained in the first impurity layer 1 may be greater than 1 or less than 5. In FIG. 2, the horizontal axis indicates the position in the direction along the arrow X shown in FIG. The arrow X is a direction perpendicular to the surface S1. The position 0 is a position corresponding to the back surface S2. The same applies to FIGS. 3 and 4.

  As shown in FIG. 2, the second impurity layer 2 is in contact with the first impurity layer 1 at a position a2. The n-type impurity concentration D2 included in the second impurity layer 2 is lower than the n-type impurity concentration D1 included in the first impurity layer 1. The third impurity layer 3 is in contact with the second impurity layer 2 at the position a3. The n-type impurity concentration D 1 included in the third impurity layer 3 is higher than the n-type impurity concentration D 2 included in the second impurity layer 2. The concentration of the n-type impurity included in the third impurity layer 3 is substantially the same as the concentration of the n-type impurity included in the first impurity layer 1.

  The fourth impurity layer 4 is in contact with the third impurity layer 3 at the position a4. The concentration of the n-type impurity included in the fourth impurity layer 4 is lower than the concentration of the n-type impurity included in the third impurity layer 3. The concentration of the n-type impurity included in the fourth impurity layer 4 is substantially the same as the concentration of the n-type impurity included in the second impurity layer 2. Second silicon carbide layer 20 is in contact with fourth impurity layer 4 at position a5. The concentration D4 of the n-type impurity included in the second silicon carbide layer 20 may be lower than the concentration of the n-type impurity included in the second impurity layer 2. The concentration D4 of the n-type impurity included in the second silicon carbide layer 20 is higher than the concentration D2 of the n-type impurity included in the second impurity layer 2, and lower than the concentration D1 of the n-type impurity included in the first impurity layer 1. May be.

  Next, the configuration of silicon carbide epitaxial substrate 50 according to the first modification of the above embodiment will be described.

  As shown in FIG. 3, n-type impurity concentration D <b> 3 included in silicon carbide single crystal substrate 30 may be substantially the same as n-type impurity concentration D <b> 1 included in first impurity layer 1. At the position a1 of the boundary surface between the silicon carbide single crystal substrate 30 and the first impurity layer 1, the concentration D3 of the n-type impurity included in the silicon carbide single crystal substrate 30 is the concentration D1 of the n-type impurity included in the first impurity layer 1. It may be the same. The concentration D4 of the n-type impurity included in the second silicon carbide layer 20 may be lower or higher than the concentration of the n-type impurity included in the fourth impurity layer 4.

  Next, the configuration of silicon carbide epitaxial substrate 50 according to the second modification of the embodiment will be described.

  As shown in FIG. 4, the concentration D4 of the n-type impurity included in the second silicon carbide layer 20 may be substantially the same as the concentration D2 of the n-type impurity included in the fourth impurity layer 4. At the position a5 of the boundary surface between the second silicon carbide layer 20 and the fourth impurity layer 4, the concentration D4 of the n-type impurity contained in the second silicon carbide layer 20 is the concentration D2 of the n-type impurity contained in the fourth impurity layer 4. It may be the same.

  The concentration D3 of the n-type impurity included in the silicon carbide single crystal substrate 30 may be substantially the same as the concentration D1 of the n-type impurity included in the first impurity layer 1. The concentration D3 of the n-type impurity contained in the silicon carbide single crystal substrate 30 may be higher or lower than the concentration D1 of the n-type impurity contained in the first impurity layer 1.

  Next, the configuration of silicon carbide epitaxial substrate 50 according to the third modification of the above embodiment will be described.

  As shown in FIG. 5, the first silicon carbide layer 10 includes a first impurity layer 1, a second impurity layer 2, a third impurity layer 3, a fourth impurity layer 4, and a fifth impurity layer 5 ( And a sixth impurity layer 6 (corresponding to the second impurity layer). A fifth impurity layer 5 is provided on the fourth impurity layer 4. A sixth impurity layer 6 is provided on the fifth impurity layer 5. A second silicon carbide layer 20 is provided on sixth impurity layer 6. The fifth impurity layer 5 and the sixth impurity layer 6 constitute a third stacked film 13. The thickness T5 of the fifth impurity layer 5 is substantially the same as the thickness T1 of the first impurity layer 1. Similarly, the thickness T6 of the sixth impurity layer 6 is substantially the same as the thickness T2 of the second impurity layer 2. As shown in FIG. 5, when the first impurity layer 1 and the second impurity layer 2 have one period, the stacking period of the first impurity layer 1 and the second impurity layer 2 is three periods. Preferably, the stacking cycle is 3 cycles or more and 50 cycles or less, more preferably 5 cycles or more and 10 cycles or less.

  As shown in FIG. 6, n-type impurity concentration D3 included in silicon carbide single crystal substrate 30 may be higher than n-type impurity concentration D1 included in first impurity layer 1. The fifth impurity layer 5 is in contact with the fourth impurity layer 4 at the position a5. The concentration of the n-type impurity included in the fifth impurity layer 5 is substantially the same as the concentration D1 of the n-type impurity included in the first impurity layer 1. The sixth impurity layer 6 is in contact with the fifth impurity layer 5 at the position a6. The concentration of the n-type impurity included in the sixth impurity layer 6 is substantially the same as the concentration D2 of the n-type impurity included in the second impurity layer 2. Second silicon carbide layer 20 is in contact with sixth impurity layer 6 at position a7. The concentration D4 of the n-type impurity included in the second silicon carbide layer 20 may be lower than the concentration of the n-type impurity included in the sixth impurity layer 6. In FIG. 6, the horizontal axis indicates the position in the direction along the arrow X shown in FIG. The arrow X is a direction perpendicular to the surface S1. The position 0 is a position corresponding to the back surface S2. The same applies to FIG. 7 and FIG.

  Next, the configuration of silicon carbide epitaxial substrate 50 according to the fourth modification of the above embodiment will be described.

  As shown in FIG. 7, n-type impurity concentration D <b> 3 included in silicon carbide single crystal substrate 30 may be substantially the same as n-type impurity concentration D <b> 1 included in first impurity layer 1. At the position a1 of the boundary surface between the silicon carbide single crystal substrate 30 and the first impurity layer 1, the concentration D3 of the n-type impurity included in the silicon carbide single crystal substrate 30 is the concentration D1 of the n-type impurity included in the first impurity layer 1. It may be the same. The concentration D4 of the n-type impurity contained in the second silicon carbide layer 20 may be lower or higher than the concentration of the n-type impurity contained in the sixth impurity layer 6.

  Next, the configuration of silicon carbide epitaxial substrate 50 according to the fifth modification of the above embodiment will be described.

  As shown in FIG. 8, the concentration D4 of the n-type impurity included in the second silicon carbide layer 20 may be substantially the same as the concentration of the n-type impurity included in the sixth impurity layer 6. At the position a7 of the boundary surface between the second silicon carbide layer 20 and the sixth impurity layer 6, the concentration D4 of the n-type impurity included in the second silicon carbide layer 20 is equal to the concentration of the n-type impurity included in the sixth impurity layer 6. It may be the same.

  The concentration D3 of the n-type impurity included in the silicon carbide single crystal substrate 30 may be substantially the same as the concentration D1 of the n-type impurity included in the first impurity layer 1. The concentration D3 of the n-type impurity contained in the silicon carbide single crystal substrate 30 may be higher or lower than the concentration D1 of the n-type impurity contained in the first impurity layer 1.

  In the present embodiment, the first silicon carbide layer 10 is configured by alternately laminating the first impurity layer 1 and the second impurity layer 2 in the direction of arrow X (see FIG. 5). In (stacking direction), it means that the concentration of n-type impurities changes alternately. Therefore, the concentration of the n-type impurity included in the third impurity layer 3 and the fifth impurity layer 5 may be different from the concentration of the n-type impurity included in the first impurity layer 1. Similarly, the concentration of the n-type impurity included in the fourth impurity layer 4 and the sixth impurity layer 6 may be different from the concentration of the n-type impurity included in the second impurity layer 2. The thicknesses of the third impurity layer 3 and the fifth impurity layer 5 may be different from the thickness of the first impurity layer 1. Similarly, the thickness of the fourth impurity layer 4 and the sixth impurity layer 6 may be different from the thickness of the second impurity layer 2.

  Next, the structure of the manufacturing apparatus of the silicon carbide epitaxial substrate which concerns on this embodiment is demonstrated.

  As shown in FIG. 9, a CVD apparatus 40 as an example of an apparatus for manufacturing a silicon carbide epitaxial substrate includes a quartz tube 43, an induction heating coil 44, a heat insulating material 42, a heating element 41, a pipe 60, 1 gas cylinder 51, 2nd gas cylinder 52, 3rd gas cylinder 53, 4th gas cylinder 54, and substrate holder 46 are mainly included. Specifically, the heating element 41 has a hollow structure and has a reaction chamber 45 formed therein. The heat insulating material 42 is disposed so as to surround the outer periphery of the heating element 41. The quartz tube 43 is disposed so as to surround the outer peripheral side of the heat insulating material 42. The induction heating coil 44 is provided so as to wind the outer peripheral side of the quartz tube 43. The pipe 60 communicates with the reaction chamber 45.

The first gas cylinder 51 is filled with, for example, hydrogen (H ₂ ) gas that is a carrier gas. The second gas cylinder 52 and the third gas cylinder 53 are filled with, for example, silane (SiH ₄ ) gas and propane (C ₃ H ₈ ) gas, which are raw materials for silicon carbide, respectively. The fourth gas cylinder 54 is filled with, for example, ammonia (NH ₃ ) gas or nitrogen (N ₂ ) gas that is a dopant gas. The pipe 60 is configured such that the gas can be introduced into the reaction chamber 45.

Next, the manufacturing method of the silicon carbide epitaxial substrate which concerns on embodiment is demonstrated.
First, a step of preparing a silicon carbide single crystal substrate is performed. For example, a silicon carbide single crystal substrate 30 having a front surface S1 and a back surface S2 is prepared by slicing an ingot made of a silicon carbide single crystal formed by a sublimation method (see FIG. 10). As shown in FIG. 10, the surface S1 is a surface inclined by an off angle from the basal plane S3. The basal plane S3 is, for example, a {0001} plane, preferably a (0001) plane. The off angle is, for example, not less than 2 ° and not more than 8 °. The off direction may be the <1-100> direction or the <11-20> direction. Silicon carbide single crystal substrate 30 is made of, for example, polytype 4H hexagonal silicon carbide. The maximum diameter of surface S1 of silicon carbide single crystal substrate 30 is, for example, 100 mm or more, and preferably 150 mm or more. As shown in FIG. 10, basal plane dislocations B <b> 1 and B <b> 2 are formed on silicon carbide single crystal substrate 30. The basal plane dislocations B1 and B2 are dislocations extending in a direction parallel to the basal plane S3. The basal plane dislocations B1 and B2 may be exposed, for example, on the front surface S1 and the back surface S2.

Next, a step of forming a first silicon carbide layer is performed. First, silicon carbide single crystal substrate 30 is arranged inside reaction chamber 45 of CVD apparatus 40. Silicon carbide single crystal substrate 30 is placed on a substrate holder 46 such as a susceptor. Next, a carrier gas containing hydrogen (H ₂ ) and a source gas containing monosilane (SiH ₄ ), propane (C ₃ H ₈ ), nitrogen (N ₂ ), and the like are introduced into the reaction chamber 45. That is, the source gas has a gas containing Si, a gas containing C, and a dopant gas containing N. The source gas may have ammonia gas. A mixed gas G containing a source gas and a dopant gas is supplied into the reaction chamber 45.

  When a high frequency current is passed through the induction heating coil 44, the heating element 41 is induction heated by electromagnetic induction. Thereby, silicon carbide single crystal substrate 30 and mixed gas G in reaction chamber 45 are heated to a predetermined temperature. Silicon carbide single crystal substrate 30 and mixed gas G are heated to, for example, about 1500 ° to 1700 °. Thereby, first impurity layer 1 is formed on silicon carbide single crystal substrate 30. Preferably, in the step of forming the first impurity layer 1, a source gas having a ratio (C / Si ratio) obtained by dividing the number of carbon atoms by the number of silicon atoms is 2.0 or less is used.

  The C / Si ratio may be 0.8 or more and 1.5 or less, or 0.9 or more and 1.3 or less. When the C / Si ratio is small, nitrogen atoms as dopants are easily taken into the first impurity layer 1. Therefore, the concentration of the n-type impurity included in the first impurity layer 1 can be increased. The thickness T1 of the first impurity layer 1 is, for example, not less than 20 nm and not more than 500 nm. As shown in FIG. 11, a large number of basal plane dislocations B <b> 1 and B <b> 2 existing in silicon carbide single crystal substrate 30 are taken over by first impurity layer 1.

  Next, a step of forming a second impurity layer is performed. Similar to the step of forming the first impurity layer, the mixed gas G containing the carrier gas and the source gas and the silicon carbide single crystal substrate 30 are heated in the reaction chamber 45, so that the first impurity layer 1 is formed on the first impurity layer 1. A second impurity layer 2 is formed (see FIG. 12). Preferably, in the step of forming the second impurity layer 2, a source gas having a ratio (C / Si ratio) obtained by dividing the number of carbon atoms by the number of silicon atoms is greater than 1.0.

  The C / Si ratio may be greater than 1.0 and 3.0 or less, for example, or 1.5 or more and 2.5 or less. When the C / Si ratio is large, nitrogen atoms as dopants are difficult to be taken into the second impurity layer 2. Therefore, the n-type impurity concentration included in the second impurity layer 2 can be lowered. By reducing the flow rate of nitrogen in the step of forming the second impurity layer 2 below the flow rate of nitrogen in the step of forming the first impurity layer 1, the concentration of the n-type impurity contained in the second impurity layer 2 is reduced. You may make it lower than the density | concentration of the n-type impurity which 1 impurity layer 1 contains. The thickness T2 of the second impurity layer 2 is, for example, not less than 20 nm and not more than 500 nm.

  As shown in FIG. 12, in the vicinity of the boundary surface between the first impurity layer 1 and the second impurity layer 2, the basal plane dislocation B1 existing in the first impurity layer 1 is converted to B3 as a threading edge dislocation. Is done. The mechanism by which the basal plane dislocation B1 is converted into the threading edge dislocation B3 is as described above. In the second impurity layer 2, there may be basal plane dislocations B2 that are not converted to threading edge dislocations.

  Next, a step of forming a third impurity layer is performed. The third impurity layer 3 is formed by the same method as the first impurity layer 1. As shown in FIG. 2, the concentration of nitrogen included in the third impurity layer 3 may be substantially the same as the concentration of nitrogen included in the first impurity layer 1. The thickness of the third impurity layer 3 may be substantially the same as the thickness of the first impurity layer 1. As shown in FIG. 13, the threading edge dislocations B <b> 3 in the second impurity layer 2 are inherited by the third impurity layer 3. Similarly, the basal plane dislocations B <b> 2 in the second impurity layer 2 are inherited by the third impurity layer 3.

  Next, a step of forming a fourth impurity layer is performed. The fourth impurity layer 4 is formed by the same method as the second impurity layer 2. As shown in FIG. 2, the concentration of nitrogen contained in the fourth impurity layer 4 may be substantially the same as the concentration of nitrogen contained in the second impurity layer 2. The thickness of the fourth impurity layer 4 may be substantially the same as the thickness of the second impurity layer 2. As shown in FIG. 14, the basal plane dislocation B2 existing in the third impurity layer 3 in the vicinity of the boundary surface between the third impurity layer 3 and the fourth impurity layer 4 is converted into a threading edge dislocation B4. Is done. The threading edge dislocation B3 in the third impurity layer 3 is taken over by the fourth impurity layer 4. As described above, at the boundary surface between the first impurity layer 1 and the second impurity layer 2, the basal plane dislocation B2 that has not been converted into the threading edge dislocation is the boundary surface between the third impurity layer 3 and the fourth impurity layer 4. , The basal plane dislocation B2 is converted to the threading edge dislocation B4. Thus, as the number of stacked first impurity layers 1 and second impurity layers 2 increases, the opportunity for conversion from the basal plane dislocation B2 to the threading edge dislocation B4 increases. As a result, the conversion rate is improved.

Next, a step of forming a second silicon carbide layer is performed. In the reaction chamber 45, the mixed gas G containing the carrier gas and the source gas and the silicon carbide single crystal substrate 30 are heated, whereby the second silicon carbide layer 20 is formed on the fourth impurity layer 4. In the step of forming the second silicon carbide layer 20, the ratio (C / Si ratio) obtained by dividing the number of carbon atoms by the number of silicon atoms may be less than 1.0, or 1.0 or more. Also good. The concentration of nitrogen included in second silicon carbide layer 20 is, for example, 5 × 10 ¹⁵ cm ⁻³ . The thickness of second silicon carbide layer 20 may be larger than the thickness of first silicon carbide layer 10.

  The C / Si ratio of the source gas can be changed by changing the flow rate of propane gas while maintaining the flow rate of monosilane gas at a constant value, for example. Similarly, the C / Si ratio of the source gas can be changed by changing the flow rate of the monosilane gas while maintaining the flow rate of the propane gas at a constant value.

  Next, the effect of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment will be described.

  According to silicon carbide epitaxial substrate 50 according to the present embodiment, first silicon carbide layer 10 is configured by alternately stacking first impurity layer 1 and second impurity layer 2. When the first impurity layer 1 and the second impurity layer 2 have one period, the stacking period of the first impurity layer 1 and the second impurity layer 2 is two or more periods. The concentration of the n-type impurity included in the first impurity layer 1 is higher than the concentration of the n-type impurity included in the second impurity layer 2. Thereby, the conversion rate from a basal plane dislocation to a threading edge dislocation can be improved.

  In addition, according to silicon carbide epitaxial substrate 50 according to the present embodiment, the value obtained by dividing the concentration of n-type impurity contained in silicon carbide single crystal substrate 30 by the concentration of n-type impurity contained in first impurity layer 1 is 0. Greater than 1 and less than 10. When the difference between the concentration of n-type impurity contained in silicon carbide single crystal substrate 30 and the concentration of n-type impurity contained in first impurity layer 1 is large, the interface between silicon carbide single crystal substrate 30 and first impurity layer 1 In this case, a new stacking fault may occur. The silicon carbide epitaxial substrate 50 according to the present embodiment has a small difference between the concentration of the n-type impurity contained in the silicon carbide single crystal substrate 30 and the concentration of the n-type impurity contained in the first impurity layer 1. It is possible to suppress the occurrence of a new stacking fault at the interface between the substrate 30 and the first impurity layer 1.

Furthermore, according to silicon carbide epitaxial substrate 50 according to the present embodiment, the value obtained by dividing the concentration of n-type impurity contained in first impurity layer 1 by the concentration of n-type impurity contained in second impurity layer 2 is 10 ² or more. 10 ⁵ or less. Thereby, the difference between the nitrogen concentration contained in the second impurity layer 2 and the nitrogen concentration contained in the first impurity layer 1 is increased, and the compressive stress acting on the second impurity layer 2 is increased. Therefore, the conversion rate from the basal plane dislocation to the threading edge dislocation can be further improved.

Furthermore, according to silicon carbide epitaxial substrate 50 according to the present embodiment, the value obtained by dividing the concentration of n-type impurity contained in first impurity layer 1 by the concentration of n-type impurity contained in second impurity layer 2 is 10 ³ or more. 10 ⁴ or less.

  Furthermore, according to silicon carbide epitaxial substrate 50 according to the present embodiment, the thickness of first impurity layer 1 is not less than 20 nm and not more than 500 nm.

  Furthermore, according to silicon carbide epitaxial substrate 50 according to the present embodiment, the thickness of second impurity layer 2 is not less than 20 nm and not more than 500 nm.

  Furthermore, according to silicon carbide epitaxial substrate 50 according to the present embodiment, the lamination period is not less than 3 periods and not more than 50 periods. By setting the stacking period to 3 cycles or more, the opportunity to convert from basal plane dislocations to threading edge dislocations increases. Therefore, the conversion rate from the basal plane dislocation to the threading edge dislocation can be further improved. By setting the stacking cycle to 50 cycles or less, it is possible to suppress an increase in the lead time.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 1st impurity layer 2 2nd impurity layer 3 3rd impurity layer 4 4th impurity layer 5 5th impurity layer 6 6th impurity layer 10 1st silicon carbide layers 11, 12, 13 Period 20 2nd silicon carbide layer 30 Carbonization Silicon single crystal substrate 40 manufacturing apparatus 41 heating element 42 heat insulating material 43 quartz tube 44 induction heating coil 45 reaction chamber 46 substrate holder 50 silicon carbide epitaxial substrate 51 first gas cylinder 52 second gas cylinder 53 third gas cylinder 54 fourth gas cylinder 60 piping a1 , A2, a3, a4, a5, a6, a7 position B1, B2 basal plane dislocation B3, B4 threading edge dislocation D1, D2, D3, D4 concentration G mixed gas S1 surface S2 back surface S3 basal plane T1, T2, T3 T4, T5, T6, T7, T8 thickness

Claims (7)

A silicon carbide single crystal substrate;
A first silicon carbide layer on the silicon carbide single crystal substrate;
A second silicon carbide layer on the first silicon carbide layer,
The first silicon carbide layer is configured by alternately laminating first impurity layers and second impurity layers,
When the first impurity layer and the second impurity layer have one cycle, the stacking cycle of the first impurity layer and the second impurity layer is two cycles or more,
The silicon carbide single crystal substrate, the first impurity layer, the second impurity layer, and the second silicon carbide layer have n-type impurities,
The n-type impurity concentration included in the first impurity layer is higher than the n-type impurity concentration included in the second impurity layer.
The first impurity layer is a silicon carbide epitaxial substrate in contact with the silicon carbide single crystal substrate.   2. The carbonization according to claim 1, wherein a value obtained by dividing the concentration of the n-type impurity contained in the silicon carbide single crystal substrate by the concentration of the n-type impurity contained in the first impurity layer is greater than 0.1 and less than 10. 3. Silicon epitaxial substrate. The value obtained by dividing the concentration of the n-type impurity contained in the first impurity layer by the concentration of the n-type impurity contained in the second impurity layer is 10 ² or more and 10 ⁵ or less. Silicon carbide epitaxial substrate. 4. The silicon carbide epitaxial film according to claim 3, wherein a value obtained by dividing the concentration of the n-type impurity contained in the first impurity layer by the concentration of the n-type impurity contained in the second impurity layer is 10 ³ or more and 10 ⁴ or less. substrate.   The thickness of the said 1st impurity layer is a silicon carbide epitaxial substrate of any one of Claims 1-4 which are 20 nm or more and 500 nm or less.   The thickness of the said 2nd impurity layer is a silicon carbide epitaxial substrate of any one of Claims 1-5 which are 20 nm or more and 500 nm or less.   The silicon carbide epitaxial substrate according to any one of claims 1 to 6, wherein the lamination period is not less than 3 periods and not more than 50 periods.

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