JP2017005332A - Cyclic ad converter, digital corrector for cyclic ad converter, and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cyclic AD converter capable of automatically measuring an error coefficient based on an error which occurs in the cyclic AD converter at a desired timing, a digital corrector for the cyclic AD converter, and a method thereof.SOLUTION: A cyclic AD converter 1 comprises: a plurality of capacitors C, C, and Cfor cyclic AD conversion and an operational amplifier 12; a sub-AD converter 13; a DAC 11 which generates a voltage value for cyclic AD conversion on the basis of digital output code; a DAC control clock generating unit 14 which controls the DAC 11; switches S, S, S, S, S, and Swhich control switching of operation phases; and switch groups Sand Swhich can be switched so as to achieve a circuit configuration of error coefficient measuring mode of errors which occur. A digital corrector and a method thereof instruct the cyclic AD converter 1 to switch the switch groups S, S, S, S, and S, and perform digital correction.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technology of a cyclic analog-digital converter, and in particular, a cyclic analog-to-digital (AD) converter for an image sensor with a high frame rate and an ultra-high definition, and a cyclic type. The present invention relates to a digital corrector for an AD converter and a method thereof.

  Conventionally, it is known that a cyclic AD converter is used for a CMOS image sensor (see, for example, Non-Patent Document 1).

  In particular, research and development of a CMOS image sensor with 33 million pixels that operates at a frame rate of 120 Hz has been conducted as an ultra-high-definition image sensor at a high frame rate (see, for example, Non-Patent Documents 2 to 4).

  For example, in a 33 million pixel CMOS image sensor operating at a frame rate of 120 Hz disclosed in Non-Patent Document 2, one horizontal scanning period is as short as about 1.9 μs, and an AD converter arranged for each column includes: High speed is required to perform 12-bit conversion within this period. In the CMOS image sensor, since the AD converters are arranged in about 8000 rows, low power consumption is also an important technical problem. As an AD converter that satisfies these requirements, Non-Patent Document 2 proposes a two-stage cyclic AD converter.

  Here, more specifically, the single-stage cyclic AD converter in the prior art shown in FIG. 12 will be described, and then the single-stage cyclic AD converter shown in FIG. The operation timing of the two-stage cyclic AD converter and the CMOS image sensor to which the two-stage cyclic AD converter is applied will be briefly described.

(One-stage cyclic AD converter)
First, as shown in FIG. 12, cyclic AD converter 1 of one-stage configuration, the switch _{S P,} S _N, a digital-to-analog converter having an _{S MS:} and (DAC Digital-Analog Converter) 11 , 1 single An operational amplifier (operational amplifier) 12, two-stage capacitors C _s (C _s = C _s1 + C _s2 ), C _f, and switches S _R , S _S , S ₀ , S ₁ that can switch each operation phase described later. , S ₂ , S ₃ , a sub AD converter (Sub-ADC) 13, a DAC control clock generation unit 14, and a phase control clock generation unit 15. Each switch is configured to be capable of on / off control using a switch transistor. The DAC control clock generation unit 14 controls each of the clocks Φ _P , S _P , S _MS , S _N to control the DAC 11 based on the digital output code D of the sub AD converter (Sub-ADC) 13. Φ _MS and Φ _N are configured to be generated. The phase control clock generator 15 controls the clocks Φ _S , Φ _R , Φ ₁ for controlling the switches S _S , S _R , S ₁ , S ₂ , S ₃ , S ₀ in order to control each operation phase. , Φ ₂ , Φ ₃ , Φ ₀ are generated.

The one-stage cyclic AD converter 1 shown in FIG. 12 can be classified into four operation phases as described below. V _in is an analog input signal, V _RL and V _RH are input terminals of a reference power source that define a lower limit and an upper limit, respectively, and V _COM is an input terminal of a ground power source that determines a virtual ground.

The first one) reset phase AD conversion operation, the switch _{S 1} off, while turning on the switch _{S 2, S 3, S 0} and _{S R,} the capacitor _C s1 turns on the switch _{S MS} in DAC _{11, C s2} The DAC 11 side electrode plate is connected, and the capacitors C _s1 , C _s2 , and C _f are reset.

2) sampling phase then turns off the switch _{S 0,} and turns on the switch _{S S,} samples the input signal _{V in} input to the sub-AD converter 13, the three values of {0, 1 / 2,1} A / D conversion is performed. The sub A / D converter 13 uses the two comparators (not shown) in the sub A / D converter 13 to generate the digital output code D as shown in Expression (1) using the determination voltages (V _RCH and V _RCL ). Ask.

Such a system using binary values and ternary values is called a 1.5-bit redundancy system. Here, the full scale of the AD conversion by the cyclic AD converter 1 is from the reference power supply _VRL to _VRH . In addition, the determination voltages (V _RCH , V _RCL ) are each expressed as Expression (2).

3) Double Amplification Phase Next, the switches S _S , S ₃ and S _R are turned off, the switch S ₀ is turned on, and the switch in the DAC 11 has two reference power sources V _RH based on the output of the sub AD converter 13. or _V either the _RL that operates to connect the capacitor _{C s1, C s2,} the input signal _{V in} is sampled capacitors _{C s1, C} one terminal of _s2 2 one reference power supply _{V RH} or V _{One of the RLs} is connected, and the other is connected to the negative input terminal of the operational amplifier 12. Thus, the output of the operational amplifier 12, appears the value DA conversion value is subtracted by DAC11 from twice the input signal value _{V in.}

4) feedback phase then turns off the switch _{S 2,} and turns on the switch _{S MS} in the switch _S 1, _{S 3} and DAC 11, one terminal of the amplifier output of 2-fold amplification phase capacitance _{C s1, C s2} ( The sub-A / D converter 13 performs AD conversion using the three values {0, 1/2, 1} on the output voltage value V _out of the operational amplifier 12.

By repeating the operations 3) and 4) as one cycle and repeating a predetermined number of times, AD conversion with a resolution corresponding to the number of times is performed. Now, assuming that V _RH = V _r , V _RL = 0 (the generality of the discussion is not lost even if set in this way), the output of the operational amplifier 12 in the i-th cycle is V _out (i), Assuming that the digital output code of the sub AD converter 13 at that time is D (i), the output V _out (i) of the operational amplifier 12 in the i-th cycle can be expressed as in Expression (3).

Here, C _s = C _s1 + C _s2 . At this time, if C _s = C _f , it can be expressed as in Expression (3).

The conversion characteristic represented by Equation (4) is illustrated in FIG. Thus, since a digital output corresponding to the ternary digital output code D (i) of {0, 1/2, 1} with respect to the output voltage value _Vout per cycle is obtained, this digital output code D ( The digital output corresponding to i) is 2 bits long and can be expressed as 00, 01, 10 respectively. Then, each time of performing N times of patrol, DAC 11 is to the digital output code D (i) is if {0} of the three values _{"S P OFF,} S _N, on the _{S MS"} and digital If the output code D (i) is {1/2} of the ternary value, “ _SP and _SN are turned on and _SMS is turned off”, and the digital output code D (i) is {1} of the ternary value. if _{"S P,} on the _{S MS,} off _{S N"} outputs a DA converted value as. In general, AD conversion with a resolution of N + 1 bits can be performed by redundant N bits by N-1 cycles.

(Two-stage cyclic AD converter)
FIG. 14 shows an example in which the cyclic AD converter shown in FIG. 12 is connected in two stages in cascade to form the two-stage cyclic AD converter 1. In FIG. 14, components corresponding to those between the first-stage cyclic AD converter 1a and the second-stage cyclic AD converter 1b are denoted by subscripts A and B (or a, b) respectively. ) Is attached. The two-stage cyclic AD converter 1, a resolution of _{N F} bits, upper M bits in the first stage of the cyclic AD converter 1a, lower _N F -M bit second-stage cyclic AD converter 1b It is configured to perform AD conversion by dividing the image into two. First, in cyclic AD converter 1a in the first stage, according to the operation method described above, 3) and 4 the operation phase) is repeated M-1 cycles, AD converts the M upper bits as a digital output D _A To do. Here, during the operation shown in 3) of the M-1 cycle, the switch S _SB is turned on, the analog output of the first-stage cyclic AD converter 1a and the second-stage cyclic AD converter 1b. Connect the input. At this time, the second-stage cyclic AD converter 1b performs the operation shown in 2), and the output of the first-stage cyclic AD converter 1a is input to the second-stage cyclic AD converter 1b. Is done. Thereafter, the switch _SSB is turned off to disconnect the second-stage cyclic AD converter 1b from the first-stage cyclic AD converter 1a, and the cycles of 3) and 4) are repeated N _F -M times. , it is possible to AD convert remaining lower _N F -M bits as a digital output _{D B} in cyclic AD converter 1b in the second stage.

(Operation timing of the CMOS image sensor to which a two-stage cyclic AD converter is applied)
In the CMOS image sensor in which the two-stage cyclic AD converter 1 is arranged in each column, the signal of one pixel is AD-converted by the first-stage cyclic AD converter 1a, and then the second-stage cyclic type is converted. When the AD converter 1b AD-converts the remaining lower N _F -M bits, the first-stage cyclic AD converter 1a receives the pixel signal of the next row and similarly AD converts the upper M bits. Thus, by performing pipeline parallel operation between the first-stage cyclic AD converter 1a and the second-stage cyclic AD converter 1b, the effective conversion speed can be increased. For example, the operation timing when N _F = 12 and M = 4 is shown in FIG.

In FIG. 15, the operation 1) in the above description is R (reset), the operation 2) is S (sample), the operation 3) is A (amplifier), and the operation 4) is F (feedback). . Also, the numerical values 1 to 12 described alongside “R” and “S” indicate the bit depth at which each stage of the cyclic AD converters 1a and 1b performs AD conversion. Pixel signal of the CMOS image sensor, after resetting the pixel signals a reset pulse is output by the pixel transfer pulse is sampled by the clock [Phi _SA for controlling ON / OFF of the switches S _A in the first stage of the cyclic AD converter 1a The The analog output of the sampled first stage of the cyclic AD converter 1a is transferred by a clock [Phi _SB for controlling the on / off switch S _B to the second-stage cyclic AD converter 1b. At this time, a pipeline parallel operation is performed between the first-stage cyclic AD converter (first-stage ADC) 1a and the second-stage cyclic AD converter (second-stage ADC) 1b. the analog output of the cyclic AD converter 1a remaining lower 8 bits when AD conversion, the first stage of the cyclic AD converter 1a, the pixel signal of the next line samples to AD conversion by the clock [Phi _SA Therefore, the effective conversion speed can be increased.

  In addition, a cyclic AD converter that satisfies the conditions of high speed, high accuracy, and a small area required for a CMOS image sensor with a high frame rate and an ultra-high definition as disclosed in Non-Patent Document 2, or a two-stage cascaded AD converter It is also known that, in a connected two-stage cyclic AD converter, an error generated in an analog circuit unit that deteriorates AD conversion characteristics can be corrected in the digital domain by a digital output code after AD conversion (for example, Non-patent documents 5 and 6).

Edited by Kiyoharu Aizawa and Takayuki Hamamoto / Takao Kuroda, Junichi Nakamura, Hidekazu Takahashi, Shoji Kawahito, Jun Ota, “CMOS Image Sensor”, The Institute of Image Information and Television Engineers, Corona Publishing Co. Toshihisa Watanabe, et al., “33-megapixel 120fps CMOS image sensor using 12-bit column parallel cyclic ADC,” ITE Technical Report, vol. 34, No. 18, IST2013-13, CE2012-25, pp. 31-36, 2012. T. Watabe, et al., “A 33Mpixel 120fps CMOS Image Sensor Using 12b Column-Parallel Pipelined Cyclic ADCs,” ISSCC Dig. Tech Papers, pp.388-389, 2012. K. Kitamura, et al., “A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters,” IEEE Trans. Electron Devices, Vol. 59, No.12, pp.3426-3433, 2012. T. Watabe, et al., “Digital Calibration Algorithm for a 2-Stage Cyclic Analog-to-Digital Converter Used in a 33-Mpixel 120-fps SHV CMOS Image Sensor,” ITE Trans. Media Technology and Applications, Vol. 2 , No. 2, pp. 102-107, 2014. T. Watabe, et al., “A Digitally-Calibrated 2-Stage Cyclic ADC for a 33-Mpixel 120-fps Super High-Vision CMOS Image Sensor,” in Proc. IEEE SENSORS, pp. 66-69, 2014.

  As described above, in Non-Patent Documents 5 and 6, a cyclic AD converter that satisfies the conditions of high speed, high accuracy, and a small area required for a high frame rate / ultra high definition CMOS image sensor, or two stages thereof are cascaded. In the two-stage cyclic AD converter connected to the AD converter, it is shown that an error generated in an analog circuit unit that deteriorates AD conversion characteristics is corrected in the digital domain by a digital output code after AD conversion.

  However, in the conventional technique, in order to accurately obtain the value of the error coefficient that is a parameter describing the error, trial and error are repeatedly performed based on the error coefficient estimated in the design of each component, and the final result is obtained. Because it is configured to determine a specific error coefficient and hold it as a unique value, it is not easy to absorb variations in solids, and furthermore, there is a problem that it cannot cope with a time change of an error such as a temperature change. . For this reason, there has been a problem that high-precision digital correction cannot be realized.

  In addition, since the analog circuit part constituting the AD conversion circuit includes various errors, the actual output cannot be expressed as in Expression (3). FIG. 16 shows factors of these errors generated in the cyclic AD converter 1 shown in FIG. Each error (and its error coefficient) will be described below.

(Capacity mismatch error)
Since a capacitance mismatch error ΔC = C _s −C _f due to a capacitor manufacturing error is included between the capacitors C _s (= C _s1 + C _s2 ) and C _f of the cyclic AD converter 1 shown in FIG. Equation (3) is expressed as Equation (5).

As shown in equation (5), the amplification factor deviates from twice due to the capacitance mismatch error ΔC. For a ternary digital output code D of {0, 1/2, 1}, when a capacitance mismatch error ΔC _s = C _s1 −C _s2 is included between the capacitors C _s1 and C _s2 , FIG. An error occurs in the straight line in the D = 1/2 region of the input / output characteristics shown in FIG.

Here, D _s (i) is a constant determined by D (i). When D (i) = 0 or 1, D _s (i) = 0, and when D (i) = 1/2, D _s (I) = 1. If each error coefficient of the capacity mismatch error is defined as e _m = ΔC / C _f and e _ms = ΔC _s / C _s , the equation (6) can be expressed as the equation (7).

  Therefore, when Expression (7) is expressed in the digital domain, Expression (8) is obtained.

Here, X (i) = _Vout (i) / _Vr . In the equation (8), the error coefficients e _m and e _ms are sufficiently small. _Therefore , when the term of the product e _m · e _ms is ignored, the capacity mismatch error E _m (i) in the i-th cycle is expressed by the equation (8). 9).

The sum of capacity mismatch errors after N-bit conversion is obtained by integrating E _m (i) from i = 1 to N−1. The sum of capacity mismatch errors after N-bit conversion in the one-stage cyclic AD converter 1 can be expressed as shown in Equation (10).

  Here, assuming that the error included in the digital output code is sufficiently small, X (i) shown in Expression (8) can be approximated as shown in Expression (11).

  Here, i takes an integer value ranging from 0 to N-1 when the resolution of the AD converter circuit is N bits. By substituting equation (11) into equation (10), the total capacity mismatch error is expressed as equation (12).

  On the other hand, the sum of the capacity mismatch errors after N-bit conversion in the two-stage cyclic AD converter 1 shown in FIG. 14 is equal to the first M-bit AD conversion performed by the first-stage cyclic AD converter 1a and 2 By separately calculating the remaining NM bits of AD conversion performed by the cyclic AD converter 1b at the stage, the following expression (13) is obtained.

Here, e _mA and e _mB are the error coefficient of mismatch error between the capacitors C _sA and C _fA of the first-stage cyclic AD converter 1a and the second-stage cyclic AD converter 1b, respectively. _Represents the error coefficient of the capacitance mismatch error between the capacitors C _sB and C _fB , where e _msA and e _msB are capacitance mismatches between the capacitors C _s1A and C _s2A of the first-stage cyclic AD converter 1a, respectively. The error coefficient of the error and the error coefficient of the capacity mismatch error between the capacitors C _s1B and C _s2B of the second-stage cyclic AD converter 1b are shown. Therefore, by substituting Equation (11) into Equation (13), for example, the sum of the capacity mismatch errors when N = 12, M = 4 is expressed as Equation (14).

(Finite amplifier gain error)
In the cyclic AD converter 1 shown in FIG. 12, when the open-loop gain of the operational amplifier 12 is assumed to be infinite, the negative input of the operational amplifier 12 becomes virtual ground (V _COM ), and the closed-loop gain of the double amplification circuit is a capacitance. Since it is determined only by the ratio of C _s to C _f , if C _s = C _f , the input / output characteristics in the double amplification phase have the ideal form expressed by Equation (4), but the actual open loop Since the gain is finite, it is expressed as in equation (15).

Here, G ₀ and C _i represent the open loop gain and input capacitance of the operational amplifier 12, respectively. When the error coefficient of the finite gain error is defined as e _fg = (C _s + C _f + C _i ) / (C _f · G ₀ ) and Expression (15) is expressed in the digital domain, it is expressed as Expression (16). The

Therefore, the finite gain error E _fg (i) in the i-th cycle is expressed as in Expression (17).

  For this reason, the sum of the finite gain errors after the N-bit conversion in the one-stage cyclic AD converter 1 is expressed as in Expression (18).

By substituting equation (11) into equation (18), the total finite gain error is expressed as equation (19) by the error coefficient e _fg of the finite gain error and the digital output code D (i). .

  On the other hand, the sum of the finite gain errors after N-bit conversion in the two-stage cyclic AD converter 1 shown in FIG. 14 is equal to the first M-bit AD conversion performed by the first-stage cyclic AD converter 1a and 2 By separately calculating the remaining NM bits of AD conversion performed by the cyclic AD converter 1b at the stage, the following expression (20) is obtained.

Here, e _fgA and e _fgB represent error coefficients of finite gain errors of the first-stage and second-stage cyclic AD converter circuits, respectively. By substituting equation (11) into equation (20), for example, the sum of finite gain errors when N = 12, M = 4 is expressed as equation (21).

(Amplifier settling error)
In the cyclic AD converter 1 shown in FIG. 12, since the band of the operational amplifier 12 is finite, a settling error occurs due to an output within a finite time being deviated from an ideal value (an output at an infinite time). _Assuming that the _settling error coefficient is _est , the actual input / output characteristics are expressed as in Expression (22).

  When Expression (22) is expressed in the digital domain, Expression (23) is obtained.

Therefore, the _settling error E _st (i) in the i-th cycle is expressed as in Expression (24).

  For this reason, the total settling error after the N-bit conversion in the one-stage cyclic AD converter 1 is expressed as in Expression (25).

By substituting equation (11) into equation (25), the total _settling error is expressed by equation (26) from the _settling error coefficient _est and the digital output code D (i).

On the other hand, the sum of settling errors after N-bit conversion in the two-stage cyclic AD converter 1 shown in FIG. 14 is equal to the first M-bit AD conversion performed by the first-stage cyclic AD converter 1a and 2 The remaining NM bits of AD conversion performed by the cyclic AD converter 1b at the stage are separately calculated, but the cyclic AD converter 1a at the first stage performs the M-1 cycle (M bit AD conversion). The first-stage cyclic AD converter 1a is connected to the second-stage cyclic AD converter 1b that operates in the sampling phase. Is greater than the error in the previous cycle. Therefore, the total _settling error _{Est_t} is calculated as shown in Equation (27).

Here, e _stA and e _stB represent error coefficients of _settling errors of the first-stage and second-stage cyclic AD converters 1a and 1b, respectively, and e _stAB represents the first-stage cyclic AD converter. When 1a is operating in the M-1 cycle double amplification phase, that is, when the first-stage and second-stage cyclic AD converters 1a, 1b are connected, the first-stage cyclic type The error coefficient of the settling error of the AD converter 1a is represented. By substituting equation (11) into equation (27), for example, the total settling error when N = 12, M = 4 is expressed as equation (28).

  Since the finite gain error and the settling error of the operational amplifiers 12a and 12b are expressed in the same format from the equations (17) and (24), the equation (19) in the cyclic AD converter 1 having a single-stage configuration is used. And Expression (26), and Expression (21) and Expression (28) in the two-stage cyclic AD converter 1 (when N = 12, M = 4) are respectively expressed by Expressions (29) and (30) below. Can be summarized as follows.

(Offset error)
In the cyclic AD converter 1 shown in FIG. 12, the offset error caused by the charge injection flowing into the negative input terminal of the operational amplifier 12 and the clock feedthrough charge is caused by switching when shifting from the sampling phase to the double amplification phase. .

Assuming that the offset error coefficient is e _off , the input / output characteristics expressed in the digital domain are expressed by Equation (31).

  Therefore, the sum of the offset errors after N-bit conversion in the one-stage cyclic AD converter 1 is expressed by Equation (32).

  On the other hand, the total offset error after N-bit conversion in the two-stage cyclic AD converter 1 shown in FIG. 14 is equal to the first M-bit AD conversion performed in the first-stage cyclic AD converter 1a and the two-stage cyclic AD converter 1a. By separately calculating the remaining NM bits of AD conversion performed by the cyclic AD converter 1b of the eye, the following expression (33) is obtained.

Here, e _offA and e _offB represent offset error coefficients of the first-stage and second-stage cyclic AD conversions 1a and 1b, respectively.

(Digital correction)
Since the above-described error is very small, it is considered that the second-order or higher-order error coefficient term can be ignored. Therefore, the total error E _sum generated in the one-stage or two-stage cyclic AD converter 1 due to the capacitance mismatch, the amplifier finite gain, the amplifier incomplete settling, and the offset voltage is expressed by the equation ( 12), Equation (19), Equation (26) and Equation (32), and in the case of two stages, Equation (14), Equation (21), Equation (28) and This is the sum of the errors calculated by equation (33), and is expressed as equation (34).

The digital correction processing is performed by subtracting the total error E _sum represented by the equation (34) from the digital output code X (0) (digital output code including an error) approximated by the equation (11). The corrected digital code D _calibration is expressed as shown in Expression (35), for example, when the AD conversion bit number N is 12.

  As can be seen from the above description, in order to perform high-precision digital correction processing, it is necessary to obtain the error generated in the cyclic AD converter 1 as accurately as possible.

  However, in the conventional technique, in order to accurately obtain the value of the error coefficient that is a parameter describing the error, trial and error are repeatedly performed based on the error coefficient estimated in the design of each component, and the final result is obtained. Therefore, it is not easy to absorb the solid variation, and further, there arises a problem that it is not possible to cope with a time change of an error such as a temperature change. For this reason, there has been a problem that high-precision digital correction cannot be realized.

  The present invention has been made in view of the above problems, and an object of the present invention is to enable an error coefficient based on an error generated in a cyclic AD converter to be automatically measured at a desired timing. It is an object of the present invention to provide a cyclic AD converter that can be determined with high accuracy, a digital corrector for the cyclic AD converter, and a method thereof.

  A cyclic AD converter of the present invention is a cyclic AD converter configured to be capable of automatically measuring an error coefficient of a predetermined error generated therein, and includes a sampling means for sampling an input analog signal, In order to AD-convert the analog signal with the number of cycles according to the resolution, and having a capacitor group consisting of capacitors and an operational amplifier, with respect to a voltage value obtained by amplifying the output at the previous cycle twice, the previous cycle Switched capacitor amplifying means for generating a differential output with a voltage value corresponding to a digital output code that is sometimes AD converted, and sub AD conversion for generating a redundant bit digital output code by AD conversion of the output of the switched capacitor amplifying means Means, a DA conversion means for generating a voltage value corresponding to the AD-converted digital output code, and the digital A DA conversion control means for controlling the DA conversion means to generate a voltage value corresponding to a force code; and an operation phase for AD conversion with the number of cycles according to the resolution in the sampling means and the switched capacitor amplification means. Phase control means for switching control, and the error from a digital output code obtained by AD conversion of the output of the switched capacitor amplification means including an error coefficient of an error caused by one or both of the capacitor group and the operational amplifier In order to make it possible to specify the coefficient, a switch group including a plurality of switches that can be switched to have a circuit configuration in a predetermined measurement mode for measuring the error coefficient is provided.

  Another aspect of the cyclic AD converter according to the present invention is characterized in that the cyclic AD converter of the present invention is connected in two stages in cascade.

  In the cyclic AD converter of the present invention, the switch group is arranged so that a circuit configuration equal to or more than the number of types of the error coefficients can be realized as the circuit configuration of the predetermined measurement mode. .

  In the cyclic AD converter of the present invention, the error is one of a capacitance mismatch error of the capacitor group, a finite gain error of the operational amplifier, a settling error of the operational amplifier, and an offset error of the operational amplifier. The switch group includes two or more errors, and is arranged to be switchable so as to have a circuit configuration in a predetermined measurement mode for measuring an error coefficient of the error.

  In the cyclic AD converter of the present invention, the switch group includes all of a capacitance mismatch error of the capacitor group, a finite gain error of the operational amplifier, a settling error of the operational amplifier, and an offset error of the operational amplifier. It is arranged to be switchable so as to have a circuit configuration of a predetermined measurement mode for measuring the error coefficient.

  In the cyclic AD converter of the present invention, the switch group has a bias that can be measured within the full scale of the cyclic AD converter when the output of the operational amplifier including the error coefficient is AD converted. It arrange | positions so that it may become the circuit structure which arises, It is characterized by the above-mentioned.

  Further, the digital corrector for the cyclic AD converter according to the present invention is configured to instruct the cyclic AD converter according to the present invention to switch the switch group so as to measure the error coefficient, and to measure by the switching instruction. Means for calculating a corresponding error from the digital output code of the voltage value including the error coefficient and subtracting it from the digital output of the analog signal.

  Furthermore, the digital correction method for the cyclic AD converter according to the present invention is a digital correction method for correcting an error of the analog signal in the digital domain with respect to the cyclic AD converter according to the present invention. A step of instructing the switch to switch the switch group so as to measure the error coefficient, and calculating a corresponding error from the digital output code of the voltage value including the error coefficient measured by the switching instruction, and the analog signal Subtracting from the digital output.

  According to the present invention, a signal including an error coefficient of a predetermined error generated inside a cyclic AD converter is sampled as an input of the cyclic AD converter, and an output code obtained by AD conversion of this signal is obtained. Since the error coefficient value can be measured automatically and at a desired timing based on this, it is easy to absorb the variation in solids, and it is possible to cope with a time change of error such as a temperature change. For example, the error of the cyclic AD converter can be automatically measured when the CMOS image sensor or cyclic AD converter is turned on or during the blanking period of the CMOS image sensor. Digital correction of accuracy is possible.

It is a block diagram which shows the structure of the cyclic AD converter of 1st Embodiment by this invention. It is a block diagram which shows the structure of the cyclic AD converter of 2nd Embodiment by this invention. It is a block diagram which shows the circuit structure of the 1st measurement mode in the cyclic AD converter of each embodiment by this invention. It is a block diagram which shows the circuit structure of the 2nd measurement mode in the cyclic AD converter of each embodiment by this invention. It is a block diagram which shows the circuit structure of the 3rd measurement mode in the cyclic AD converter of each embodiment by this invention. It is a block diagram which shows the additional circuit structure of the 3rd measurement mode in the cyclic AD converter of 2nd Embodiment by this invention. It is a block diagram which shows the circuit structure of the 4th measurement mode in the cyclic AD converter of each embodiment by this invention. It is a figure which shows the operation timing of the 1st measurement mode in the cyclic | annular AD converter of each embodiment by this invention. It is a figure which shows the operation timing of the 2nd measurement mode in the cyclic AD converter of each embodiment by this invention. It is a figure which shows the operation timing of the 3rd and 4th measurement mode in the cyclic | annular AD converter of each embodiment by this invention. It is a figure which shows the additional operation timing of the 3rd measurement mode in the cyclic | annular AD converter of 2nd Embodiment by this invention. It is a block diagram which shows the structure of the cyclic | annular AD converter of the 1 step | paragraph structure in a prior art. It is a figure which shows the digital output example of a cyclic AD converter of a redundant bit system. It is a block diagram which shows the structure of the 2-stage cyclic AD converter in a prior art. It is explanatory drawing which shows the operation example at the time of applying a two-stage cyclic AD converter to a CMOS image sensor. It is explanatory drawing of the error which generate | occur | produces in a cyclic | annular AD converter.

  Hereinafter, with reference to the drawings, a cyclic AD converter 1 according to each embodiment of the present invention, a digital corrector for the cyclic AD converter 1, and a method thereof will be described. In addition, the same code | symbol is attached | subjected to the same component in each figure, and the overlapping description is abbreviate | omitted. In particular, in the description of the cyclic AD converter 1 of the second embodiment, corresponding similar components are individually overlapped by adding A, B (or a, b) to the suffix of the reference number. The explanation is omitted. The cyclic AD converter 1 of each embodiment according to the present invention is configured as an AD converter applicable to a CMOS image sensor disclosed in Non-Patent Document 2, for example.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a cyclic AD converter 1 according to the first embodiment of the present invention. Cyclic AD converter 1 shown in FIG. 1 is automatically measured configured to be able to error coefficients of a predetermined error generated therein, a switch S _S for sampling the analog signal V _in to be inputted, the analog signal In order to perform AD conversion for Vin _{in the} number of cycles according to the resolution, as expressed by Equation (4), the AD value is amplified during the previous cycle with respect to the voltage value obtained by amplifying the output in the previous cycle by a factor of two. A plurality of capacitors C _s1 , C _s2 , and C _f that are components of a switched capacitor amplifier circuit that generates an output with a voltage value corresponding to the converted digital output code, and an operational amplifier 12, and an output of the operational amplifier 12 is AD converted. A sub AD converter 13 for generating a digital output code D (i) of redundant bits, and a DAC 11 for generating a voltage value corresponding to the digital output code, A DAC control clock generating unit 14 which controls the DAC 11, switches _S R to control the switching operation _{phase, S 0, S 1, S} 2, S 3 (and _{S S),} a plurality of capacitors _{C s1, C s2, C In} order to make it possible to specify the error coefficient from the digital output code obtained by AD-converting the output of the operational amplifier 12 including the error coefficient of the error caused by one or both of _f and the operational amplifier 12, the error coefficient is measured. And a plurality of switches S _P , S _MS , S _N , S _X , and S _ER that can be switched so as to have a circuit configuration in a predetermined measurement mode.

Cyclic AD converter 1 of the present embodiment shown in FIG. 1 is mainly as compared to cyclic AD converter 1 shown in FIG. 12, by adding a switch _{S X} in the DAC 11, the input line of the analog signal _{V in} If it is different in that it inserts the switch _{S ER} between the DAC 11.

In addition, the cyclic AD converter 1 of the present embodiment includes the operation mode control unit 17 in order to enable the cyclic AD converter 1 of the present embodiment to measure each error coefficient automatically and at a desired timing. Is different in that each operation mode can be switched between “during error coefficient measurement” and “during normal operation”. The operation mode control unit 17 sends a DAC control instruction signal and a phase instruction signal to the DAC control clock generation unit 14 and the phase control clock generation unit 15 in order to instruct switching between the operation modes at the time of error coefficient measurement and normal operation, respectively. , And supply clocks Φ _cal and Φ _err for controlling on / off of the switches S _cal and S _err in the correction control unit 16 for performing digital correction to the correction control unit 16, respectively. It is a functional unit that controls each operation mode during measurement and during normal operation. Therefore, the operation other than the measurement of the error coefficient, that is, the normal operation in the cyclic AD converter 1 of the present embodiment, is controlled in the same manner as the cyclic AD converter 1 shown in FIG.

In addition, the DAC control clock generation unit 14 that controls the DAC 11 is configured to generate the clocks Φ _P , Φ _MS , Φ _N , and Φ _X that control the switches S _P , S _MS , S _N , and S _X. In order to make it possible to switch between the operation modes at the time of error coefficient measurement and normal operation, the phase control clock generator 15 for controlling each operation phase has switches S _ER , S _R , S _S , S ₀ , S _1. , S ₂ , S ₃ is also different in that it is configured to generate each clock Φ _ER , Φ _R , Φ _S , Φ ₀ , Φ ₁ , Φ ₂ , Φ ₃ . Timing examples of these clocks will be described later with reference to FIGS.

Under the control of the operation mode control unit 17, the correction control unit 16 converts the error represented by the equation (34) from the digital output code X (0) (digital output code including an error) approximated by the equation (11). The digital correction processing is performed by subtracting the total E _sum .

More specifically, the correction control unit 16 includes switches S _cal and S _err , a calculation unit 161, an error coefficient register 162, an error calculator 163, an error register 164, and a subtraction unit 165. .

In the operation mode when measuring the error coefficient in the correction control unit 16, as a first step, the switch _Scal is turned off and the switch _Serr is turned on, and the digital output code D corresponding to the number of cycles is held by the computing unit 161. Then, the error coefficient of each error generated in the cyclic AD converter 1 is calculated by the capacity mismatch, the amplifier finite gain, the amplifier incomplete settling, and the offset voltage, and is stored in the error coefficient register 162. The The error coefficient register 162 is configured to be updated every time the switch _Serr is turned on and the error coefficient is calculated by the calculation unit 161. Subsequently, as a second step in the operation mode at the time of measuring the error coefficient, the switch S _cal is turned on and the switch S _err is turned off (similar to the operation mode in the normal operation), and the error calculator 163 is set for the number of cycles. The digital output code D is stored, and the total number E _{sum of} bits corresponding to the resolution of the cyclic AD converter 1 is calculated using the error coefficient value stored in the error coefficient register 162. It is held in the error register 164. The error register 164 is configured to be updated whenever the switch S _cal is turned on and the switch S _err is turned off and the total E _sum is calculated by the error calculator 163.

In the normal operation mode of the correction control unit 16, the switch _Scal is turned on and the switch _Serr is turned off, and the subtraction unit 165 adds the digital output code D for the number of cycles to the error register 164. The stored total error E _sum is subtracted to output the digitally corrected output D ′ (that is, the corrected digital code D _calib expressed by the equation (35)).

  In particular, the correction control unit 16 and the operation mode control unit 17 are configured as “digital correctors”. Such a digital corrector can also function as a computer such as a microcomputer, and a program for causing the computer to realize the functions of the correction control unit 16 and the operation mode control unit 17 is stored in the computer or It is stored in a memory (not shown) provided outside. A program in which processing details for realizing these functions are described is appropriately read from a memory by controlling a central processing unit (CPU) provided in the computer, and the function of the digital corrector is realized in the computer. Can be made. Here, a part or all of the functions of the digital corrector may be realized by hardware using a logic circuit, a register, or the like.

  First, the cyclic AD converter 1, the phase control clock generator 15 and the digital corrector (the correction controller 16 and the operation mode controller 17) of the present embodiment include the above-described capacity mismatch, amplifier finite gain, and amplifier amplifier. It operates so that error coefficients, which are parameters related to errors generated in the cyclic AD converter 1 due to incomplete settling and offset voltage, can be specified in a plurality of predetermined measurement modes, and the error measurement operation And normal operation can be switched.

That is, in the normal operation, the on / off control of the switches S _P , S _MS , and S _N constituting the DAC 11 shown in FIG. 1 is performed based on the digital output D. In the sampling phase and the double amplification phase, switches S _P , S _MS , and so on in the DAC 11 are configured so as to have a circuit configuration (FIGS. 3, 4, 5, and 7 described later) in each error coefficient measurement mode. On / off control of S _N , S _X and switch _SER can be forcibly controlled from the outside (in this example, a DAC control instruction signal and a phase instruction signal by the operation mode control unit 17).

The on / off control of the switch _SER will be described in detail later. In the normal operation, the switch _SER is turned on in the same manner as the configuration shown in FIG. 12, and in the error coefficient measurement mode, the feedback capacitor is used during the sampling phase. turning off the switch _{S ER} as the voltage input to the C _f is connected to the _{V in} terminal, it turns on the switch _{S ER} during subsequent 2-fold amplification phase.

Then, the operation mode control unit 17 causes the correction control unit 16 to change the capacitance mismatch and the finite gain of the amplifier from the circuit configuration (FIGS. 3, 4, 5, and 7 described later) in each error coefficient measurement mode. Each error coefficient related to an error generated in the cyclic AD converter 1 by the incomplete settling of the amplifier and the offset voltage is calculated and held, and an error from the sub AD converter (Sub-ADC) 13 is included. The corrected digital output D ′ is obtained by subtracting the total error E _sum represented by the equation (34) from the digital output D (the digital output code X (0) approximated by the equation (11)). (That is, the corrected digital code D _calib expressed by Expression (35)) is obtained.

(Second Embodiment)
FIG. 2 is a block diagram showing the configuration of the two-stage cyclic AD converter 1 according to the second embodiment of the present invention. A two-stage cyclic AD converter 1 according to the second embodiment shown in FIG. 2 is configured by connecting the one-stage cyclic AD converter 1 shown in FIG. 1 in two stages in cascade. For this reason, in FIG. 2, the components corresponding to each other between the first-stage cyclic AD converter 1a and the second-stage cyclic AD converter 1b have subscripts A and B (or a, b) is attached. The two-stage cyclic AD converter 1 of the present embodiment shown in FIG. 2 is mainly compared with the two-stage cyclic AD converter 1 shown in FIG. 15 in the first and second stages. 1a, each DAC 11 a, the switches _S XA in 11b in _1b, add the _{S XB,} with inserting a switch _{S ERA} between the input line and the DAC 11 a of the analog signal _{V in,} the second-stage cyclic AD converter It is different in that it inserts the switch _{S ERB} between the input line and DAC11b analog signal _{V in} the vessel 1b.

Further, in order to enable each cyclic error AD to be measured automatically and at a desired timing in the cyclic AD converter 1 of the present embodiment, the respective DAC control clock generators 14a and 14b for controlling the DACs 11a and 11b, respectively. 14b respectively controls the clocks Φ _PA , Φ _MSA , Φ _NA , Φ _XA , and Φ _PB that control the corresponding switches S _PA , _SMSA , S _NA , S _XA , and S _PB , S _MSB , S _NB , S _XB , respectively. , Φ _MSB , Φ _NB , Φ _XB are generated, and in order to be able to switch between the operation modes at the time of error coefficient measurement and normal operation, the first stage and the second stage cyclic type AD converter 1a, phase control clock generating section 15a for controlling each operation phase of 1b, 15b, respectively corresponding switch _{S ERA, S RA, S SA} , S 0A _{S 1A, S 2A, S 3A} , and _{S ERB, S RB, S SB} , S 0B, S 1B, S 2B, each clock [Phi _ERA controlling the _{S 3B, Φ RA, Φ SA} , Φ 0A, Φ 1A, Φ _2A , Φ _3A , and Φ _ERB , Φ _RB , Φ _SB , Φ _0B , Φ _1B , Φ _2B , Φ _3B , and the digital output code approximated by equation (11) Each of the correction control units 16a and 16b, which performs digital correction processing by subtracting the total error E _sum represented by the equation (34) from X (0) (digital output code including error), controls the operation mode. In order to enable each error coefficient to be measured automatically and at a desired timing under the control of the units 17a and 17b, the DAC control clock generators 14a and 14b, and the phase control clock, respectively. Raw portion 15a, with respect to 15b, respectively different in the point that is configured to provide a DAC control instruction signal and the phase indication signal. An example of the timing of each clock will be described later with reference to FIGS. Therefore, the operation other than the measurement of the error coefficient, that is, the normal operation in the cyclic AD converter 1 of the present embodiment, is controlled in the same manner as the two-stage cyclic AD converter 1 shown in FIG.

In FIG. 2, although illustrated as individual functional blocks for controlling the correction control units 16a and 16b under the control of the operation mode control units 17a and 17b, the operation mode control units 17a and 17b are shown as one functional block. The correction control units 16a and 16b can measure each error coefficient automatically and at a desired timing with respect to the first-stage and second-stage cyclic AD converters 1a and 1b. The digital correction processing may be performed by subtracting the total error E _sum represented by the equation (34) from the digital output code X (0) (digital output code including an error) approximated by it can.

  In particular, the correction controllers 16a and 16b and the operation mode controllers 17a and 17b are configured as “digital correctors”. Such a digital corrector can also function as a computer such as a microcomputer. A program for causing the computer to realize the functions of the correction control units 16a and 16b and the operation mode control units 17a and 17b is It is stored in a memory (not shown) provided inside or outside the computer. A program in which processing details for realizing these functions are described is appropriately read from a memory by controlling a central processing unit (CPU) provided in the computer, and the function of the digital corrector is realized in the computer. Can be made. Here, a part or all of the functions of the digital corrector may be realized by hardware using a logic circuit, a register, or the like.

  In the two-stage cyclic AD converter 1, the phase control clock generators 15a and 15b and the digital corrector thereof according to the second embodiment, the above-described capacitance mismatch, finite gain of the amplifier, incomplete settling of the amplifier, and Operates so that error coefficients, which are parameters related to errors generated in the two-stage cyclic AD converter 1 by the offset voltage, can be specified in a plurality of predetermined measurement modes, and switch between the error measurement operation and the normal operation Is also configured to work.

That is, in normal operation, DAC 11 a shown in FIG. 2, of each switch constituting the 11b on / off control each of the digital output D _A, have been made based on D _B, the first time measuring operation of the error factor In the sampling phase and the double amplification phase, the switches in the DACs 11a and 11b and the switches S _ERA and S _ERB are arranged so that the circuit configurations (FIGS. 3 to 7 to be described later) in the respective error coefficient measurement modes are obtained. ON / OFF control can be forcibly controlled from the outside (in this example, the DAC control instruction signal and the phase instruction signal by the operation mode control units 17a and 17b).

The on / off control of the switches S _ERA and _SERB will be described in detail later. In the normal operation, the switches S _ERA and _SERB are turned on in the same manner as the configuration shown in FIG. during sampling phase, it turns off the switch _{S ERA,} the _{S ERB} so that the input voltage to the feedback capacitor _{C f} is connected to the _{V in} terminal, turns on the switch _{S ERA,} the _{S ERB} during subsequent 2-fold amplification phase.

Then, the operation control units 17a and 17b allow the correction control units 16a and 16b to change the capacity mismatch, the amplifier finite gain, and the amplifier from the circuit configurations (FIGS. 3 to 7 to be described later) in the respective error coefficient measurement modes. Error coefficients from sub AD converters (Sub-ADC) 13a and 13b are calculated and held with respect to errors generated in the two-stage cyclic AD converter 1 due to incomplete settling and offset voltage. _Is corrected by subtracting the total error E _sum represented by the equation (34) from the digital outputs D _A and D _B (the digital output code X (0) approximated by the equation (11)). It is configured to obtain later digital outputs D _A ′ and D _B ′.

(Error coefficient measurement mode)
Here, a measurement mode in which each error coefficient can be calculated will be described. In this example, in order to specify four types of error coefficients, the one-stage or two-stage cyclic AD converter 1 shown in FIGS. 1 and 2 is configured to operate so as to be switchable in four types of measurement modes. These four types of measurement modes are determined by the operation mode control unit 17 (the operation mode control units 17a and 17b in the second embodiment shown in FIG. 2) in the first embodiment shown in FIG. It is executed in the operation mode at the time of measurement.

The key to the operation principle of each measurement mode is to sample a voltage value including a desired error coefficient by the first sampling phase and the double amplification phase during the measurement operation. In particular, in the present embodiment, since the sampled voltage value is cyclically AD converted, the voltage value is devised to be included in the AD conversion range. Hereinafter, the circuit configuration (FIGS. 2 to 5) and operation in each measurement mode will be described. The bias voltage applied to the input terminal of V _COM shown in FIG. 1 is 0, and the offset voltage V _OS of the operational amplifier 12 is added.

(1) First Measurement Mode As a representative example, in the cyclic AD converter 1 shown in FIG. 1, a circuit of the first sampling phase (Sampling phase) and the double amplification phase (Amplification phase) during the measurement operation in the first measurement mode The configuration is shown in FIG. The operation of each clock in the first measurement mode is shown in FIG. V _RH and V _RL indicate the upper limit and the lower limit of the AD conversion range, respectively. As in the above description, V _RH = V _r , V _RL = 0, and from the charge conservation law at the negative input terminal of the operational amplifier 12, the output voltage V _{out_md1} of the operational amplifier 12 in the first measurement mode is _expressed by Equation (36). It becomes.

The definition of each error coefficient is as described in the above description. e _{m, e ms} but may take both positive and negative values, (the first term of equation (36)) for 0.5V _r is applied as a bias value, the output voltage _{V Out_md1} becomes longitudinal 0.5V _r, It is definitely included in the AD conversion range. The output voltage _{Vout_md1} sampled in this way is used as an input to the cyclic AD converter 1, and cyclic AD conversion is performed as in the normal operation. That is, in the first sampling phase (Sampling phase) and double amplification phase (Amplification phase) at the time of error measurement, each clock in the DAC 11 is actively controlled to realize the circuit configuration shown in FIG. When the voltage V _{out_md1} is _cyclically AD-converted, every time N rounds are performed, the DAC 11 turns off “S _P and S _X if the digital output code D (i) is the ternary {0}”. , S _N , S _MS are turned on ”, and if the digital output code D (i) is {1/2} of the three values,“ S _P , S _N are turned on, S _MS , S _X are turned off ”, If the digital output code D (i) is the ternary {1}, the DA conversion value is output with “S _P and _SMS turned on and S _N and S _X turned off”. In the error coefficient measurement mode, unlike the normal operation mode, redundant N bits are converted by N cycles, and AD conversion with a resolution of N + 1 bits can be performed.

When the output voltage _{Vout_md1} represented by the equation (36) is AD-converted, an error is included in the obtained digital output code D (i). From the above description, the total error E _sum included in the digital output code D (i) is expressed as shown in Expression (34), but Expression (12), Expression (19), Expression (26), and Expression ( From 32), E _{m — t} , E _{fg — t} , E _{st — t} , and E off — _t are as shown in Expression (37).

The coefficients a ₁ , a ₂ , and b _{1 on} the right side of the equation (37) are substituted with the digital output code D (i) into the equations (12), (19), and (26) for each operation phase. And ask. Further, c ₁ is a constant value for each operation phase. Therefore, the digital output code X _{out_md1} including a plurality of errors obtained by AD converting V _{out_md1} represented by Expression (36) is expressed by Expression (38).

In the equation (38), since the digital output code X _{out_md1} is _close to 0.5, assuming that the error is very small, the calculation of the total error E _sum is performed by the equations (12), (19), and ( 26), instead of X (i) = 0.5, D (i) = 0.5, and D _s (i) = 1 in Equation (10), Equation (18) and Equation (25), For example, in a redundant 14-bit conversion (N = 14) in one measurement mode, Expression (39) is obtained.

  In the case of the two-stage cyclic AD converter 1 shown in FIG. 2, the first measurement mode is applied to the first-stage and second-stage cyclic AD converters 1a and 1b, respectively.

(2) Second Measurement Mode As a representative example, in the cyclic AD converter 1 shown in FIG. 1, a circuit of the first sampling phase and the amplification phase (Amplification phase) during the measurement operation in the second measurement mode The configuration is shown in FIG. The operation of each clock in the second measurement mode is shown in FIG. V _RH and V _RL indicate the upper limit and the lower limit of the AD conversion range, respectively. As in the above description, V _RH = V _r , V _RL = 0, and from the charge conservation law at the negative input terminal of the operational amplifier 12, the output voltage V _{out_md2} of the operational amplifier 12 in the second measurement mode is _expressed by Equation (40). It becomes.

Similarly to the first measurement mode, 0.5 _Vr is added as a bias value in the second measurement mode (the first term in the equation (40)), and therefore it is definitely included in the AD conversion range. The output voltage _{Vout_md2} sampled in this way is used as an input to the cyclic AD converter 1, and cyclic AD conversion is performed as in the normal operation. When the voltage represented by Expression (40) is AD-converted, the error included in the obtained digital output code D (i) is represented in the form of Expression (37), and therefore V represented by Expression (40). _A digital output code X _{out_md2} including a plurality of errors obtained by _performing AD conversion on _{out_md2} is expressed by Expression (41).

In the equation (41), since the digital output code X _{out_md2} is _close to 0.5, assuming that the error is very small, the calculation of the total error E _sum is performed by the equations (12), (19), and ( 26) in place of X (i) = 0.5, D (i) = 0.5, and D _s (i) = 1 in Equation (10), Equation (18) and Equation (25), For example, in redundant 14-bit conversion (N = 14) in the two measurement mode, Expression (42) is obtained.

  In the case of the two-stage cyclic AD converter 1 shown in FIG. 2, the second measurement mode is applied to the first-stage and second-stage cyclic AD converters 1a and 1b, respectively.

(3) Third Measurement Mode As a representative example, in the cyclic AD converter 1 shown in FIG. 1, circuits for the first sampling phase and the amplification phase in the measurement operation in the third measurement mode The configuration is shown in FIG. The operation of each clock in the first measurement mode is shown in FIG. V _RH and V _RL indicate the upper limit and the lower limit of the AD conversion range, respectively. As in the above description, V _RH = V _r , V _RL = 0, and from the charge conservation law at the negative input terminal of the operational amplifier 12, the output voltage V _{out_md3} of the operational amplifier 12 in the third measurement mode is _expressed by Equation (43). It becomes.

Similarly to the first measurement mode, since 0.5 _Vr is added as a bias value in the third measurement mode (the first term of the equation (43)), it is surely included in the AD conversion range. The output voltage _{Vout_md3} sampled in this way is used as an input to the cyclic AD converter 1, and cyclic AD conversion is performed as in the normal operation. When the voltage represented by Expression (43) is AD-converted, the error included in the obtained digital output code D (i) is represented by the form of Expression (37), and therefore the output represented by Expression (43). A digital output code X _{out_md3} including a plurality of errors obtained by AD conversion of the voltage V _{out_md3} is _expressed by Expression (44).

In the equation (44), since the digital output code X _{out_md3} is _close to 0.5, assuming that the error is very small, the calculation of the total error E _sum is performed by the equations (12), (19), and ( 26) in place of X (i) = 0.5, D (i) = 0.5, and D _s (i) = 1 in Equation (10), Equation (18) and Equation (25), For example, in redundant 14-bit conversion (N = 14) in the two measurement mode, Expression (45) is obtained.

In the case of the two-stage cyclic AD converter 1 shown in FIG. 2, the third measurement mode is applied to the first-stage and second-stage cyclic AD converters 1a and 1b, respectively. However, in the case of the two-stage cyclic AD converter 1, in the third measurement mode, the first-stage cyclic AD conversion when the first-stage and second-stage cyclic AD converters 1a and 1b are connected. Since the _settling error coefficient _estAB of the device 1a must be considered separately, this point will be described with reference to FIGS.

In the third measurement mode 3 in the case of the two-stage cyclic AD converter 1, the first-stage cyclic AD converter when the first-stage and second-stage cyclic AD converters 1a and 1b are connected. The _settling error coefficient _estAB of 1a is considered separately. That is, in order to sample a signal including a _settling error _estAB when the first-stage cyclic AD converter 1a is connected to the second-stage cyclic AD converter 1b, the first-stage cyclic AD converter 1a is used. When the AD converter 1a operates in the double amplification phase, the second-stage cyclic AD converter 1b that operates in the sampling phase is connected. FIG. 6 shows the circuit configuration of the first sampling phase and the amplification phase at this time. The operation of each clock in the third measurement mode at this time is shown in FIG. The output voltage _{Vout_md3b} thus sampled is cyclically AD-converted by a normal operation as an input to the first-stage cyclic AD converter 1a. _Assuming that the digital output code D _A (i) at this time is X _{out_md3b} , the _settling error e _stA in the equation obtained by applying the equation (44) to the first-stage cyclic AD converter 1a may be replaced with e _stAB . Equation (46) is obtained.

  When it is assumed that the error is very small, when redundant 14-bit conversion (N = 14) is executed in this operation mode, Expression (47) is obtained.

  Expressions (46) and (47) are applied only to the first-stage cyclic AD converter 1a in the two-stage cyclic AD converter 1.

(4) Fourth Measurement Mode In the cyclic AD converter 1 shown in FIG. 1 as a representative, a circuit of the first sampling phase (Sampling phase) and double amplification phase (Amplification phase) during the measurement operation in the fourth measurement mode The configuration is shown in FIG. The operation of each clock in the fourth measurement mode is shown in FIG. V _RH and V _RL indicate the upper limit and the lower limit of the AD conversion range, respectively. As in the above description, V _RH = V _r , V _RL = 0, and from the charge conservation law at the negative input terminal of the operational amplifier 12, the output voltage V _{out_md4} of the operational amplifier 12 in the fourth measurement mode is _expressed by Equation (48). It becomes.

Here, the error coefficient e _off of the offset error is caused by an error due to the charge injection due to switching and the clock feedthrough charge flowing into the negative input terminal of the operational amplifier 12, so that e _off > 0, so that the output voltage V _{out_md4} is definitely included in the AD conversion range. The output voltage _{Vout_md4} sampled in this way is used as an input to the cyclic AD converter 1, and cyclic AD conversion is performed as in the normal operation. When the voltage represented by Expression (48) is AD-converted, the error included in the obtained digital output code D is represented in the form of Expression (37), and thus the output voltage V _{out_md4} represented by Expression (48). A digital output code X _{out_md4} including a plurality of errors, obtained by AD conversion of, is expressed by Equation (49).

In Equation (49), since the digital output code X _{out_md4} is _close to 0, assuming that the error is very small, the total error E _sum is calculated using Equation (12), Equation (19), and Equation (26). For example, in Expression (10), Expression (18), and Expression (25), X (i) = 0, D (i) = 0, and D _s (i) = 0 are simplified. In the 14-bit conversion (N = 14), Expression (50) including only the error coefficient e _off of the offset error is obtained.

  In the case of the two-stage cyclic AD converter 1 shown in FIG. 2, the fourth measurement mode is applied to the first-stage and second-stage cyclic AD converters 1a and 1b, respectively.

(Error coefficient calculation)
In the case of the cyclic AD converter 1 shown in FIG. 1, for example, redundant 14-bit conversion is performed in each of the operation modes described above by combining the equations (38), (41), (44), and (49). Is expressed in the form of a determinant below.

  Here, the parameters in the matrix in Expression (51) are given by Expression (52) and Expression (53).

The coefficients a ₁ , a ₂ , and b ₁ represented by the equation (53) are obtained by substituting the digital output code for each operation mode. From these equations, the error coefficient can be calculated as in Equation (54).

  By executing the function of the calculation unit 161 in the correction control unit 16 by a “digital corrector” configured as a computer so as to obtain the respective error coefficients by solving the simultaneous equations given by the equation (54), high-precision digital correction is performed. However, when it is desired to reduce the processing load, the equation (55) obtained by combining the equations (39), (42), (45), and (50) is used. The function of the calculation unit 161 can be configured. If it is Formula (55), the function of the calculating part 161 in the correction | amendment control part 16 can be comprised with a comparatively simple logic circuit.

In the case of the two-stage cyclic AD converter 1 shown in FIG. 2, each measurement mode is applied to the first-stage and second-stage cyclic AD converters 1a and 1b, whereby the above-described one-stage cyclic AD is obtained. Similarly to the case of the converter 1, the first stage error coefficients e _mA , e _msA , e _fgA + _{est A} , e _offA and the second stage error coefficients e _mB , e _msB , e _fgB + _{est B} , e _offB Can be calculated. Further, the error coefficient e _stAB can be obtained as shown in Expression (56) by substituting the calculated error coefficients e _mA , e _msA , and e _offA into Expression (46).

  Further, by combining the simplified expressions (39), (42), (45), (47), and (50), the error coefficient of the first-stage cyclic AD converter 1a is as follows. As in equation (57), the error coefficient of the second-stage cyclic AD converter 1b can be calculated as in equation (58). In the equations (57) and (58), the subscripts “ADC_1ST” and “ADC_2ND” of the reference symbol X are used in the first-stage cyclic AD converter 1a and the second-stage cyclic AD converter 1b. A digital output code X including each error coefficient is shown.

  8 to 11 described above, the times of the double amplification phase and the feedback phase can be the same as the times of the double amplification phase and the feedback phase in the normal operation. The “digital corrector” that constitutes the correction control unit 16 and the operation mode control unit 17 (or the correction control units 16a and 16b and the operation mode control units 17a and 17b) includes each measurement mode for specifying each error coefficient. In the cyclic AD converter 1 which is a measurement target by substituting the digital output code obtained by the above equation into the equations (51) to (56) or the simplified equations (57) and (58) It is possible to calculate an error coefficient due to the generated error with high accuracy. Each error coefficient calculated in this way is stored in the error coefficient register 162 in the example shown in FIG.

Then, in the case of the one-stage cyclic AD converter 1, the “digital corrector” uses the error coefficient stored in the error coefficient register 162 by the error calculator 163. Using the coefficients, the equations (12), (29), (32) and (34) are used. In the case of the two-stage cyclic AD converter 1, the equations (14), (30), By calculating the total error E _sum based on each error in Equation (33) and Equation (34) and holding it in the error register 164, the error held in the error register 164 by the subtractor 165 is used. By applying the digital correction to the calculation formula of the digital correction expressed by the equation (35) and performing the digital correction, a highly accurate digital correction process can be performed.

  The present invention has been described above with reference to specific embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical concept thereof. For example, in the example of the above-described embodiment, the correction control unit 16 and the operation mode control unit 17 (or the correction control units 16a and 16b and the operation) are used as “digital correctors” for the one-stage or two-stage cyclic AD converter 1. The mode control units 17a and 17b) have been described as individual functional blocks. However, the mode control units 17a and 17b are configured as microcomputers, and for example, a part of the functions of a central processing unit (CPU) or ASIC (integrated circuit), or a combination of these functions. It can be configured in one piece of hardware.

  Further, in the example of the embodiment described above, it is possible to measure all errors generated in the one-stage or two-stage cyclic AD converter 1 due to the capacitance mismatch, the amplifier finite gain, the amplifier incomplete settling, and the offset voltage. Although the preferred example has been described, the technique according to the present invention described above can be used to enable digital correction for at least one of these errors. For example, when only the capacity mismatch error is measured using the technique according to the present invention, the error coefficient value other than the capacity mismatch error among the error coefficients represented by the equation (34) may be treated as zero. The error coefficient can be selectively measured and corrected.

  Moreover, although the example which applies the cyclic AD converter 1 which concerns on this invention to a CMOS image sensor was demonstrated as a suitable example in the example mentioned above, it is not limited to this.

  According to the present invention, a signal including the error coefficient is sampled as an input of the cyclic AD converter, and the error coefficient value is automatically determined based on an output code obtained by performing AD conversion on the signal. Since measurement is possible at timing, it is useful for applications using cyclic AD conversion.

DESCRIPTION OF SYMBOLS 1 Cyclic AD converter 1a First-stage cyclic AD converter 1b in two-stage cyclic AD converter 1b Second-stage cyclic AD converter 11 in two-stage cyclic AD converter 11, 11a, 11b Digital / analog Converter (DAC)
12, 12a, 12b Operational amplifier 13, 13a, 13b Sub AD converter (Sub-ADC)
14, 14a, 14b DAC control clock generation unit 15, 15a, 15b Phase control clock generation unit 16, 16a, 16b Correction control unit 17, 17a, 17b Operation mode control unit 161 Calculation unit 162 Error coefficient register 163 Error calculator 164 error register 165 subtracter _{C s, C s1, C s2} , C f capacitor _{C sA, C s1A, C s2A} , C fA capacitor _{C sB, C s1B, C s2B} , C fB capacitor _{S P,} S N, S _MS , _S X switch S _PA in _{DAC, S} NA, _{S MSA,} switch S _PB in _{S XA DAC, S NB, S} MSB, S XB switches S _R in the _{DAC, S S, S 0,} S 1, S _{2, S 3} switches _{S RA, S SA, S 0A} , S 1A, S 2A, S 3A switches S _{RB, S SB, S 0B,} S 1B, S 2B, S 3B switch S _err, switches in _{S cal} correction control unit

Claims (8)

A cyclic AD converter configured to automatically measure an error coefficient of a predetermined error generated internally,
Sampling means for sampling an input analog signal;
A capacitor group including a plurality of capacitors and an operational amplifier, and for analog-to-digital conversion of the analog signal with the number of cycles according to the resolution, a voltage value obtained by amplifying the output at the previous cycle by a factor of 2 Switched capacitor amplifying means for generating an output that is a difference in voltage value according to a digital output code that is AD-converted at the time of circulation;
Sub AD conversion means for generating a redundant bit digital output code by AD converting the output of the switched capacitor amplification means;
DA conversion means for generating a voltage value corresponding to the AD-converted digital output code;
DA conversion control means for controlling the DA conversion means to generate a voltage value corresponding to the digital output code;
Phase control means for switching and controlling an operation phase for AD conversion with the number of cycles according to the resolution in the sampling means and the switched capacitor amplification means;
In order to make it possible to specify the error coefficient from a digital output code obtained by AD-converting the output of the switched capacitor amplification means including an error coefficient of an error caused by one or both of the capacitor group and the operational amplifier A switch group composed of a plurality of switches that can be switched so as to have a circuit configuration in a predetermined measurement mode for measuring the error coefficient;
A cyclic AD converter comprising:   A cyclic AD converter according to claim 1, wherein the cyclic AD converter according to claim 1 is connected in two stages in cascade.   3. The cyclic AD according to claim 1, wherein the switch group is arranged so that a circuit configuration equal to or more than the number of types of the error coefficients can be realized as the circuit configuration of the predetermined measurement mode. converter.   The error includes one or more errors of a capacitance mismatch error of the capacitor group, a finite gain error of the operational amplifier, a settling error of the operational amplifier, and an offset error of the operational amplifier, and the switch group includes: 4. The cyclic AD according to claim 1, wherein the cyclic AD is arranged to be switchable so as to have a circuit configuration of a predetermined measurement mode for measuring an error coefficient of the error. 5. converter.   The switch group is a predetermined measurement for measuring all error coefficients of a capacitance mismatch error of the capacitor group, a finite gain error of the operational amplifier, a settling error of the operational amplifier, and an offset error of the operational amplifier. The cyclic AD converter according to any one of claims 1 to 3, wherein the cyclic AD converter is arranged so as to be switchable so as to have a mode circuit configuration.   The switch group is arranged to have a circuit configuration in which a bias that can be measured within the full scale of the cyclic AD converter is generated when the output of the operational amplifier including the error coefficient is AD converted. The cyclic AD converter according to claim 1, wherein the cyclic AD converter is characterized in that Means for instructing the cyclic AD converter according to any one of claims 1 to 6 to switch the switch group so as to measure the error coefficient;
Means for calculating a corresponding error from the digital output code of the voltage value including the error coefficient measured by the switching instruction and subtracting from the digital output of the analog signal;
A digital corrector for a cyclic AD converter, comprising: A digital correction method for correcting an error of the analog signal in a digital domain with respect to the cyclic AD converter according to any one of claims 1 to 6,
Instructing the cyclic AD converter to switch the switch group to measure the error coefficient;
Calculating a corresponding error from the digital output code of the voltage value including the error coefficient measured by the switching instruction, and subtracting from the digital output of the analog signal;
A digital correction method for a cyclic AD converter, comprising: