JP2017005039A - Thin film transistor, thin film transistor substrate, liquid crystal display and method for manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a thin film transistor in which at least reduction of contact resistance between a source electrode and a drain electrode and a channel area is contrived.SOLUTION: On a gate insulator 3 of a pixel TFT30, oxide semiconductor layers 4a and 4b are selectively formed at a part of an area overlapping a gate electrode 2 in plan view, and a source electrode 16 and a drain electrode 17 are provided on the oxide semiconductor layers 4a and 4b. Consequently, since a gate field is applied from the gate electrode 2 to the oxide semiconductor layers 4a and 4b in a lower layer of the source electrode 16 and the drain electrode 17, a current path I5 is formed in an area where the source electrode 16 and the drain electrode 17 overlap the oxide semiconductor layers 4a and 4b in plan view. Namely, the pixel TFT 30 has a channel area consisting of: an area forming the current path I5 of the oxide semiconductor layers 4a and 4b; and a channel main area RC5 of an oxide semiconductor layer 5.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a thin film transistor, a thin film transistor substrate, and a method of manufacturing the thin film transistor that constitute a liquid crystal display device.

  Liquid crystal display (LCD), one of the conventional thin panels, is widely used for monitors of personal computers and personal digital assistants, taking advantage of low power consumption and small size and light weight. ing. In recent years, it has been widely used as a TV application.

  Generally, when the LCD display modes are roughly classified, there are horizontal electric field methods represented by the Twisted Nematic (TN) method, the In-Plane Switching method, and the Fringe Field Switching (FFS) method. A horizontal electric field type liquid crystal display device is characterized in that a wide viewing angle and a high contrast can be obtained.

  In-Plane Switching type liquid crystal display device is a display type that performs display by applying a horizontal electric field to liquid crystal sandwiched between opposing substrates, but the pixel electrode that applies the horizontal electric field and the common electrode are the same layer. Therefore, the liquid crystal molecules located directly above the pixel electrode cannot be driven sufficiently, and the transmittance is low.

  On the other hand, in the FFS method, since the common electrode and the pixel electrode are disposed with the interlayer insulating film interposed therebetween, an oblique electric field (fringe electric field) is generated, and the liquid crystal molecules directly above the pixel electrode are also in the lateral direction. This electric field can be applied, and sufficient driving can be achieved. Therefore, it is possible to obtain a higher transmittance than the In-Plane Switching method with a wide viewing angle. Further, the FFS mode liquid crystal display device has a fringe electric field generated between a liquid crystal control slit electrode provided in an upper layer and a pixel electrode provided in a lower layer of the liquid crystal control slit electrode via an interlayer insulating film. To drive the liquid crystal. In this configuration, the pixel electrode and the liquid crystal control slit electrode are formed of an oxide-based transparent conductive film such as ITO (Indium Tin Oxide) containing indium oxide and tin oxide and InZnO containing indium oxide and zinc oxide. Thus, the pixel aperture ratio can be prevented from being lowered. In addition, since the storage capacitor is formed by the pixel electrode and the liquid crystal control slit electrode, unlike the TN mode liquid crystal display device, it is not always necessary to separately form the storage capacitor pattern in the pixel. For this reason, it is possible to realize a high pixel aperture ratio.

  Conventionally, amorphous silicon (a-Si) has been used as a semiconductor channel layer in a switching device of a TFT TFT substrate (thin film transistor substrate) for LCD. The main reason is that it is amorphous, so that a film with good uniformity of characteristics can be formed even on a large-area substrate, and it can also be manufactured on an inexpensive glass substrate with poor heat resistance because it can be formed at a relatively low temperature. Therefore, the compatibility with a general display for a liquid crystal display device for TV is good.

  However, in recent years, TFTs (thin film transistors) used for channel layers using oxide semiconductors as constituent materials have been actively developed. Oxide semiconductors can be stably obtained as amorphous films with good uniformity by optimizing the composition, and have higher mobility than conventional a-Si, realizing compact and high-performance TFTs. There is an advantage that you can. Therefore, by applying such an oxide semiconductor film to a pixel TFT, there is an advantage that a TFT substrate having a high pixel aperture ratio can be realized.

  Further, since the mobility of a-Si is low, a drive circuit for applying a drive voltage to the pixel TFT requires a relatively large circuit area, and thus it has to be attached to the TFT substrate. However, if an oxide semiconductor TFT with high mobility is used for a driver circuit, it can be realized with a relatively small circuit area, and thus a driver circuit can be manufactured over the same substrate as the pixel TFT. Accordingly, it is not necessary to attach a driving circuit, so that a liquid crystal display device can be manufactured at a low cost and the frame area of the LCD required for the driving circuit can be narrowed.

  In a-Si, a back channel etching (BCE) structure in which a channel region of a semiconductor layer is exposed to wet etching when forming a source electrode and a drain electrode is mainstream. However, when an oxide semiconductor is applied to the TFT having the BCE structure, the oxide semiconductor is also etched during wet etching of the source electrode and the drain electrode, and a highly reliable channel region cannot be formed.

  In order to solve this problem, for example, in Patent Document 1, the technology uses a channel semiconductor layer made of an oxide semiconductor that is resistant to wet etching of the source electrode and the drain electrode. By using such a channel semiconductor layer, the channel region can be formed without etching the channel semiconductor layer when forming the source electrode and the drain electrode.

  In the technique disclosed in Patent Document 2, a channel semiconductor layer composed of an oxide semiconductor layer is realized by forming a TFT having a coplanar structure by forming an oxide semiconductor layer after forming a source electrode and a drain electrode. Therefore, the channel can be formed without being exposed to the wet etching when forming the source electrode and the drain electrode.

  Further, the technique disclosed in Patent Document 3 uses an etch stopper structure (ES structure) in which a protective semiconductor layer is formed on a channel region of a channel semiconductor layer made of an oxide semiconductor. In this structure, since the channel semiconductor layer is not exposed during the wet etching process of the source electrode and the drain electrode after the formation of the protective film semiconductor layer, a channel region using an oxide semiconductor as a constituent material can be formed. Therefore, a TFT using an oxide semiconductor for a channel can be manufactured.

JP 2010-118407 A JP 2010-93238 A JP 2010-212672 A

  In the technique disclosed in Patent Document 1 (adopting a BCE structure), a BCE structure is formed by using a channel semiconductor layer made of an oxide semiconductor that is resistant during wet etching of a source electrode and a drain electrode. However, an oxide semiconductor serving as a constituent material of the channel semiconductor layer is exposed to a wet etching process when the source electrode and the drain electrode are formed. At this time, there is a problem that damage is introduced into the oxide semiconductor of the channel semiconductor layer and causes deterioration of characteristics.

  In the coplanar structure used in the technique of Patent Document 2, the channel semiconductor layer made of an oxide semiconductor is not exposed to wet etching when forming the source electrode and the drain electrode, but the gate electric field is shielded by the source electrode and the drain electrode. However, it is not applied to the channel semiconductor layer formed on the source and drain electrodes. Therefore, there is a problem that the contact resistance between the source and drain electrodes and the channel semiconductor layer is high.

  In the coplanar structure used in the technique of Patent Document 2, when a two-layer structure of aluminum (Al) and molybdenum (Mo) is used for the source electrode and the drain electrode, an upper layer of Al having a high etching rate is formed, and Mo having a low etching rate is formed. Is preferably the lower layer. In this case, the region where the channel semiconductor layer is in contact with the source electrode and the drain electrode is dominated by Al having a high contact resistance, and the contact resistance is increased.

  In the technique (ES structure) disclosed in Patent Document 3, an overlap region between the protective semiconductor layer and the source and drain electrodes is required. There is a problem that the channel length is increased and the TFT size is increased by the overlap region. Further, parasitic capacitance between the source electrode, the drain electrode and the gate electrode in the overlap region is generated, which causes a problem of display unevenness.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a thin film transistor in which the contact resistance between the source and drain electrodes and the channel region is reduced.

  According to a first aspect of the present invention, a thin film transistor includes a gate electrode formed on a substrate, a gate insulating film formed to cover the gate electrode, and a region facing the gate electrode through the gate insulating film A first semiconductor layer formed on the gate insulating film, and a source electrode and a drain electrode selectively formed on the gate insulating film, and a region on the gate insulating film between the source electrode and the drain electrode is formed on the gate insulating film. A region facing the gate electrode, at least one of the source electrode and the drain electrode is further formed on the first semiconductor layer, and is formed in a region between the source electrode and the drain electrode on the gate insulating film. The semiconductor device further includes at least a second semiconductor layer formed, and the second semiconductor layer includes the source electrode, the drain electrode, and the first semiconductor. A main channel region formed in a region between the source electrode and the drain electrode on the gate insulating film in the second semiconductor layer in contact with each, and the first semiconductor layer under the at least one electrode Defines a channel region.

  In the thin film transistor according to the first aspect of the present invention, since a gate electric field is applied from the gate electrode to the first semiconductor layer below at least one of the source electrode and the drain electrode, at least one electrode and the first semiconductor Since a current path flowing through the channel region can be formed also in a region where the layers overlap with each other in plan view, contact resistance between at least one of the electrodes and the channel region can be reduced.

It is a top view which illustrates typically the whole structure of a TFT substrate. 2 is a plan view showing a planar structure of a pixel TFT according to Embodiment 1. FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of a pixel TFT according to Embodiment 1. FIG. It is explanatory drawing which shows schematic structure of the liquid crystal display device provided with the TFT substrate shown in FIG. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing step of the pixel TFT of the first embodiment. FIG. 6 is a cross-sectional view illustrating a cross-sectional structure of a modification of the pixel TFT according to the first embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the second embodiment. 6 is a cross-sectional view illustrating a cross-sectional structure of a pixel TFT according to Embodiment 3. FIG. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the third embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the third embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the third embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the pixel TFT of the third embodiment. FIG. 6 is a cross-sectional view illustrating a planar structure of a pixel TFT according to a fourth embodiment. 6 is a plan view showing a cross-sectional structure of a pixel TFT according to Embodiment 4. FIG. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the pixel TFT of the fourth embodiment. It is a graph which shows a reflectance spectral characteristic when an oxide semiconductor layer is formed into a film on Mo. FIG. 10 is a cross-sectional view illustrating a planar structure of a pixel TFT according to a fifth embodiment. FIG. 10 is a plan view showing a cross-sectional structure of a pixel TFT according to a fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the pixel TFT according to the fifth embodiment.

  A thin film transistor (TFT) provided in a semiconductor device according to the first to fifth embodiments described below is used as a switching device. The TFT is used in a flat display device (flat panel display) such as a liquid crystal display device (LCD), and can be applied to a pixel and a drive circuit.

<Embodiment 1>
FIG. 1 is a plan view schematically illustrating the entire configuration of the TFT substrate 100. As shown in the figure, a TFT substrate 100 includes a display area 24 in which pixels (areas) including pixel TFTs 30 are arranged in a matrix, and a frame provided around the display area 24 so as to surround the display area 24. The area 23 is roughly divided.

  In the display region 24, a plurality of gate lines 13 and a plurality of source lines 12 are arranged so as to cross each other at right angles, and the pixel TFT 30 and the pixel electrode corresponding to each intersection of the source lines 12 and the gate lines 13. Is provided.

  A scanning signal driving circuit 25 for applying a driving voltage to the gate wiring 13 and a display signal driving circuit 26 for supplying a driving voltage to the source wiring 12 are arranged in the frame region 23. When a current selectively flows through one gate line 13 by the scanning signal driving circuit 25 and a current selectively flows through one source line 12 by the display signal driving circuit 26, the current exists at the intersection of these lines. The pixel TFT 30 of the pixel is turned on, and charges are accumulated in the pixel electrode connected to the pixel TFT 30.

  When the pixel TFT 30 having a channel layer made of an oxide semiconductor is used, the oxide semiconductor has high mobility and can be downsized. Therefore, the driving used for the channel layer made of the same oxide semiconductor as the pixel TFT 30 is used. By making the scanning signal driving circuit 25 and the display signal driving circuit 26 using the TFT 20 for use, the scanning signal driving circuit 25 and the display signal driving circuit 26 can be downsized. As a result, the scanning signal drive circuit 25 and the display signal drive circuit 26 can be housed in the frame region 23 of the TFT substrate 100, so that the drive circuits 25 and 26 described above can be reduced in cost and the frame region 23 can be narrowed. be able to.

  The scanning signal drive circuit 25 includes a plurality of drive voltage generation circuits SC having drive TFTs 20 (T1, T2, T3) as shown in a region of interest A25 in FIG. Similarly, the display signal drive circuit 26 includes a plurality of drive voltage generation circuits SC. Here, it is assumed that the current flowing through the driving TFT 20 flows from the drain electrode to the source electrode. The NMOS transistors T1 to T3 are each formed in a TFT configuration.

  The drive voltage generation circuit SC includes an NMOS transistor T1 to which the clock signal CLK is applied to the drain, an NMOS transistor T2 to which the ground potential VSS is applied to the source, a drain connected to the source of the NMOS transistor T1, and a power supply potential VDD to the drain. And an NMOS transistor T3 having a source connected to the gate of the NMOS transistor T1. The source of the NMOS transistor T3 is connected to the connection node N1 between the NMOS transistors T1 and T2 via the capacitor C1, and the connection node N1 between the NMOS transistors T1 and T2 serves as an output node of the drive voltage generation circuit SC. The driving voltage is applied to the corresponding gate wiring 13 and source wiring 12.

  When the NMOS transistor T3 is turned on by a signal applied to the gate of the NMOS transistor T3, the NMOS transistor T1 is turned on and the clock signal CLK is output from the connection node N1, and the NMOS transistor T1 is output by the signal applied to the gate of the NMOS transistor T2. When the transistor T2 is turned on, the potential of the connection node N1 is fixed to the ground potential VSS.

  In the present invention, the TFTs in Embodiment Modes 1 to 5 are used for at least one of TFTs for pixels and driving circuits. Hereinafter, the pixel TFT 30 when used for a pixel will be described as a representative.

  2 is a plan view showing the planar structure of the pixel TFT 30 according to the first embodiment of the present invention, and FIG. 3 is a sectional view showing the AA sectional structure of FIG. 2 and 3 also show the XYZ orthogonal coordinate system. Hereinafter, the pixel TFT 30 will be described with reference to FIGS. 2 and 3.

  As shown in FIG. 3, the pixel TFT 30 is formed on a transparent insulating substrate 1 (substrate) such as glass, and the gate electrode 2 made of metal is selectively formed on the transparent insulating substrate 1. Is formed. A gate wiring 13 (see FIG. 1) is also formed on the transparent insulating substrate 1, and the gate electrode 2 is electrically connected to the gate wiring 13 (see FIG. 1).

  A gate insulating film 3 is formed on the entire surface of the transparent insulating substrate 1 so as to cover the gate electrode 2. On the gate insulating film 3, an oxide semiconductor layer 4 (first semiconductor layer) is selectively formed in a part of a region overlapping with the gate electrode 2 in plan view (viewed from above). Here, the oxide semiconductor layer 4 may have a region protruding from the gate electrode 2 in plan view. In the structure shown in FIG. 3, the oxide semiconductor layer 4 is composed of two oxide semiconductor layers 4a and 4b (one and the other partial semiconductor layers) that are separated from each other. In other words, the oxide semiconductor layer 4a is provided on the left side (−X direction side) with the center of the gate electrode 2 as a reference and the oxide semiconductor layer on the right side (+ X direction side) in a mode facing the gate electrode 2 in plan view. Layer 4b is provided.

  A source electrode 16 and a drain electrode 17 are selectively formed so as to cover a partial region of the gate insulating film 3. The source electrode 16 is electrically connected to the source wiring 12 (see FIG. 1), and the drain electrode 17 is electrically connected to the pixel electrode 15 (see FIG. 1). Note that the source electrode 16 and the drain electrode 17 are formed in a laminated structure of a molybdenum layer 21 and an aluminum layer 22, respectively. A region on the gate insulating film 3 between the source electrode 16 and the drain electrode 17 is a region facing the gate electrode 2.

  Here, the source electrode 16 is also formed on the oxide semiconductor layer 4a, and the drain electrode 17 is also formed on the oxide semiconductor layer 4b. The oxide semiconductor layers 4 a and 4 b may have the same shape as the source electrode 16 and the drain electrode 17 in a plan view, or may have a region protruding from the source electrode 16 and the drain electrode 17.

  Then, the oxide semiconductor layer 5 (second semiconductor layer) is formed to extend from the gate insulating film 3 between the source electrode 16 and the drain electrode 17 to the source electrode 16 and the drain electrode 17, respectively. The drain electrodes 17 are connected to each other through the oxide semiconductor layer 5.

  When there is a region where the oxide semiconductor layer 4 protrudes from the source electrode 16 and the drain electrode 17 in plan view, the oxide semiconductor layer 5 is also formed on the protruded region. Here, the oxide semiconductor layer 5 is in contact with the side surfaces and the top surface of the source electrode 16 and the drain electrode 17 and is adjacent to and in contact with the oxide semiconductor layer 4a and the oxide semiconductor layer 4b. 4 is connected.

  That is, the oxide semiconductor layer 4a under the source electrode 16 and the oxide semiconductor layer 4b under the drain electrode 17 are interposed via the oxide semiconductor layer 5 formed on the gate insulating film 3 between the oxide semiconductor layers 4a and 4b. Connected.

  In the oxide semiconductor layer 5, a region sandwiched between the source electrode 16 and the drain electrode 17 (a region facing the gate electrode 2) on the gate insulating film 3 is a channel main region RC <b> 5.

  Further, a protective insulating film 18 is formed on the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, and the gate insulating film 3. The location where the protective insulating film 18 is formed on the gate insulating film 3 is not shown in FIG.

  FIG. 4 is an explanatory diagram showing a schematic configuration of a liquid crystal display device 200 including the TFT substrate 100 shown in FIG. The TFT substrate 100 has the pixel TFT 30 shown in FIGS.

  As shown in FIG. 4, the liquid crystal display device 200 employs a configuration in which a polarizing plate 101, a TFT substrate 100, a color filter 102, and a polarizing plate 101 are arranged in this order on a backlight 104. The polarization directions of 101 are arranged so as to be orthogonal to each other.

  An alignment film and a spacer are formed on the surface of the TFT substrate 100 using the pixel TFT 30. The alignment film is a film for aligning liquid crystals and is made of polyimide or the like.

  On the other hand, the color filter 102 is actually provided on a counter substrate disposed to face the TFT substrate 100. The TFT substrate 100 and the counter substrate are bonded together with a certain gap by the spacer, and liquid crystal is injected into this gap and sealed.

  That is, a liquid crystal layer (not shown in FIG. 4) is sandwiched between the TFT substrate 100 and the counter substrate. The liquid crystal display device 200 is obtained by disposing the two polarizing plates 101 and the backlight 104 shown in FIG. 4 on the outer surfaces of the TFT substrate 100 and the counter substrate (color filter 102) bonded in this manner. be able to.

(Production method)
5 to 19 are cross-sectional views showing the processing procedure of the manufacturing process of the pixel TFT 30 of the first embodiment. Hereinafter, the processing content of the manufacturing method of the pixel TFT 30 of the first embodiment will be described with reference to FIGS. A cross-sectional view showing the final process corresponds to FIG.

  First, as shown in FIG. 5, a transparent insulating substrate 1 such as glass is prepared. As shown in FIG. 6, for example, an aluminum (Al) alloy film, more specifically, an alloy film in which 3 mol% of Ni is added to Al (Al-3 mol%) is formed on the entire surface of the transparent insulating substrate 1. A metal film 19 (first metal film) is formed using a Ni film. The “Al-3 mol% Ni film” means a film in which Ni is alloyed with Al at a mole fraction of 3%.

  The Al-3 mol% Ni film can be formed by a sputtering method using an Al-3 mol% Ni alloy target. Here, a metal film 19 was formed by forming an Al-3 mol% Ni film having a thickness of 100 nm. Note that Ar gas, Kr gas, or the like can be used as the sputtering gas.

  Next, as shown in FIG. 7, the photoresist applied and formed on the metal film 19 is patterned by a photolithography (photoengraving) process to form a resist pattern RM1. As the photoresist, for example, a photoresist material composed of a novolac positive photosensitive resin is applied on the metal film 19 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 8, using the resist pattern RM1 as an etching mask, the metal film is formed by a wet etching method using a PAN-based solution containing phosphoric acid, acetic acid, and nitric acid. The gate electrode 2 is formed on the transparent insulating substrate 1 by performing a patterning process (first patterning process) on the substrate 19.

Next, after stripping and removing the resist pattern RM1 using an amine-based resist stripping solution, the gate insulating film 3 is formed on the transparent insulating substrate 1 so as to cover the gate electrode 2 as shown in FIG. Form. The gate insulating film 3 is formed to a thickness of, for example, about 50 to 500 nm by, for example, a plasma CVD (Chemical Vapor Deposition) method using silane (SiH ₄ ) gas and dinitrogen monoxide (N ₂ O) gas. The

Next, as shown in FIG. 10, a manufacturing oxide semiconductor layer 41 (first manufacturing semiconductor layer) is formed on the gate insulating film 3. In this embodiment, an InGaZnO-based oxide semiconductor in which gallium oxide (Ga ₂ O ₃ ) and zinc oxide (ZnO) are added to indium oxide (In ₂ O ₃ ) is used as a constituent material of the manufacturing oxide semiconductor layer 41. Is used.

Here, for example, DC sputtering using an InGaZnO target [In ₂ O _3. (Ga ₂ O ₃ ). (ZnO) ₂ ] in which the atomic composition ratio of In: Ga: Zn: O is 1: 1: 1: 4. The manufacturing oxide semiconductor layer 41 is formed by the method. At this time, a known argon (Ar) gas, krypton (Kr) gas, or the like can be used as the sputtering gas. In an InGaZnO film formed using such a sputtering method, the atomic composition ratio of oxygen is usually smaller than the stoichiometric composition, and an oxygen ion deficient state (in the above example, the O composition ratio is 4). Less than) oxide film. Therefore, it is desirable to mix Ar gas with oxygen (O ₂ ) gas and perform sputtering. Here, sputtering is performed using a mixed gas obtained by adding 10% O ₂ gas in a partial pressure ratio to Ar gas, and the InGaZnO-based manufacturing oxide semiconductor layer 41 is formed with a thickness of, for example, 40 nm. Note that the InGaZnO film may have an amorphous structure.

  Next, as shown in FIG. 11, the photoresist applied and formed on the manufacturing oxide semiconductor layer 41 is patterned by a photolithography process to form a resist pattern RM2. As the photoresist, for example, a photoresist material composed of a novolac-based positive photosensitive resin is applied onto the manufacturing oxide semiconductor layer 41 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 12, a patterning process (second patterning process) is performed on the manufacturing oxide semiconductor layer 41 by wet etching using a solution containing nitric acid using the resist pattern RM2 as an etching mask. A patterned semiconductor layer 41P (patterned first manufacturing semiconductor layer) is formed in a region overlapping the gate electrode 2 as viewed. Here, the patterned semiconductor layer 41P may have a region where the gate electrode 2 protrudes in plan view. Thereafter, the resist pattern RM2 is stripped and removed using an amine-based resist stripping solution. Note that in the case where the shape of the completed oxide semiconductor layer 4 (4a and 4b) illustrated in FIG. 3 is the same as that of the source electrode 16 and the drain electrode 17 as illustrated in FIGS. The adding step can be omitted.

  Next, a metal film that will later become the source electrode 16 and the drain electrode 17 is formed. In this embodiment, the metal film of the source electrode 16 and the drain electrode 17 has a two-layer structure of, for example, molybdenum (Mo) and aluminum (Al).

  First, as shown in FIG. 13, a molybdenum (Mo) layer 21 is formed on the entire surface so as to cover the patterned semiconductor layer 41 </ b> P and the gate insulating film 3. For example, the molybdenum layer 21 is formed by DC sputtering using a Mo target.

  Next, as shown in FIG. 14, an aluminum (Al) layer 22 is formed on the molybdenum layer 21. For forming the aluminum layer 22, an Al-3 mol% Ni film is formed by sputtering using an Al-3 mol% Ni alloy target, for example. The film thicknesses of the molybdenum layer 21 and the aluminum layer 22 are each 10 to 100 nm, for example. The laminated metal layers 21 and 22 made of MO and Al serve as a second metal film for forming the source electrode 16 and the drain electrode 17.

  Next, as shown in FIG. 15, the photoresist applied and formed on the aluminum layer 22 is patterned by a photolithography process to form a resist pattern RM3 for forming the source electrode 16 and the drain electrode 17. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the aluminum layer 22 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 16, by performing a patterning process (third patterning process) on the molybdenum layer 21 and the aluminum layer 22 by a wet etching method using a PAN-based solution using the resist pattern RM3 as an etching mask. The source electrode 16 and the drain electrode 17 are obtained.

  By this third patterning process, the patterned semiconductor layer 41P is also patterned. That is, the target of the third patterning process is the molybdenum layer 21, the aluminum layer 22, and the patterned semiconductor layer 41P. As a result, oxide semiconductor layers 4 a and 4 b are obtained under the source electrode 16 and the drain electrode 17. That is, as the oxide semiconductor layer 4 (first semiconductor layer), the oxide semiconductor layer 4a (one partial semiconductor layer) on the source electrode 16 side and the oxide semiconductor layer 4b (other partial semiconductor layer) on the drain electrode 17 side. And are obtained separately.

  In this manner, the oxide semiconductor layer 4 (first semiconductor layer) can be formed simultaneously with the source electrode 16 and the drain electrode 17 by the third patterning process.

  After the third patterning process, an opening 28 where the surface of the gate insulating film 3 is exposed is formed between the source electrode 16 and the drain electrode 17. The opening 28 completely overlaps with the gate electrode 2 in plan view. That is, after the third patterning process, the region on the gate insulating film 3 between the source electrode 16 and the drain electrode 17 becomes a region facing the gate electrode 2.

Next, as illustrated in FIG. 17, the manufacturing oxide semiconductor layer 51 (second electrode) is formed on the source electrode 16, the drain electrode 17, and the oxide semiconductor layer 4 and on the gate insulating film 3 in the opening 28. A semiconductor layer for manufacturing) is formed. For example, an InGaZnO-based oxide semiconductor is used as the manufacturing oxide semiconductor layer 51. Here, for example, DC sputtering using an InGaZnO target [In ₂ O _3. (Ga ₂ O ₃ ). (ZnO) ₂ ] in which the atomic composition ratio of In: Ga: Zn: O is 1: 1: 1: 4. A manufacturing oxide semiconductor layer 51 is formed by a method. For example, sputtering is performed using a mixed gas obtained by adding 10% O ₂ gas at a partial pressure ratio to Ar gas, and an InGaZnO-based oxide semiconductor layer is formed to a thickness of 40 nm. Note that the InGaZnO film may have an amorphous structure.

  Next, as shown in FIG. 18, the photoresist applied and formed on the manufacturing oxide semiconductor layer 51 is patterned by a photolithography process while filling the opening 28, thereby forming a resist pattern RM4. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the manufacturing oxide semiconductor layer 51 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 19, by performing a patterning process (fourth patterning process) on the manufacturing oxide semiconductor layer 51 by wet etching using a solution containing nitric acid using the resist pattern RM4 as an etching mask. An oxide semiconductor layer 5 (second semiconductor layer) is obtained.

  Here, the oxide semiconductor layer 5 may have a region protruding from the gate electrode 2 in plan view. In addition, the carrier density of the oxide semiconductor layer 4 may be higher than that of the oxide semiconductor layer 5. Thereafter, the resist pattern RM4 is stripped and removed using an amine-based resist stripping solution.

  The oxide semiconductor layer 5 has a channel main region RC5 formed in a region facing the gate electrode 2 between the source electrode 16 and the drain electrode 17 on the gate insulating film 3, and the source electrode 16 and the drain electrode 17 respectively. And the main channel region RC5 is sandwiched between the oxide semiconductor layers 4a and 4b, thereby contacting the oxide semiconductor layers 4a and 4b.

Next, a protective insulating film 18 is formed over the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, and the gate insulating film 3. The protective insulating film 18 is formed to a thickness of about 50 to 500 nm, for example, by plasma CVD using silane (SiH ₄ ) gas and dinitrogen monoxide (N ₂ O) gas. Then, the pixel TFT 30 shown in FIG. 3 is completed.

  That is, a part of the oxide semiconductor layers 4a and 4b under the source electrode 16 and the drain electrode 17 and the channel main region RC5 of the oxide semiconductor layer 5 as a channel region, the source electrode 16, the drain electrode 17, the gate electrode 2 and the gate. A pixel TFT 30 having a transistor structure made of the insulating film 3 is completed.

  Thus, the pixel TFT 30 of the first embodiment can be manufactured by four times of the first to fourth patterning processes.

(effect)
In the pixel TFT 30 of Embodiment 1, since the constituent materials of the oxide semiconductor layers 4 and 5 are oxide semiconductors, a transistor structure having a channel path with high mobility can be obtained. As a result, energy saving of the TFT substrate 100 having the pixel TFT 30 and the liquid crystal display device 200 can be achieved.

  Further, by using an oxide semiconductor with high mobility for the oxide semiconductor layers 4 and 5, the on-current of the pixel TFT 30 can be increased, and even if variations in characteristics in the manufacturing process occur, good characteristics can be obtained. Since it can be expected that the proportion of the pixel TFTs 30 having an on-current higher than a certain level will be manufactured more than a TFT having a normal coplanar structure, the yield can be improved.

  Note that the above-described effects can be achieved although the degree is reduced by using only one constituent material of the oxide semiconductor layers 4 and 5 as an oxide semiconductor.

  According to the pixel TFT 30 of the first embodiment, the gate electric field is applied from the gate electrode 2 to the oxide semiconductor layers 4a and 4b below the source electrode 16 and the drain electrode 17, so A current path is formed in a region where the physical semiconductor layers 4a and 4b overlap in plan view. That is, as shown in FIG. 3, a current path I5 is formed between the source electrode 16 and the drain electrode 17.

  Therefore, in addition to the main channel region RC5 of the oxide semiconductor layer 5, part of the oxide semiconductor layers 4a and 4b through which the current path I5 flows functions as a channel region of the pixel TFT 30.

  As described above, the pixel TFT 30 according to the first embodiment includes a channel region in which the current path I5 illustrated in FIG. 3 flows (the region where the current path I5 is formed in the oxide semiconductor layers 4a and 4b and the main channel of the oxide semiconductor layer 5). By having the region RC5), it is possible to realize the pixel TFT 30 having a coplanar structure in which the contact resistance between the source electrode 16 and the drain electrode 17 and the channel region is reduced.

  The oxide semiconductor layers 4a and 4b (one and the other partial semiconductor layers) are formed simultaneously with the source electrode 16 and the drain electrode 17 during the third patterning process for the stacked metal layers 21 and 22 (second metal film). can do.

  Further, since the pixel TFT 30 has a structure in which an overlap region between the protective film semiconductor layer and the source electrode and the drain electrode does not occur as compared with the ES structure, the TFT size and the parasitic capacitance can be reduced.

  In addition, since the oxide semiconductor layer 5 having the channel main region RC5 is formed after the source electrode 16 and the drain electrode 17 are formed, the pixel TFT 30 having a highly reliable channel region can be obtained.

  That is, compared with the back channel etching structure, the channel main region RC5 of the oxide semiconductor layer 5 is not exposed to the wet etching performed as the third patterning process when the source electrode 16 and the drain electrode 17 are formed. Defect density can be suppressed. As a result, it is possible to obtain the pixel TFT 30 having a long lifetime while suppressing deterioration due to defects.

  Consider a case where a two-layer structure of Al and Mo is used for the source electrode 16 and the drain electrode 17 of the pixel TFT 30 of the first embodiment. When etching was performed on Al and Mo with a PAN-based solution at about 40 ° C., the etching rates were 324 nm / min and 277 nm / min, respectively.

  Here, when Mo is used as the upper layer, the lower layer Al is etched faster than the upper Mo layer having a low etching rate, and the cross-sectional shapes of the source electrode 16 and the drain electrode 17 become eaves. As described above, when the cross-sectional shape of the source electrode 16 and the drain electrode 17 becomes an elongate shape, the TFT characteristics deteriorate.

  Therefore, it is desirable to form the aluminum layer 22 on the molybdenum layer 21 and form Al with a high etching rate as the upper layer as in the pixel TFT 30 of the first embodiment. In addition, when an oxide TFT, which is a TFT using an oxide semiconductor for a channel region using Al for the source electrode 16 and the drain electrode 17, was manufactured, the contact resistance was 101 kΩ.

  On the other hand, the contact resistance when an oxide semiconductor TFT was manufactured using Mo for the source electrode 16 and the drain electrode 17 was 15 kΩ. From this, it can be seen that Mo has a smaller contact resistance with a region having an oxide semiconductor as a constituent material than Al. Therefore, the oxide semiconductor layers 4a and 4b are formed by the pixel TFT 30 of this embodiment in which the oxide semiconductor layers 4a and 4b made of an oxide semiconductor are in contact with the molybdenum layer 21 which is the lower layer of the source electrode 16 and the drain electrode 17. The contact resistance with can be reduced.

  Further, the carrier density of the oxide semiconductor layer 4 (first semiconductor layer) is made higher than that of the oxide semiconductor layer 5 (second semiconductor layer), whereby the source electrode 16 and the drain electrode 17 and the oxide semiconductor layer 4a. And the contact resistance with 4b can be made small. Further, in the coplanar structure, carriers diffuse from a region having a high carrier density (oxide semiconductor layer 4) into a channel region having a low carrier density (channel main region RC5 of the oxide semiconductor layer 5), whereby a threshold voltage when a positive bias is applied. The effect of suppressing the shift of can be expected.

  For example, the literature [SH Ha, DH Kang, I. Kang, JU Han, M. Mativenga, and J. Jang, “Channel Length Dependent Bias-Stability of Self-Aligned Coplanar a-IGZO TFTs,” IEEE / OSA J. Disp. Technol., Vol. 9, no. 12, pp. 985-988, 2013.]. That is, the carrier TFT diffuses into the oxide semiconductor layer 5 from the oxide semiconductor layer 4 (4a, 4b), whereby the reliability of the pixel TFT 30 can be improved.

  Thus, by making the carrier density of the oxide semiconductor layer 4 higher than that of the oxide semiconductor layer 5, the contact resistance between the oxide semiconductor layers 4a and 4b and the source electrode 16 and the drain electrode 17 can be reduced.

  Further, in the transistor structure of the pixel TFT 30 having a coplanar structure, carriers are diffused from a region having a high carrier density (oxide semiconductor layer 4) to a channel region having a low carrier density (oxide semiconductor layer 5). Shift of the threshold voltage can be suppressed. As a result, the diffusion of carriers from the oxide semiconductor layer 4 into the oxide semiconductor layer 5 can improve the reliability of the transistor structure.

  Further, the area of the pixel electrode can be increased by reducing the pixel TFT 30, and the wiring density of the source wiring 12 and the gate wiring 13 is increased by reducing the contact resistance between the source electrode 16, the drain electrode 17, and the channel region. be able to.

  Accordingly, the TFT substrate 100 having the pixel TFT 30 of Embodiment 1 is used, and includes the TFT substrate 100, the counter substrate (having the color filter 102), and the liquid crystal layer sandwiched between the TFT substrate 100 and the counter substrate. The constructed liquid crystal display device 200 (see FIG. 4) has the effects of high aperture ratio, high definition (high resolution), high frame rate, long life, and high reliability.

(Modification)
FIG. 20 is a cross-sectional view showing a cross-sectional structure of a pixel TFT 30B which is a modification of the pixel TFT. As shown in the figure, the oxide semiconductor layer 4 (4b) is formed only below the drain electrode 17.

  Also in such a coplanar pixel TFT 30B, since the drain electrode 17 and the oxide semiconductor layer 4 overlap in plan view, the contact resistance between the drain electrode 17 and the channel region can be reduced. Play.

  That is, at least one of the source electrode 16 and the drain electrode 17 (the source electrode 16 and the drain electrode 17 in the structure shown in FIG. 3 and the drain electrode 17 in the structure of the modification shown in FIG. 20) is on the oxide semiconductor layer 4. Thus, a gate electric field is applied from the gate electrode 2 to the oxide semiconductor layer 4 below at least one of the source electrode 16 and the drain electrode 17.

  As a result, a current path can be formed even in a region where at least one electrode and the oxide semiconductor layer 4 overlap each other in plan view, so that the contact resistance between at least one electrode and the channel region can be suppressed. There is an effect.

<Embodiment 2>
In this embodiment, as in Embodiment 1, TFTs are used for at least one of a pixel and a driver circuit. The pixel TFT 30 has the same structure as that of the pixel TFT 30 of Embodiment 1, and a manufacturing oxide semiconductor layer 42 is used in place of the manufacturing oxide semiconductor layer 41, and the source electrode 16 and the drain are used as constituent materials of the manufacturing oxide semiconductor layer 42. The difference is that an oxide semiconductor that is resistant to wet etching performed during the third patterning process for the electrode 17 is used.

(Production method)
FIG. 21 to FIG. 30 are cross-sectional views showing the processing procedure of the manufacturing process of the pixel TFT 30 of the second embodiment. Hereinafter, a method of manufacturing the pixel TFT 30 of the second embodiment will be described with reference to FIGS. A cross-sectional view showing the final process has the same structure as the pixel TFT 30 of the first embodiment shown in FIG.

  Similar to the manufacturing method of the first embodiment, after the steps shown in FIGS. 5 to 9, as shown in FIG. 21, the manufacturing oxide semiconductor layer 42 (for the first manufacturing) is formed on the gate insulating film 3. Oxide semiconductor layer). In this embodiment, the manufacturing oxide semiconductor layer 42 is made of an oxide semiconductor having wet etching resistance with respect to the wet etching process performed as the third patterning process for the source electrode 16 and the drain electrode 17. As an oxide semiconductor exhibiting PAN resistance, for example, an oxide semiconductor containing In, Ga, Zn, and tin element (Sn) disclosed in Japanese Patent Application Laid-Open No. 2010-118407 is used.

  Here, for example, the manufacturing oxide semiconductor layer 42 is formed to a thickness of, for example, 40 nm by a DC sputtering method using a target containing In, Ga, Zn, and Sn. Note that the manufacturing oxide semiconductor layer 42 may have an amorphous structure.

  Next, as shown in FIG. 22, a photoresist applied and formed on the manufacturing oxide semiconductor layer 42 is patterned by a photolithography process to form a resist pattern RM12. For the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the manufacturing oxide semiconductor layer 42 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 23, by performing a patterning process (second patterning process) on the manufacturing oxide semiconductor layer 42 by wet etching using a solution containing nitric acid using the resist pattern RM12 as an etching mask. An oxide semiconductor layer 4 (4a and 4b) is formed so as to overlap with the gate electrode 2 in plan view. Here, the oxide semiconductor layer 4 may have a region protruding from the gate electrode 2 in plan view.

  Thus, as the oxide semiconductor layer 4 (first semiconductor layer) during the second patterning process, the source electrode 16 side oxide semiconductor layer 4a (one partial semiconductor layer) to be manufactured later, and the drain to be manufactured later The oxide semiconductor layer 4b (the other partial semiconductor layer) on the electrode 17 side is obtained separately. That is, in the second embodiment, the oxide semiconductor layer 4 completed after the second patterning process is obtained as a structure corresponding to the patterned semiconductor layer 41P of the first embodiment. Thereafter, the resist pattern RM12 is stripped and removed using an amine resist stripping solution.

  Next, a metal film for forming the source electrode 16 and the drain electrode 17 is formed later. In this embodiment, the metal film (second metal film) of the source electrode 16 and the drain electrode 17 has, for example, a two-layer structure of Mo and Al.

  First, as illustrated in FIG. 24, a molybdenum layer 21 is formed so as to cover the oxide semiconductor layer 4 and the gate insulating film 3. For example, the molybdenum layer 21 is formed by DC sputtering using a Mo target.

  Next, as shown in FIG. 25, an aluminum layer 22 is formed on the molybdenum layer 21. For the film formation of Al, for example, an Al-3 mol% Ni film is formed by sputtering using an Al-3 mol% Ni alloy target. The film thicknesses of the molybdenum layer 21 and the aluminum layer 22 are each 10 to 100 nm, for example.

  Next, as shown in FIG. 26, the photoresist applied and formed on the aluminum layer 22 is patterned by a photolithography process to obtain a resist pattern RM13 for forming the source electrode 16 and the drain electrode 17. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the aluminum layer 22 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 27, by performing a patterning process (third patterning process) on the molybdenum layer 21 and the aluminum layer 22 by a wet etching method using a PAN-based solution using the resist pattern RM13 as an etching mask. The source electrode 16 and the drain electrode 17 are obtained. At this time, an opening 28 where the surface of the gate insulating film 3 is exposed is formed between the source electrode 16 and the drain electrode 17.

  Here, the oxide semiconductor layer 4 existing below the resist pattern RM13 is not patterned. That is, the objects of the third patterning process are the molybdenum layer 21 and the aluminum layer 22, and the oxide semiconductor layer 4 corresponding to the patterned semiconductor layer after the second patterning process is not included.

  Next, as shown in FIG. 28, a manufacturing oxide semiconductor layer 51 (second manufacturing) is formed on the source electrode 16, the drain electrode 17, and the oxide semiconductor layer 4 and on the gate insulating film 3 in the opening 28. An oxide semiconductor layer) is formed. As the manufacturing oxide semiconductor layer 51, an oxide semiconductor resistant to wet etching in the third patterning process may not be used. Here, as in Embodiment 1, for example, an InGaZnO-based oxide semiconductor is used.

  Next, as shown in FIG. 29, a photoresist applied and formed on the manufacturing oxide semiconductor layer 51 is patterned by a photolithography process while filling the opening 28 to obtain a resist pattern RM14. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the manufacturing oxide semiconductor layer 51 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 30, the resist pattern RM14 is used as an etching mask, and oxidation is performed by performing a patterning process (fourth patterning process) on the manufacturing oxide semiconductor layer 51 by wet etching using a solution containing nitric acid. The physical semiconductor layer 5 is obtained. Here, the oxide semiconductor layer 5 may have a region protruding from the gate electrode 2 in plan view. In addition, the carrier density of the oxide semiconductor layer 4 may be higher than that of the oxide semiconductor layer 5. Thereafter, the resist pattern RM14 is stripped and removed using an amine-based resist stripping solution.

  Next, a protective insulating film 18 is formed over the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, and the gate insulating film 3 in the same manner as in Embodiment 1. Then, the pixel TFT of the second embodiment having the same structure as the pixel TFT 30 shown in FIG. 3 is obtained.

(effect)
As a constituent material of the manufacturing oxide semiconductor layer 42 for manufacturing the oxide semiconductor layer 4, an oxide semiconductor resistant to wet etching performed as the third patterning process for the source electrode 16 and the drain electrode 17 is used. Thus, the oxide semiconductor layer 4 can be formed with high accuracy during the second patterning process that is performed prior to the third patterning process.

  As described above, in the manufacturing method of the pixel TFT 30 of the second embodiment, the laminated metal layers 21 and 22 (second metal film) are used as the constituent materials of the manufacturing oxide semiconductor layer 42 (first manufacturing semiconductor layer). By using a constituent material that is not patterned when the third patterning process is performed on the oxide semiconductor layer 4, the oxide semiconductor layer 4 (4a and 4b) can be formed with high accuracy during the second patterning process in the step shown in FIG.

  Further, after the oxide semiconductor layer 4 is obtained by executing the second patterning process in the step shown in FIG. 23, the source electrode 16 and the drain electrode 17 are obtained by executing the third patterning process in the step shown in FIG. Therefore, a structure in which the oxide semiconductor layers 4a and 4b protrude from the source electrode 16 and the drain electrode 17 in a plan view can be easily formed. As a result, there is an effect that a structure in which the oxide semiconductor layer 4 and the oxide semiconductor layer 5 are in contact with each other can be obtained relatively easily.

<Embodiment 3>
In this embodiment mode, a TFT is used for at least one of a pixel and a driver circuit as in Embodiment Modes 1 and 2. Below, it demonstrates as a case where it uses for a pixel.

  FIG. 31 is a cross-sectional view showing a cross-sectional structure of the pixel TFT 30C of the third embodiment. A pixel TFT 30C shown in FIG. 31 corresponds to the AA cross section of FIG. Hereinafter, the pixel TFT 30C of the third embodiment will be described with reference to FIG.

  As shown in the figure, the pixel TFT 30C according to the third embodiment has the channel protective layer 6 formed on the oxide semiconductor layer 5 in that the pixel according to the first embodiment shown in FIGS. Different from TFT30. Therefore, the transparent insulating substrate 1, the gate electrode 2, the gate insulating film 3, the oxide semiconductor layers 4 (4a, 4b), the oxide semiconductor layer 5, the source electrodes 16 (21, 22) and the drain electrode 17 in the pixel TFT 30C. The structure composed of (21, 22) is the same as that of the pixel TFT 30.

  Note that the channel protective layer 6 formed over the oxide semiconductor layer 5 may have a region where the oxide semiconductor layer 5 protrudes from the channel protective layer 6 in plan view.

  Then, a protective insulating film 18 is formed on the channel protective layer 6, the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, and the gate insulating film 3.

(Production method)
32 to 35 are cross-sectional views showing the processing procedure of the manufacturing process of the pixel TFT 30C of the third embodiment. Hereinafter, a method for manufacturing the pixel TFT 30C of the third embodiment will be described with reference to FIGS. A sectional view showing the final process has a structure shown in FIG.

First, the manufacturing oxide semiconductor layer 51 (second manufacturing oxidation) is performed through the manufacturing method of the first embodiment shown in FIGS. 5 to 17 or the manufacturing method of the second embodiment shown in FIGS. After the physical semiconductor layer is formed, a protective insulating film 61 (protective film intermediate layer) is formed on the entire surface as shown in FIG. The protective insulating film 61 is formed to a thickness of, for example, about 50 to 500 nm by a plasma CVD method using, for example, silane (SiH ₄ ) gas and dinitrogen monoxide (N ₂ O) gas.

  Next, as shown in FIG. 33, the photoresist applied and formed on the protective insulating film 61 is patterned by a photolithography process to form a resist pattern RM24 for forming the channel protective layer 6. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied on the protective insulating film 61 by a coating method to have a thickness of about 1.5 μm.

Next, as shown in FIG. 34, the protective insulating film 61 is formed by dry etching using a fluorine-containing gas such as CHF ₃ , CF ₄ , SF ₆ and oxygen (O ₂ ) gas using the resist pattern RM 24 as a mask. The channel protective layer 6 is formed by performing a patterning process (fifth patterning process) on the above.

  Next, as shown in FIG. 35, patterning processing (fourth patterning processing) is performed on the manufacturing oxide semiconductor layer 51 by wet etching using a solution containing nitric acid with the channel protective layer 6 as an etching mask. Thus, the oxide semiconductor layer 5 is obtained. Here, the oxide semiconductor layer 5 may have a region protruding from the gate electrode 2 in plan view. In addition, the carrier density of the oxide semiconductor layer 4 may be higher than that of the oxide semiconductor layer 5.

  Thereafter, the resist pattern RM24 is stripped and removed using an amine-based resist stripper. At this time, since the channel protective layer 6 is formed on the oxide semiconductor layer 5, the oxide semiconductor layer 5 is not damaged by the removal of the resist pattern RM24.

  Next, as in Embodiments 1 and 2, a protective insulating film 18 is formed over the channel protective layer 6, the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, and the gate insulating film 3. A pixel TFT 30C shown in FIG. 31 is obtained.

  Through the manufacturing steps described above, the pixel TFT 30C of the third embodiment having the channel protective layer 6 can be manufactured.

(effect)
Since the channel protective layer 6 is formed on the oxide semiconductor layer 5 when the resist pattern RM24 is peeled and removed after the fourth patterning process (wet etching) on the manufacturing oxide semiconductor layer 51, the oxide semiconductor layer The damage introduction to 5 can be suppressed. Therefore, the channel main region RC5 with few defects can be formed in the oxide semiconductor layer 5, and the pixel TFT 30C of Embodiment 3 can obtain good TFT characteristics and improve the yield.

  Thus, in the pixel TFT 30C of Embodiment 3, the oxide semiconductor layer 5 is formed by the fourth patterning process by providing the channel protective layer 6 on the oxide semiconductor layer 5 (second semiconductor layer). Since the channel protective layer 6 can remain even after the etching, the oxide semiconductor layer 5 can be prevented from being damaged even after the fourth patterning process. As a result, damage to the oxide semiconductor layer 5 after the fourth patterning process can be suppressed, and deterioration of the characteristics of the pixel TFT 30C can be prevented.

  Note that, as the damage, for example, in the case of the pixel TFT 30 of the first embodiment, the damage that the oxide semiconductor layer 5 receives during the peeling process of the resist pattern RM14 shown in FIGS. 18 and 19 corresponds to the damage of the third embodiment. In the pixel TFT 30C, since the channel protective layer 6 is provided on the oxide semiconductor layer 5, the damage of the first embodiment is not caused.

<Embodiment 4>
In this embodiment, as in Embodiments 1 to 3, TFTs are used for at least one of a pixel and a driver circuit. Below, it demonstrates as a case where it uses for a pixel.

  36 is a plan view showing a planar structure of the pixel TFT 30D of the fourth embodiment, and FIG. 37 is a sectional view showing a BB sectional structure of FIG. 36 and 37 also show the XYZ orthogonal coordinate system. Hereinafter, the pixel TFT 30 </ b> D will be described with reference to FIGS. 36 and 37.

  As shown in FIG. 37, the pixel TFT 30D of the fourth embodiment includes a transparent insulating substrate 1, a gate electrode 2 and a gate insulating film having the same structure as the pixel TFT 30 of the first embodiment shown in FIGS. 3. The pixel TFT 30D of the fourth embodiment is different from the pixel TFT 30 of the first embodiment shown in FIGS. 2 and 3 except that an oxide semiconductor layer 8 (8a and 8b), which will be described in detail later, is formed. It has a similar structure.

  An oxide semiconductor layer 4 and an oxide semiconductor layer 8 are formed on the gate insulating film 3. Here, four oxide semiconductor layers 4a and 4b and oxide semiconductor layers 8a and 8b formed of the same constituent material are formed at a distance from each other. The oxide semiconductor layers 4a and 4b constitute the oxide semiconductor layer 4 and are formed under the source electrode 16 and the drain electrode 17 in the same manner as in the first to third embodiments. The oxide semiconductor layer 5 is connected in such a manner as to be adjacent to and in contact with the RC 5.

  The pixel TFT 30D of the fourth embodiment further includes the oxide semiconductor layers 8a and 8b, and includes the oxide semiconductor layer 8 (third semiconductor layer) formed of the same constituent material as the oxide semiconductor layer 4. It is characterized by that. The oxide semiconductor layer 8 a is provided between the gate insulating film 3 and the source electrode 16 on the left side (−X direction side) of the oxide semiconductor layer 4 a below the source electrode 16, and the oxide semiconductor layer 8 b Below, it is provided between the gate insulating film 3 and the source electrode 16 on the right side (+ X direction side) of the oxide semiconductor layer 4b.

  The oxide semiconductor layers 8a and 8b are preferably formed below the source electrode 16 and the drain electrode 17, and further, there is a region where each part overlaps the gate electrode 2 in plan view.

  Then, the source electrode 16 and the drain electrode 17 are formed so as to cover partial regions of the oxide semiconductor layer 4, the oxide semiconductor layer 8, and the gate insulating film 3. As described above, the source electrode 16 is formed on the oxide semiconductor layer 4a and the oxide semiconductor layer 8a, and the drain electrode 17 is formed on the oxide semiconductor layer 4b and the oxide semiconductor layer 8b. Here, the oxide semiconductor layers 4a and 4b and the oxide semiconductor layers 8a and 8b may have regions protruding from the source electrode 16 and the drain electrode 17 in plan view.

  Then, the oxide semiconductor layer 5 (second semiconductor layer) is formed on the source electrode 16 and the drain electrode 17 and on the gate insulating film 3 between the source electrode 16 and the drain electrode 17. Are connected to each other through the oxide semiconductor layer 5.

  When there is a region where the oxide semiconductor layers 4 a and 4 b protrude from the source electrode 16 and the drain electrode 17 in plan view, the oxide semiconductor layer 5 is also formed on the protruding region. Here, the oxide semiconductor layer 5 is provided in contact with the oxide semiconductor layer 4a and the oxide semiconductor layer 4b. On the other hand, the oxide semiconductor layer 5 is not connected to the oxide semiconductor layers 8a and 8b.

  That is, the oxide semiconductor layer 4a under the source electrode 16 and the oxide semiconductor layer 4b under the drain electrode 17 are interposed via the oxide semiconductor layer 5 formed on the gate insulating film 3 between the oxide semiconductor layers 4a and 4b. Connected. On the other hand, the oxide semiconductor layers 8 a and 8 b are formed of the same material as that of the oxide semiconductor layer 4, provided independently of the oxide semiconductor layer 4 on the gate insulating film 3, and the oxide semiconductor layer 5 Do not touch.

  In the oxide semiconductor layer 5, a region sandwiched between the source electrode 16 and the drain electrode 17 on the gate insulating film 3 becomes the channel main region RC5.

  Further, a protective insulating film 18 is formed on the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, and the gate insulating film 3.

(Production method)
38 to 44 are cross-sectional views showing the processing procedure of the manufacturing process of the pixel TFT 30D of the fourth embodiment. Hereinafter, a method for manufacturing the pixel TFT 30D of the fourth embodiment will be described with reference to FIGS. A sectional view showing the final process has a structure shown in FIG.

  First, the manufacturing oxide semiconductor layer 44 is formed on the gate insulating film 3 as shown in FIG. 38 through the manufacturing process of the first embodiment shown in FIGS.

  Here, as the constituent material of the manufacturing oxide semiconductor layer 44, as in the manufacturing oxide semiconductor layer 41 of the first embodiment, the wet etching performed as the third patterning process for the source electrode 16 and the drain electrode 17 is performed. An oxide semiconductor that is resistant to wet etching may be used in the same manner as the oxide semiconductor layer 42 for manufacturing in Embodiment 2, even if an oxide semiconductor that is not resistant to wet etching is used.

In this embodiment, as the manufacturing oxide semiconductor layer 44, in the same manner as the manufacturing oxide semiconductor layer 41 of Embodiment 1, gallium oxide (Ga ₂ O ₃ ) and oxide are added to indium oxide (In ₂ O ₃ ). An InGaZnO-based oxide semiconductor to which zinc (ZnO) is added is used.

  Next, as shown in FIG. 39, a photoresist applied and formed on the manufacturing oxide semiconductor layer 44 is patterned by a photolithography process to form a resist pattern RM32. As the photoresist, for example, a photoresist material composed of a novolac-based positive photosensitive resin is applied on the manufacturing oxide semiconductor layer 44 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 40, by performing a patterning process (second patterning process) on the manufacturing oxide semiconductor layer 44 by wet etching using a solution containing nitric acid using the resist pattern RM32 as an etching mask, The central residual oxide semiconductor layer 44x is formed so as to overlap the gate electrode 2 in plan view, and the oxide semiconductor layers 8a and 8b are formed so as to sandwich the gate electrode 2 in plan view.

  As described above, the central residual oxide semiconductor layer 44x and the oxide semiconductor layers 8a and 8b become the patterned first manufacturing semiconductor layer obtained by the second patterning process, and the patterned first manufacturing semiconductor layer becomes the first manufacturing semiconductor layer. Oxide semiconductor layers 8a and 8b are included.

  The central residual oxide semiconductor layer 44x and the oxide semiconductor layers 8a and 8b are formed separately from each other, and the central residual oxide semiconductor layer 44x is a connection target with the oxide semiconductor layer 5 to be manufactured later. On the other hand, the oxide semiconductor layers 8 a and 8 b are not connected to the oxide semiconductor layer 5.

  The central residual oxide semiconductor layer 44x may have a region protruding from the gate electrode 2 in plan view. Thereafter, the resist pattern RM32 is stripped and removed using an amine-based resist stripping solution.

  Next, as shown in FIG. 41, a molybdenum layer 21 is formed on the entire surface so as to cover the central residual oxide semiconductor layer 44x, the oxide semiconductor layers 8a and 8b, and the gate insulating film 3. For example, the molybdenum layer 21 is formed by DC sputtering using a Mo target.

  Next, as shown in FIG. 42, an aluminum layer 22 is formed on the molybdenum layer 21 as in the first embodiment. These laminated metal layers 21 and 22 become the second metal film for forming the source electrode 16 and the drain electrode 17.

  Next, as shown in FIG. 43, the photoresist applied and formed on the aluminum layer 22 is patterned by a photolithography process to form a resist pattern RM33 for forming the source electrode 16 and the drain electrode 17. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the aluminum layer 22 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 44, by performing a patterning process (third patterning process) on the molybdenum layer 21 and the aluminum layer 22 by a wet etching method using a PAN-based solution using the resist pattern RM33 as an etching mask. The source electrode 16 and the drain electrode 17 are obtained.

  Through the third patterning process, the central residual oxide semiconductor layer 44x is also patterned. That is, the target of the third patterning process is the molybdenum layer 21, the aluminum layer 22, and the central residual oxide semiconductor layer 44x (a part of the patterned first manufacturing semiconductor layer). As a result, oxide semiconductor layers 4 a and 4 b are obtained under the source electrode 16 and the drain electrode 17.

  Furthermore, the oxide semiconductor layers 8a and 8b already formed in the second patterning process are provided under the source electrode 16 and the drain electrode 17 in a manner to be separated from the oxide semiconductor layers 4a and 4b.

  That is, the oxide semiconductor layer 4a (one partial semiconductor layer) on the source electrode 16 side and the oxide semiconductor layer 4b (other partial semiconductor layer) on the drain electrode 17 side are separated and formed as a result. Thus, oxide semiconductor layers 4a and 4b and oxide semiconductor layers 8a and 8b are obtained.

  Thereafter, by performing the same steps as in the first embodiment (see FIGS. 17 to 20), the pixel TFT 30D shown in FIGS. 37 and 38 can be completed.

  Therefore, after the formation of the oxide semiconductor layer 5 by the fourth patterning process, the oxide semiconductor layers 8 a and 8 b are provided in a manner that does not contact the oxide semiconductor layer 5.

  In Embodiment 4, a process of providing the channel protective layer 6 over the oxide semiconductor layer 5 is added as in Embodiment 3, so that the channel protective layer 6 is provided over the oxide semiconductor layer 5. It is good to realize.

  Through the manufacturing steps described above, the pixel TFT 30D of Embodiment 4 having the oxide semiconductor layers 8a and 8b can be manufactured.

(effect)
In the oxide semiconductor TFT, when light enters the oxide semiconductor layers 4 and 5, the threshold voltage shifts and the reliability deteriorates. However, by having the oxide semiconductor layers 8a and 8b that are not connected to the oxide semiconductor layer 5 under the source electrode 16 and the drain electrode 17, the light of the backlight is reflected by the source electrode 16 and the drain electrode 17 and is oxidized. It can suppress entering into the physical semiconductor layer 4 and the oxide semiconductor layer 5. FIG.

  FIG. 45 is a graph showing reflectance spectral characteristics when an oxide semiconductor layer is formed on Mo. In the figure, the film thickness dependence curves L1 to L6 indicate the reflectance (%) with respect to the wavelength (nm) when the film thickness of the oxide semiconductor layer is 0 nm, 23 nm, 48 nm, 72 nm, 96 nm, and 148 nm.

  45 that the reflectance of a desired wavelength can be suppressed at the interface between the molybdenum layer 21 and the oxide semiconductor layer 8 by changing the thickness of the oxide semiconductor layer 8 (8a and 8b). For example, by setting the thickness of the oxide semiconductor layer 8 to 48 nm, the reflectance of light having a wavelength of 200 to 1000 nm can be kept relatively low.

  As described above, when light enters one of the oxide semiconductor layers 4 and 5 constituting the pixel TFT 30D, the threshold voltage may shift, and the reliability of the pixel TFT 30D may deteriorate.

  In the pixel TFT 30D of Embodiment 4, the oxide semiconductor layers 8a and 8b, the source electrode 16 and the drain electrode 17 (the molybdenum layer 21 thereof) are formed by changing the film thickness of the oxide semiconductor layer 8 (third semiconductor layer). ), The reflectance of a desired wavelength can be suppressed for incident light.

  Therefore, by having the oxide semiconductor layers 8 a and 8 b below the source electrode 16 and the drain electrode 17, the backlight light is reflected by the source electrode 16 and the drain electrode 17, and the oxide semiconductor layer 4 or the oxide semiconductor layer 5. Can be effectively suppressed and suppressed. As a result, the reliability of the pixel TFT 30D of the fourth embodiment can be improved.

  Note that the above-described reliability improvement effect can be achieved even when only one of the oxide semiconductor layers 8a and 8b is formed. In other words, the oxide semiconductor layer 8 is not connected to the oxide semiconductor layer 5 and is provided under at least one of the source electrode 16 and the drain electrode 17, whereby the above-described reliability improvement effect can be achieved. .

<Embodiment 5>
46 is a plan view showing the configuration of the pixel portion of the TFT substrate 100 having the pixel TFT 30E according to the fifth embodiment, and FIG. 47 is a cross-sectional configuration taken along the line CC in FIG. 46 (source wiring portion, TFT). FIG. 6 is a cross-sectional view illustrating a cross-sectional configuration of a portion and a transmissive pixel portion.

  In the following description, the TFT substrate 100 is described as being used in a TN liquid crystal display device, but may be used in an In-Plane Switching method and an FFS liquid crystal display device.

  As shown in the figure, a plurality of source lines 12 and a plurality of gate lines 13 (only two source lines 12 and two gate lines 13 are shown in FIG. 46) are provided in a matrix on a pixel substrate (not shown). It is done.

  A plurality of pixel TFTs 30E are provided corresponding to the intersections of the plurality of gate lines 13 and the plurality of source lines 12, and a plurality of pixel electrodes 15 are provided corresponding to the plurality of pixel TFTs 30E. That is, one unit of the pixel TFT 30 </ b> E and the pixel electrode 15 are formed in each pixel formation region provided between the two gate lines 13 and the two source lines 12.

  The corresponding gate wiring 13 and the gate electrode 2 of the pixel TFT 30E are electrically connected, the corresponding source wiring 12 and the source electrode 16 of the pixel TFT 30E are electrically connected, and the drain electrode 17 of each pixel TFT 30E The corresponding pixel electrode 15 is electrically connected.

  Note that the pixel TFT 30E of the fifth embodiment has substantially the same structure as the pixel TFT 30D of the fourth embodiment, except that the oxide semiconductor layers 8a and 8b are replaced with the oxide semiconductor layers 9x and 9y. Therefore, the following description will focus on the characteristic part of the pixel TFT 30E of the fifth embodiment.

  As shown in FIG. 47, the pixel TFT 30E is formed of, for example, glass or the like, is formed on the transparent insulating substrate 1 that functions as the pixel substrate, and the gate from the metal film 19 is formed on the transparent insulating substrate 1. An electrode 2 is formed.

  A gate insulating film 3 is formed on the entire surface of the transparent insulating substrate 1 so as to cover the gate electrode 2. On the gate insulating film 3, an oxide semiconductor layer 4 (first semiconductor layer) and an oxide semiconductor layer 9 (third semiconductor layer) made of the same constituent material are formed.

  The oxide semiconductor layer 4 is composed of oxide semiconductor layers 4a and 4b, and the oxide semiconductor layer 9 is composed of conductive oxide semiconductor layers 9x and 9y, and the oxide semiconductor layers 4a and 4b and oxide The semiconductor layers 9x and 9y are formed to be separated from each other.

  The oxide semiconductor layers 4a and 4b are connected to the oxide semiconductor layer 5 similarly to the pixel TFT 30 of the first embodiment, and the oxide semiconductor layers 9x and 9y (the semiconductor layer under the drain electrode and the semiconductor layer under the source electrode) are implemented. Similarly to the oxide semiconductor layers 8a and 8b of the fourth embodiment, the oxide semiconductor layers 5 are not connected but formed under the drain electrode 17 and the source electrode 16, respectively.

  Note that the source electrode 16 is formed to extend to the source wiring region R12 that functions as the source wiring 12, and the oxide semiconductor layer 9y is formed to extend below the source wiring region R12.

  A part of the pixel electrode region R15 of the oxide semiconductor layer 9x functions as the pixel electrode 15. That is, the pixel electrode 15 (pixel electrode region R15) of the pixel TFT 30E of Embodiment 5 is formed integrally with the oxide semiconductor layer 9x (semiconductor layer under the drain electrode) by using the same material as that of the oxide semiconductor layers 4 and 9. It is characterized by being.

  In other words, the oxide semiconductor layer 9x has a pixel electrode region R15 that functions as the pixel electrode 15.

  Here, when the TFT substrate 100 having the pixel TFT 30E is used in an In-Plane Switching type liquid crystal display device, the pixel electrode 15 preferably has a comb-like shape. The oxide semiconductor layers 9x and 9y desirably have a region overlapping with the gate electrode 2 in plan view.

  Then, the source electrode 16 and the drain electrode 17 are formed on the oxide semiconductor layer 4, the oxide semiconductor layer 9 (excluding the pixel electrode region R 15 of the oxide semiconductor layer 9 x), and the gate insulating film 3.

  The source electrode 16 is formed on the oxide semiconductor layer 4a and the oxide semiconductor layer 9y, and the drain electrode 17 is formed on the oxide semiconductor layer 4b and the oxide semiconductor layer 9x. Here, the oxide semiconductor layer 4 and the oxide semiconductor layer 9 (excluding the pixel electrode region R15) may have a region protruding from the source electrode 16 and the drain electrode 17 in plan view. Note that the pixel electrode region R15 of the oxide semiconductor layer 9x needs to function as the pixel electrode 15, and thus protrudes from the drain electrode 17 in plan view.

  The pixel electrode 15 (pixel electrode region R15) which is a part of the oxide semiconductor layer 9x is electrically connected to the oxide semiconductor layer 5 and the oxide semiconductor layer 4 through the drain electrode 17.

  Then, the oxide semiconductor layer 5 (second semiconductor layer) is formed on the source electrode 16 and the drain electrode 17 and on the gate insulating film 3 between the source electrode 16 and the drain electrode 17. Are connected to each other through the oxide semiconductor layer 5.

  When there is a region where the oxide semiconductor layer 4 protrudes from the source electrode 16 and the drain electrode 17 in plan view, the oxide semiconductor layer 5 is also formed on the protruded region. Here, the oxide semiconductor layer 5 is provided in a manner in contact with the oxide semiconductor layer 4 by forming the channel main region RC5 between the oxide semiconductor layer 4a and the oxide semiconductor layer 4b so as to be adjacent to each other.

  That is, the oxide semiconductor layer 4a under the source electrode 16 and the oxide semiconductor layer 4b under the drain electrode 17 are interposed via the oxide semiconductor layer 5 formed on the gate insulating film 3 between the oxide semiconductor layers 4a and 4b. Connected. In the oxide semiconductor layer 5, a region sandwiched between the source electrode 16 and the drain electrode 17 on the gate insulating film 3 becomes the channel main region RC5.

  Further, the protective insulating film 18 is formed over the pixel electrode region R15 of the oxide semiconductor layer 5, the source electrode 16, the drain electrode 17, the gate insulating film 3, and the oxide semiconductor layer 9x.

(Production method)
48 to 62 are cross-sectional views showing the processing procedure of the manufacturing process of the pixel TFT 30E of the fifth embodiment. Hereinafter, with reference to FIGS. 48 to 62, the processing content of the manufacturing method of the pixel TFT 30E of the fifth embodiment will be described. A cross-sectional view showing the final process corresponds to FIG.

  First, as shown in FIG. 48, a transparent insulating substrate 1 (pixel substrate) such as glass is prepared. Then, as shown in FIG. 49, a metal film 19 (first metal film) is formed on the entire surface of the transparent insulating substrate 1 as in the first embodiment.

  Next, as shown in FIG. 50, the photoresist applied and formed on the metal film 19 is patterned by a photolithography process to form a resist pattern RM41 in the same manner as the resist pattern RM1 of the first embodiment.

  Then, as shown in FIG. 51, a patterning process (first patterning process) is performed on the metal film 19 by a wet etching method using a PAN-based solution containing phosphoric acid, acetic acid, and nitric acid using the resist pattern RM1 as an etching mask. By performing this, the gate electrode 2 is formed on the transparent insulating substrate 1.

  Next, after stripping and removing the resist pattern RM1 using an amine-based resist stripping solution, as shown in FIG. 52, the transparent insulating substrate 1 is covered so as to cover the gate electrode 2 as in the first embodiment. A gate insulating film 3 is formed on the entire surface.

  Thereafter, as shown in FIG. 53, a manufacturing oxide semiconductor layer 45 (first manufacturing oxide semiconductor layer) is formed on the gate insulating film 3. In the present embodiment, as the manufacturing oxide semiconductor layer 45, the wet etching resistance during the third patterning process when forming the source electrode 16 and the drain electrode 17 is the same as the manufacturing oxide semiconductor layer 42 of the second embodiment. A certain oxide semiconductor is used as a constituent material.

  Further, the manufacturing oxide semiconductor layer 45 is made conductive by intentionally increasing the carrier density. As a method for making the oxide semiconductor layers 4 and 5 into conductors, for example, there are a method of reducing the oxygen partial pressure during DC sputtering, a method of irradiating ultraviolet rays after film formation, and the like.

  Next, as shown in FIG. 54, a photoresist applied and formed on the manufacturing oxide semiconductor layer 45 is patterned by a photolithography process to form a resist pattern RM42. As the photoresist, for example, a photoresist material composed of a novolac-based positive photosensitive resin is applied onto the manufacturing oxide semiconductor layer 45 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 55, by performing a patterning process (second patterning process) on the manufacturing oxide semiconductor layer 45 by wet etching using a solution containing nitric acid using the resist pattern RM42 as an etching mask. The oxide semiconductor layers 4a and 4b are formed so as to overlap the gate electrode 2 in plan view, and the oxide semiconductor layers 9x and 9y are formed so as to sandwich the gate electrode 2 in plan view.

  Here, the oxide semiconductor layer 4 (4a, 4b) may have a region protruding from the gate electrode 2 in plan view. Thus, as the oxide semiconductor layer 4 (first semiconductor layer) during the second patterning process, the source electrode 16 side oxide semiconductor layer 4a (one partial semiconductor layer) to be manufactured later, and the drain to be manufactured later The oxide semiconductor layer 4b (the other partial semiconductor layer) on the electrode 17 side is obtained separately. That is, in the fifth embodiment, an oxide that has been completed after the second patterning process is formed as a structure corresponding to the patterned semiconductor layer 41P of the first embodiment (patterned first manufacturing semiconductor layer). The semiconductor layer 4 and the oxide semiconductor layer 9 are obtained.

  The oxide semiconductor layers 4a and 4b and the oxide semiconductor layers 9x and 9y are formed separately from each other, and the oxide semiconductor layers 4a and 4b are to be connected to the oxide semiconductor layer 5 to be manufactured later. On the other hand, the oxide semiconductor layers 9x and 9y are not connected to the oxide semiconductor layer 5. The oxide semiconductor layer 9x is formed to extend to the pixel electrode region R15 (see FIGS. 46 and 47) so that part of the oxide semiconductor layer 9x functions as the pixel electrode 15, and the oxide semiconductor layer 9y is formed in the source wiring region R12. (Refer to FIG. 47) It is formed so as to extend below.

  Thereafter, the resist pattern RM42 is stripped and removed using an amine-based resist stripping solution.

  Next, a metal film for forming the source electrode 16 and the drain electrode 17 is formed. In this embodiment, the metal film for forming the source electrode 16 and the drain electrode 17 has a two-layer structure of, for example, molybdenum (Mo) and aluminum (Al).

  First, as illustrated in FIG. 56, the molybdenum layer 21 is formed so as to cover the oxide semiconductor layer 4, the oxide semiconductor layer 9, and the gate insulating film 3. For example, the molybdenum layer 21 is formed by DC sputtering using a Mo target.

  Next, as shown in FIG. 57, an aluminum layer 22 is formed on the molybdenum layer 21. For the film formation of Al, for example, an Al-3 mol% Ni film is formed by sputtering using an Al-3 mol% Ni alloy target. The film thicknesses of the molybdenum layer 21 and the aluminum layer 22 are each 10 to 100 nm, for example. These laminated metal layers 21 and 22 become the second metal film for forming the source electrode 16 and the drain electrode 17.

  Next, as shown in FIG. 58, the photoresist applied and formed on the aluminum layer 22 is patterned by a photolithography process to obtain a resist pattern RM43 for forming the source electrode 16 and the drain electrode 17. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the aluminum layer 22 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 59, by performing a patterning process (third patterning process) on the molybdenum layer 21 and the aluminum layer 22 by a wet etching method using a PAN-based solution using the resist pattern RM43 as an etching mask. The source electrode 16 and the drain electrode 17 are obtained. At this time, an opening 28 where the surface of the gate insulating film 3 is exposed is formed between the source electrode 16 and the drain electrode 17. Note that the source wiring region R12 that is a partial region of the source electrode 16 is a region that functions as the source wiring 12.

  Here, the oxide semiconductor layer 4 and the oxide semiconductor layer 9 are not patterned. That is, the objects of the third patterning process are the molybdenum layer 21 and the aluminum layer 22, and the oxide semiconductor layer 4 and the oxide semiconductor layer 9 corresponding to the patterned first semiconductor layer for manufacturing are the third patterning process. Not subject to processing.

  Next, as shown in FIG. 60, the source oxide 16, the drain electrode 17, the oxide semiconductor layer 4, the oxide semiconductor layer 9, and the manufacturing oxide semiconductor layer 51 (on the gate insulating film 3 in the opening 28). A second manufacturing oxide semiconductor layer) is formed. Note that the constituent material of the manufacturing oxide semiconductor layer 51 is the same as that in Embodiment 1.

  Next, as shown in FIG. 61, a photoresist applied and formed on the manufacturing oxide semiconductor layer 51 is patterned by a photolithography process while filling the opening 28 to obtain a resist pattern RM44. As the photoresist, for example, a photoresist material made of a novolac-based positive photosensitive resin is applied onto the manufacturing oxide semiconductor layer 51 by a coating method to have a thickness of about 1.5 μm.

  Then, as shown in FIG. 62, a patterning process (fourth patterning process) is performed on the manufacturing oxide semiconductor layer 51 by wet etching using a solution containing nitric acid using the resist pattern RM44 as an etching mask. The physical semiconductor layer 5 is obtained. Here, the oxide semiconductor layer 5 may have a region protruding from the gate electrode 2 in plan view. In addition, the carrier density of the oxide semiconductor layer 4 may be higher than that of the oxide semiconductor layer 5. Thereafter, the resist pattern RM44 is stripped and removed using an amine resist stripper.

  Next, a protective insulating film 18 is formed over the oxide semiconductor layer 5, the oxide semiconductor layer 9 (pixel electrode region R 15), the source electrode 16, the drain electrode 17, and the gate insulating film 3 in the same manner as in Embodiment 1. . Then, the pixel TFT 30E of the fifth embodiment shown in FIG. 47 is obtained.

  Note that in Embodiment 5, a process of providing the channel protective layer 6 over the oxide semiconductor layer 5 is added as in Embodiment 3, so that the channel protective layer 6 is provided over the oxide semiconductor layer 5. It is good to realize.

  Through the manufacturing steps described above, the pixel TFT 30E of Embodiment 5 including the conductive oxide semiconductor layers 9x and 9y can be manufactured.

(effect)
As described above, in the step of forming the oxide semiconductor layer 4 (4a and 4b) and the oxide semiconductor layer 9 (9x and 9y), the pixel electrode 15 is formed in the pixel electrode region R15 which is a part of the oxide semiconductor layer 9x. By forming, the number of photolithography steps for the TFT substrate 100 having the pixel TFT 30E of Embodiment 5 can be reduced.

  That is, in the TFT substrate 100 having the pixel TFT 30E, the pixel electrode 15 is made of the same material as that of the oxide semiconductor layer 4 and the oxide semiconductor layer 9, and the oxide semiconductor layer 9x (semiconductor under drain electrode) included in the oxide semiconductor layer 9 is used. Since the oxide semiconductor layer 9 (third semiconductor layer) is formed, the pixel electrode 15 can be formed together. As a result, the manufacturing process of the TFT substrate 100 having the pixel TFT 30E can be simplified, and the manufacturing cost of the TFT substrate 100 can be reduced.

  In addition, by forming the conductive oxide semiconductor layer 9y also under the source wiring region R12 (source wiring 12), the wiring resistance of the source wiring 12 can be reduced, and disconnection of the source wiring 12 can be suppressed.

  That is, the oxide semiconductor layer 9 (third semiconductor layer) in the pixel TFT 30E of Embodiment 5 is formed under the source electrode 16 and the source wiring region R12 (a part of the source wiring 12) and is made conductive. By having the physical semiconductor layer 9y (the semiconductor layer under the source electrode), the wiring resistance of the source wiring 12 can be reduced and the disconnection of the source wiring 12 can be suppressed.

  The source wiring 12 is formed at the time of forming the source electrode 16 (at the time of the third patterning process), and the gate wiring 13 is formed at the time of forming the gate electrode 2 (at the time of the first patterning process). Therefore, the oxide semiconductor layer 9y can be formed under the entire region of the source wiring 12 including the source wiring region R12.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  2 gate electrode, 3 gate insulating film, 4, 4a, 4b, 5, 8, 8a, 8b, 9, 9x, 9y oxide semiconductor layer, 6 channel protective layer, 12 source wiring, 13 gate wiring, 16 source electrode, 17 Drain electrode, 18 Protective insulating film, 21 Molybdenum layer, 30, 30B-30E Pixel TFT, 41, 42, 44, 45 Manufacturing oxide semiconductor layer, 61 Protective insulating film, 100 TFT substrate, 102 Color filter, 200 Liquid crystal display, T1-T3 NMOS transistors.

Claims (15)

A gate electrode formed on the substrate;
A gate insulating film formed to cover the gate electrode;
A first semiconductor layer formed in a region facing the gate electrode through the gate insulating film;
A source electrode and a drain electrode selectively formed on the gate insulating film, and a region on the gate insulating film between the source electrode and the drain electrode is a region facing the gate electrode; And at least one of the drain electrodes is further formed on the first semiconductor layer,
The semiconductor device further includes a second semiconductor layer formed at least in a region between the source electrode and the drain electrode on the gate insulating film, wherein the second semiconductor layer includes the source electrode, the drain electrode, and the first semiconductor. In contact with each layer,
A main channel region formed in a region between the source electrode and the drain electrode on the gate insulating film in the second semiconductor layer, and a part of the first semiconductor layer under the at least one electrode. A channel region is defined,
Thin film transistor. The thin film transistor according to claim 1,
At least one of the first semiconductor layer and the second semiconductor layer is formed of an oxide semiconductor;
Thin film transistor. The thin film transistor according to claim 1 or 2,
The first semiconductor layer includes one partial semiconductor layer and the other partial semiconductor layer that are separated from each other with the second semiconductor layer interposed therebetween,
The at least one electrode includes the source electrode and the drain electrode;
The source electrode is formed on the one partial semiconductor layer, and the drain electrode is formed on the other partial semiconductor layer;
Thin film transistor. The thin film transistor according to any one of claims 1 to 3,
A channel protective layer formed on the second semiconductor layer;
A protective insulating film formed on the channel protective layer;
Thin film transistor. The thin film transistor according to any one of claims 1 to 4,
The first semiconductor layer has a higher carrier density than the second semiconductor layer,
Thin film transistor. The thin film transistor according to any one of claims 1 to 5,
A third semiconductor layer formed of the same material as that of the first semiconductor layer, and provided on the gate insulating film independently of the first semiconductor layer;
The third semiconductor layer is provided under at least one of the source electrode and the drain electrode without being in contact with the second semiconductor layer.
Thin film transistor. A plurality of source wirings and a plurality of gate wirings arranged to cross each other on the pixel substrate;
A plurality of thin film transistors disposed at intersections of the gate wiring and the source wiring;
A plurality of pixel electrodes corresponding to the plurality of thin film transistors,
The plurality of thin film transistors are electrically connected to the corresponding pixel electrode and the drain electrode,
The plurality of thin film transistors each include the thin film transistor according to claim 6, wherein the source electrode and the gate electrode are electrically connected to the source wiring and the gate wiring, and the pixel substrate includes the substrate,
The third semiconductor layer includes a semiconductor layer under a drain electrode formed under the drain electrode,
The pixel electrode is integrally formed with the semiconductor layer under the drain electrode, using the same constituent material as the first and third semiconductor layers.
Thin film transistor substrate. The thin film transistor substrate according to claim 7,
The third semiconductor layer has conductivity,
The third semiconductor layer further includes a semiconductor layer under the source electrode formed under at least a part of the source electrode and the source wiring.
Thin film transistor substrate. A thin film transistor substrate comprising the thin film transistor according to any one of claims 1 to 6,
A counter substrate disposed opposite to the thin film transistor substrate, and a liquid crystal layer is sandwiched between the thin film transistor substrate and the counter substrate.
Liquid crystal display device. (a) after forming a first metal film on the substrate, obtaining a gate electrode by a first patterning process on the first metal film;
(b) forming a gate insulating film on the substrate covering the gate electrode;
(c) After forming the first manufacturing semiconductor layer on the gate insulating film, the second patterning process is performed on the first manufacturing semiconductor layer to form a patterned first region in a region facing the gate electrode. Obtaining a manufacturing semiconductor layer;
(d) After the step (c), the second metal film is formed on the gate insulating film so as to cover the patterned first manufacturing semiconductor layer, and then the second metal film is formed. Obtaining a source electrode and a drain electrode independent from each other by a third patterning process, and after the step (d), a region on the gate insulating film between the source electrode and the drain electrode is the gate electrode. The patterned first manufacturing semiconductor layer formed under at least one of the source electrode and the drain electrode becomes a first semiconductor layer,
(e) A second manufacturing semiconductor layer is formed on the gate insulating film while covering the source electrode and the drain electrode, and then a second patterning process is performed on the second manufacturing semiconductor layer. A step of obtaining a semiconductor layer, wherein the second semiconductor layer has a channel main region formed in a region facing the gate electrode between the source electrode and the drain electrode on the gate insulating film; Contacting each of the source electrode, the drain electrode and the first semiconductor layer;
A method of manufacturing a thin film transistor, wherein a channel region is defined by the channel main region and a part of the first semiconductor layer under the at least one electrode after the execution of the step (e). A method of manufacturing a thin film transistor according to claim 10,
The third patterning process executed in step (d) includes a patterning process for the second metal film and the patterned first manufacturing semiconductor layer.
A method for manufacturing a thin film transistor. A method of manufacturing a thin film transistor according to claim 10,
The patterned first manufacturing semiconductor layer is not patterned by the fourth patterning process in the step (d),
The patterned first manufacturing semiconductor layer after execution of step (c) includes the first semiconductor layer,
A method for manufacturing a thin film transistor. A method of manufacturing a thin film transistor according to any one of claims 10 to 12,
The step (e)
(e-1) After forming a second manufacturing semiconductor layer on the gate insulating film so as to cover the source electrode and the drain electrode, a protective film intermediate layer is further formed on the second manufacturing semiconductor layer. Forming a layer;
(e-2) obtaining a channel protective layer by a fifth patterning process on the protective film intermediate layer;
(e-3) including obtaining the second semiconductor layer by the fourth patterning process on the second manufacturing semiconductor layer using the channel protective layer as a mask,
A method for manufacturing a thin film transistor. A method of manufacturing a thin film transistor according to any one of claims 10 to 13,
The patterned first manufacturing semiconductor layer obtained after the execution of step (c) includes a third semiconductor layer in a part thereof,
After the execution of the step (d), the third semiconductor layer is provided in a manner to be separated from the first semiconductor layer under the at least one electrode,
After the execution of the step (e), the third semiconductor layer is provided in a mode that does not contact the second semiconductor layer.
A method for manufacturing a thin film transistor. A method of manufacturing a thin film transistor according to claim 14,
The third semiconductor layer includes a semiconductor layer under a drain electrode formed under the drain electrode,
The semiconductor layer under the drain electrode has a pixel electrode region that functions as a pixel electrode,
A method for manufacturing a thin film transistor.

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