JP2017085536A - Circuit device, oscillator, electronic equipment and mobile body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device, an oscillator, electronic equipment, a mobile body and the like, capable of suppressing generation of defects caused by frequency drift of an oscillation frequency and the like.SOLUTION: A circuit device includes: an A/D conversion part 20 that performs A/D conversion of a temperature detection voltage VTD from a temperature sensor part 10, and outputs temperature detection data DTD; a processing part 50 that performs temperature compensation processing of an oscillation frequency on the basis of the temperature detection data DTD, and outputs frequency control data DDS of the oscillation frequency; and an oscillation signal generation circuit 140 that generates an oscillation signal by using the frequency control data DDS and a vibrator XTAL. When a frequency variable range of the oscillation frequency is defined as FR, and an allowable frequency drift is defined as FD, and a full scale value of the frequency control data DDS is defined as DFS, and a change value of the frequency control data at an output interval of the frequency control data DDS of the processing part 50 is defined as DV, DV<(FD/FR)×DFS is satisfied.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a circuit device, an oscillator, an electronic device, a moving object, and the like.

  Conventionally, a temperature compensated oscillator called a TCXO (temperature compensated crystal oscillator) is known. This TCXO is used as a reference signal source or the like in, for example, a mobile communication terminal, a GPS related device, a wearable device, or an in-vehicle device.

  The TCXO includes an ATCXO that is an analog type temperature compensated oscillator and a DTCXO that is a digital type temperature compensated oscillator. As a conventional technique of ATCXO, a technique disclosed in Patent Document 1 is known. As a conventional technique of DTCXO, a technique disclosed in Patent Document 2 is known.

JP 2012-199631 A Japanese Unexamined Patent Publication No. 64-82809

  A digital oscillator such as DTCXO has an advantage in reducing power consumption and the like as compared with an analog oscillator such as ATCXO. For example, in ATCXO, a large amount of current consumption flows in the analog circuit of the circuit device. In particular, in ATCXO, in order to improve the frequency accuracy, increasing the order of the approximation function in the temperature compensation circuit (approximation function generation circuit) that is an analog circuit, or increasing the current flowing through the transistor of the analog circuit to reduce noise, Power consumption will increase significantly. For this reason, there is a problem that it is difficult to achieve both improvement in frequency accuracy and reduction in power consumption.

  On the other hand, in a digital oscillator such as DTCXO, if the frequency drift of the oscillation frequency accompanying a temperature change exceeds the range of the allowable frequency drift, for example, various problems occur in the device using the oscillation signal of the oscillator. It has been found.

  According to some aspects of the present invention, it is possible to provide a circuit device, an oscillator, an electronic device, a moving body, and the like that can suppress the occurrence of problems caused by frequency drift of the oscillation frequency.

  One embodiment of the present invention performs A / D conversion of a temperature detection voltage from a temperature sensor unit and outputs temperature detection data, and performs temperature compensation processing of an oscillation frequency based on the temperature detection data. And generating the oscillation signal of the oscillation frequency set by the frequency control data using the processing unit that outputs the frequency control data of the oscillation frequency, and the frequency control data and the vibrator from the processing unit. A frequency generation range of the oscillation frequency by the oscillation signal generation circuit as FR, an allowable frequency drift of the oscillation frequency within a predetermined period as FD, and a full-scale value of the frequency control data as DFS. When the change value of the frequency control data at the output interval of the frequency control data of the processing unit is DV, DV <(FD / R) × relating to the circuit device is a DFS.

  According to one aspect of the present invention, temperature compensation processing of the oscillation frequency is performed based on the temperature detection data, and an oscillation signal is generated using the obtained frequency control data and the vibrator. Here, it is assumed that the frequency variable range of the oscillation frequency is FR, the allowable frequency drift of the oscillation frequency is FD, the full scale value of the frequency control data is DFS, and the change value at the output interval of the frequency control data is DV. . Then, according to one aspect of the present invention, the frequency control data changes with a change value DV such that DV <(FD / FR) × DFS. By changing the frequency control data with such a change value DV, it becomes possible to keep the frequency drift of the oscillation frequency within a predetermined period, for example, within the allowable frequency drift. Therefore, it is possible to provide a circuit device or the like that can suppress the occurrence of problems caused by frequency drift of the oscillation frequency.

In one aspect of the present invention, when the output frequency of the frequency control data of the processing unit is fs and the change in the oscillation frequency due to the change in the change value DV of the frequency control data is Δf, Δf / fs <1/10 ⁶ may be sufficient.

In one aspect of the present invention, the output frequency fs of the frequency control data and the change Δf of the oscillation frequency due to the change in the change value DV of the frequency control data satisfy Δf / fs <1/10 ⁶ . As a result, it is also possible to suppress the deterioration of the C / N characteristics due to spurious due to the fluctuation of the frequency control data.

In one embodiment of the present invention, Δf / fs <1/10 ⁶ may be satisfied when fs ≧ 1 kHz, and Δf <1 mHz may be satisfied when fs <1 kHz.

  Thereby, in order to suppress the deterioration of the C / N characteristic, it is possible to use an appropriate condition according to fs.

  In one aspect of the present invention, when the output frequency of the frequency control data of the processing unit is fs and the change in the oscillation frequency due to the change in the change value DV of the frequency control data is Δf, fs <1 kHz In this case, Δf <1 mHz may be sufficient.

  In one aspect of the present invention, when the output frequency fs of the frequency control data and the change Δf of the oscillation frequency due to the change in the change value DV of the frequency control data satisfy fs <1 kHz, Δf <1 mHz is satisfied. As a result, it is also possible to suppress the deterioration of the C / N characteristics due to spurious due to the fluctuation of the frequency control data.

  In the aspect of the invention, the oscillation signal generation circuit includes a D / A conversion unit that performs D / A conversion of the frequency control data from the processing unit, an output voltage of the D / A conversion unit, and the vibration. An oscillation circuit that generates the oscillation signal using a child, fs corresponds to a sampling frequency of the D / A conversion unit, and Δf is a change in the oscillation frequency by one D / A conversion. It may be an amount.

  Thus, when the oscillation signal generation circuit has a D / A converter and an oscillation circuit, the sampling frequency of the D / A converter is fs, and the amount of change in the oscillation frequency by one D / A conversion is Δf. It becomes possible.

  In one aspect of the present invention, the D / A converter includes a D / A converter that performs D / A conversion of the frequency control data, and a filter circuit that smoothes an output voltage of the D / A converter. , May be included.

  As a result, the output of the D / A converter is smoothed by the filter circuit, so that substantial fluctuations in the oscillation frequency can be suppressed.

In one embodiment of the present invention, when the resolution of the D / A conversion unit is i bits, 1/2 ⁱ <(FD / FR) may be satisfied.

  As a result, the resolution of the D / A converter can be set to the number of bits that can suppress the occurrence of problems caused by frequency drift or the like.

  In the aspect of the invention, the D / A converter receives the frequency control data of i = (n + m) bits from the processing unit, and performs the frequency control based on the m-bit data of the frequency control data. A modulation circuit that modulates n-bit data may be included.

  As a result, a D / A converter having a high resolution of i = (n + m) bits can be realized by using a D / A converter having an n-bit resolution, for example, only by providing a modulation circuit or the like in the D / A converter. . Further, by increasing the resolution of the D / A converter that performs D / A conversion of the frequency control data in this way, it is possible to achieve high accuracy of the frequency accuracy of the oscillation signal generated based on the frequency control data. Further, the increase in power consumption by providing such a modulation circuit is not so great. It is not so difficult to supply, for example, i-bit frequency control data from the processing unit to the D / A conversion unit. Accordingly, it is possible to provide a circuit device or the like that can achieve both improvement in frequency accuracy and reduction in power consumption.

  In one embodiment of the present invention, the vibrator may be a crystal vibrator.

  Thereby, it is possible to use a crystal resonator as the resonator.

  In the aspect of the invention, the crystal resonator may be an AT cut resonator, an SC cut resonator, or a SAW (Surface Acoustic Wave) resonator.

  As a result, at least one of a plurality of vibrators (resonators) having different characteristics can be used as the crystal vibrator.

  In one embodiment of the present invention, the processing unit corresponds to the second temperature based on the first data corresponding to the first temperature when the temperature changes from the first temperature to the second temperature. The frequency control data that changes in units of k × LSB (k ≧ 1) may be output to the second data.

  Thus, even when the temperature changes from the first temperature to the second temperature, the first data corresponding to the first temperature changes to the second data corresponding to the second temperature, k × LSB. Frequency control data that changes in units is input to the oscillation signal generation circuit, and an oscillation signal is generated. Therefore, when the temperature changes from the first temperature to the second temperature, it is possible to suppress a situation in which the frequency control data changes greatly and a large frequency drift or the like occurs in the oscillation frequency.

  In the aspect of the invention, the processing unit may include the first data that is the calculation result data of the previous temperature compensation process and the second data that is the calculation result data of the current temperature compensation process. If the second data is larger than the first data, a process of adding a predetermined value to the first data is performed, and the addition result data is added to the second data. The addition result data is output as the frequency control data while performing the process until the second data is reached, and when the second data is smaller than the first data, a predetermined value is subtracted from the first data. The subtraction result data may be output as the frequency control data while performing subtraction until the subtraction result data reaches the second data.

  Thus, it is possible to change the frequency control data in units of k × LSB by performing a process of adding a predetermined value to the first data or a process of subtracting the predetermined value from the first data. become.

  In one aspect of the present invention, the processing unit performs an operation of the temperature compensation processing of the oscillation frequency based on the temperature detection data, and outputs an operation result data of the temperature compensation processing; and the operation An output unit that receives the calculation result data from a unit and outputs the frequency control data, the output unit including the first data corresponding to the first temperature from the first data. When the second data corresponding to the second temperature is changed, the frequency control data changing from the first data to the second data may be output in units of k × LSB.

  Thereby, the temperature compensation process of the oscillation frequency is realized by the calculation process in the calculation unit. When the calculation result data from the calculation unit changes from the first data to the second data, the output unit changes the frequency control data from the first data to the second data in units of k × LSB. Is output. Thus, when the temperature changes from the first temperature to the second temperature, the first data corresponding to the first temperature changes to the second data corresponding to the second temperature, k × Frequency control data that changes in units of LSBs can be output from the processing unit.

  Another aspect of the invention relates to an oscillator including any one of the circuit devices described above and the vibrator.

  Another aspect of the invention relates to an electronic device including any one of the circuit devices described above.

  Moreover, the other aspect of this invention is related with the moving body containing the circuit apparatus in any one of said.

The relationship between frequency accuracy and chip size. Diagram showing ATCXO frequency drift The figure which shows the frequency drift of the conventional DTCXO. 2 is a basic configuration example of a circuit device according to the present embodiment. 3 is a detailed configuration example of a circuit device according to the present embodiment. The figure which shows the example of the temperature characteristic of a vibrator | oscillator, and its variation. Explanatory drawing of the temperature compensation process of this embodiment. Explanatory drawing of the communication error which arises because of frequency drift. Explanatory drawing about the change of the frequency control voltage at the time of changing from 1st temperature to 2nd temperature. Explanatory drawing about the change of the frequency control voltage at the time of changing from 1st temperature to 2nd temperature. Explanatory drawing of the method of this embodiment. Explanatory drawing of the method of this embodiment. Explanatory drawing of the method of this embodiment. Explanatory drawing about frequency hopping. Explanatory drawing of the improvement of the frequency drift at the time of employ | adopting the method of this embodiment. Explanatory drawing of the relationship between the C / N characteristic of a vibrator | oscillator, and the spurious which deteriorates a C / N characteristic. The figure which shows the example of a characteristic of the spurious according to (DELTA) f and fs. The figure which shows the example of a setting of (DELTA) f and fs which does not deteriorate a C / N characteristic. Explanatory drawing of the method to change the setting of (DELTA) f and fs in time series. The detailed structural example of a process part. Explanatory drawing of the method of changing frequency control data per kxLSB. Explanatory drawing of the method of changing frequency control data per kxLSB. 3 is a detailed configuration example of a D / A conversion unit. The detailed example of a structure of a D / A conversion part. Explanatory drawing of PWM modulation. Explanatory drawing of PWM modulation. Explanatory drawing of PWM modulation. The detailed structural example of a temperature sensor part. The detailed structural example of a temperature sensor part. Explanatory drawing of a temperature sensor part. The detailed structural example of an oscillation circuit. Explanatory drawing of the modification of this embodiment. Explanatory drawing of the modification of this embodiment. Explanatory drawing of the modification of this embodiment. The figure which shows the frequency drift in a modification. The figure which shows the frequency drift in a modification. The figure which shows the frequency drift in a modification. 3 is a detailed configuration example of an A / D conversion unit. The structural example of the circuit apparatus of the modification of this embodiment. Configuration example of an oscillator. Configuration example of an electronic device. Configuration example of a moving body.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Frequency drift TCXO, which is a temperature compensated oscillator, has demands for improved frequency accuracy and lower power consumption. For example, in a wearable device such as a GPS built-in clock or a device for measuring biological information such as a pulse wave, it is necessary to lengthen the operation duration of the battery. For this reason, TCXO serving as a reference signal source is required to have lower power consumption while ensuring frequency accuracy.

  Various systems have been proposed as a communication system between a communication terminal and a base station. For example, in the TDD (Time Division Duplex) method, each device transmits data in an assigned time slot. By setting a guard time between time slots (uplink slot, downlink slot), it is possible to prevent time slots from overlapping. In the next generation communication system, for example, it is proposed to perform data communication by the TDD method using one frequency band (for example, 50 GHz).

  However, when such a TDD method is adopted, it is necessary to perform time synchronization in each device, and accurate time measurement is required. In order to realize such a request, for example, a method of providing each device with an atomic clock (atomic oscillator) as a reference signal source is conceivable. However, the cost of the device is increased or the size of the device is increased. Occurs.

  The TCXO includes an ATCXO which is an analog type temperature compensated oscillator and a DTCXO which is a digital type temperature compensated oscillator.

  If the ATCXO is used as the reference signal source and the frequency accuracy is to be increased, the chip size of the circuit device increases as shown in FIG. 1, which realizes cost reduction and power consumption reduction. It becomes difficult.

  On the other hand, as shown in FIG. 1, DTCXO has an advantage that it is possible to achieve high frequency accuracy without increasing the chip size of the circuit device so much.

  However, a digital oscillator such as DTCXO has a problem that a communication error or the like occurs in a communication device in which the oscillator is incorporated due to a frequency drift of the oscillation frequency. For example, in a digital oscillator, the temperature detection voltage from the temperature sensor unit is A / D converted, temperature compensation processing of frequency control data is performed based on the obtained temperature detection data, and an oscillation signal is generated based on the frequency control data. Is generated. In this case, it has been found that if the value of the frequency control data changes greatly due to temperature change, this causes a problem of frequency hopping. When such frequency hopping occurs, if a GPS-related communication device is taken as an example, problems such as the GPS being unlocked will occur.

  For this reason, although various circuit systems have been proposed for digital oscillators such as DTCXO, digital oscillators are mostly used as reference signal sources for actual products in which such communication errors are a problem. First of all, an analog oscillator such as ATCXO is used.

  For example, FIG. 2 is a diagram showing the frequency drift of ATCXO. In ATCXO, even when the temperature changes with time as shown in FIG. 2, the frequency drift is within the range of allowable frequency drift (allowable frequency error) (± FD). In FIG. 2, the frequency drift (frequency error) is shown as a ratio (frequency accuracy, ppb) to the nominal oscillation frequency (for example, about 16 MHz). For example, in order to prevent a communication error from occurring, it is necessary to keep the frequency drift within the allowable frequency drift range (± FD) within a predetermined period TP (for example, 20 msec). Here, FD is, for example, about several ppb.

  On the other hand, FIG. 3 is a diagram showing frequency drift when a conventional DTCXO is used. As shown in FIG. 3, in the conventional DTCXO, the frequency drift is not within the allowable frequency drift range, and frequency hopping that exceeds the range occurs. For this reason, a communication error (such as GPS lock-out) due to this frequency hopping occurs, which hinders the use of DTCXO as a reference signal source for actual products.

  Further, it is known that an oscillator generates phase noise corresponding to the characteristics of the vibrator. D1 in FIG. 16 to be described later is an example of a general C / N characteristic of the crystal resonator, and the intensity of the phase noise (vertical axis, unit dBc / Hz) is a detuning frequency (horizontal axis, unit Hz) with respect to the oscillation frequency. ) Is low, it is inversely proportional to the cube of the detuning frequency f, and in the range of about 1 k to 10 kHz, it is inversely proportional to the square of f. In the frequency range of 10 kHz or less, the effect of so-called 1 / f noise is large. On the other hand, at a frequency higher than 10 kHz, the influence of thermal noise is large, and the flat characteristic does not depend on f. That is, the generation of a signal having a frequency other than the desired oscillation frequency is unavoidable due to the characteristics of the vibrator, and an oscillator (and a circuit device including the oscillator) such as DTCXO has a C / N characteristic like D1. A design is made so that there is no problem even if phase noise occurs.

However, in DTCXO, spurious with an intensity corresponding to the output frequency fs of the data (frequency control data DDS) for controlling the oscillation frequency and the change Δf of the oscillation frequency is generated. The details will be described later using the following equation (10) and the like, but the generated spurious has a detuning frequency of fs with respect to the fundamental wave (oscillation frequency) and an intensity corresponding to (Δf / fs) ² . Depending on the values of fs and Δf, there is a possibility that a spurious intensity that is larger than the original phase noise of the oscillator shown in D1 may occur. D2 in FIG. 16 is an example of spurious when Δf = 0.1 Hz and fs = 100 kHz, and D3 is an example of spurious when Δf = 0.1 Hz and fs = 600 kHz. Both the spurs D2 and D3 have higher strength than the phase noise (D1) inherent to the oscillator.

  When spurious as shown in D2 and D3 occurs, the signal intensity at a frequency different from the desired oscillation frequency becomes relatively large, and the C / N characteristic of the oscillator 400 is deteriorated. The deterioration of the C / N characteristic leads to a decrease in accuracy of data acquired using the oscillation signal. For example, in the case of the GPS described above, the accuracy of the GPS reception signal is lowered, and specifically, the accuracy of the position information obtained from the GPS reception signal is lowered. As described above, the occurrence of spurious according to the frequency fluctuation is also an obstacle to adopting DTCXO as a reference signal source of an actual product. Note that the spurious shown in D2 and D3 in FIG. 16 deteriorates the C / N characteristics when the strength is not reduced. Therefore, if noise reduction processing that reduces the spurious intensity, such as smoothing by a filter circuit, is performed, it is prevented from adopting the values of Δf and fs corresponding to D2 and D3 in the method of this embodiment. Absent. Details will be described later.

2. Configuration FIG. 4 shows a basic configuration example of the circuit device according to the present embodiment. This circuit device is a circuit device (semiconductor chip) that realizes a digital oscillator such as DTCXO or OCXO. For example, a digital oscillator is realized by housing the circuit device and the vibrator XTAL in a package.

  The circuit device of FIG. 4 includes an A / D conversion unit 20, a processing unit 50, and an oscillation signal generation circuit 140. The circuit device may include the temperature sensor unit 10 and the buffer circuit 160. The configuration of the circuit device is not limited to the configuration shown in FIG. 4, and some of the components (for example, a temperature sensor unit, a buffer circuit, an A / D conversion unit, etc.) are omitted or other components are added. Various modifications such as these are possible.

  The vibrator XTAL is a piezoelectric vibrator such as a quartz vibrator. The vibrator XTAL may be an oven-type vibrator (OCXO) provided in a constant temperature bath. The resonator XTAL may be a resonator (an electromechanical resonator or an electrical resonance circuit). As the vibrator XTAL, a piezoelectric vibrator, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator, or the like can be used. As a substrate material of the vibrator XTAL, a piezoelectric single crystal such as crystal, lithium tantalate, and lithium niobate, a piezoelectric material such as piezoelectric ceramics such as lead zirconate titanate, or a silicon semiconductor material can be used. As the excitation means of the vibrator XTAL, one using a piezoelectric effect may be used, or electrostatic driving using Coulomb force may be used.

  The temperature sensor unit 10 outputs a temperature detection voltage VTD. Specifically, a temperature-dependent voltage that changes according to the temperature of the environment (circuit device) is output as the temperature detection voltage VTD. A specific configuration example of the temperature sensor unit 10 will be described later.

  The A / D conversion unit 20 performs A / D conversion of the temperature detection voltage VTD from the temperature sensor unit 10 and outputs temperature detection data DTD. For example, digital temperature detection data DTD (A / D result data) corresponding to the A / D conversion result of the temperature detection voltage VTD is output. As the A / D conversion method of the A / D conversion unit 20, for example, a successive approximation method, a method similar to the successive approximation method, or the like can be adopted. The A / D conversion method is not limited to such a method, and various methods (counting type, parallel comparison type, serial parallel type, etc.) can be adopted.

  The processing unit 50 (DSP unit: digital signal processing unit) performs various signal processing. For example, the processing unit 50 (temperature compensation unit) performs temperature compensation processing of the oscillation frequency (frequency of the oscillation signal) based on the temperature detection data DTD. Then, frequency control data DDS of the oscillation frequency is output. Specifically, the processing unit 50 has a temperature change based on temperature detection data DTD (temperature-dependent data) that changes according to temperature, coefficient data for temperature compensation processing (coefficient data of an approximate function), and the like. In this case, temperature compensation processing is performed to keep the oscillation frequency constant. The processing unit 50 may be realized by an ASIC circuit such as a gate array, or may be realized by a processor and a program operating on the processor.

  The oscillation signal generation circuit 140 generates an oscillation signal SSC. For example, the oscillation signal generation circuit 140 generates the oscillation signal SSC having the oscillation frequency set by the frequency control data DDS, using the frequency control data DDS from the processing unit 50 and the vibrator XTAL. As an example, the oscillation signal generation circuit 140 oscillates the vibrator XTAL at the oscillation frequency set by the frequency control data DDS, and generates the oscillation signal SSC.

  The oscillation signal generation circuit 140 may be a circuit that generates the oscillation signal SSC by a direct digital synthesizer method. For example, the oscillation signal SSC having the oscillation frequency set by the frequency control data DDS may be digitally generated using the oscillation signal of the vibrator XTAL (an oscillation source having a fixed oscillation frequency) as a reference signal.

  The oscillation signal generation circuit 140 can include a D / A conversion unit 80 and an oscillation circuit 150. However, the oscillation signal generation circuit 140 is not limited to such a configuration, and various modifications may be made such as omitting some of the components or adding other components.

  The D / A conversion unit 80 performs D / A conversion of the frequency control data DDS (output data of the processing unit) from the processing unit 50. The frequency control data DDS input to the D / A conversion unit 80 is frequency control data (frequency control code) after the temperature compensation processing by the processing unit 50. As the D / A conversion method of the D / A conversion unit 80, for example, a resistance string type (resistance division type) can be adopted. However, the D / A conversion method is not limited to this, and various methods such as a resistance ladder type (R-2R ladder type, etc.), a capacitance array type, and a pulse width modulation type can be adopted. Further, the D / A converter 80 can include a control circuit, a modulation circuit, a filter circuit, and the like in addition to the D / A converter.

  The oscillation circuit 150 generates an oscillation signal SSC using the output voltage VQ of the D / A conversion unit 80 and the vibrator XTAL. The oscillation circuit 150 is connected to the vibrator XTAL via the first and second vibrator terminals (vibrator pads). For example, the oscillation circuit 150 generates an oscillation signal SSC by oscillating a vibrator XTAL (a piezoelectric vibrator, a resonator, or the like). Specifically, the oscillation circuit 150 oscillates the vibrator XTAL at an oscillation frequency with the output voltage VQ of the D / A converter 80 as a frequency control voltage (oscillation control voltage). For example, when the oscillation circuit 150 is a circuit (VCO) that controls the oscillation of the vibrator XTAL by voltage control, the oscillation circuit 150 has a variable capacitance capacitor (varicap or the like) whose capacitance value changes according to the frequency control voltage. ) Can be included.

  As described above, the oscillation circuit 150 may be realized by a direct digital synthesizer system. In this case, the oscillation frequency of the vibrator XTAL becomes a reference frequency, and is different from the oscillation frequency of the oscillation signal SSC. .

  The buffer circuit 160 buffers the oscillation signal SSC generated by the oscillation signal generation circuit 140 (oscillation circuit 150), and outputs a buffered signal SQ. That is, buffering is performed so that an external load can be sufficiently driven. The signal SQ is, for example, a clipped sine wave signal. However, the signal SQ may be a rectangular wave signal. Alternatively, the buffer circuit 160 may be a circuit that can output both a clipped sine wave signal and a rectangular wave signal as the signal SQ.

  FIG. 5 shows a detailed configuration example of the circuit device of this embodiment. In FIG. 5, the D / A converter 80 includes a modulation circuit 90, a D / A converter 100, and a filter circuit 120.

  The modulation circuit 90 of the D / A conversion unit 80 receives the frequency control data DDS of i = (n + m) bits from the processing unit 50 (i, n, m are integers of 1 or more). As an example, i = 20, n = 16, and m = 4. The modulation circuit 90 modulates n-bit (eg, 16 bits) data of the frequency control data DDS based on m-bit (eg, 4 bits) data of the frequency control data DDS. Specifically, the modulation circuit 90 performs PWM modulation of the frequency control data DDS. The modulation method of the modulation circuit 90 is not limited to PWM modulation (pulse width modulation), and may be pulse modulation such as PDM modulation (pulse density modulation), or may be a modulation method other than pulse modulation. . For example, bit expansion (bit expansion from n bits to i bits) may be realized by performing m-bit dither processing (dithering processing) on n-bit data of the frequency control data DDS.

  The D / A converter 100 performs D / A conversion of the n-bit data modulated by the modulation circuit 90. For example, D / A conversion of n = 16 bit data is performed. As a D / A conversion method of the D / A converter 100, for example, a resistance string type or a resistance ladder type can be adopted.

  The filter circuit 120 smoothes the output voltage VDA of the D / A converter 100. For example, low-pass filter processing is performed to smooth the output voltage VDA. By providing such a filter circuit 120, for example, PWM demodulation of a PWM-modulated signal becomes possible. The cut-off frequency of the filter circuit 120 can be set according to the PWM modulation frequency of the modulation circuit 90. That is, since the signal of the output voltage VDA from the D / A converter 100 includes a ripple of the fundamental frequency and harmonic component of PWM modulation, the filter circuit 120 attenuates this ripple. As the filter circuit 120, for example, a passive filter using a passive element such as a resistor or a capacitor can be employed. However, it is also possible to use an active filter such as SCF as the filter circuit 120.

  As will be described later, in order to suppress the occurrence of the communication error caused by the frequency hopping described in FIG. 3 and improve the frequency accuracy, it is necessary to increase the resolution of the D / A converter 80 as much as possible. .

  However, it is difficult to realize high-resolution D / A conversion such as i = 20 bits, for example, using only the D / A converter 100 such as a resistor string type. Further, if the output noise of the D / A converter 80 is large, it is difficult to realize improvement in frequency accuracy due to the noise.

  Therefore, in FIG. 5, a modulation circuit 90 is provided in the D / A conversion unit 80. Further, the processing unit 50 outputs the frequency control data DDS of i = m + n bits having a larger number of bits than n bits (for example, 16 bits) which is the resolution of the D / A converter 100. Since the processing unit 50 performs floating point arithmetic operation or the like in order to realize digital signal processing such as temperature compensation processing, for example, i = has a larger number of bits than such n bits (for example, n = 16 bits). It is easy to output m + n-bit frequency control data DDS.

  The modulation circuit 90 modulates n-bit data (i.e., PWM modulation) of i = m + n based on m-bit data of i = m + n, and converts the modulated n-bit data DM to D / A converter 100 to output. Then, the D / A converter 100 performs D / A conversion of the data DM, and the filter circuit 120 performs smoothing processing of the obtained output voltage VDA, so that i = m + n bits (for example, 20 bits) is high. Resolution D / A conversion can be realized.

  According to this configuration, for example, a resistor string type with little output noise can be adopted as the D / A converter 100, so that the output noise of the D / A converter 80 can be reduced and the deterioration of frequency accuracy can be easily suppressed. . For example, noise is generated by modulation in the modulation circuit 90, but the noise can also be sufficiently attenuated by setting the cutoff frequency of the filter circuit 120, and deterioration of frequency accuracy caused by the noise can be suppressed. .

  The resolution of the D / A converter 80 is not limited to i = 20 bits, and may be a resolution higher than 20 bits or a lower resolution. Also, the number of bits of modulation of the modulation circuit 90 is not limited to m = 4 bits, and may be larger than 4 bits (for example, m = 8 bits) or smaller.

  In FIG. 5, the fact that the processing unit 50 that performs digital signal processing such as temperature compensation processing is provided upstream of the D / A conversion unit 80 is effectively utilized. That is, the processing unit 50 performs digital signal processing such as temperature compensation processing with high accuracy by, for example, floating point arithmetic. Therefore, for example, if the lower-order bits of the mantissa part of the floating-point arithmetic result are treated as valid data and converted into binary data, the frequency control data DDS with a high bit number such as i = m + n = 20 bits is also obtained. Can output easily. In FIG. 5, focusing on this point, i = m + n-bit frequency control data DDS having such a high number of bits is supplied to the D / A converter 80, and the m-bit modulation circuit 90 and the n-bit D / D are supplied. Using the A converter 100, a high-resolution D / A conversion such as i = m + n bits has been successfully realized.

  Thus, by making the resolution of the D / A converter 80 high, occurrence of the above-described frequency hopping can be suppressed. As a result, it is possible to suppress the occurrence of communication errors caused by frequency hopping.

  In addition to the problem of frequency hopping, a digital oscillator such as DTCXO or OCXO requires very high frequency accuracy with respect to the oscillation frequency. For example, in the above-described TDD system, data is transmitted and received in time division using the same frequency in the upward and downward directions, and a guard time is set between time slots assigned to each device. For this reason, in order to implement | achieve appropriate communication, it is necessary to perform time synchronization in each apparatus, and exact time-measurement of an absolute time is requested | required. For example, when a holdover occurs in which a reference signal (a GPS signal or a signal via the Internet) disappears or becomes abnormal, it is necessary for the oscillator side to accurately time the absolute time without the reference signal. For this reason, an oscillator used for such devices (GPS-related devices, base stations, etc.) is required to have a very high oscillation frequency accuracy.

  In order to realize such a requirement, for example, when a method of providing an atomic clock or the like in each device is adopted, the cost of the device is increased and the scale is increased. Even if an oscillator with high frequency accuracy is realized, it is not desirable that the circuit device used for the oscillator becomes large-scale or that power consumption becomes very large.

  In this regard, according to the configuration of the circuit device of FIG. 5, the D / A converter 80 is provided only with the modulation circuit 90 and the filter circuit 120. Since the A conversion unit 80 can be realized and the resolution becomes high in this way, it is possible to improve the accuracy of the oscillation frequency. The increase in the chip size and the power consumption of the circuit device due to the provision of the modulation circuit 90 and the filter circuit 120 are not so great. Furthermore, since the processing unit 50 performs the temperature compensation processing by floating point decimal point calculation or the like, it is easy to output the frequency control data DDS such that, for example, i ≧ 20 bits to the D / A conversion unit 80. Therefore, the configuration of the circuit device in FIG. 5 has an advantage that it is possible to achieve both the high accuracy of the oscillation frequency and the suppression of the increase in the size and power consumption of the circuit device.

  4 and 5 can also be used as an oscillation IC in a PLL circuit having a phase comparison circuit that compares an input signal based on a reference signal (a GPS signal or a signal via the Internet) and an oscillation signal. it can. In this case, for example, the processing unit 50 may perform a temperature compensation process, an aging correction process, or the like on the frequency control data from the phase comparison circuit, and the oscillation signal generation circuit 140 may generate an oscillation signal.

In addition, when the temperature changes from the first temperature to the second temperature, the processing unit 50 calculates the second temperature (first temperature) from the first data corresponding to the first temperature (first temperature detection data). Frequency control data DDS that changes in units of k × LSB (changes by k × LSB) is output to second data corresponding to (temperature detection data of 2). Here, k ≧ 1, and k is an integer of 1 or more. For example, when i is the number of bits of the frequency control data DDS (the resolution of the D / A converter), k <2 ⁱ and k is an integer sufficiently smaller than 2 ⁱ (for example, k = 1 to 8). ). More specifically, k <2 ^m . For example, when k = 1, the processing unit 50 outputs the frequency control data DDS that changes from the first data to the second data in 1 LSB units (1 bit unit). That is, the frequency control data DDS that changes while shifting by 1 LSB (1 bit) from the first data to the second data is output. The change step width of the frequency control data DDS is not limited to 1 LSB, and may be a change step width of 2 × LSB or more, for example, 2 × LSB, 3 × LSB, 4 × LSB,.

  For example, the processing unit 50 includes a calculation unit 60 and an output unit 70. The calculation unit 60 calculates a temperature compensation process for the oscillation frequency based on the temperature detection data DTD. For example, temperature compensation processing is realized by digital signal processing such as floating point arithmetic. The output unit 70 receives the calculation result data CQ from the calculation unit 60 and outputs the frequency control data DDS. When the output unit 70 changes the calculation result data CQ from the first data corresponding to the first temperature to the second data corresponding to the second temperature, the output unit 70 outputs the first in k × LSB units. The output processing of the frequency control data DDS that changes from the first data to the second data is performed.

  Thus, if the frequency control data DDS output from the processing unit 50 changes by k × LSB, for example, when the temperature changes from the first temperature to the second temperature, the D / A conversion is performed. A large voltage change occurs in the output voltage VQ of the unit 80, and the situation where the frequency hopping of FIG. 3 occurs due to this voltage change can be suppressed. As a result, it is possible to prevent a communication error or the like from occurring due to the frequency hopping.

  More specifically, the processing unit 50 includes the first data which is the calculation result data (CQ) of the previous temperature compensation process and the calculation result data of the temperature compensation process of this time (current timing). Some second data is compared.

  Then, when the second data is larger than the first data, the processing unit 50 (output unit 70) performs a process of adding a predetermined value to the first data. For example, a process of adding k × LSB as a predetermined value is performed. For example, when k = 1, a process of adding 1LSB as a predetermined value is performed. The predetermined value to be added is not limited to 1 LSB, and may be 2 × LSB or more. Then, the processing unit 50 outputs the addition result data as the frequency control data DDS, for example, while performing this addition processing until the addition result data reaches the second data.

  On the other hand, when the second data corresponding to the second temperature is smaller than the first data corresponding to the first temperature, the processing unit 50 (the output unit 70) starts from the first data. A process of subtracting a predetermined value is performed. For example, a process of subtracting k × LSB as a predetermined value is performed. For example, when k = 1, a process of subtracting 1LSB as a predetermined value is performed. The predetermined value to be subtracted is not limited to 1 LSB, and may be 2 × LSB or more. Then, the processing unit 50 outputs the subtraction result data as the frequency control data DDS, for example, while performing this subtraction processing until the subtraction result data reaches the second data.

  As described above, if a process of adding a predetermined value to the first data or subtracting the predetermined value from the first data is performed, if the frequency control data DDS is output, the calculation result data of the temperature compensation process is obtained. When the first data corresponding to the first temperature is changed to the second data corresponding to the second temperature, for example, the first data is changed to the second data in units of k × LSB corresponding to the predetermined value. It is possible to output changing frequency control data DDS.

  Further, in the first mode (normal mode), the processing unit 50 (output unit 70) performs output processing of the frequency control data DDS that changes in units of k × LSB. Thereby, generation | occurrence | production of the communication error etc. resulting from a frequency hopping can be suppressed.

  On the other hand, in the second mode (high-speed mode), the processing unit 50 outputs the calculation result data of the temperature compensation process as the frequency control data DDS without performing the output process of the frequency control data DDS that changes in units of k × LSB. To do. Specifically, the calculation result data CQ from the calculation unit 60 is output as the frequency control data DDS. By doing so, the frequency control data DDS that changes at a higher speed than in the first mode can be supplied to the D / A converter 80, and the high-speed mode can be realized.

  The first mode is set during the normal operation (normal operation period) of the circuit device. On the other hand, the second mode is set, for example, when the circuit device is activated (activation period) or at the time of inspection (test period). In other words, the circuit device is set to the second mode during an operation other than the normal operation.

  For example, during the normal operation of the circuit device, by setting the first mode, the processing unit 50 outputs the frequency control data DDS that changes in units of k × LSB. As a result, problems such as frequency hopping can be prevented, and the accuracy of the oscillation frequency can be improved.

  On the other hand, when the circuit device is activated or inspected, the second mode is set so that the process of changing the frequency control data DDS in units of k × LSB is not performed, and the calculation result data from the calculation unit 60 CQ is output as frequency control data DDS as it is. As a result, the startup time of the circuit device can be shortened, and the circuit device can be started up at high speed. Further, the inspection period (test period) at the time of manufacturing circuit devices and oscillators can be shortened, and the manufacturing period can be shortened.

  In the present embodiment, the processing unit 50 outputs the frequency control data DDS at an output rate faster than the output rate of the temperature detection data DTD from the A / D conversion unit 20. By doing so, it becomes possible to output the frequency control data DDS that changes from the first data to the second data in units of k × LSB. For example, the frequency control data DDS can be changed step by step by k × LSB within a period corresponding to the A / D conversion period.

  FIG. 6 is a diagram illustrating an example of the frequency deviation of the oscillation frequency depending on the temperature of the vibrator XTAL (such as an AT vibrator). The processing unit 50 performs temperature compensation processing for making the oscillation frequency of the vibrator XTAL having temperature characteristics as shown in FIG. 6 constant without depending on the temperature.

  Specifically, in the processing unit 50, the output data (temperature detection data) of the A / D conversion unit 20 and the input data (frequency control data) of the D / A conversion unit 80 have a correspondence relationship as shown in FIG. Such temperature compensation processing is executed. The correspondence relationship (frequency correction table) in FIG. 7 is that, for example, an oscillator in which a circuit device is incorporated is placed in a constant temperature bath, and the input data (DDS) of the D / A converter 80 at each temperature and the A / D converter 20 It can be obtained by a method such as monitoring output data (DTD).

  Then, coefficient data of an approximate function for temperature compensation for realizing the correspondence relationship of FIG. 7 is stored in a memory unit (nonvolatile memory) of the circuit device. Then, the processing unit 50 performs an arithmetic process based on the coefficient data read from the memory unit and the temperature detection data DTD from the A / D conversion unit 20, thereby setting the oscillation frequency of the vibrator XTAL to the temperature. A temperature compensation process is made to make it constant without depending on it.

  The temperature detection voltage VTD of the temperature sensor unit 10 has, for example, a negative temperature characteristic as will be described later. Therefore, the temperature compensation characteristic as shown in FIG. 7 can be compensated by canceling the temperature dependence of the oscillation frequency of the vibrator XTAL in FIG.

3. Next, the details of the method of this embodiment will be described. First, a GPS (Global Positioning System) communication error that occurs due to frequency hopping will be described with reference to FIG. Further, the C / N characteristic and spurious of the oscillator 400 will be described with reference to FIGS.

3.1 Frequency Hopping GPS satellites include information on satellite orbits and times in the navigation message of FIG. 8 and are transmitted as GPS satellite signals at a data rate of 50 bps. For this reason, the length of 1 bit is 20 msec (20 periods of the PN code). One navigation message is composed of one master frame, and one master frame is composed of 25 frames of 1500 bits.

  The GPS satellite signal is modulated by the BPSK modulation method according to the bit value of the navigation message as shown in FIG. Specifically, the navigation message is multiplied by a PN code (pseudorandom code) to perform spread spectrum, and the signal after spread spectrum is multiplied by a carrier wave (1575.42 MHz), thereby performing BPSK modulation. Is called. In FIG. 8, the PN code of the B1 part of the navigation message is shown, and the carrier wave of the B2 part of the PN code is shown. At the timing when the logic level of the PN code changes, the carrier wave undergoes phase inversion as indicated by B3. The period of one wavelength of the carrier wave is about 0.635 ns. The GPS receiver receives the navigation message carrier modulated by the BPSK modulation method, and acquires the navigation message by performing demodulation processing on the received signal of the carrier.

  When such a received signal is demodulated, if the residual frequency with the carrier frequency (1575.42 MHz) does not fall within 4 Hz / 20 msec, an erroneous determination occurs in the demodulation process. That is, if TP = 20 msec, which is a 1-bit length period of the GPS navigation message (GPS navigation message period), if the residual frequency with the carrier frequency is not within 4 Hz, a communication error due to frequency hopping occurs. .

  Since the ratio of the above 4 Hz to the carrier frequency of 1575.42 MHz is about several ppb, the allowable drift frequency FD shown in FIGS. 2 and 3 is also about several ppb.

  For example, in a GPS receiver, the frequency of a carrier wave in demodulation processing is set by an oscillation signal generated by the circuit device (oscillator) of this embodiment. For this reason, it is necessary to keep the frequency drift of the oscillation frequency of the oscillation signal within ± FD at TP = 20 msec. By doing so, it is possible to prevent erroneous determination in the demodulation processing of the received signal of the GPS satellite signal, and to avoid the occurrence of a communication error (reception error).

  However, a conventional digital oscillator such as DTCXO does not suppress the frequency drift within ± FD (about several ppb) in the period TP (20 msec). For this reason, there has been a problem that a communication error due to an erroneous determination of demodulation processing occurs due to frequency hopping as shown in FIG.

  Therefore, in this embodiment, the frequency hopping problem is solved by adopting the method described with reference to FIGS.

  In FIG. 9, the frequency control voltage corresponding to the first temperature T1 is defined as a first control voltage VC1. The frequency control voltage corresponding to the second temperature T2 is defined as a second control voltage VC2. This frequency control voltage (oscillation control voltage) is the frequency control voltage of the oscillation circuit 150 in FIGS. 4 and 5 and corresponds to, for example, the output voltage VQ of the D / A converter 80. The first and second temperatures T1 and T2 are temperatures detected by the temperature sensor unit 10 and correspond to the temperature detection data DTD from the A / D conversion unit 20.

  For example, the temperature detection data DTD of the A / D converter 20 when the temperature is the first temperature T1 is set as the first temperature detection data DTD1. The temperature detection data DTD of the A / D conversion unit 20 when the temperature is the second temperature T2 is set as second temperature detection data DTD2.

  In this case, the first control voltage VC1 of FIG. 9 is a frequency control voltage corresponding to the first temperature detection data DTD1 in the temperature compensation characteristic described with reference to FIG. The second control voltage VC2 is a frequency control voltage corresponding to the second temperature detection data DTD2 in the temperature compensation characteristic.

  In FIG. 9, for convenience, it is assumed that the frequency control voltage increases as the temperature increases. That is, as is clear from FIGS. 6 and 7, there is a temperature range in which the frequency control voltage increases and a temperature range in which the frequency control voltage decreases when the temperature increases. An explanation will be given assuming this.

  As shown in FIG. 10, when the temperature changes from the first temperature T1 to the second temperature T2, the differential voltage between the first control voltage VC1 and the second control voltage VC2 is VDF. Therefore, if no measures are taken, the output voltage VQ of the D / A converter 80 changes from VC1 to VC2 when the first temperature T1 changes to the second temperature T2. That is, the output voltage VQ of the D / A converter 80 changes with the step width of the differential voltage VDF.

  That is, as described above, the first control voltage VC1 is the frequency control voltage corresponding to the first temperature detection data DTD1 in the temperature compensation characteristic of FIG. 7, and the second control voltage VC2 is the second temperature voltage. This is a frequency control voltage corresponding to the detection data DTD2. Therefore, under normal conditions, the D / A conversion unit 80 outputs the first control voltage VC1 that is the frequency control voltage corresponding to the first temperature detection data DTD1 at the first temperature T1, and outputs the second control voltage VC1. At the temperature T2, a second control voltage VC2 that is a frequency control voltage corresponding to the second temperature detection data DTD2 is output. For this reason, the output voltage VQ of the D / A conversion unit 80 greatly changes from the first control voltage VC1 to the second control voltage VC2 with the step width of the differential voltage VDF.

  Then, when the output voltage VQ of the D / A converter 80 changes greatly with the step width of the differential voltage VDF as described above, frequency hopping as shown in FIG. 3 occurs. That is, the oscillation circuit 150 in FIGS. 4 and 5 oscillates the vibrator XTAL using the output voltage VQ of the D / A converter 80 as a frequency control voltage. Therefore, if the output voltage VQ of the D / A converter 80 changes with the step width of the differential voltage VDF, the oscillation frequency of the vibrator XTAL also changes with the step width corresponding to the differential voltage VDF. As a result, frequency hopping as shown in FIG. 3 occurs, and the communication error described with reference to FIG. 8 occurs.

  Therefore, in this embodiment, as shown in FIG. 11, when the temperature changes from the first temperature T1 to the second temperature T2, the difference voltage VDF between the first control voltage VC1 and the second control voltage VC2 is changed. The output voltage VQ that changes with a voltage width smaller than the absolute value is output from the D / A converter 80 to the oscillation circuit 150.

  The absolute value of the differential voltage VDF is, for example, | VC1−VC2 |. In this case, VC1> VC2 may be satisfied, or VC1 <VC2 may be satisfied. Further, when VC1 = VC2 (DTD1 = DTD2) due to the absence of temperature change, the output voltage VQ change voltage width is naturally 0 V, and the absolute value of the differential voltage VDF and the change of the output voltage VQ The voltage width matches. That is, this case is an exception of the method of the present embodiment.

  For example, when the method of this embodiment is not adopted, when the temperature changes from T1 to T2, the output voltage VQ of the D / A converter 80 is equal to the differential voltage VDF as shown by C1 in FIG. It changes with the step width.

  On the other hand, in the method of the present embodiment, as shown by C2 in FIG. 11, the output voltage VQ of the D / A conversion unit 80 is changed with a voltage width VA smaller than the absolute value of the differential voltage VDF. The voltage width VA is, for example, a voltage change of the output voltage VQ within the period TDAC.

  As shown in C2 of FIG. 11, if the output voltage VQ of the D / A conversion unit 80 is changed so that VA <VDF, the change in the oscillation frequency of the oscillation circuit 150 is much greater than in the case of C1. Get smaller. Therefore, the occurrence of frequency hopping as shown in FIG. 3 is suppressed, and the occurrence of the communication error described with reference to FIG. 8 can be prevented.

  More specifically, in the present embodiment, the D / A conversion unit 80 sets the step width of the voltage corresponding to k × LSB (k ≧ 1) when the minimum resolution of data in the D / A conversion is LSB. The output voltage VQ which changes at For example, as indicated by C2 in FIG. 11, the output voltage VQ of the D / A converter 80 changes stepwise (stepwise) with a step width of the voltage corresponding to k × LSB. That is, the above-described voltage width VA is a step width of a voltage corresponding to k × LSB of the D / A conversion unit 80, for example. The voltage width VA is sufficient if it is equal to or smaller than the step width of the voltage corresponding to k × LSB. For example, using a method of a modification example described later, VA is larger than the step width of the voltage corresponding to k × LSB. It may be made smaller.

  Here, LSB is the minimum resolution of data (frequency control data DDS output from the processing unit 50) input to the D / A conversion unit 80. The voltage corresponding to LSB is a minimum resolution voltage that is a voltage per minimum resolution of D / A conversion. Therefore, the voltage corresponding to k × LSB corresponds to a voltage k times the minimum resolution voltage.

For example, when the resolution of the D / A converter 80 is i bits, k <2 ⁱ and k is an integer sufficiently smaller than 2 ⁱ (for example, k = 1 to 8). More specifically, when the resolution of the D / A converter 80 is expanded from n bits to i = n + m bits by providing the modulation circuit 90, k <2 ^m can be obtained.

  For example, when k = 1, the output voltage VQ of the D / A conversion unit 80 changes with a step width of a voltage corresponding to 1LSB (1 bit). For example, the output voltage VQ of the D / A converter 80 changes (increases or decreases) stepwise (stepwise) with a step width of the voltage corresponding to 1LSB.

  That is, without depending on the input data DDS to the D / A conversion unit 80, the output voltage VQ of the D / A conversion unit 80 changes with a step width of a voltage corresponding to 1LSB (k × LSB in a broad sense). . For example, when the processing unit 50 (the output unit 70) in FIG. 5 changes the temperature from the first temperature to the second temperature, the second temperature from the first data corresponding to the first temperature. Can be realized by outputting frequency control data DDS that changes in units of 1 LSB (k × LSB units) to the second data corresponding to.

  Further, the step-like change in the step width of the voltage corresponding to k × LSB as indicated by C2 in FIG. 11 is faster than the output rate of the temperature detection data DTD (DTD1, DTD2) from the A / D converter 20. This is realized by the processing unit 50 outputting the frequency control data DDS at the output rate (the D / A conversion unit 80 performs D / A conversion).

  For example, the A / D converter 20 outputs temperature detection data DTD for each period TAD as shown in FIG. For example, the A / D converter 20 outputs the first temperature detection data DTD1 corresponding to the first temperature T1, and then the second temperature detection data corresponding to the second temperature T2 after the elapse of the period TAD. DTD2 is output. The period TAD corresponds to the A / D conversion interval (temperature detection voltage sampling interval) of the A / D conversion unit 20, and 1 / TAD corresponds to the output rate of the A / D conversion unit 20.

  When the A / D conversion unit 20 outputs the second temperature detection data DTD2, the processing unit 50 that receives the second temperature detection data DTD performs digital signal processing such as temperature compensation processing, and the frequency corresponding to the second temperature detection data DTD2. Control data DDS is output. At this time, the processing unit 50 changes the frequency control data DDS stepwise in units of k × LSB as shown in FIGS. 21 and 22 described later. Therefore, the output voltage VQ of the D / A converter 80 that receives the frequency control data DDS that changes in units of k × LSB and performs D / A conversion is also k × LSB for each period TDAC, as indicated by C2 in FIG. Changes with the step width of the voltage corresponding to.

  Here, the period TDAC corresponds to the D / A conversion interval (output interval of the frequency control data DDS of the processing unit 50) of the D / A conversion unit 80, and 1 / TDAC is the processing unit 50 or the D / A conversion unit. This corresponds to an output rate of 80.

  As shown in FIG. 11, TAD> TDAC, and 1 / TDAC that is the output rate of the processing unit 50 and the D / A converter 80 as compared to 1 / TAD that is the output rate of the A / D converter 20. Is getting faster. Therefore, even if the change width of the output voltage VQ for each period TDAC (output rate 1 / TDAC) is as small as VA = k × LSB, the output voltage VQ is The control voltage VC1 can be changed to the control voltage VC2. That is, when the temperature changes from T1 to T2 and the temperature detection data changes from DTD1 to DTD2, the temperature detection is performed from the control voltage VC1 corresponding to the temperature detection data DTD1 within the period TAD that is the A / D conversion interval. It becomes possible to change the output voltage VQ to the control voltage VC2 corresponding to the data DTD2. In this case, since the voltage width VA of the voltage change is small, occurrence of frequency hopping can be suppressed.

  FIG. 12 is a diagram for explaining the method of the present embodiment in the frequency domain. For example, the frequency variable range of the oscillation frequency by the oscillation signal generation circuit 140 (D / A converter 80 and oscillation circuit 150) is FR. For example, the oscillation signal generation circuit 140 performs frequency adjustment as shown in FIG. 13 with respect to the temperature change, and the frequency variable range in this frequency adjustment is FR. That is, if the temperature change is within the frequency variable range FR, the frequency adjustment by the oscillation signal generation circuit 140 is possible.

  Further, let FD be the allowable frequency drift of the oscillation frequency within the predetermined period TP. For example, in order to prevent the occurrence of the communication error described with reference to FIG. 8, it is necessary to keep the frequency drift of the oscillation frequency within the predetermined period TP within the allowable frequency drift FD. If the frequency drift of the oscillation frequency does not fall within the allowable frequency drift FD due to the frequency hopping as shown in FIG. 3, an erroneous determination occurs in the demodulation process of the received signal such as a GPS satellite signal, and a communication error occurs. End up.

The full scale voltage of the D / A converter 80 is VFS. The D / A converter 80 can change the output voltage VQ within the range of the full-scale voltage VFS. The full-scale voltage VFS corresponds to a voltage range when the frequency control data DDS input to the D / A conversion unit 80 changes in a full range such as 0 to 2 ⁱ .

  The voltage width of the voltage change of the output voltage VQ at the D / A conversion interval (TDAC) of the D / A conversion unit 80 described with reference to FIG. In this case, in the method of the present embodiment, the following expression (1) is established as shown in FIG.

VA <(FD / FR) × VFS (1)
Specifically, the following equation (2) is established when the resolution of the D / A converter 80 is i bits.

1/2 ⁱ <(FD / FR) (2)
By adopting the method of the present embodiment shown in the above equations (1) and (2), as shown in FIG. 12, the oscillation with respect to the nominal oscillation frequency fos (for example, about 16 MHz) in a predetermined period TP (for example, 20 msec). It becomes possible to keep the frequency drift of the frequency within the allowable frequency drift FD (for example, about several ppb). As a result, the occurrence of a communication error or the like caused by the frequency hopping described with reference to FIG. 3 or the like can be suppressed.

  For example, (FD / FR) × VFS, which is the right side of the above equation (1), is the ratio of the allowable frequency drift FD to the frequency variable range FR (FD / FR), and the full-scale voltage VFS of the D / A converter 80. Is multiplied by.

  If the voltage width VA of the change of the output voltage VQ at the D / A conversion interval (TDAC) of the D / A converter 80 is made smaller than (FD / FR) × VFS, in the frequency domain, FIG. As shown, the frequency drift with respect to the nominal oscillation frequency fos can be accommodated in the allowable frequency drift FD. That is, the voltage width VA of the change in the output voltage VQ of the D / A converter 80 can be reduced as shown by C2 in FIG. 11, and the occurrence of frequency hopping can be suppressed.

  For example, if the above equation (1) does not hold, as shown in FIG. 14, frequency hopping occurs in which the frequency drift with respect to the nominal oscillation frequency fos does not fall within the allowable frequency drift FD, and the communication error described in FIG. 8 occurs. End up. In the present embodiment, by changing the output voltage VQ of the D / A converter 80 so that the above equation (1) is satisfied, occurrence of such frequency hopping is suppressed, and communication errors and the like can be prevented. .

  That is, the D / A converter 80 changes the output voltage VQ within the range of the full scale voltage VFS, and adjusts the oscillation frequency of the oscillation circuit 150 within the frequency variable range FR as shown in FIG. The temperature compensation processing of the oscillation frequency described in FIGS. 6 and 7 is realized.

  However, when the voltage width VA of the change in the output voltage VQ of the D / A converter 80 becomes large, for example, VA ≧ (FD / FR) × VFS, the frequency drift of the oscillation frequency becomes the allowable frequency drift FD. Thus, frequency hopping as shown in FIG. 14 occurs.

  On the other hand, in the present embodiment, the output voltage VQ of the D / A conversion unit 80 is changed with a small voltage width VA that satisfies the relationship of VA <(FD / FR) × VFS. Generation of such frequency hopping can be suppressed.

In this embodiment, when the resolution of the D / A conversion unit 80 is i bits, 1/2 ⁱ <(FD / FR) is satisfied as shown in the above equation (2).

  For example, when both sides of the above equation (2) are multiplied by the full scale voltage VFS of the D / A converter 80, the following equation (3) is obtained.

VFS × 1/2 ⁱ <(FD / FR) × VFS (3)
VFS × 1/2 ⁱ that is the left side of the above equation (3) corresponds to a voltage of 1 LSB (minimum resolution voltage) of the D / A converter 80. The above equations (2) and (3) mean that VFS × 1/2 ⁱ corresponding to the voltage of 1LSB is made smaller than (FD / FR) × VFS. As described above, when VFS × 1/2 ⁱ <(FD / FR) × VFS, the output voltage VQ of the D / A conversion unit 80 is changed by the step width of the voltage of 1LSB as in C2 of FIG. Further, the frequency drift of the oscillation frequency does not exceed the allowable frequency drift FD, and the occurrence of frequency hopping can be suppressed.

  In other words, i bits, which are the resolution of the D / A converter 80, are set so that the above equations (2) and (3) hold.

In this case, in order to secure a sufficient margin in consideration of various variations such as manufacturing variations, D / A conversion is performed so that 1/2 ⁱ is sufficiently smaller than (FD / FR). It is desirable to set the resolution of the unit 80. Specifically, the resolution of the D / A converter 80 is set to, for example, i = 20 bits or more.

  In this way, even when the allowable frequency drift within the predetermined period TP is about several ppb as described with reference to FIG. 8, the above equations (2) and (3) have a margin. It will be established. Therefore, the occurrence of a communication error caused by frequency hopping can be effectively suppressed.

  For example, FIG. 15 is a diagram illustrating improvement in frequency drift when the method of the present embodiment described in FIGS. 11 to 13 is employed. As apparent from a comparison between FIGS. 2, 3 and 15, according to the method of the present embodiment, even when a circuit configuration such as DTCXO is used, the frequency drift is comparable to that of ATCXO in FIG. Can fit in.

  That is, in a conventional circuit device such as DTCXO, a frequency drift as shown in FIG. 3 occurs, causing a communication error or the like.

  On the other hand, if the method of the present embodiment is adopted, the frequency drift can be made comparable to the ATCXO of FIG. 2 as shown in FIG. Therefore, for example, by adopting a circuit configuration such as DTCXO, it is possible to suppress the occurrence of communication errors and the like by suppressing frequency hopping while realizing reduction in the chip size of the circuit device and improvement in frequency accuracy. Play.

3.2 Spurious and C / N Characteristics of Oscillator Spurious is generated by fluctuations in the frequency control data DDS (in a narrow sense, bit changes in the D / A converter 80). First, the characteristics of the spurious will be described. The main signal amplitude voltage of the oscillator 400 is Vo, and the main signal frequency (oscillation frequency) of the oscillator 400 is f0. With respect to Vo and f0, the phase noise (spurious) in the case where the minimum bit fluctuates in the D / A converter 80 and changes in phase satisfies the following equations (4) to (10).

  Each formula will be specifically described. When the frequency of phase fluctuation is fs, fs corresponds to the output frequency of the frequency control data DDS. Here, as shown in FIG. 4, when the oscillation signal generation circuit 140 includes the D / A conversion unit 80 and the oscillation circuit 150, fs that is the output frequency of the frequency control data DDS is the D / A conversion unit 80. Sampling frequency (1 / TDAC), and Δf, which is a change in oscillation frequency, is a change in oscillation frequency due to a single D / A conversion.

Since the minimum frequency resolution is Δf, assuming that the phase fluctuation amplitude of the phase fluctuation is φs, φs fluctuates at a frequency change of 0, + Δf, or −Δf every sampling frequency fs. Since it is considered that the frequency fluctuates with an amplitude ± Δf, φs is expressed by the following equation (4).
φs = 2π (Δf) t / 2π (fs) t = Δf / fs (4)

Using these variables, a signal obtained by adding phase fluctuation to the main signal can be expressed by the following equation (5).
Vo (t) = Vo · sin {2π (f0) t + φs · sin (2π (fs) t)} (5)

From the trigonometric product formula, the above equation (5) can be transformed into the following equation (6).
Vo (t) = Vo {sin (2π (f0) t) ・ cos (φs ・ sin (2π (fs) t)) +
cos (2π (f0) t) · sin (φs · sin (2π (fs) t))} (6)

Further, by simplifying on the assumption that φs is sufficiently smaller than 1 in the above equation (6), the above equation (6) can be transformed into the following equation (7).
Vo (t) = Vo {sin (2π (f0) t) + φs ・ cos (2π (f0) t) ・ sin (2π (fs) t)} (7)

Furthermore, from the product-sum formula of trigonometric functions, the above equation (7) can be transformed into the following equation (8).

As can be seen from the above equation (8), the signal component is the sum of the first term of the main signal and the second and third terms located symmetrically with respect to the main signal frequency in the sideband of the phase fluctuation component. As observed. The power ratio P_ratio (fs) between the main signal and the sideband is obtained by the following equation (9) according to the mutual amplitude level. Further, when the spurious intensity L (fs) for the main signal is expressed in units of dBc / Hz, the following equation (10) is obtained.

  D1 in FIG. 16 is a graph showing a general C / N characteristic (phase noise characteristic) of the oscillator 400. The horizontal axis in FIG. 16 represents the detuning frequency with respect to the fundamental wave (oscillation frequency) in logarithm, and the vertical axis represents the signal intensity. As can be seen from D1, generation of phase noise is inevitable in the oscillator 400, and the design is performed on the assumption that the phase noise is generated. That is, even if the spurious intensity shown in the above equation (10) occurs, if the intensity is small compared to the phase noise inherent in the oscillator, the influence of the spurious in the circuit device 500 is sufficiently small, and the accuracy of the acquired data is reduced. Can be suppressed. On the contrary, as shown in D2 and D3 of FIG. 16, when the spurious intensity is excessively larger than the phase noise inherent in the oscillator, the C / N characteristic of the oscillator 400 is deteriorated due to the spurious. The accuracy of the data to be reduced. For example, the accuracy of the position information obtained from the GPS reception signal is reduced.

  In the circuit device 500 according to the present embodiment, as described above, the variation in the frequency control data DDS is set to be not more than k × LSB in order to suppress a problem due to frequency drift. Therefore, although the value of Δf is expected to be reduced to some extent, there is no guarantee that the deterioration of the C / N characteristic due to spurious can be suppressed under this condition. That is, it is necessary to define the relationship between Δf and fs so that the fluctuation of the frequency control data DDS is less than or equal to k × LSB and the spurious is strong enough to be buried in the phase noise inherent in the oscillator.

  A specific relationship example will be described with reference to FIG. E1 in FIG. 17 is the same as D1 in FIG. 16, and represents a general C / N characteristic of the crystal resonator. E1 is the C / N characteristic of an AT-cut crystal resonator, for example, and corresponds to the case where the Q value characteristic is the worst in the required range (the C / N characteristic is bad). In other words, the actual circuit device 500 is designed so that there is no problem even if the phase noise having the intensity indicated by E1 occurs, so that if the spurious is sufficiently strong to be buried in E1, the data accuracy decreases. Can be suppressed.

E2 in FIG. 17 represents the strength of spurious when Δf / fs = 1/10 ⁶ , E3 represents the strength of spurious when Δf / fs = 1/10 ⁷ , and E4 represents Δf / fs = The spurious intensity in the case of 1/10 ⁸ is expressed. As shown in the above equation (10), since the spurious intensity is determined by Δf / fs, when Δf / fs is a predetermined value, the spurious intensity is a constant value regardless of the detuning frequency. It becomes a straight line parallel to the horizontal axis like E2 to E4. Since the spurious detuning frequency is fs, for E2 to E4, the horizontal axis may be considered to be the output frequency fs of the frequency control data DDS. This also applies to E5 and E6 described later.

Here, if Δf / fs <1/10 ⁸ can be achieved, the spurious intensity is lower than the straight line indicated by E4, and therefore can be smaller than the phase noise inherent to the oscillator indicated by E1. That is, in the circuit device 500 of the present embodiment, Δf / fs <1/10 ⁸ may be satisfied. However, in order to reduce Δf / fs, fs must be increased or Δf must be decreased. If fs is increased, the power consumption in the D / A converter 80 increases, and in order to reduce Δf, the resolution in the D / A converter 80 is increased (the change width of the frequency corresponding to the change of 1LSB). Need to be smaller). In other words, under the condition that Δf / fs is set to be less than a predetermined value, if Δf is increased to suppress the requirement for resolution, fs must be increased to increase the conversion speed in the D / A converter 80. In other words, if fs is reduced and the demand for the D / A converter 80 is suppressed, Δf must be reduced to ensure a high resolution. Therefore, the condition of satisfying Δf / fs <1/10 ⁸ is ideal, but it may be difficult to realize.

Therefore, in the present embodiment, it may be used loose condition as compared to Δf / fs <1/10 ^8. For example, the D / A converter 80 of the present embodiment includes a filter circuit 120 (or a filter circuit 130 described later) at the subsequent stage of the D / A converter 100. By smoothing the output voltage of the D / A converter 100 by the filter circuit 120, it is possible to reduce the fluctuation of the oscillation frequency. That is, the filter circuit 120 can reduce the substantial Δf.

For example, if the sampling frequency fs of the D / A converter 100 is set high and the cutoff rate is set to about 1/100 by the filter circuit 120, the spurious intensity can be improved by about 1/100 (−40 dB or less). It becomes possible. In this case, even if Δf / fs = 1/10 ⁶ (E2), the spurious intensity improved by the filter circuit 120 is equal to or less than E1, so that the spurious is buried in the phase noise inherent in the oscillator. That is, even if the condition of Δf / fs <1/10 ⁶ is used, it is possible to suppress a decrease in accuracy due to the deterioration of the C / N characteristics.

  As described above, the circuit device 500 of the present embodiment performs A / D conversion of the temperature detection voltage from the temperature sensor unit 10 and outputs the temperature detection data DTD, and the temperature detection data DTD. Is set by the frequency control data DDS using the processing unit 50 that performs the temperature compensation processing of the oscillation frequency based on the output frequency and outputs the frequency control data DDS of the oscillation frequency, the frequency control data DDS from the processing unit 50, and the vibrator XTAL. An oscillation signal generation circuit 140 that generates an oscillation signal having an oscillation frequency is included. In order to suppress problems due to frequency hopping, the frequency variable range of the oscillation frequency by the oscillation signal generation circuit 140 is FR, the allowable frequency drift of the oscillation frequency within a predetermined period is FD, and the full scale of the frequency control data DDS When the value is DFS and the change value of the frequency control data DDS at the output interval of the frequency control data DDS of the processing unit 50 is DV, DV <(FD / FR) × DFS.

Further, in the present embodiment, in order to increase the accuracy of data acquired using the oscillation signal, the output frequency of the frequency control data DDS of the processing unit 50 is set to fs, and the change in the change value DV of the frequency control data DDS is used. When the change in the oscillation frequency is Δf, fs and Δf satisfy Δf / fs <1/10 ⁶ .

  By setting the change value DV of the frequency control data DDS to DV <(FD / FR) × DFS, the magnitude of Δf is also limited. For example, when the circuit device 500 includes the D / A converter 100, the change width ΔVDAC of the output voltage of the D / A converter 100 is a value corresponding to the change value DV of the frequency control data DDS. The variable capacitance included in the oscillation circuit has a capacitance value that changes according to the voltage, and its change coefficient (C / V) is determined. In addition, the oscillation frequency of the oscillation circuit 150 changes according to the capacitance value of the variable capacitor, and the change coefficient (f / C) is also determined. That is, in this example, since Δf = ΔVDAC × (C / V) × (f / C), the oscillation frequency change Δf is a value corresponding to the change value DV of the frequency control data DDS.

That is, Δf is limited to a predetermined value or less by satisfying the first condition that the change value DV of the frequency control data DDS satisfies DV <(FD / FR) × DFS. The second condition that Δf / fs <1/10 ⁶ is satisfied is satisfied. In this way, it is possible to suppress problems due to frequency hopping and the like, and it is possible to suppress a decrease in accuracy due to spurious.

It should be noted that the value Δf of the change value DV of the frequency control data DDS specifically corresponds to the full scale of the D / A converter 100, the characteristics of the variable capacitance, the characteristics of the oscillation circuit 150, and the like. Determined. A specific value of Δf for satisfying Δf / fs <1/10 ⁶ is determined according to the output frequency fs of the frequency control data DDS. Therefore, which of the first condition and the second condition is a severe condition differs depending on the situation, but in any case, in this embodiment, if a setting that satisfies a more severe condition is performed, Good.

Further, the condition of Δf / fs <1/10 ⁶ allows spurious to be buried in the original phase noise of the oscillator whatever the value of the detuning frequency (the output frequency fs of the frequency control data DDS). It was requested from the viewpoint. However, as is clear from E1 in FIG. 17, in the frequency band where the influence of 1 / f noise is large, the phase noise inherent to the oscillator is larger as the frequency is smaller. That is, even in the band where the detuning frequency is relatively low, even if a spurious signal with higher strength occurs, the spurious signal is buried in the phase noise of the oscillator 400, and the influence on accuracy is small.

In other words, the condition that Δf / fs <1/10 ⁶ is satisfied regardless of the spurious detuning frequency (fs) is sufficient from the viewpoint of suppressing a decrease in accuracy of data based on the oscillation signal. It is possible that the conditions are excessive.

Therefore, in the present embodiment, conditions different from Δf / fs <1/10 ⁶ may be used. E5 and E6 in FIG. 17 are diagrams showing spurious characteristics when Δf is a given fixed value. As shown in FIG. 17, when the unit of the vertical axis is dBc / Hz and the horizontal axis is the logarithm of the detuning frequency, the spurious intensity when Δf is a fixed value is expressed as a monotonically decreasing straight line. Then, by changing Δf, the intercept of the straight line changes, and the greater the Δf, the higher the spurious intensity at the same detuning frequency. E5 in FIG. 17 represents the spurious characteristic when Δf = 0.1 mHz, and E6 represents the spurious characteristic when Δf = 1 mHz.

As can be seen from FIG. 17, E5 where Δf = 0.1 mHz is located below E1 representing the C / N characteristic of the oscillator 400 regardless of the position on the horizontal axis. That is, by satisfying Δf <0.1 mHz, the spurious intensity can be made smaller than the original phase noise of the oscillator. However, Delta] f <is also ideal conditions in the same manner as Δf / fs = 1/10 ⁸ for 0.1 mHz, actually influence on the accuracy is less a looser condition. Specifically, in the present embodiment, the upper limit is the straight line indicated by E6, and the condition is that Δf <1 mHz.

  However, the condition of Δf <1 mHz is an excessively severe condition in a situation where the detuning frequency (fs) is relatively large. As can be seen from the above equation (10), the greater the fs, the smaller the spurious strength. That is, when fs is large, even if Δf is large, an increase in spurious intensity can be suppressed, and the influence on accuracy is small. Under the condition of Δf <1 mHz, even if fs is large, there is a possibility that Δf is excessively decreased, which is a severe condition.

Therefore, in the present embodiment, Δf / fs <1/10 ⁶ and Δf <1 mHz may be switched depending on the situation. Specifically, the conditions may be switched with fs = 1 kHz being the intersection of E2 and E6 in FIG. In the case of the right side of the intersection, that is, when fs ≧ 1 kHz, E2 is higher than E6, so the condition of E2 is looser. On the other hand, in the case of the left side of the intersection, that is, when fs <1 kHz, E6 is higher than E2, so the condition of E6 is looser. That is, in the present embodiment, Δf / fs <1/10 ⁶ when fs ≧ 1 kHz, and Δf <1 mHz when fs <1 kHz. In this way, since the condition to be satisfied can be relaxed, for example, the requirement for the resolution of the D / A converter 100 can be lowered, and the circuit device 500 can be easily realized.

Further, the method of the present embodiment is not limited to the method using a combination of Δf / fs <1/10 ⁶ and Δf <1 mHz. Specifically, when the output frequency of the frequency control data DDS is fs and the change of the oscillation frequency due to the change in the change value DV of the frequency control data DDS is Δf, when fs <1 kHz, Δf <1 mHz. There may be. At this time, when fs ≧ 1 kHz, it is possible to adopt a condition different from Δf / fs <1/10 ^6, and fs ≧ 1 kHz may be excluded from the application of the method of the present embodiment. Is possible.

Various circuit device design techniques are conceivable in which Δf and fs satisfy the above conditions. For example, the conversion speed (sampling frequency) required for the D / A converter 80 differs depending on the circuit device. In a given circuit device, it is possible to set a high sampling frequency such as fs = 100 kHz, but in a different circuit device, only a low sampling frequency such as fs = 100 Hz is allowed from the viewpoint of power consumption and the like. . In a circuit device in which fs = 100 kHz is allowed, Δf / fs <1/10 ⁶ may be used as a condition as described above, and Δf <100 mHz. In this case, since Δf can be increased as compared with Δf <1 mHz, there is no problem even if the resolution is relatively coarse. On the other hand, in the circuit device in which fs = 100 Hz, Δf <1 mHz may be used as described above. In this case, the demand for resolution becomes relatively large, but it becomes possible to realize a circuit device with low power consumption.

  Here, the vibrator XTAL according to the present embodiment is, for example, a crystal vibrator. Note that it is known that the characteristics of the oscillation frequency and the like differ depending on the cutting orientation from the crystal axis. The crystal resonator according to the present embodiment may be a widely used AT cut resonator, SC cut (Stress Compensation-cut) resonator, or SAW resonator.

  The AT-cut vibrator has an angle of 35.15 ° with respect to the crystal axis and is used for SPXO, TCXO, and VCXO as an oscillation source of 10 MHz to 500 MHz. Further, the SC cut vibrator is a vibrator used in OCXO as an oscillation source of 10 MHz to 100 MHz due to the characteristic that the temperature characteristic becomes minimum at high temperature. Note that the oscillation frequency of the AT cut vibrator and the SC cut vibrator is determined by the thickness slip. The SAW resonator is a vibrator applying surface acoustic wave, and vibrates depending on the electrode pattern on the quartz surface. The SAW resonator is a vibrator having an oscillation frequency as high as 100 MHz to 3.5 GHz and good C / N characteristics (high Q value).

Note that Δf / fs <1/10 ⁶ is a condition regarding the ratio of Δf to fs. Therefore, many combinations of Δf and fs satisfying Δf / fs <1/10 ⁶ are conceivable. FIG. 18 is an example of a set of Δf and fs values when accurate data can be acquired without deteriorating the C / N characteristics. F1 in FIG. 18 is (Δf, fs) = (0.1 Hz, 4 MHz), F2 is (Δf, fs) = (4 mHz, 100 kHz), and F3 is (Δf, fs) = (1 mHz, 10 kHz). It is.

  In the present embodiment, it is not hindered to limit the set of Δf and fs values to one. For example, only one of F1 to F3 is set as a set of values of Δf and fs, and the circuit device 500 operates so as to satisfy the set value. However, the method of the present embodiment is not limited to this, and the set of Δf and fs values may be variable. For example, three sets of F1 to F3 may be held as candidates for a pair of values of Δf and fs, and any one of the three may be adopted depending on the situation.

  For example, a set of Δf and fs values to be used is determined according to whether or not the circuit device 500 is within a predetermined period from the start of operation. At the start of operation, since temperature compensation processing for the temperature detection data DTD has not been performed so far, the difference between the oscillation frequency of the output oscillation signal SSC and a desired oscillation frequency (hereinafter referred to as a frequency error) is large. There is. Although it is possible to obtain the frequency control data DDS for reducing the frequency error (set to 0 in a narrow sense) by the temperature compensation processing in the processing unit 50, in this embodiment, the oscillation frequency per one time is obtained. There is a limitation of suppressing the fluctuation to Δf. That is, during a single output of the frequency control data DDS, the frequency error is reduced only by Δf, and it may take a long time to make the frequency error zero.

Therefore, in this embodiment, Δf is set to a relatively large value at the start of operation, and fs is preferably set to a relatively large value in order to satisfy Δf / fs <1/10 ⁶ . In the example of F1 to F3, (Δf, fs) = (0.1 Hz, 4 MHz) shown in F1 is used. In this way, since Δf is relatively large, the oscillation frequency of the oscillation signal can be brought close to a desired frequency (frequency error is brought close to 0) in a short time.

  However, in order to increase Δf, fs must be increased, leading to an increase in power consumption. Therefore, when a certain amount of time has elapsed (or when the frequency error has decreased to some extent), it is desirable to decrease Δf and decrease fs. In the example of FIG. 18, the set of Δf and fs values to be used is changed from (F1 to F2) to (Δf, fs) = (4 mHz, 100 kHz). Further, even when the time has passed (when the frequency error becomes small), even if the set of Δf and fs values used is changed from F2 to F3 (Δf, fs) = (1 mHz, 10 kHz) Good.

  FIG. 19 is a diagram for explaining the above control. The vertical axis in FIG. 19 represents the frequency error (Hz), and the horizontal axis represents the elapsed time from the start of operation (at the time of activation) in logarithm. As indicated by t1 to t2 in FIG. 19, the operation is performed with the parameter indicated by F1 for a predetermined period from the start. Since the sampling frequency fs is high and Δf, which is the amount of change in frequency per time, is large, it is possible to bring the frequency error of 0.2 Hz or more at the time of startup close to 0 in a short time. In the period from t2 to t3, the operation is performed with the parameter indicated by F2, and in the period after t3, the operation is performed with the parameter indicated by F3.

In this way, the condition shown by Δf / fs <1/10 ⁶ can be realized using parameters according to the situation. Specifically, in a situation where there is a possibility that the frequency error is large, the target value is followed at high speed, and when a certain amount of tracking is completed, fs is reduced to suppress an increase in power consumption.

Here, an example in which there are three combinations of Δf and fs values has been described, but it goes without saying that there may be two or four or more. Further, Δf and fs only need to satisfy Δf / fs <1/10 ⁶ , and specific numerical values are not limited to F1 to F3 in FIG. In addition, an example in which Δf and fs are variable on the condition that Δf / fs <1/10 ⁶ is satisfied has been shown. However, on the condition that the frequency control data DDS is changed in units of k × LSB (k ≧ 1), k may be variable.

Further, the configuration in which the oscillation signal generation circuit 140 includes the D / A conversion unit 80 has been described above, but the method of the present embodiment is not limited to this. For example, even when an oscillation signal generation circuit 140 having a configuration that does not include the D / A conversion unit 80 described later with reference to FIG. 39 is used, the conditions Δf / fs <1/10 ⁶ and Δf <1 mHz are satisfied. As a result, it is possible to suppress the deterioration of the C / N characteristic due to spurious and to achieve accurate data acquisition and the like. When the oscillation signal generation circuit 140 does not include the D / A conversion unit 80, the filter circuit 120 (filter circuit 130) is not included, and there is a possibility that spurious reduction by the filter circuit 120 is not performed. In that case, conditions to be satisfied by Δf and fs may be made stricter than conditions such as Δf / fs <1/10 ⁶ and Δf <1 mHz.

4). Detailed Configuration Example 4.1 Processing Unit Next, a detailed configuration example of each unit of the circuit device according to the present embodiment will be described. FIG. 20 is a diagram illustrating a detailed configuration example of the processing unit 50.

  As illustrated in FIG. 20, the processing unit 50 (DSP unit) includes a control unit 52, a calculation unit 60, and an output unit 70. The control unit 52 controls the calculation unit 60 and the output unit 70 and performs various determination processes. The calculation unit 60 calculates a temperature compensation process for the oscillation frequency based on the temperature detection data DTD from the A / D conversion unit 20. The output unit 70 receives calculation result data from the calculation unit 60 and outputs frequency control data DDS.

  The control unit 52 includes a determination unit 53. The determination unit 53 includes comparison units 54 and 55, and performs various determination processes based on the comparison results of the comparison units 54 and 55.

  The calculation unit 60 includes type conversion units 61, 62, and 68, multiplexers 63 and 65, a calculation unit 64, and work registers 66, 67, and 69. The computing unit 64 includes a multiplier 58 and an adder 59.

  The type conversion unit 61 receives coefficient data from the memory unit 180, performs type conversion from a binary type (integer) to a floating point type (single precision), and outputs the coefficient data after type conversion to the multiplexer 63. . The type conversion unit 62 receives the temperature detection data DTD from the A / D conversion unit 20, performs type conversion from the binary type to the floating point type, and outputs the temperature detection data DTD after type conversion to the multiplexer 63. . For example, 15-bit binary temperature detection data DTD is converted into a 32-bit floating point (exponent part = 8 bits, mantissa part = 23 bits, sign = 1 bit). The multiplexer 63 receives the constant data from the ROM 190 that stores constant data of fixed values for temperature compensation processing.

  The multiplexer 63 selects any one of the output data of the computing unit 64, the output data of the work registers 66 and 67, the output data of the type conversion units 61 and 62, and the output data of the ROM 190 and outputs the selected data to the computing unit 64. The arithmetic unit 64 performs temperature compensation processing by performing arithmetic processing such as 32-bit floating-point product-sum operation using the multiplier 58 and the adder 59, for example. The multiplexer 65 selects any one of the output data of the multiplier 58 and the adder 59 of the arithmetic unit 64 and outputs the selected data to any of the work registers 66 and 67 and the type conversion unit 68. The type conversion unit 68 converts the calculation result data of the calculation unit 60 (calculator 64) from a floating point type to a binary type. For example, type conversion is performed on 32-bit floating-point operation result data into 20-bit binary operation result data. The operation result data after the type conversion is held in the work register 69.

  As shown in the following equation (11), the calculation unit 60 (calculator 64) performs a temperature compensation process for approximating the temperature characteristic curve of FIG. 6 with, for example, a fifth-order approximation function (polynomial).

Vcp = b · (T−T0) ⁵ + c · (T−T0) ⁴ + d · (T−T0) ³ + e · (T−T0)
(11)
In the above equation (11), T corresponds to the temperature represented by the temperature detection data DTD, and T0 corresponds to the reference temperature (for example, 25 ° C.). “b”, “c”, “d”, and “e” are coefficients of the approximate function, and data of the coefficients is stored in the memory unit 180. The arithmetic unit 64 executes arithmetic processing such as a product-sum operation of the above equation (11).

  The output unit 70 includes a multiplexer 71, an output register 72, an LSB adder 73, and an LSB subtracter 74. The multiplexer 71 selects any one of operation result data, which is output data from the operation unit 60, output data from the LSB adder 73, and output data from the LSB subtractor 74, and outputs the selected data to the output register 72. The determination unit 53 of the control unit 52 monitors the output data of the work register 69 and the output data of the output register 72. Then, various comparison determinations using the comparison units 54 and 55 are performed, and the multiplexer 71 is controlled based on the determination results.

  In the present embodiment, as shown in FIGS. 21 and 22, the output unit 70, when the temperature changes from the first temperature to the second temperature, from the first data DAT1 corresponding to the first temperature, The frequency control data DDS that changes in units of k × LSB is output to the second data DAT2 corresponding to the second temperature. For example, k = 1, and frequency control data DDS that changes in units of 1 LSB is output.

  For example, the output register 72 stores the first data DAT1 that is the calculation result data of the previous calculation unit 60 (timing n-1). The work register 69 stores second data DAT2 which is the calculation result data of the calculation unit 60 this time (nth timing).

  Then, as shown in FIG. 21, the output unit 70 determines that the first data DAT2, which is the current calculation result data, is larger than the first data DAT1, which is the previous calculation result. The addition result data is output as the frequency control data DDS while performing the process of adding 1LSB (k × LSB in a broad sense), which is a predetermined value, to the data DAT1 until the addition result data reaches the second data DAT2. .

  On the other hand, as shown in FIG. 22, when the second data DAT2, which is the current calculation result data, is smaller than the first data DAT1, which is the previous calculation result, the output unit 70 outputs the first data DAT2. The subtraction result data is output as the frequency control data DDS while performing the process of subtracting 1LSB (k × LSB), which is a predetermined value, from the data DAT1 until the subtraction result data reaches the second data DAT2.

  Specifically, the determination unit 53 of the control unit 52 compares the first data DAT1 stored in the output register 72 with the second data DAT2 stored in the work register 69. This comparison is determined by the comparison unit 54.

  Then, as shown in FIG. 21, when DAT2 is larger than DAT1, the process of adding 1LSB to DAT1 of the output register 72 is performed by the LSB adder 73, and the output data of the LSB adder 73 is Are selected by the multiplexer 71. As a result, as shown in FIG. 21, the output register 72 holds the addition result data obtained by sequentially adding 1LSB to DAT1. Then, addition result data in which 1 LSB is sequentially added and updated is output as frequency control data DDS. Then, the addition process is repeated until the addition result data reaches DAT2. Comparison processing for determining whether the addition result data matches DAT2 is performed by the comparison unit 55.

  On the other hand, as shown in FIG. 22, when DAT2 is smaller than DAT1, the process of subtracting 1LSB from DAT1 of the output register 72 is performed by the LSB subtractor 74, and the output data of the LSB subtractor 74 is It is selected by the multiplexer 71. As a result, as shown in FIG. 22, the output register 72 holds subtraction result data obtained by sequentially subtracting 1 LSB from DAT1. Then, subtraction result data that is updated by sequentially subtracting 1LSB is output as frequency control data DDS. Then, the subtraction process is repeated until the subtraction result data reaches DAT2.

  The maximum number of addition processes and subtraction processes by the LSB adder 73 and LSB subtractor 74 is set to a predetermined number (for example, 8 times). For example, the maximum temperature change of the environmental temperature can be defined (for example, 2.8 ° C./10 seconds). Therefore, for example, a temperature change corresponding to 1LSB × predetermined number of times (for example, a temperature change corresponding to 1LSB × 8 times of voltage) is set to sufficiently exceed the maximum temperature change.

  As described with reference to FIG. 11, the output rate (1 / TDAC) of the frequency control data DDS of the processing unit 50 is faster than the output rate (1 / TAD) of the temperature detection data DTD of the A / D conversion unit 20. Therefore, for example, in the period TAD from when the temperature detection data DTD2 is input from the A / D conversion unit 20 to the processing unit 50 in FIG. 11 until the next temperature detection data DTD3 is input, the configuration shown in FIGS. Such a process of adding or subtracting 1 LSB by a given number of times can be executed. For example, the addition process or the subtraction process can be executed a predetermined number (for example, 8 times) which is the maximum number as described above.

  As described above, according to the processing unit 50 configured as shown in FIG. 20, as shown in FIGS. 21 and 22, for example, from the first data DAT1 corresponding to the first temperature (first temperature detection data DTD1), The frequency control data DDS that changes in units of k × LSB can be output to the second data DAT2 corresponding to the second temperature (second temperature detection data DTD2). As a result, the method of this embodiment described with reference to FIGS. 11 to 13 can be realized by output control of the frequency control data DDS of the processing unit 50.

  In the present embodiment, for example, the processing of the arithmetic unit 60 is realized by high-precision arithmetic processing such as 32 bits. Therefore, for example, when the type conversion unit 68 performs type conversion of 32-bit floating-point operation result data, for example, based on the 23-bit mantissa part for which accuracy is maintained, for example, 20-bit binary frequency control data DDS ( Calculation result data). As a result, as described with reference to FIG. 5, for example, frequency control data DDS of i = 20 bits can be input from the processing unit 50 to the D / A conversion unit 80. Then, the modulation circuit 90 modulates n = 16 bit data of the frequency control data DDS based on the m = 4 bit data of i = 20 bits, and the D / A converter 100 performs the modulation n = D / A conversion of 16-bit data makes it possible to realize D / A conversion with a resolution of i = 20 bits.

4.2 D / A Conversion Unit FIGS. 23 and 24 are diagrams illustrating a detailed configuration example of the D / A conversion unit 80. The D / A conversion unit 80 includes a modulation circuit 90, a D / A converter 100, and a filter circuit 120.

  As shown in FIG. 23, the D / A converter 100 includes a higher-order D / A converter DACA, a lower-order D / A converter DACB, and operational amplifiers (operational amplifiers) OPA and OPB connected in a voltage follower. , Including OPC.

  The higher-order DACA is inputted with higher-order q-bit data among n-bit (n = q + p) data DM from the modulation circuit 90, and the lower-order DACB is inputted with lower-order p bits (for example, p = q = 8). ) Data is input. These upper-side DACA and lower-side DACB are, for example, resistance string type D / A converters that select a voltage corresponding to input data from a plurality of divided voltages divided by a plurality of resistors connected in series. It is.

  As shown in FIG. 24, the higher-order DACA includes a plurality of resistors RA1 to RAN connected in series between the node of the high-potential-side power supply voltage VDDA and the node of the low-potential-side power supply voltage VSS. Further, the higher-order DACA turns on the switch elements SA1 to SAN + 1 based on the plurality of switch elements SA1 to SAN + 1 whose one ends are connected to the voltage dividing nodes by the resistors RA1 to RAN and the upper q bits of the data DM. It also includes a decoder 104 (switch control circuit) that generates a switch control signal to be turned off.

  Then, the higher-order DACA outputs one divided voltage to the non-inverting input terminal of the operational amplifier OPA among the divided voltages at both ends of the resistor specified by the upper q-bit data among the plurality of resistors RA1 to RAN, and the other The divided voltage is output to the non-inverting input terminal of the operational amplifier OPB. As a result, the one voltage is impedance-converted by the operational amplifier OPA connected as a voltage follower, and is supplied to the lower-order DACB as the voltage VX. The other voltage is impedance-converted by an operational amplifier OPB connected as a voltage follower, and supplied to the lower DACB as the voltage VY.

  For example, when the resistor RA1 is specified by the upper q-bit data, among the divided voltages at both ends of the resistor RA1, the divided voltage on the high potential side is supplied via the switch element SA1 and the operational amplifier OPA that are turned on. Supplied as VX. The divided voltage on the low potential side is supplied as the voltage VY via the switch element SA2 and the operational amplifier OPB that are turned on. When the resistor RA2 is specified by the upper q-bit data, the divided voltage on the low potential side among the divided voltages at both ends of the resistor RA2 is supplied via the switch element SA3 and the operational amplifier OPA which are turned on. Supplied as VX. Further, the divided voltage on the high potential side is supplied as the voltage VY via the switch element SA2 and the operational amplifier OPB that are turned on.

  The lower-order DACB includes a plurality of resistors RB1 to RBM connected in series between a node of voltage VX and a node of voltage VY. The lower-side DACB turns on the switch elements SB1 to SBM + 1 based on the plurality of switch elements SB1 to SBM + 1 whose one ends are connected to the voltage dividing nodes by the resistors RB1 to RBM and the lower p-bit data of the data DM. It also includes a decoder 106 (switch control circuit) that generates a switch control signal to be turned off.

  The low-order DACB is connected to the voltage follower via the switch element that is turned on using one divided voltage selected by the low-order p-bit data among the plurality of divided voltages by the resistors RB1 to RBM. Output to the non-inverting input terminal of the operational amplifier OPC. As a result, the selected voltage is output as the output voltage VDA of the D / A converter 100.

  25, 26, and 27 are explanatory diagrams of the modulation circuit 90. FIG. As shown in FIG. 25, the modulation circuit 90 receives i = (n + m) -bit frequency control data DDS from the processing unit 50. Based on the lower m bits of data (bits b1 to b4) of the frequency control data DDS, the PWM modulation of the upper n bits (bits b5 to b20) of the frequency control data DDS is performed. 23 and FIG. 24, the upper q-bit data (bits b13 to b20) among the n-bit data is input to the higher-order DACA and the lower p-bit data (bit b5). ˜b12) are input to the lower-order DACB.

  FIG. 26 is an explanatory diagram of the first method of PWM modulation. DY and DZ are high-order n-bit data of the data DM, and DY = DZ + 1 holds in the n-bit representation.

  When the duty ratio represented by the lower-order m = 4-bit data used for PWM modulation is 8 to 8, for example, as shown in FIG. 26, 8 pieces of 16-bit data DY and 8 pieces of data DY The 16-bit data DZ is output from the modulation circuit 90 to the D / A converter 100 in a time division manner.

  When the duty ratio represented by the lower order m = 4 bit data is 10 to 6, the 10 data DY and the 6 data DZ are time-divisionally converted from the modulation circuit 90 to the D / A converter. 100 is output. Similarly, when the duty ratio represented by the lower order m = 4 bit data is 14 to 2, 14 data DY and 2 data DZ are output in a time division manner.

  FIG. 27 is an explanatory diagram of the second method of PWM modulation. When each bit b4, b3, b2, b1 of m = 4 bits used for PWM modulation is a logic level “1”, an output pattern (shown on the right side of each bit) corresponding to each bit in FIG. Output pattern) is selected.

  For example, when bit b4 = 1 and b3 = b2 = b1 = 0, only the output pattern associated with bit b4 is output in periods P1 to P16. That is, n = 16-bit data is output from the modulation circuit 90 to the D / A converter 100 in time division in the order of DZ, DY, DZ, DY. As a result, the number of times data DY and DZ are output is eight, and the same PWM modulation as in the case where the duty ratio is 8 to 8 in FIG. 26 is realized.

  When bits b4 = b2 = 1 and b3 = b1 = 0, output patterns associated with bits b4 and b2 are output in periods P1 to P16. As a result, the data DY and DZ are output 10 times and 6 times, respectively, and the same PWM modulation as in the case where the duty ratio is 10 to 6 is realized. Similarly, when bits b4 = b3 = b2 = 1 and b1 = 0, the data DY and DZ are output 14 times and 2 times, respectively, and the duty ratio is 14 to 2. The same PWM modulation is realized.

  As described above, according to the modulation circuit 90 of FIGS. 5 and 23, PWM modulation can be realized only by controlling the number of output times of the data DY and DZ. For example, the D / A converter 100 having a resolution of 16 bits can be realized. While being used, for example, a resolution of D / A conversion of 20 bits or more can be realized.

  For example, in a resistor string type or resistor ladder type D / A conversion with less noise, for example, a resolution of about 16 bits is a practical limit. In this regard, according to the configurations of FIGS. 5 and 23, the D / A conversion resolution can be improved to, for example, 20 bits or more simply by providing the modulation circuit 90 and the filter circuit 120 with a small circuit scale. Therefore, it is possible to improve the resolution of the D / A conversion unit 80 while minimizing an increase in circuit scale. Further, by improving the resolution of the D / A conversion unit 80, it is possible to achieve high accuracy of the oscillation frequency accuracy, and it is possible to realize suppression of frequency hopping and provision of an oscillator suitable for time synchronization.

4.3 Temperature Sensor Unit and Oscillator Circuit FIG. 28 shows a first configuration example of the temperature sensor unit 10. The temperature sensor unit 10 of FIG. 28 includes a current source IST and a bipolar transistor TRT to which a current from the current source IST is supplied to a collector. The bipolar transistor TRT has a diode connection to which the base of the bipolar transistor TRT is connected, and a temperature detection voltage VTD having temperature characteristics is output to the collector node of the bipolar transistor TRT. The temperature characteristic of the temperature detection voltage VTD is caused by the temperature dependence of the base-emitter voltage of the bipolar transistor TRT. As shown in FIG. 30, the temperature detection voltage VTD has a negative temperature characteristic (a first-order temperature characteristic having a negative gradient).

  FIG. 29 shows a second configuration example of the temperature sensor unit 10. In FIG. 29, the current source IST of FIG. 28 is realized by the resistor RT. One end of the resistor RT is connected to the node of the power supply voltage, and the other end is connected to the collector of the bipolar transistor TRT1. The emitter of the bipolar transistor TRT1 is connected to the collector of the bipolar transistor TRT2. The bipolar transistors TRT1 and TRT2 are both diode-connected, and the voltage VTSQ output to the collector node of the bipolar transistor TRT1 has a negative temperature characteristic (first-order temperature having a negative gradient) as shown in FIG. Characteristic).

  In the temperature sensor unit 10 of FIG. 29, an operational amplifier OPD and resistors RD1 and RD2 are further provided. The voltage VTSQ is input to the non-inverting input terminal of the operational amplifier OPD, and one end of the resistor RD1 and one end of the resistor RD2 are connected to the inverting input terminal. The reference temperature voltage VTA0 is supplied to the other end of the resistor RD1, and the other end of the resistor RD2 is connected to the output terminal of the operational amplifier OPD.

  The operational amplifier OPD and the resistors RD1 and RD2 constitute an amplification amplifier that forwardly amplifies the voltage VTSQ with reference to the reference temperature voltage VAT0. As a result, the temperature detection voltage VTD = VAT0 + (1 + RD2 / RD1) × (VTSQ−VAT0) is output from the temperature sensor unit 10. The reference temperature T0 can be adjusted by adjusting the reference temperature voltage VAT0.

  FIG. 31 shows a configuration example of the oscillation circuit 150. The oscillation circuit 150 includes a current source IBX, a bipolar transistor TRX, a resistor RX, a variable capacitor CX1, and capacitors CX2 and CX3.

  The current source IBX supplies a bias current to the collector of the bipolar transistor TRX. The resistor RX is provided between the collector and base of the bipolar transistor TRX.

  One end of the variable capacitor CX1 having a variable capacitance is connected to one end of the vibrator XTAL. Specifically, one end of the variable capacitor CX1 is connected to one end of the vibrator XTAL via the first vibrator terminal (vibrator pad) of the circuit device. One end of the capacitor CX2 is connected to the other end of the vibrator XTAL. Specifically, one end of the capacitor CX2 is connected to the other end of the vibrator XTAL via a second vibrator terminal (vibrator pad) of the circuit device. One end of the capacitor CX3 is connected to one end of the vibrator XTAL, and the other end is connected to the collector of the bipolar transistor TRX.

  A current between the base and the emitter generated by the oscillation of the vibrator XTAL flows through the bipolar transistor TRX. When the base-emitter current increases, the collector-emitter current of the bipolar transistor TRX increases, and the bias current branched from the current source IBX to the resistor RX decreases, so the collector voltage VCX decreases. On the other hand, when the base-emitter current of the bipolar transistor TRX decreases, the collector-emitter current decreases and the bias current branching from the current source IBX to the resistor RX increases, so that the collector voltage VCX increases. The collector voltage VCX is fed back to the vibrator XTAL via the capacitor CX3.

  The oscillation frequency of the vibrator XTAL has a temperature characteristic (for example, the temperature characteristic of FIG. 6), and this temperature characteristic is compensated by the output voltage VQ (frequency control voltage) of the D / A converter 80. That is, the output voltage VQ is input to the variable capacitor CX1, and the capacitance value of the variable capacitor CX1 is controlled by the output voltage VQ. When the capacitance value of the variable capacitor CX1 changes, the resonance frequency of the oscillation loop changes, so that the fluctuation of the oscillation frequency due to the temperature characteristics of the vibrator XTAL is compensated. The variable capacitor CX1 is realized by, for example, a variable capacitor diode (varactor).

  Note that the oscillation circuit 150 of the present embodiment is not limited to the configuration of FIG. 31, and various modifications can be made. For example, FIG. 31 illustrates the case where CX1 is a variable capacitor, but CX2 or CX3 may be a variable capacitor controlled by the output voltage VQ. A plurality of CX1 to CX3 may be variable capacitors controlled by VQ.

5. Modified Examples Next, various modified examples of the present embodiment will be described. For example, in the above, when the processing unit 50 outputs the frequency control data DDS that changes in units of k × LSB as shown in FIGS. 21 and 22, the method of the present embodiment of FIGS. 11 to 13 is realized. However, the present embodiment is not limited to this.

  In the modification of FIG. 32, a filter circuit 130 composed of an SCF (switched capacitor filter) is provided after the D / A converters DACC and DACD. For example, the 8-bit D / A converter DACC outputs the voltage DA1 based on the data D (n) at the timing n. The 8-bit D / A converter DACD outputs the voltage DA2 based on the data D (n + 1) at the next timing n + 1.

  When the clock frequency fck of the SCF of the filter circuit 130 is set, a resistor of RG = 1 / (CS1 × fck) is realized by a circuit including the capacitor CS1 and the switch elements SS1 and SS2. A circuit composed of the capacitor CS2 and the switch elements SS3 and SS4 realizes a resistance of RF = 1 / (CS2 × fck).

  Further, the time constant τ of the filter circuit 130 is expressed as the following expression (12).

τ = RF × CS3 = (CS3 / CS2) × (1 / fck) (12)
For example, by setting CS3 = 5 pF, CS2 = 0.1 pF, and fck = 5 KHz, τ = 10 msec can be realized. By making the time constant τ sufficiently long in this way, an output voltage VQ that slowly changes from the voltage DA1 to the voltage DA2 with the time constant τ can be realized as shown in FIG.

  For example, as shown in FIG. 33, the slope when the horizontal axis is the period TP (for example, 20 msec) described in FIG. 8 and the vertical axis is the allowable frequency drift FD (for example, about several ppb) is SL1 = FD / TP. . In this case, the method of the present embodiment shown in FIGS. 11 to 13 can be realized by making the slope SL2 realized by the time constant τ of FIG. 34 smaller than the slope SL1. That is, a filter circuit 130 having a low-pass filter characteristic that is so strong that the slope SL1 defined by the period TP and the allowable frequency drift FD cannot be formed is provided at the subsequent stage of the D / A converters DACC and DACD. As a result, as shown by C2 in FIG. 11, the voltage waveform equivalent to the voltage waveform in which the output voltage VQ of the D / A converter 80 changes with the step width of the voltage of 1LSB can be realized. Can be solved.

  However, when the time constant τ of the filter circuit 130 becomes longer than the period TP, the variation in the temperature characteristic of the vibrator XTAL cannot be corrected by the output voltage VQ of the filter circuit 130, and the frequency shifts.

  For example, FIG. 35 is a diagram showing frequency drift with respect to temperature change when the time constant is τ = TP = 20 msec. As shown in FIG. 35, by setting τ = TP, the problem of frequency hopping can be solved. On the other hand, FIGS. 36 and 37 are diagrams showing frequency drifts with respect to temperature changes when τ = 22 msec and 40 msec, respectively. As described above, the modification of FIG. 32 has a disadvantage that the characteristic of frequency drift deteriorates when the time constant τ is long, and it is difficult to obtain an optimal solution.

  FIG. 38 is a configuration example of the A / D conversion unit 20. As shown in FIG. 38, the A / D conversion unit 20 includes a processing unit 23, a register unit 24, D / A converters DACE and DACF, and a comparison unit 27. A temperature sensor amplifier 28 may be included. The processing unit 23 and the register unit 24 are provided as the logic unit 22, and the D / A converters DACE and DACF, the comparison unit 27, and the temperature sensor unit amplifier 28 are provided as the analog unit 26.

  The register unit 24 stores result data such as an intermediate result or final result of A / D conversion. The register unit 24 corresponds to, for example, a successive approximation result register in the successive approximation method. The D / A converters DACE and DACF D / A convert the result data of the register unit 24. As these DACE and DACF, D / A converters having the same configurations as those shown in FIGS. 23 and 24 can be adopted. The comparison unit 27 compares the output voltage of the D / A converters DACE and DACF with the temperature detection voltage VTD (the voltage after amplification by the temperature sensor unit amplifier 28). The comparison unit 27 can be realized by a chopper type comparator, for example. The processing unit 23 performs determination processing based on the comparison result of the comparison unit 27 and performs update processing of the result data of the register unit 24. The final temperature detection data DTD obtained by the update process is output from the A / D conversion unit 20 as an A / D conversion result of the temperature detection voltage VTD. With such a configuration, for example, successive approximation A / D conversion, A / D conversion similar to the successive approximation, and the like can be realized. The method of the present embodiment described with reference to FIGS. 11 to 13 can also be realized by devising the output mode of the temperature detection data DTD of the A / D conversion unit 20 of FIG.

  FIG. 39 shows a configuration example of a circuit device according to a modification of the present embodiment.

  The circuit device of FIG. 39 performs A / D conversion of the temperature detection voltage VTD from the temperature sensor unit 10 and outputs temperature detection data DTD, and the oscillation frequency based on the temperature detection data DTD. A processing unit 50 that performs temperature compensation processing and outputs frequency control data DDS of the oscillation frequency, and an oscillation signal generation circuit 140 are included.

  Then, when the temperature changes from the first temperature to the second temperature, the processing unit 50 changes the first data corresponding to the first temperature to the second data corresponding to the second temperature. X Outputs frequency control data DDS that changes in units of LSB. The oscillation signal generation circuit 140 generates an oscillation signal SSC having an oscillation frequency set by the frequency control data DDS, using the frequency control data DDS from the processing unit 50 and the vibrator XTAL.

  That is, in FIG. 39, unlike FIGS. 4 and 5, the oscillation signal generation circuit 140 is not provided with the D / A converter 80. Then, the oscillation frequency of the oscillation signal SSC generated by the oscillation signal generation circuit 140 is directly controlled based on the frequency control data DDS from the processing unit 50. That is, the oscillation frequency of the oscillation signal SSC is controlled without going through the D / A converter.

  For example, in FIG. 39, the oscillation signal generation circuit 140 includes a variable capacitance circuit 142 and an oscillation circuit 150. The oscillation signal generation circuit 140 is not provided with the D / A converter 80 shown in FIGS. In addition, the variable capacitance circuit 142 is provided instead of the variable capacitance capacitor CX1 of FIG. 31, and one end of the variable capacitance circuit 142 is connected to one end of the vibrator XTAL.

  The variable capacitance circuit 142 has its capacitance value controlled based on the frequency control data DDS from the processing unit 50. For example, the variable capacitance circuit 142 includes a plurality of capacitors (capacitor array) and a plurality of switch elements (switch array) whose on / off of each switch element is controlled based on the frequency control data DDS. Each switch element of the plurality of switch elements is electrically connected to each capacitor of the plurality of capacitors. Then, by turning on or off the plurality of switch elements, the number of capacitors connected to one end of the transducer XTAL among the plurality of capacitors is changed. Thereby, the capacitance value of the variable capacitance circuit 142 is controlled, and the capacitance value of one end of the vibrator XTAL changes. Accordingly, the capacitance value of the variable capacitance circuit 142 is directly controlled by the frequency control data DDS, and the oscillation frequency of the oscillation signal SSC can be controlled.

  As described above, in the method of this embodiment in which the frequency control data DDS is changed in units of k × LSB as shown in FIGS. 21 and 22, the D / A converter 80 is provided in the oscillation signal generation circuit 140 as shown in FIG. It can be realized even in a configuration that does not. Then, by changing the frequency control data DDS in units of k × LSB, it is possible to achieve the same effect as the method of the present embodiment described with reference to FIGS. 11 to 13, and the occurrence of frequency hopping in FIG. It is possible to suppress the occurrence of communication errors caused by frequency hopping. Also in the configuration of FIG. 39, the oscillation signal SSC can be generated by the direct digital synthesizer method.

  39, for example, the following equation (13) can be adopted as the equation corresponding to the equation (1) described with reference to FIGS. 12 and 13 in the method of the present embodiment.

DV <(FD / FR) × DFS (13)
That is, as described above, the frequency variable range of the oscillation frequency by the oscillation signal generation circuit 140 is FR, and the allowable frequency drift of the oscillation frequency within a predetermined period (TP) is FD. Further, the full scale value of the frequency control data DDS is assumed to be DFS. For example, when the number of bits of the frequency control data DDS is i, the full scale value DFS can be expressed as 2 ⁱ (0 to 2 ⁱ ), for example. However, the full scale value DFS is not limited to this. Further, a change value of the frequency control data DDS at the output interval of the frequency control data DDS of the processing unit 50 is assumed to be DV. This output interval corresponds to the TDAC in FIG. For example, in FIG. 21 and FIG. 22, the frequency control data DDS changes in units of k × LSB for each output interval. In this case, in this embodiment, DV <(FD / FR) × DFS holds as shown in the above equation (13).

  For example, the processing unit 50 changes the frequency control data DDS in the range of the full-scale value DFS and adjusts the oscillation frequency of the oscillation signal generation circuit 140 in the frequency variable range FR as shown in FIG. 6. The temperature compensation process of the oscillation frequency described in FIG. 7 is realized.

  However, when the change value DV in the output interval (TDAC) of the frequency control data DDS becomes large, for example, DV ≧ (FD / FR) × DFS, the frequency drift of the oscillation frequency becomes the allowable frequency drift FD. The frequency hopping as shown in FIG. 14 occurs.

  On the other hand, in the present embodiment, since the frequency control data DDS is changed with a small change value DV that satisfies the relationship DV <(FD / FR) × DFS, the occurrence of frequency hopping as shown in FIG. Can be suppressed. For example, as shown in FIGS. 21 and 22, occurrence of frequency hopping can be suppressed by changing the frequency control data DDS in units of k × LSB.

  Also in the above equation (13), it is desirable that the following equation (14) holds as in the above equation (2).

1/2 ⁱ <(FD / FR) (14)
In this case, i in the above equation (14) is the number of bits of the frequency control data DDS. The processing unit 50 outputs the frequency control data DDS with a high number of bits = i such that 1/2 ⁱ <(FD / FR) is satisfied, so that occurrence of frequency hopping can be suppressed.

  For example, when both sides of the above equation (14) are multiplied by the full scale value DFS of the frequency control data DDS, the following equation (15) is obtained.

DFS × 1/2 ⁱ <(FD / FR) × DFS (15)
DFS × 1/2 ⁱ that is the left side of the above equation (15) corresponds to 1 LSB of the frequency control data DDS. The above expressions (14) and (15) mean that DFS × 1/2 ⁱ corresponding to 1LSB is made smaller than (FD / FR) × DFS. Thus, if DFS × 1/2 ⁱ <(FD / FR) × DFS, the frequency drift of the oscillation frequency when the frequency control data DDS is changed in units of 1 LSB as shown in FIGS. The allowable frequency drift FD is not exceeded, and the occurrence of frequency hopping can be suppressed.

6). Oscillator, Electronic Device, Mobile Object FIG. 40 shows a configuration example of an oscillator 400 including the circuit device 500 of the present embodiment. As shown in FIG. 40, the oscillator 400 includes a vibrator 420 and a circuit device 500. The vibrator 420 and the circuit device 500 are mounted in the package 410 of the oscillator 400. The terminals of the vibrator 420 and the terminals (pads) of the circuit device 500 (IC) are electrically connected by the internal wiring of the package 410.

  In FIG. 41, the structural example of the electronic device containing the circuit apparatus 500 of this embodiment is shown. The electronic apparatus includes a circuit device 500 according to the present embodiment, a vibrator 420 such as a crystal vibrator, an antenna ATN, a communication unit 510, and a processing unit 520. An operation unit 530, a display unit 540, and a storage unit 550 can be included. An oscillator 400 is configured by the vibrator 420 and the circuit device 500. Note that the electronic apparatus is not limited to the configuration shown in FIG. 41, and various modifications such as omitting some of these components or adding other components are possible.

  41, for example, wearable devices such as a GPS built-in clock, a biological information measuring device (pulse meter, pedometer, etc.) or a head-mounted display device, a smartphone, a mobile phone, a portable game device, a notebook Various devices such as personal digital assistants (mobile terminals) such as PCs or tablet PCs, content providing terminals for distributing content, video equipment such as digital cameras or video cameras, or network-related equipment such as base stations or routers Can be assumed.

  The communication unit 510 (wireless circuit) performs processing of receiving data from the outside via the antenna ATN and transmitting data to the outside. The processing unit 520 performs electronic device control processing, various digital processing of data transmitted and received via the communication unit 510, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer.

  The operation unit 530 is for a user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information and can be realized by a display such as a liquid crystal or an organic EL. When a touch panel display is used as the operation unit 530, the touch panel display also functions as the operation unit 530 and the display unit 540. The storage unit 550 stores data, and the function can be realized by a semiconductor memory such as a RAM or a ROM, an HDD (hard disk drive), or the like.

  FIG. 42 shows an example of a moving object including the circuit device of this embodiment. The circuit device (oscillator) of this embodiment can be incorporated into various moving bodies such as a car, an airplane, a motorcycle, a bicycle, or a ship. The moving body is, for example, a device / device that moves on the ground, in the sky, or on the sea, including a drive mechanism such as an engine or motor, a steering mechanism such as a steering wheel or rudder, and various electronic devices (on-vehicle devices). FIG. 42 schematically shows an automobile 206 as a specific example of the moving object. The automobile 206 incorporates the circuit device of this embodiment and an oscillator (not shown) having a vibrator. The control device 208 is operated by a clock signal generated by this oscillator. The control device 208 controls the hardness of the suspension, for example, according to the posture of the vehicle body 207, and controls the brakes of the individual wheels 209. For example, automatic driving of the automobile 206 may be realized by the control device 208. The device in which the circuit device and the oscillator of this embodiment are incorporated is not limited to such a control device 208, and can be incorporated in various devices (on-vehicle devices) provided in a moving body such as the automobile 206. .

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Also, the configuration and operation of circuit devices, oscillators, electronic devices, moving objects, D / A conversion techniques, frequency control data processing techniques, processing section frequency control data output techniques, D / A conversion section voltage output techniques The frequency control method of the vibrator is not limited to that described in the present embodiment, and various modifications can be made.

XTAL ... vibrator, DACA to DACF ... D / A converter,
OPA-OPD, OPS ... operational amplifier, CX1-CX3 ... capacitor,
VTD ... temperature detection voltage, DTD ... temperature detection data, DDS ... frequency control data,
VQ: output voltage (frequency control voltage), SSC: oscillation signal,
T1, T2 ... first and second temperatures, DTD1, DTD2 ... first and second temperature detection data,
VC1, VC2 ... first and second control voltages, VDF ... differential voltage, VA ... voltage width,
TAD, TDAC ... period, TP ... predetermined period, FD ... allowable frequency drift,
FR: frequency variable range, VFS: full scale voltage,
DAT1, DAT2, ... 1st and 2nd data,
DESCRIPTION OF SYMBOLS 10 ... Temperature sensor part, 20 ... A / D conversion part, 22 ... Logic part, 23 ... Processing part,
24 ... register part, 26 ... analog part, 27 ... comparison part,
28 ... Temperature sensor unit amplifier, 50 ... Processing unit, 52 ... Control unit, 53 ... Determination unit,
54, 55 ... comparison unit, 58 ... multiplier, 59 ... adder, 60 ... calculation unit,
61, 62 ... type conversion unit, 63 ... multiplexer, 64 ... arithmetic unit,
65: Multiplexer, 66, 67 ... Work register, 68 ... Type converter,
69 ... Work register, 70 ... Output unit, 71 ... Multiplexer,
72 ... Output register, 73 ... LSB adder, 74 ... LSB subtractor,
80 ... D / A converter, 90 ... modulation circuit, 100 ... D / A converter,
104, 106 ... Decoder, 120 ... Filter circuit, 130 ... Filter circuit,
140 ... oscillation signal generation circuit, 142 ... variable capacitance circuit, 150 ... oscillation circuit,
160 ... buffer circuit, 180 ... memory unit, 190 ... ROM,
206 ... Automobile, 207 ... Car body, 208 ... Control device, 209 ... Wheel,
400: oscillator, 410 package, 420 ... vibrator, 500 ... circuit device,
510: Communication unit, 520 ... Processing unit, 530 ... Operation unit, 540 ... Display unit, 550 ... Storage unit

Claims (16)

An A / D converter that performs A / D conversion of the temperature detection voltage from the temperature sensor unit and outputs temperature detection data;
A processing unit that performs temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency;
An oscillation signal generation circuit that generates an oscillation signal of the oscillation frequency set by the frequency control data using the frequency control data and the vibrator from the processing unit;
Including
The frequency variable range of the oscillation frequency by the oscillation signal generation circuit is FR, the allowable frequency drift of the oscillation frequency within a predetermined period is FD, the full-scale value of the frequency control data is DFS, and the frequency of the processing unit A circuit device characterized in that DV <(FD / FR) × DFS, where DV is a change value of the frequency control data at an output interval of control data. The circuit device according to claim 1,
When the output frequency of the frequency control data of the processing unit is fs and the change in the oscillation frequency due to the change in the change value DV of the frequency control data is Δf, Δf / fs <1/10 ⁶ A circuit device characterized by the above. The circuit device according to claim 2,
In the case of fs ≧ 1 kHz, Δf / fs <1/10 ⁶
In the case of fs <1 kHz, Δf <1 mHz. The circuit device according to claim 1,
When the output frequency of the frequency control data of the processing unit is fs, and the change of the oscillation frequency due to the change in the change value DV of the frequency control data is Δf,
In the case of fs <1 kHz, Δf <1 mHz. The circuit device according to any one of claims 2 to 4,
The oscillation signal generation circuit includes:
A D / A converter that performs D / A conversion of the frequency control data from the processor;
An oscillation circuit that generates the oscillation signal using the output voltage of the D / A converter and the vibrator;
Including
fs corresponds to the sampling frequency of the D / A converter,
Δf is a circuit device in which the oscillation frequency is changed by one D / A conversion. The circuit device according to claim 5,
The D / A converter is
A D / A converter for performing D / A conversion of the frequency control data;
A filter circuit for smoothing the output voltage of the D / A converter;
A circuit device comprising: The circuit device according to claim 5 or 6,
1/2 ⁱ <(FD / FR) where the resolution of the D / A converter is i bits. The circuit device according to any one of claims 5 to 7,
The D / A converter is
A modulation circuit that receives the frequency control data of i = (n + m) bits from the processing unit and modulates the n-bit data of the frequency control data based on the m-bit data of the frequency control data; A circuit device. The circuit device according to any one of claims 1 to 8,
The circuit device, wherein the vibrator is a crystal vibrator. The circuit device according to claim 9, wherein
The crystal resonator is
A circuit device comprising an AT cut resonator, an SC cut resonator, or a SAW resonator. The circuit device according to any one of claims 1 to 10,
The processor is
When the temperature changes from the first temperature to the second temperature, from the first data corresponding to the first temperature to the second data corresponding to the second temperature, k × LSB (k ≧ 1) The circuit device that outputs the frequency control data that changes in units. The circuit device according to claim 11,
The processor is
Comparing the first data which is the calculation result data of the previous temperature compensation process and the second data which is the calculation result data of the current temperature compensation process;
When the second data is larger than the first data, a process of adding a predetermined value to the first data is performed until the addition result data reaches the second data. , Outputting the addition result data as the frequency control data,
When the second data is smaller than the first data, the process of subtracting a predetermined value from the first data is performed until the subtraction result data reaches the second data. A circuit device that outputs subtraction result data as the frequency control data. The circuit device according to claim 12, wherein
The processor is
An operation unit that performs the temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs the operation result data of the temperature compensation processing;
An output unit that receives the calculation result data from the calculation unit and outputs the frequency control data;
Including
The output unit is
When the calculation result data changes from the first data corresponding to the first temperature to the second data corresponding to the second temperature, the first data is converted from the first data in units of k × LSB. A circuit device that outputs the frequency control data that changes to second data. A circuit device according to any one of claims 1 to 13,
The vibrator;
An oscillator comprising:   An electronic apparatus comprising the circuit device according to claim 1.   A moving body comprising the circuit device according to claim 1.