JP2017083679A - Display device and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a display device which can make wiring resistance of a scan line low while improving light shielding property more than a conventional one and which comprises a TFT enabling a stable drive state to be obtained; and an electronic apparatus.SOLUTION: A liquid crystal display device 1 comprises: a substrate 10a; a substrate 20a; a liquid crystal layer 40; and a TFT 30 including a semiconductor layer 30a disposed on the substrate 10a for each pixel P, a gate insulation layer 11c covering the semiconductor layer 30a and a gate electrode 30g disposed to face a channel region 30c via the gate insulation layer 11c. The liquid crystal display device further comprises a lower side light-shielding layer 3b disposed on the substrate 10a so as to overlap the semiconductor layer 30a in a planar view and set at the same potential as the gate electrode 30g, an interlayer insulation layer 11a disposed to cover the lower side light-shielding layer 3b and an upper side light-shielding layer 3c disposed on the interlayer insulation layer 11a so as to overlap the semiconductor layer 30a and the lower side light-shielding layer 3b in a planar view and set at the same potential as the gate electrode 30g.SELECTED DRAWING: Figure 4B

Description

  The present invention relates to a display device and an electronic apparatus.

  There is known a display device including a liquid crystal or the like between an element substrate provided with a plurality of pixels and switching elements and a counter substrate disposed opposite to the element substrate. Examples of the display device include a liquid crystal display device used as a liquid crystal light valve of a projector.

  Powerful light from the light source is incident on the liquid crystal light valve. However, when light is applied to the semiconductor layer that constitutes the switching element, flicker and pixel unevenness occur in the display image due to light leakage current, which degrades the display quality. End up. For this reason, conventionally, the light shielding performance against incident light has been improved. In recent years, with the increase in the amount of light from the light source, an inorganic polarizing plate having a higher reflectance than the conventional case may be used, so that the light shielding property against the incident light from the side from which the light of the liquid crystal display is emitted (rear surface) is blocked. A technique for improving the above has been proposed (see, for example, Patent Document 1 and Patent Document 2).

  In Patent Document 1, a metal light-shielding film A, an insulating film (metal oxide film or metal nitride film) B, and a metal light-shielding film C are stacked below a semiconductor layer of an inverted staggered (bottom gate) TFT. A configuration in which scanning lines (gate wirings) are arranged is disclosed. Patent Document 2 discloses a configuration in which a first light-shielding film and a second light-shielding film are stacked via an insulating film between lower layers of a semiconductor layer, and the second light-shielding film is set to a gate potential or a constant voltage. ing.

  In addition, there is an increasing need for driving with a high-frequency drive signal in a large liquid crystal display device. On the other hand, in a small liquid crystal display device, a light shielding region is narrowed in order to achieve a high aperture ratio in a narrow pixel arrangement pitch. There is a tendency to become. Therefore, a technique for improving the light shielding property and reducing the wiring resistance has been proposed (see, for example, Patent Document 3). Patent Document 3 discloses a configuration in which a scanning line formed by laminating three layers of metal films is disposed below a semiconductor layer.

JP 2004-302475 A JP 2011-238835 A JP 2011-158700 A

  However, in Patent Document 1 and Patent Document 2, the two light shielding layers are insulated from each other, and the wiring resistance of the scanning line is not taken into consideration. Further, in Patent Document 3, a light shielding layer (scanning line) is composed of three layers of metal films stacked in contact with each other, and a layer having a different optical refractive index such as an insulating film is interposed between the light shielding layers. Compared to the case, there is a possibility that the light shielding property is not sufficient. Therefore, there is a demand for a display device that can reduce the wiring resistance of the scanning line while improving the light shielding performance.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A display device according to this application example includes a first substrate, a second substrate disposed opposite to the first substrate, and between the first substrate and the second substrate. A liquid crystal layer sandwiched between, a semiconductor layer including a channel region disposed on the first substrate for each pixel, a gate insulating layer covering the semiconductor layer, and the channel region via the gate insulating layer A switching element having a gate electrode disposed so as to face the first electrode, and overlaps the semiconductor layer on the first substrate in a plan view between the first substrate and the semiconductor layer. A first light-shielding layer that is disposed at the same potential as the gate electrode, a first insulating layer that is disposed to cover the first light-shielding layer, and the first insulating layer. Arranged so as to overlap the semiconductor layer and the first light-shielding layer in plan view. A second light-shielding layer that is set on the gate electrode at the same potential, characterized in that it comprises a second insulating layer disposed to cover the second light-shielding layer.

  According to the configuration of this application example, the first light shielding layer, the first insulating layer, the second light shielding layer, and the second insulating layer are arranged between the first substrate and the semiconductor layer. Therefore, the light incident from the first substrate side toward the semiconductor layer side is reflected at the interface between the first substrate and the first light shielding layer, and further, the first insulating layer and the second light shielding layer Therefore, light incident on the semiconductor layer from the first substrate side can be effectively shielded. In addition, since both the first light-shielding layer and the second light-shielding layer are set to the same potential as the gate electrode, a scanning line can be constituted by two light-shielding layers, and the gate wiring is arranged in the same layer as the gate electrode. In this case, since the scanning line can be constituted by three layers including the two light shielding layers, the wiring resistance of the scanning line can be reduced. As a result, it is possible to reduce the wiring resistance of the scanning lines while improving the light shielding performance as compared with the conventional case, and thus it is possible to provide a display device with high display quality.

  Application Example 2 In the display device according to the application example, it is preferable that the first light shielding layer and the second light shielding layer are formed across the pixels.

  According to the configuration of this application example, since the first light shielding layer and the second light shielding layer constituting the scanning line are formed across the pixels, even when the display device is large and the scanning line is long. Further, it is possible to reduce the wiring resistance of the scanning line while improving the light shielding property.

  Application Example 3 In the display device according to the application example, the first light shielding layer or the second light shielding layer may be divided for each pixel.

  In the case where the display device is not large and reduction in wiring resistance is not so important, it may be configured such that either one of the light shielding layers is divided for each pixel.

  Application Example 4 In the display device according to the application example described above, a first contact that penetrates the first insulating layer and electrically connects the first light shielding layer and the second light shielding layer. A hole and a second contact hole, and the first contact hole and the second contact hole are arranged on both sides of the semiconductor layer in a direction intersecting with the extending direction of the semiconductor layer in plan view. It is preferable that

  According to the configuration of this application example, the pair of light shielding portions along the normal direction of the first substrate between the first light shielding layer and the second light shielding layer by the contact hole penetrating the first insulating layer. The pair of light shielding portions are disposed on both sides of the semiconductor layer in plan view. Therefore, the light incident obliquely with respect to the normal direction of the first substrate from the first substrate side, or the light reflected and propagated between the first light shielding layer and the second light shielding layer, Since the light shielding portion formed by the contact hole can shield light from both sides of the semiconductor layer, the light shielding property can be further improved.

  Application Example 5 In the display device according to the application example, the second light shielding layer is formed so as to fill the first contact hole and the second contact hole, and has a substantially flat surface. It is preferable to have.

  According to the configuration of this application example, the second light shielding layer having a substantially flat surface is formed on the first insulating layer by filling the pair of contact holes penetrating the first insulating layer. Therefore, when forming a contact hole for electrical connection with the second light-shielding layer from the upper layer side (gate electrode side), the position where the contact hole is arranged is not restricted. Can be increased.

  Application Example 6 In the display device according to the application example described above, the display device penetrates the gate insulating layer and the second insulating layer and electrically connects the gate electrode and the second light shielding layer. 3 contact holes and a fourth contact hole, the third contact hole is disposed so as to overlap the first contact hole in a plan view, and the fourth contact hole is the second contact hole. It is preferable that they are arranged so as to overlap the contact holes in plan view.

  According to the configuration of this application example, the pair of contact holes penetrating the first insulating layer and electrically connecting the first light shielding layer and the second light shielding layer, the gate insulating layer, and the second insulating layer And a pair of contact holes that electrically connect the gate electrode and the second light shielding layer so as to overlap each other in plan view. Therefore, the area shielded by the contact hole can be reduced, so that the aperture ratio of the display device can be improved. In addition, a pair of light shielding portions along the normal direction of the first substrate is formed by a contact hole penetrating the gate insulating layer and the second insulating layer, and the pair of light shielding portions are formed on both sides of the semiconductor layer in plan view. Therefore, the light shielding property can be further improved.

  Application Example 7 In the display device according to the application example, a fifth contact that penetrates the first insulating layer and electrically connects the first light shielding layer and the second light shielding layer. The second light-shielding layer has a hole and is located at a bottom portion and a side portion of the fifth contact hole and outside the fifth contact hole in a cross-sectional view along the extending direction of the semiconductor layer. Preferably, the semiconductor layer is disposed so as to cover the second light shielding layer with the second insulating layer interposed therebetween. .

  According to the configuration of this application example, in the cross-sectional view along the extending direction of the semiconductor layer, the bottom portion of the contact hole that penetrates the first insulating layer, the side portion thereof, and the first insulating layer on the outer side thereof The second light shielding layer is disposed over the surface of the semiconductor layer, and the semiconductor layer is disposed so as to cover the second light shielding layer with the second insulating layer interposed therebetween. Therefore, the substantial length of the semiconductor layer can be made longer than the length in plan view. In other words, the length of the semiconductor layer in plan view can be shortened with respect to the required length of the semiconductor layer, so that the light shielding region can be reduced and the aperture ratio of the display device can be improved.

  Application Example 8 In the display device according to the application example described above, it is preferable that at least the channel region of the semiconductor layer is disposed at the bottom of the fifth contact hole.

  According to the configuration of this application example, at least the channel region of the semiconductor layer is disposed at the bottom of the contact hole, so that the channel length can be ensured even when the display device is small. When the LDD regions are provided on both sides of the channel region, the LDD region can be disposed within a range extending from the bottom of the contact hole to the outside through the side, and thus a sufficient LDD region can be secured. . Therefore, a switching element having excellent operating characteristics can be formed. In addition, since the second light-shielding layer disposed below the semiconductor layer is disposed so as to cover the bottom and side portions where the channel region is disposed and the surface of the first insulating layer outside the channel region, Light incident on the region can be effectively blocked.

  Application Example 9 In the display device according to the application example described above, the display device penetrates through the gate insulating layer and the second insulating layer and electrically connects the gate electrode and the second light shielding layer. 3 and 4, wherein the third contact hole and the fourth contact hole are in the direction intersecting the extending direction of the semiconductor layer in plan view. It is preferable that it is arrange | positioned at both sides.

  According to the configuration of this application example, the pair of light shielding portions along the normal direction of the first substrate is formed by the contact hole penetrating the gate insulating layer and the second insulating layer. Arranged on both sides of the semiconductor layer in plan view. For this reason, light incident obliquely from the first substrate side with respect to the normal direction of the first substrate or light reflected and propagated between the gate electrode and the second light shielding layer is transmitted through the contact hole. Since the formed light shielding part can shield light from both sides of the semiconductor layer, the light shielding property can be further improved.

  Application Example 10 In the display device according to the application example described above, a plurality of contact holes penetrating the first insulating layer and electrically connecting the first light shielding layer and the second light shielding layer are provided. And the number of the contact holes may be smaller than the number of the pixels.

  In the case where the first light shielding layer and the second light shielding layer are formed across the pixels, the number of contact holes may be smaller than the number of pixels.

  Application Example 11 An electronic apparatus according to this application example includes the display device according to the application example.

  According to the configuration of this application example, it is possible to provide an electronic apparatus including a display device having stable display quality.

1 is a schematic plan view showing a configuration of a liquid crystal display device according to a first embodiment. FIG. 1B is a schematic cross-sectional view taken along line H-H ′ of FIG. 1A. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal display device according to the first embodiment. 1 is a schematic cross-sectional view showing a structure of an element substrate of a liquid crystal display device according to a first embodiment. FIG. 2 is a schematic plan view showing a configuration of a TFT portion of the element substrate according to the first embodiment. FIG. 4B is a schematic sectional view taken along line A-A ′ of FIG. 4A. The graph which shows the light-shielding effect of the element substrate which concerns on 1st Embodiment. The schematic plan view which shows the structure of the TFT part of the element substrate which concerns on 2nd Embodiment. FIG. 6B is a schematic sectional view taken along line A-A ′ of FIG. 6A. The schematic plan view which shows the structure of the TFT part of the element substrate which concerns on 3rd Embodiment. FIG. 7B is a schematic cross-sectional view taken along line A-A ′ of FIG. 7A. The schematic plan view which shows the structure of the TFT part of the element substrate which concerns on 4th Embodiment. FIG. 8B is a schematic sectional view taken along line B-B ′ of FIG. 8A. Schematic which shows the structure of the projector as an electronic device which concerns on 5th Embodiment. The schematic plan view which shows the structural example of the TFT part of the conventional element substrate. FIG. 10A is a schematic sectional view taken along line A-A ′ of FIG. 10A.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. The drawings to be used are appropriately enlarged, reduced or exaggerated so that the part to be described can be recognized. In addition, illustrations of components other than those necessary for the description may be omitted.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

(First embodiment)
<Liquid crystal display device>
Here, an active matrix liquid crystal display device including a thin film transistor (TFT) as a pixel switching element will be described as an example of the display device. This liquid crystal display device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (projector) described later.

  First, a liquid crystal display device as a display device according to the first embodiment will be described with reference to FIGS. 1A and 1B. FIG. 1A is a schematic plan view showing the configuration of the liquid crystal display device according to the first embodiment. 1B is a schematic cross-sectional view taken along line H-H ′ of FIG. 1A. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal display device according to the first embodiment.

  As shown in FIGS. 1A and 1B, the liquid crystal display device 1 according to the first embodiment includes an element substrate 10, a counter substrate 20 disposed opposite to the element substrate 10, and the element substrate 10 and the counter substrate 20. And a liquid crystal layer 40 disposed therebetween. For the substrate 10a as the first substrate constituting the element substrate 10 and the substrate 20a as the second substrate constituting the counter substrate 20, for example, a substrate made of a light transmissive material such as glass or quartz. Is used.

  The element substrate 10 is slightly larger than the counter substrate 20, and both the substrates are joined via a sealing material 42 arranged in a frame shape. The liquid crystal layer 40 is made of liquid crystal having positive or negative dielectric anisotropy enclosed in a space surrounded by the element substrate 10, the counter substrate 20, and the sealing material 42.

  The sealing material 42 is made of an adhesive such as a thermosetting or ultraviolet curable epoxy resin. Spacers (not shown) are mixed in the sealing material 42 to keep the distance between the element substrate 10 and the counter substrate 20 constant. A frame-shaped light shielding layer 21 provided on the counter substrate 20 is disposed inside the seal material 42 disposed in a frame shape. The light shielding layer 21 is made of, for example, a light shielding metal or metal oxide.

  Inside the light shielding layer 21 is a display area E in which a plurality of pixels P are arranged. The display area E is an area that substantially contributes to display in the liquid crystal display device 1. Although not shown in FIGS. 1A and 1B, in the display area E, a lattice-shaped light shielding portion that partitions a plurality of pixels P in a plane is provided on the counter substrate 20, for example.

  A data line driving circuit 51 and a plurality of external connection terminals 54 are provided along one side portion outside the sealing material 42 on one side portion of the element substrate 10. Further, an inspection circuit 53 is provided inside the sealing material 42 along the other one side facing the one side. Further, a scanning line driving circuit 52 is provided inside the sealing material 42 along the other two sides that are orthogonal to these two sides and face each other.

  A plurality of wirings 55 that connect the two scanning line driving circuits 52 are provided inside the sealing material 42 on one side where the inspection circuit 53 is provided. Wirings connected to the data line driving circuit 51 and the scanning line driving circuit 52 are connected to a plurality of external connection terminals 54. In addition, a vertical conduction portion 56 for providing electrical conduction between the element substrate 10 and the counter substrate 20 is provided at a corner portion of the counter substrate 20. The arrangement of the inspection circuit 53 is not limited to this, and the inspection circuit 53 may be provided at a position along the inner side of the seal material 42 between the data line driving circuit 51 and the display area E.

  In the following description, the direction along one side where the data line driving circuit 51 is provided is defined as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other is defined as the Y direction. . The direction of the H-H ′ line in FIG. 1A is a direction along the Y direction. Further, a direction perpendicular to the X direction and the Y direction and directed upward in FIG. 1B is defined as a Z direction. In the present specification, viewing from the normal direction (Z direction) of the surface of the counter substrate 20 of the liquid crystal display device 1 is referred to as “plan view”.

  As shown in FIG. 1B, on the surface of the substrate 10a on the liquid crystal layer 40 side, a TFT 30 (see FIG. 2) as a switching element provided for each pixel P, a light-transmissive pixel electrode 15, and a signal wiring (Not shown) and an alignment film 18 covering the pixel electrode 15 are provided. The pixel electrode 15 is made of a light-transmitting conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

  Further, the element substrate 10 of the present embodiment employs a light shielding structure that prevents light from entering the semiconductor layer 30a (see FIG. 4A) of the TFT 30 to make the switching operation unstable. The light shielding structure will be described later.

  A light shielding layer 21, an interlayer 22, a common electrode 23, and an alignment film 24 that covers the common electrode 23 are provided on the liquid crystal layer 40 side of the counter substrate 20.

  As shown in FIGS. 1A and 1B, the light shielding layer 21 is provided in a frame shape at a position that overlaps the scanning line driving circuit 52, the plurality of wirings 55, and the inspection circuit 53 in a plan view. The light shielding layer 21 serves to shield light incident from the counter substrate 20 side and prevent malfunction caused by light in peripheral circuits including these drive circuits. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

The interlayer 22 shown in FIG. 1B is formed so as to cover the light shielding layer 21. The interlayer 22 is formed of an insulating film such as silicon oxide (SiO ₂ ), for example, and has optical transparency. The interlayer layer 22 is provided so that unevenness caused by the light shielding layer 21 and the like is alleviated and the surface on the liquid crystal layer 40 side on which the common electrode 23 is formed is flat. Examples of the method for forming the interlayer 22 include a method of forming a film using a plasma CVD (Chemical Vapor Deposition) method.

  The common electrode 23 is made of a light-transmitting conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), for example, covers the interlayer layer 22 and is formed at the four corners of the counter substrate 20 as shown in FIG. 1A. The vertical conductive portion 56 provided is electrically connected to the wiring on the element substrate 10 side.

  The alignment film 18 and the alignment film 24 are selected based on the optical design of the liquid crystal display device 1. For example, the alignment film 18 and the alignment film 24 are formed by depositing an organic material such as polyimide and rubbing the surface thereof, so that liquid crystal molecules are subjected to a substantially horizontal alignment process, or SiOx (silicon oxide). ) And the like formed by using a vapor phase growth method and aligned substantially perpendicularly to the liquid crystal molecules.

  The liquid crystal constituting the liquid crystal layer 40 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. For example, in the normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each pixel P. In the normally black mode, the transmittance for incident light increases according to the voltage applied in units of each pixel P, and light having a contrast corresponding to an image signal is emitted from the liquid crystal display device 1 as a whole. .

  As shown in FIG. 2, in the display area E, gate lines (scanning lines) 3a and data lines 6a are formed so as to be insulated and intersect with each other. The direction in which the gate line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction. The pixel P is provided corresponding to the intersection of the gate line 3a and the data line 6a. Each pixel P is provided with a pixel electrode 15 and a TFT 30 (Thin Film Transistor) as a switching element.

  The source electrode 31 (see FIG. 3) of the TFT 30 is electrically connected to the data line 6a. The data line 6a is connected to the data line driving circuit 51 (see FIG. 1A), and supplies image signals (data signals) S1, S2,..., Sn supplied from the data line driving circuit 51 to the pixels P. The image signals S1, S2,..., Sn supplied from the data line driving circuit 51 to the data lines 6a may be supplied in line order in this order, and for each group of data lines 6a adjacent to each other. You may supply.

  A gate electrode 30g (see FIG. 3) of the TFT 30 is electrically connected to a gate wiring (scanning line) 3a. In the present embodiment, the gate electrode 30g is a part of the gate wiring (scanning line) 3a. The gate wiring (scanning line) 3a is connected to the scanning line driving circuit 52 (see FIG. 1A), and supplies scanning signals G1, G2,..., Gm supplied from the scanning line driving circuit 52 to each pixel P. . The scanning line driving circuit 52 supplies the scanning signals G1, G2,..., Gm to the gate wiring (scanning line) 3a in a pulse-sequential manner at a predetermined timing. The drain electrode 32 (see FIG. 3) of the TFT 30 is electrically connected to the pixel electrode 15.

  The image signals S1, S2,..., Sn are written to the pixel electrode 15 through the data line 6a at a predetermined timing by turning on the TFT 30 for a certain period. The image signal of a predetermined level written in the liquid crystal layer 40 through the pixel electrode 15 in this way is constant by the liquid crystal capacitance formed between the common electrode 23 (see FIG. 1B) provided on the counter substrate 20. Hold for a period.

  In order to prevent the held image signals S1, S2,..., Sn from leaking, a storage capacitor 16 is formed between the capacitor line 16a and the pixel electrode 15 formed in parallel along the data line 6a. And arranged in parallel with the liquid crystal capacitor. Thus, when a voltage signal is applied to the liquid crystal of each pixel P, the alignment state of the liquid crystal changes depending on the applied voltage level. As a result, the light incident on the liquid crystal layer 40 (see FIG. 1B) is modulated to enable gradation display.

  Note that a data line 6a is connected to the inspection circuit 53 shown in FIG. 1A, and an operation defect or the like of the liquid crystal display device 1 can be confirmed by detecting the image signal in the manufacturing process of the liquid crystal display device 1. Although it is configured, it is omitted in the equivalent circuit of FIG. The inspection circuit 53 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

<Element substrate>
FIG. 3 is a schematic cross-sectional view showing the structure of the element substrate of the liquid crystal display device according to the first embodiment. As shown in FIG. 3, the element substrate 10 includes a substrate 10a as a first substrate, a lower light shielding layer 3b as a first light shielding layer, an interlayer insulating layer 11a as a first insulating layer, The upper light-shielding layer 3c as the second light-shielding layer, the interlayer insulating layer 11b as the second insulating layer, the TFT 30, the data line 6a, the storage capacitor 16, and the pixel electrode 15 are provided.

  The lower light shielding layer 3b is formed on the substrate 10a. The lower light-shielding layer 3b is a single metal containing at least one of metals such as Al (aluminum), Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). , Alloy, metal silicide, polysilicide, nitride, or a laminate of these, and has conductivity and light shielding properties. The film thickness of the lower light shielding layer 3b is, for example, about 200 nm.

  An interlayer insulating layer 11a is formed so as to cover the substrate 10a and the lower light-shielding layer 3b. The interlayer insulating layer 11a is made of, for example, a silicon oxide film. The film thickness of the interlayer insulating layer 11a is, for example, about 300 nm to 400 nm.

  The upper light shielding layer 3c is formed on the interlayer insulating layer 11a. The upper light-shielding layer 3c is made of a metal simple substance containing at least one of the same metals as the lower light-shielding layer 3b, an alloy, a metal silicide, a polysilicide, a nitride, or a laminate of these. It has sex. The film thickness of the upper light shielding layer 3c is, for example, about 100 nm. The lower light-shielding layer 3b and the upper light-shielding layer 3c serve to shield light incident from the substrate 10a side and also serve as scanning lines.

  An interlayer insulating layer 11b is formed so as to cover the interlayer insulating layer 11a and the upper light shielding layer 3c. The interlayer insulating layer 11b is made of, for example, a silicon oxide film. The film thickness of the interlayer insulating layer 11b is, for example, about 300 nm to 400 nm.

  A TFT 30 is provided on the interlayer insulating layer 11b. The TFT 30 includes a semiconductor layer 30a, a gate insulating layer 11c, a gate electrode 30g, a source electrode 31, and a drain electrode 32. The semiconductor layer 30a is formed in an island shape on the interlayer insulating layer 11b. The semiconductor layer 30a is made of, for example, a polycrystalline silicon film and is implanted with N-type impurity ions such as P (phosphorus) ions.

  The semiconductor layer 30a includes a data line side source / drain region (hereinafter referred to as a source region) 30s, a pixel electrode side source / drain region (hereinafter referred to as a drain region) 30d, a channel region 30c, a source region 30s and a channel region. An LDD (Lightly Doped Drain) structure having a data line side LDD region 30e provided between the pixel region 30c and a pixel electrode side LDD region 30f provided between the channel region 30c and the drain region 30d. ing. The film thickness of the semiconductor layer 30a is, for example, about 50 nm.

  The channel region 30c is doped with P-type impurity ions such as B (boron) ions. The source region 30s, the drain region 30d, the data line side LDD region 30e, and the pixel electrode side LDD region 30f are doped with N-type impurity ions such as P (phosphorus) ions. With such a configuration, the TFT 30 is formed as an N-type TFT.

  The gate insulating layer 11c is formed so as to cover the interlayer insulating layer 11b and the semiconductor layer 30a. The gate insulating layer 11c is made of, for example, a silicon oxide film. The gate electrode 30g is formed on the gate insulating layer 11c so as to face the channel region 30c with the gate insulating layer 11c interposed therebetween. The gate electrode 30g (gate wiring 3a) is made of, for example, a polycrystalline silicon film.

  An interlayer insulating layer 11d is formed so as to cover the gate insulating layer 11c and the gate electrode 30g. The interlayer insulating layer 11d is made of, for example, a silicon oxide film. A contact hole CH1 penetrating the interlayer insulating layer 11d and the gate insulating layer 11c is formed at a position overlapping the end of the semiconductor layer 30a on the source region 30s side. Further, a contact hole CH2 penetrating the interlayer insulating layer 11d and the gate insulating layer 11c is formed at a position overlapping with the end portion on the drain region 30d side.

  A data line 6a and a relay electrode 6b are formed on the interlayer insulating layer 11d. The data line 6a and the relay electrode 6b are, for example, a single metal containing at least one of metals such as Al, Ti, Cr, W, Ta, and Mo, an alloy, a metal silicide, a polysilicide, a nitride, or a laminate thereof. It has a conductivity and a light shielding property.

  The data line 6a and the relay electrode 6b are obtained, for example, by forming a conductive film using the same material and patterning the conductive film. Further, the source electrode 31 is formed by filling the contact hole CH1 with the material forming the data line 6a and the relay electrode 6b, and the drain electrode 32 is formed by filling the contact hole CH2.

  An interlayer insulating layer 11e is formed so as to cover the data line 6a, the relay electrode 6b, and the interlayer insulating layer 11d. The interlayer insulating layer 11e is made of, for example, silicon oxide or nitride. The interlayer insulating layer 11e is subjected to a flattening process for flattening surface irregularities caused by covering the region where the TFT 30 is provided. Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating.

  In the interlayer insulating layer 11e, a contact hole CH3 penetrating the interlayer insulating layer 11e is formed at a position overlapping the relay electrode 6b. A capacitor line 16a (COM potential) that forms part of the storage capacitor 16 is formed on the interlayer insulating layer 11e. The capacitor line 16a has, for example, a laminated structure in which an Al (aluminum) film is disposed in the lower layer and a TiN (titanium nitride) film is disposed in the upper layer.

  A capacitive insulating film 16b made of alumina, a silicon nitride film or the like is formed so as to cover the capacitive line 16a. In addition, a stopper film 16c1 made of a silicon oxide film or the like is formed in the vicinity of the region overlapping the contact hole CH4 region in plan view on the capacitor insulating film 16b. The stopper film 16c1 may be formed before the capacitor insulating film 16b is formed, that is, between the capacitor line 16a and the capacitor insulating film 16b.

  On the stopper film 16c1, the capacitor insulating film 16b, and the interlayer insulating layer 11e, a capacitor electrode 16c constituting a part of the storage capacitor 16 is formed so as to overlap the relay electrode 6b in a plan view. The capacitor electrode 16c is formed by forming a conductive film using a light-shielding conductive part material such as Al (aluminum) and patterning the conductive film. Note that the capacitor electrode 16c and the capacitor electrode 16c adjacent to each other are patterned on the stopper film 16c1 described above.

  The capacitive electrode 16c is also formed inside the contact hole CH3. Thereby, the capacitive electrode 16c is electrically connected to the relay electrode 6b via the contact hole CH3 and is electrically connected to the drain electrode 32. The capacitor electrode 16c also serves as a relay electrode that electrically connects the relay electrode 6b and the pixel electrode 15 via the contact hole CH3.

  An interlayer insulating layer 11f is formed on the capacitor electrode 16c. The interlayer insulating layer 11f is made of, for example, silicon oxide or nitride. The interlayer insulating layer 11f may be subjected to a planarization process similarly to the interlayer insulating layer 11e. A contact hole CH4 penetrating the interlayer insulating layer 11f is formed at a position overlapping the capacitor electrode 16c. The contact hole CH4 is formed, for example, at a position overlapping the stopper film 16c1 in plan view in the capacitor electrode 16c.

  The pixel electrode 15 is formed on the interlayer insulating layer 11f so as to overlap the capacitor electrode 16c and the contact hole CH4 in plan view. The pixel electrode 15 is formed of a transparent conductive film such as ITO, and is also formed inside the contact hole CH4. Thereby, the pixel electrode 15 is electrically connected to the capacitor electrode 16c through the contact hole CH4, and is electrically connected to the drain electrode 32 through the contact hole CH3 and the relay electrode 6b.

<Light shielding structure of element substrate>
When the liquid crystal display device 1 shown in FIG. 1B is used as a liquid crystal light valve of a projector, light emitted from a light source enters from the counter substrate 20 side, passes through the liquid crystal layer 40, and is emitted to the element substrate 10 side. The In the element substrate 10 shown in FIG. 3, the capacitor electrode 16c, the data line 6a, and the relay electrode 6b shield light incident on the semiconductor layer 30a from the counter substrate 20 side (upper side in FIG. 3), and the TFT 30 is exposed to light. It plays a role in preventing malfunction.

  In recent years, with the increase in the amount of light from the light source, an inorganic polarizing plate having a higher reflectance than the conventional case may be used, and the reflected light incident from the element substrate 10 side (back surface) from which the light of the liquid crystal display device 1 is emitted. Therefore, it is required to improve the light-shielding property against the above. In addition, there is an increasing need for driving with a high-frequency drive signal in a large-sized liquid crystal display device having a diagonal size of about 1 inch, and it is also required to reduce the wiring resistance of the gate wiring 3a.

  Therefore, the liquid crystal display device 1 according to the present embodiment includes a light shielding structure that shields light incident from the element substrate 10 side (back surface), and the light shielding structure also serves to lower the wiring resistance of the scanning line. Below, the light-shielding structure with which the liquid crystal display device 1 is provided is demonstrated with reference to FIG. 4A and FIG. 4B.

  FIG. 4A is a schematic plan view showing the configuration of the TFT portion of the element substrate according to the first embodiment. FIG. 4B is a schematic cross-sectional view along the line A-A ′ of FIG. 4A. A line A-A ′ in FIG. 4A is a line along the X direction that intersects the direction in which the semiconductor layer 30 a extends. In FIG. 4A and FIG. 4B, illustration of the components above the gate electrode 30g (gate wiring 3a) is omitted.

  4A shows an intersection of the gate wiring 3a extending along the X direction and the data line 6a extending along the Y direction (see FIG. 2) in the element substrate 10 according to the first embodiment. The parts are shown. The semiconductor layer 30a of the TFT 30 extends on both sides of the intersection between the gate wiring 3a and the data line 6a along the Y direction, and is disposed so as to overlap the data line 6a in plan view. A portion of the gate wiring 3a that overlaps the channel region 30c of the semiconductor layer 30a in plan view is a gate electrode 30g. That is, the gate electrode 30g overlaps the channel region 30c of the semiconductor layer 30a in plan view.

  The lower light-shielding layer 3b and the upper light-shielding layer 3c are arranged so as to overlap with the gate wiring 3a in plan view, and are provided across the pixels P (see FIG. 1A) in the X direction. The lower light-shielding layer 3b and the upper light-shielding layer 3c are arranged so as to overlap at least the channel region 30c of the semiconductor layer 30a in plan view at the intersection between the gate wiring 3a and the data line 6a.

  As described above, by providing the TFT 30 in the vicinity of the intersection of the non-opening regions having the light shielding property between the pixels P, the TFT 30 is prevented from malfunctioning in light and the aperture ratio in the opening region of the pixels P is secured. .

  As shown in FIGS. 4A and 4B, on both outer sides in the X direction of the semiconductor layer 30a (channel region 30c), a contact hole CH5 as a third contact hole penetrating the gate insulating layer 11c and the interlayer insulating layer 11b. And a contact hole CH6 as a fourth contact hole is formed. By filling the contact holes CH5 and CH6 with a material for forming the gate electrode 30g (gate wiring 3a), the gate electrode 30g (gate wiring 3a) and the upper light shielding layer 3c are electrically connected.

  Further, on both outer sides in the X direction of the semiconductor layer 30a (channel region 30c), there are a contact hole CH7 as a first contact hole penetrating the interlayer insulating layer 11a and a contact hole CH8 as a second contact hole. Is formed. The contact hole CH7 is disposed outside the contact hole CH5 with respect to the semiconductor layer 30a, and the contact hole CH8 is disposed outside the contact hole CH6.

  By filling the contact holes CH7 and CH8 with a material forming the upper light-shielding layer 3c, the upper light-shielding layer 3c electrically connected to the gate electrode 30g (gate wiring 3a) and the lower light-shielding layer 3b are electrically connected. It is connected. That is, the upper light shielding layer 3c and the lower light shielding layer 3b are both set to the same potential as the gate electrode 30g. Therefore, a scanning line is constituted by three layers of the gate wiring 3a, the upper light shielding layer 3c, and the lower light shielding layer 3b.

  Note that the positions of the contact holes CH7 and CH8 are not particularly limited. However, since depressions may be formed at the positions of the contact holes CH7 and CH8 on the surface of the upper light-shielding layer 3c, the contact holes CH7 and CH8 are the upper layer contacts in plan view. It is preferable that they are arranged so as not to overlap with the holes CH5 and CH6.

  In the element substrate 10 according to the first embodiment, the upper light shielding layer 3c and the lower light shielding layer 3b are disposed between the semiconductor layer 30a and the substrate 10a so as to overlap the semiconductor layer 30a in plan view. . Therefore, it is possible to shield light incident on the semiconductor layer 30a from the substrate 10a side.

  Then, on both outer sides of the semiconductor layer 30a, a pair of light shielding portions along the Z direction formed by contact holes CH5 and CH6 penetrating the interlayer insulating layer 11b below the semiconductor layer 30a, and further below the upper light shielding layer 3c A pair of light shielding portions along the Z direction formed by contact holes CH7 and CH8 penetrating the interlayer insulating layer 11a is disposed. Therefore, light incident obliquely with respect to the Z direction from the substrate 10a side or reflected and propagated between the gate wiring 3a and the upper light shielding layer 3c or between the upper light shielding layer 3c and the lower light shielding layer 3b. Light can be shielded from both outer sides of the semiconductor layer 30a.

  Here, the light shielding effect of the element substrate 10 according to the first embodiment will be described in comparison with an element substrate having a conventional configuration. FIG. 5 is a graph showing the light shielding effect of the element substrate according to the first embodiment. FIG. 10A is a schematic plan view illustrating a configuration example of a TFT portion of a conventional element substrate. FIG. 10B is a schematic cross-sectional view along the line A-A ′ of FIG. 10A. In FIG. 10A and FIG. 10B, illustration of constituent elements above the gate electrode 30g (gate wiring 3a) is omitted.

  The conventional element substrate 60 shown in FIG. 10A and FIG. 10B has one light shielding layer (lower light shielding layer) disposed between the semiconductor layer 30a and the substrate 10a with respect to the element substrate 10 according to the first embodiment. Only the layer 3b) is different. The film thickness of the lower light-shielding layer 3b is about 200 nm, similar to the element substrate 10. The lower light-shielding layer 3b is electrically connected to the gate electrode 30g (gate wiring 3a) through the contact holes CH5 and CH6. That is, in the conventional element substrate 60, a scanning line is constituted by two layers of the gate wiring 3a and the lower light shielding layer 3b.

  As shown in FIG. 10B, in the conventional element substrate 60, a part of the incident light L incident obliquely with respect to the normal direction (Z direction) of the substrate 10a from the substrate 10a side is shielded from the substrate 10a and the lower side. Reflected at the interface with the layer 3b, the other part is absorbed and transmitted by the lower light-shielding layer 3b, and part of the transmitted light is incident on the channel region 30c of the semiconductor layer 30a. On the other hand, as shown in FIG. 4B, in the element substrate 10 according to the first embodiment, the incident light L incident from the substrate 10a side is reflected at the interface between the substrate 10a and the lower light shielding layer 3b. Further, part of the light transmitted through the lower light-shielding layer 3b is reflected at the interface between the interlayer insulating layer 11a and the upper light-shielding layer 3c. Therefore, the light incident on the channel region 30c of the semiconductor layer 30a can be shielded more effectively.

  In FIG. 5, the horizontal axis represents the wavelength (nm) of the incident light L, and the vertical axis represents the transmittance (%) of the incident light L that passes through the light shielding layer. The light shielding layer 1 layer (film thickness 200 nm) shown in FIG. 5 is the transmittance in the configuration of the element substrate 60, and the light shielding layer 2 layer (film thickness 100 nm + 200 nm) is the transmittance in the configuration of the element substrate 10 according to the first embodiment. It is. Further, the two light shielding layers (film thickness 100 nm + 100 nm) are transmittances in a comparative example in which the film thickness of the lower light shielding layer 3b on the element substrate 10 is 100 nm.

  As shown in FIG. 5, the transmittance in the configuration of the element substrate 10 according to the first embodiment is remarkably lower than the transmittance in the configuration of the conventional element substrate 60. This indicates that the light-shielding property is improved as compared with the prior art by further providing the upper light-shielding layer 3c between the semiconductor layer 30a and the lower light-shielding layer 3b.

  In the comparative example in which the film thickness of the lower light-shielding layer 3b is 100 nm on the element substrate 10, the total film thickness of the two light-shielding layers is 200 nm, which is the same as that of the conventional element substrate 60. The rate is lower than the transmittance in the configuration of the conventional element substrate 60. This is because even if the film thickness (total) of the light shielding layers is the same, interfacial reflection increases when two light shielding layers are arranged with an interlayer insulating layer (interlayer insulating layer 11a) interposed therebetween. It shows that the light shielding property is improved as compared with the conventional case. In FIG. 5, the range of the horizontal axis is the substantially central portion of the visible light wavelength range, but the above-described transmission magnitude relationship is substantially the same in the entire visible light wavelength range.

  In the configuration of the element substrate 10 according to the first embodiment, if both the lower light-shielding layer 3b and the upper light-shielding layer 3c have a thickness of 200 nm (two layers are 200 nm + 200 nm), further improvement in light-shielding properties can be expected. Since the step generated in the upper layer due to the two light shielding layers becomes large, it is preferable to set the film thickness of the upper light shielding layer 3c to 100 nm.

  Further, in the conventional element substrate 60, the scanning line is constituted by two layers of the gate wiring 3a and the lower light shielding layer 3b, whereas in the element substrate 10 according to the first embodiment, the gate wiring 3a and the lower side are formed. Since the scanning line is constituted by three layers of the light shielding layer 3b and the upper light shielding layer 3c, the wiring resistance of the scanning line can be suppressed to be lower than that of the related art. Therefore, even if the liquid crystal display device 1 is a large-sized liquid crystal display device driven by a high-frequency drive signal, the light resistance against the incident light L incident from the substrate 10a side is improved as compared with the conventional case, and the wiring resistance of the scanning line is reduced. Can be lowered.

  Since the lower light-shielding layer 3b and the upper light-shielding layer 3c are provided across the pixels P, the contact holes CH7 and CH8 that electrically connect the lower light-shielding layer 3b and the upper light-shielding layer 3c are It may not be provided for each pixel P. That is, when the lower light-shielding layer 3b and the upper light-shielding layer 3c are formed across the pixels P, the number of contact holes CH7 and CH8 may be smaller than the number of pixels P.

  As described above, according to the configuration of the element substrate 10 according to the first embodiment, the following effects can be obtained.

  (1) The lower light-shielding layer 3b, the interlayer insulating layer 11a, and the upper light-shielding layer 3c are disposed between the substrate 10a and the semiconductor layer 30a. Therefore, incident light L incident from the substrate 10a side toward the semiconductor layer 30a side is reflected at the interface between the substrate 10a and the lower light shielding layer 3b, and further, at the interface between the interlayer insulating layer 11a and the upper light shielding layer 3c. Since the light is reflected, the incident light L incident on the semiconductor layer 30a from the substrate 10a side can be effectively shielded. Further, since both the lower light-shielding layer 3b and the upper light-shielding layer 3c are set to the same potential as the gate electrode 30g, a scanning line can be constituted by three layers including the gate wiring 3a and the two light-shielding layers. The wiring resistance of the wire can be lowered. As a result, it is possible to reduce the wiring resistance of the scanning lines while improving the light shielding performance as compared with the conventional case, and thus it is possible to provide the liquid crystal display device 1 with high display quality.

  (2) Since the lower light-shielding layer 3b and the upper light-shielding layer 3c constituting the scanning line are formed across the pixels P, even when the liquid crystal display device 1 is large and the scanning line is long, the light shielding property is improved. The wiring resistance of the scanning line can be lowered while improving.

  (3) A pair of light shielding portions along the Z direction is formed between the lower light shielding layer 3b and the upper light shielding layer 3c by the contact holes CH7 and CH8 penetrating the interlayer insulating layer 11a. It is disposed on both sides of the semiconductor layer 30a as viewed. Therefore, the incident light L incident obliquely with respect to the Z direction from the substrate 10a side and the light reflected and propagated between the upper light shielding layer 3c and the lower light shielding layer 3b are formed by the contact holes CH7 and CH8. Since the light shielding part can shield light from both sides of the semiconductor layer 30a, the light shielding property can be further improved.

  (4) A pair of light shielding portions along the Z direction is formed by contact holes CH5 and CH6 penetrating the gate insulating layer 11c and the interlayer insulating layer 11b, and the pair of light shielding portions are formed on both sides of the semiconductor layer 30a in plan view. Be placed. Therefore, the incident light L incident obliquely with respect to the Z direction from the substrate 10a side and the light reflected and propagated between the gate wiring 3a and the upper light shielding layer 3c are formed by the contact holes CH5 and CH6. Since the light shielding part can shield light from both sides of the semiconductor layer 30a, the light shielding property can be further improved.

(Second Embodiment)
<Light shielding structure of element substrate>
Next, the light shielding structure of the element substrate according to the second embodiment will be described with reference to FIGS. 6A and 6B. FIG. 6A is a schematic plan view showing the configuration of the TFT portion of the element substrate according to the second embodiment. FIG. 6B is a schematic cross-sectional view taken along the line AA ′ of FIG. 6A.

  The element substrate 10A according to the second embodiment is formed by dividing the upper light shielding layer 3d as the second light shielding layer for each pixel P with respect to the element substrate 10 according to the first embodiment. Except for the difference, the configuration is the same as that of the first embodiment. Here, differences from the first embodiment will be described, and the same components as those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

  As shown in FIGS. 6A and 6B, the element substrate 10A according to the second embodiment includes a lower light-shielding layer 3b, an interlayer insulating layer 11a, and an upper light-shielding layer 3d between the substrate 10a and the semiconductor layer 30a. ing. While the upper light shielding layer 3c of the first embodiment is provided between the pixels P in the X direction, the upper light shielding layer 3d of the second embodiment is divided for each pixel P. The lower light-shielding layer 3b is formed across the pixels P.

  The upper light shielding layer 3d of the second embodiment is formed of the same material and film thickness as the upper light shielding layer 3c of the first embodiment. The upper light shielding layer 3d is electrically connected to the lower light shielding layer 3b through contact holes CH7 and CH8 that penetrate the interlayer insulating layer 11a. The contact hole CH7 is disposed outside the contact hole CH5 with respect to the semiconductor layer 30a, and the contact hole CH8 is disposed outside the contact hole CH6.

  According to the configuration of the element substrate 10A according to the second embodiment, even if the upper light shielding layer 3d is divided for each pixel P, the lower light shielding layer 3b and the interlayer insulating layer are provided between the substrate 10a and the semiconductor layer 30a. Since 11a and the upper side light shielding layer 3d are arrange | positioned, the light-shielding property can be improved rather than the past like 1st Embodiment. Further, the wiring resistance of the scanning line is made lower than in the case where only one lower light shielding layer 3b is arranged between the substrate 10a and the semiconductor layer 30a as in the conventional element substrate 60 shown in FIGS. 10A and 10B. Can be suppressed. Such a configuration of the second embodiment can be applied when the liquid crystal display device 1 is small and it is not so important to reduce the wiring resistance of the scanning lines.

  According to the configuration of the element substrate 10A according to the second embodiment, the following effects can be obtained.

  (1) Even if the upper light shielding layer 3d is divided for each pixel P, the lower light shielding layer 3b, the interlayer insulating layer 11a, and the upper light shielding layer 3d are disposed between the substrate 10a and the semiconductor layer 30a. As in the first embodiment, the light shielding property can be improved as compared with the prior art. In addition, the wiring resistance of the scanning line can be kept low.

(Third embodiment)
<Light shielding structure of element substrate>
Next, the light shielding structure of the element substrate according to the third embodiment will be described with reference to FIGS. 7A and 7B. FIG. 7A is a schematic plan view showing the configuration of the TFT portion of the element substrate according to the third embodiment. FIG. 7B is a schematic cross-sectional view taken along line AA ′ of FIG. 7A.

  The element substrate 10B according to the third embodiment is formed by dividing the upper light shielding layer 3e as the second light shielding layer for each pixel P with respect to the element substrate 10A according to the second embodiment. Is the same except that contact holes CH5 and CH6 and contact holes CH7 and CH8 are arranged so as to overlap in plan view. Here, differences from the above embodiment will be described, and the same components as those in the above embodiment will be denoted by the same reference numerals and description thereof will be omitted.

  As shown in FIGS. 7A and 7B, the element substrate 10B according to the third embodiment includes a lower light-shielding layer 3b, an interlayer insulating layer 11a, and an upper light-shielding layer 3e between the substrate 10a and the semiconductor layer 30a. ing. Contact holes CH7 and CH8 are formed in the interlayer insulating layer 11a, and a recess 34 that is recessed from the surface (upper surface) is formed in a range including the contact holes CH7 and CH8.

  The upper light shielding layer 3e of the third embodiment is formed with the same material and film thickness as the upper light shielding layer 3c of the first embodiment. The upper light shielding layer 3e is divided for each pixel P, and is formed so as to fill the recesses 34 provided in the interlayer insulating layer 11a and the contact holes CH7 and CH8. The surface of the upper light shielding layer 3e is a substantially flat surface including the positions of the contact holes CH7 and CH8. Further, the surface of the upper light shielding layer 3e and the surface of the interlayer insulating layer 11a are substantially flat surfaces. The upper light shielding layer 3e is electrically connected to the lower light shielding layer 3b through contact holes CH7 and CH8.

  Such an element substrate 10B according to the third embodiment can be manufactured as follows. After the contact holes CH7 and CH8 are formed in the interlayer insulating layer 11a, the interlayer insulating layer 11a is etched from the surface side to form the recesses 34. Then, after arranging and patterning the material of the upper light-shielding layer 3e so as to fill the recess 34 and the contact holes CH7 and CH8, a planarization process for planarizing the surface of the upper light-shielding layer 3e and the surface of the interlayer insulating layer 11a Apply.

  In the element substrate 10B according to the third embodiment, the contact hole CH7 is disposed so as to overlap with the contact hole CH5 in plan view, and the contact hole CH8 is disposed so as to overlap with the contact hole CH6 in plan view. In the element substrate 10B, since the surface of the upper light shielding layer 3e is a substantially flat surface, the positions of the contact holes CH5 and CH6 formed in the upper layer are not limited. In other words, the positions of the contact holes CH7 and CH8 are not restricted with respect to the positions of the contact holes CH5 and CH6.

  Therefore, the area shielded by the contact holes CH5, CH6, CH7, and CH8 can be reduced, so that the aperture ratio of the liquid crystal display device 1 can be improved. Therefore, the configuration of the element substrate 10B according to the third embodiment is suitable when the liquid crystal display device 1 is a small and high-definition liquid crystal display device in which the arrangement pitch of the pixels P is narrow. Further, since the surface of the upper light shielding layer 3e and the surface of the interlayer insulating layer 11a are substantially flat surfaces, a step generated in the upper layer due to the film thickness of the upper light shielding layer 3e can be suppressed.

  According to the configuration of the element substrate 10B according to the third embodiment, the following effects can be obtained.

  (1) Even if the upper light shielding layer 3e is divided for each pixel P, the lower light shielding layer 3b, the interlayer insulating layer 11a, and the upper light shielding layer 3e are disposed between the substrate 10a and the semiconductor layer 30a. As in the first embodiment, the light shielding property can be improved as compared with the prior art. In addition, the wiring resistance of the scanning line can be kept low.

  (2) The upper light shielding layer 3e having a substantially flat surface is formed on the interlayer insulating layer 11a by filling the pair of contact holes CH7 and CH8 penetrating the interlayer insulating layer 11a. Therefore, when the contact holes CH5 and CH6 for electrical connection from the upper layer side to the upper light-shielding layer 3e are formed, the positions thereof are not restricted, so that the degree of freedom of wiring pattern design can be increased.

  (3) A gate passing through a pair of contact holes CH7 and CH8 that penetrate the interlayer insulating layer 11a and electrically connect the lower light-shielding layer 3b and the upper light-shielding layer 3e, and the gate insulating layer 11c and the interlayer insulating layer 11b. A pair of contact holes CH5 and CH6 that electrically connect the electrode 30g and the upper light shielding layer 3e are arranged so as to overlap in a plan view. Therefore, the area shielded by the contact holes CH5, CH6, CH7, and CH8 can be reduced, so that the aperture ratio of the liquid crystal display device 1 can be improved.

(Fourth embodiment)
<Light shielding structure of element substrate>
Next, the light shielding structure of the element substrate according to the fourth embodiment will be described with reference to FIGS. 8A and 8B. FIG. 8A is a schematic plan view showing the configuration of the TFT portion of the element substrate according to the fourth embodiment. FIG. 8B is a schematic cross-sectional view along the line BB ′ in FIG. 8A. Note that the BB ′ line in FIG. 8A is a line along the Y direction in which the semiconductor layer 30a extends.

  The element substrate 10 </ b> C according to the fourth embodiment penetrates the interlayer insulating layer 11 a with respect to the element substrates 10, 10 </ b> A, and 10 </ b> B according to the above-described embodiment, and upper light shielding as the lower light shielding layer 3 b and the second light shielding layer. A difference is that a contact hole CH9 for electrically connecting the layer 3f is provided at a position overlapping the channel region 30c of the semiconductor layer 30a in plan view. Here, differences from the above embodiment will be described, and the same components as those in the above embodiment will be denoted by the same reference numerals and description thereof will be omitted.

  As shown in FIGS. 8A and 8B, the element substrate 10C according to the fourth embodiment includes the lower light shielding layer 3b, the interlayer insulating layer 11a, and the upper light shielding layer 3f between the substrate 10a and the semiconductor layer 30a. ing. The upper light shielding layer 3f of the fourth embodiment is formed of the same material and film thickness as the upper light shielding layer 3c of the first embodiment. Similarly to the first embodiment, the contact holes CH5 and CH6 are arranged on both sides of the semiconductor layer 30a in plan view (see FIG. 8A).

  The interlayer insulating layer 11a is provided with a through hole 35 (a contact hole CH9 as a fifth contact hole) at a position overlapping the channel region 30c of the semiconductor layer 30a in plan view. The through-hole 35 is preferably formed in a range wider than the channel region 30c including the channel region 30c of the semiconductor layer 30a in the X direction and the Y direction. The length of the through hole 35 along the Y direction is, for example, about 2 μm, and the depth of the through hole 35 is, for example, about 0.5 μm.

  As shown in FIG. 8B, since the through hole 35 is provided in a region overlapping the lower light shielding layer 3b in plan view, when the through hole 35 is formed in the interlayer insulating layer 11a, the lower light shielding layer is formed in the through hole 35. 3b is exposed. In this specification, the side part (slope) of the through hole 35 formed in the interlayer insulating layer 11a is referred to as a side part 35b of the contact hole CH9, and the surface of the lower light shielding layer 3b exposed in the through hole 35 is contacted. This is referred to as a bottom portion 35a of the hole CH9.

  8B, the upper light shielding layer 3f includes the bottom 35a of the contact hole CH9 (the surface of the lower light shielding layer 3b exposed in the through hole 35), the contact hole, and the contact hole CH9. It is disposed across the side portion 35b of CH9 and the surface of the interlayer insulating layer 11a located outside the contact hole CH9. The upper light shielding layer 3f is in contact with and electrically connected to the lower light shielding layer 3b at the bottom 35a of the contact hole CH9.

  By forming the upper light shielding layer 3f in a concave shape in a cross-sectional view in this way, the bottom 35a and the side 35b where the channel region 30c of the semiconductor layer 30a is disposed on the upper layer, and the surface of the outer interlayer insulating layer 11a are formed. Since the upper light shielding layer 3f is disposed so as to cover the light, it is possible to effectively shield the light incident on the channel region 30c.

  An interlayer insulating layer 11b is formed so as to cover the interlayer insulating layer 11a and the upper light shielding layer 3f. When the thickness of the interlayer insulating layer 11b formed on the interlayer insulating layer 11a is about 300 nm to 400 nm as described above, the thickness of the interlayer insulating layer 11b in the side portion 35b of the contact hole CH9 is, for example, about 200 nm. Become. On the surface side of the interlayer insulating layer 11b, the shape of the upper light shielding layer 3f formed along the bottom 35a and the side 35b of the contact hole CH9 is reflected, and the bottom 36a corresponding to the bottom 35a and the side 35b are reflected. A recess 36 having a side portion 36b corresponding to is formed. The length of the bottom portion 36a along the Y direction is, for example, about 1.5 μm.

  The semiconductor layer 30a is disposed on the interlayer insulating layer 11b so as to cover the upper light shielding layer 3f along the bottom portion 36a and the side portion 36b of the recess 36. By forming the semiconductor layer 30a in a concave shape in a cross-sectional view in this way, the substantial length of the semiconductor layer 30a can be made longer than the length D in the plan view of the semiconductor layer 30a shown in FIG. 8A.

  In other words, the length D of the semiconductor layer 30a in plan view can be shortened with respect to the originally required length of the semiconductor layer 30a. Therefore, since the light shielding area can be reduced, the aperture ratio of the liquid crystal display device 1 can be improved. Therefore, the configuration of the element substrate 10C according to the fourth embodiment is suitable when the liquid crystal display device 1 is a small and high-definition liquid crystal display device in which the arrangement pitch of the pixels P is narrow.

  A gate insulating layer 11c is formed so as to cover the interlayer insulating layer 11b and the semiconductor layer 30a. A gate electrode 30g is formed on the gate insulating layer 11c so as to face the channel region 30c. Since the shape of the recess 36 is also reflected on the surface of the gate insulating layer 11 c, the gate electrode 30 g is also formed along the bottom 36 a and the side 36 b of the recess 36. Therefore, the width of the gate electrode 30g in plan view can be reduced. The gate electrode 30g is electrically connected to the upper light shielding layer 3f on both outer sides in the X direction of the semiconductor layer 30a (channel region 30c) via contact holes CH5 and CH6 penetrating the gate insulating layer 11c and the interlayer insulating layer 11b. Are connected (see FIG. 8A).

  Here, at least the channel region 30 c in the semiconductor layer 30 a is preferably disposed on the bottom 36 a of the recess 36. By arranging the channel region 30c on the bottom 36a of the recess 36, the channel length of the channel region 30c can be ensured. Then, the data line side LDD region 30e and the pixel electrode side LDD region 30f arranged on both sides of the channel region 30c can be arranged in a range extending from the bottom 36a of the recess 36 to the outside through the side 36b. As a result, a sufficiently long LDD region can be secured. Therefore, even when the liquid crystal display device 1 is a small and high-definition liquid crystal display device in which the arrangement pitch of the pixels P is narrow, the TFT 30 having excellent operating characteristics can be formed.

  Note that the bottom 35a of the contact hole CH9 (through hole 35) formed in the lower interlayer insulating layer 11a so that the diameter of the bottom 36a is equal to or larger than the channel length with respect to the desired channel length of the channel region 30c. It is assumed that the diameter is appropriately set.

  According to the configuration of the element substrate 10C according to the fourth embodiment, the following effects are obtained.

  (1) In a cross-sectional view along the extending direction of the semiconductor layer 30a, on the bottom 35a of the contact hole CH9 penetrating the interlayer insulating layer 11a, its side 35b, and the surface of the outer interlayer insulating layer 11a The upper light shielding layer 3f is disposed over the semiconductor layer 30a, and the semiconductor layer 30a is disposed so as to cover the upper light shielding layer 3f via the interlayer insulating layer 11b. Therefore, the substantial length of the semiconductor layer 30a can be made longer than the length D in plan view. In other words, since the length D of the semiconductor layer 30a in plan view can be shortened with respect to the required length of the semiconductor layer 30a, the light shielding region can be reduced, and the aperture ratio of the liquid crystal display device 1 is improved. Can be made.

  (2) Since at least the channel region 30c of the semiconductor layer 30a is disposed at the bottom 35a of the contact hole CH9, the channel length of the channel region 30c can be ensured even when the liquid crystal display device 1 is small. When the data line side LDD region 30e and the pixel electrode side LDD region 30f are provided on both sides of the channel region 30c, the data line side LDD region 30e and the pixel electrode side LDD region 30f are arranged on the side from the bottom 35a of the contact hole CH9. Since it can be arranged in a range extending further outside through the portion 35b, a sufficient LDD region can be secured. Therefore, the TFT 30 having excellent operating characteristics can be formed. Further, the upper light shielding layer 3f disposed below the semiconductor layer 30a is disposed so as to cover the bottom 35a and the side 35b where the channel region 30c is disposed and the surface of the outer interlayer insulating layer 11a. The light incident on the channel region 30c can be effectively blocked.

  Note that the configuration of the element substrate 10C according to the fourth embodiment can also be applied to the first embodiment, the second embodiment, and the third embodiment.

(Fifth embodiment)
<Electronic equipment>
Next, an electronic apparatus according to a fifth embodiment will be described with reference to FIG. FIG. 9 is a schematic diagram illustrating a configuration of a projector as an electronic apparatus according to the fifth embodiment.

  As shown in FIG. 9, a projector (projection display device) 100 as an electronic apparatus according to the fifth embodiment includes a polarization illumination device 110, two dichroic mirrors 104 and 105 as light separation elements, and three Reflection mirrors 106, 107, 108, five relay lenses 111, 112, 113, 114, 115, three liquid crystal light valves 121, 122, 123, a cross dichroic prism 116 as a light combining element, and a projection lens 117 It has.

  The polarization illumination device 110 includes a lamp unit 101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 102, and a polarization conversion element 103. The lamp unit 101, the integrator lens 102, and the polarization conversion element 103 are disposed along the system optical axis Lx.

  The dichroic mirror 104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 110. Another dichroic mirror 105 reflects the green light (G) transmitted through the dichroic mirror 104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 104 is reflected by the reflection mirror 106 and then enters the liquid crystal light valve 121 via the relay lens 115. The green light (G) reflected by the dichroic mirror 105 enters the liquid crystal light valve 122 via the relay lens 114. The blue light (B) transmitted through the dichroic mirror 105 is incident on the liquid crystal light valve 123 via a light guide system composed of three relay lenses 111, 112, 113 and two reflection mirrors 107, 108.

  The transmissive liquid crystal light valves 121, 122, and 123 as light modulation elements are disposed to face the incident surfaces of the cross dichroic prism 116 for each color light. The color light incident on the liquid crystal light valves 121, 122, 123 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 116.

  The cross dichroic prism 116 is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. Yes. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 130 by the projection lens 117 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 121 is one to which the liquid crystal display device 1 of the above embodiment is applied. The liquid crystal light valve 121 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and emission side of colored light. The same applies to the other liquid crystal light valves 122 and 123.

  According to the configuration of the projector 100 according to the fifth embodiment, even when a plurality of pixels P are arranged with high definition, the aperture ratio of the pixel region through which light is transmitted is high, and generation of light leakage current in the TFT 30 can be suppressed. Since the liquid crystal display device 1 is provided, it is possible to provide a projector 100 having high quality and brightness.

  The above-described embodiments merely show one aspect of the present invention, and can be arbitrarily modified and applied within the scope of the present invention. As modifications, for example, the following can be considered.

(Modification 1)
In the element substrates 10, 10 </ b> A, 10 </ b> B, and 10 </ b> C according to the above embodiment, the lower light shielding layer 3 b has a large film thickness (about 200 nm), and the upper light shielding layers 3 c, 3 d, 3 e, 3 f have a small film thickness (about 100 nm). Although it is a structure, this invention is not limited to such a form. The lower light-shielding layer 3b may be thin (about 100 nm) and the upper light-shielding layers 3c, 3d, 3e, 3f may be thick (about 200 nm). Even if it is such a structure, the effect similar to the said embodiment is acquired.

(Modification 2)
In the element substrate 10A according to the second embodiment and the element substrate 10B according to the third embodiment, the lower light shielding layer 3b is formed across the pixels P, and the upper light shielding layers 3d and 3e are divided for each pixel P. However, the present invention is not limited to such a configuration. The lower light shielding layer 3b may be divided for each pixel P, and the upper light shielding layers 3d and 3e may be formed across the pixels P. Even if it is such a structure, the effect similar to the said embodiment is acquired.

(Modification 3)
The display device to which the light shielding structure of the element substrates 10, 10 </ b> A, 10 </ b> B, and 10 </ b> C according to the above embodiment is applicable is not limited to the liquid crystal display device 1. The light shielding structure of the element substrates 10, 10 </ b> A, 10 </ b> B, and 10 </ b> C may be applied to display devices such as organic EL devices, plasma displays, and electronic paper.

(Modification 4)
The electronic device to which the liquid crystal display device 1 according to the above embodiment can be applied is not limited to the projector 100. The liquid crystal display device 1 is, for example, a projection type HUD (head-up display), a direct-view type HMD (head-mounted display), an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type, or a monitor direct-view type. It can be suitably used as a display unit of an information terminal device such as a video recorder, a car navigation system, an electronic notebook, or a POS.

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device (display apparatus), 3a ... Gate wiring (scanning line), 3b ... Lower side light shielding layer (1st light shielding layer), 3c, 3d, 3e, 3f ... Upper side light shielding layer (2nd light shielding layer) ) 10a ... substrate (first substrate), 11a ... interlayer insulating layer (first insulating layer), 11b ... interlayer insulating layer (second insulating layer), 11c ... gate insulating layer, 20a ... substrate (second substrate) 30) TFT (switching element), 30a ... semiconductor layer, 30c ... channel region, 30g ... gate electrode, 35a ... bottom, 35b ... side, 40 ... liquid crystal layer, 100 ... projector (electronic device), CH5 ... contact hole (third contact hole), CH6 ... contact hole (fourth contact hole), CH7 ... contact hole (first contact hole), CH8 ... contact hole (second contact hole) Le), CH9 ... contact hole (fifth contact hole), P ... pixels.

Claims (11)

A first substrate;
A second substrate disposed opposite to the first substrate;
A liquid crystal layer sandwiched between the first substrate and the second substrate;
A semiconductor layer including a channel region, a gate insulating layer covering the semiconductor layer, and a channel insulating layer disposed on the first substrate so as to face the channel region via the gate insulating layer. A switching element having a gate electrode,
Between the first substrate and the semiconductor layer,
A first light-shielding layer disposed on the first substrate so as to overlap the semiconductor layer in a plan view and set at the same potential as the gate electrode;
A first insulating layer disposed to cover the first light shielding layer;
A second light-shielding layer disposed on the first insulating layer so as to overlap the semiconductor layer and the first light-shielding layer in plan view and set to the same potential as the gate electrode;
And a second insulating layer arranged to cover the second light shielding layer. The display device according to claim 1,
The display device, wherein the first light-shielding layer and the second light-shielding layer are formed across the pixels. The display device according to claim 1,
The display device, wherein the first light-shielding layer or the second light-shielding layer is divided for each pixel. A display device according to any one of claims 1 to 3,
A first contact hole and a second contact hole that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer;
The display device, wherein the first contact hole and the second contact hole are arranged on both sides of the semiconductor layer in a direction intersecting with an extending direction of the semiconductor layer in a plan view. The display device according to claim 4,
The display device, wherein the second light shielding layer is formed to fill the first contact hole and the second contact hole, and has a substantially flat surface. The display device according to claim 5,
A third contact hole and a fourth contact hole that penetrate through the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer;
The third contact hole is disposed so as to overlap with the first contact hole in plan view, and the fourth contact hole is disposed so as to overlap with the second contact hole in plan view. Display device. A display device according to any one of claims 1 to 3,
A fifth contact hole that penetrates the first insulating layer and electrically connects the first light-shielding layer and the second light-shielding layer;
In a cross-sectional view along the extending direction of the semiconductor layer,
The second light-shielding layer is disposed across the bottom and sides of the fifth contact hole and the surface of the first insulating layer located outside the fifth contact hole,
The display device, wherein the semiconductor layer is disposed so as to cover the second light-shielding layer with the second insulating layer interposed therebetween. The display device according to claim 7,
At least the channel region of the semiconductor layer is disposed at the bottom of the fifth contact hole. The display device according to claim 7 or 8,
A third contact hole and a fourth contact hole that penetrate through the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer;
The display device, wherein the third contact hole and the fourth contact hole are arranged on both sides of the semiconductor layer in a direction intersecting with the extending direction of the semiconductor layer in plan view. The display device according to claim 2,
A plurality of contact holes penetrating the first insulating layer and electrically connecting the first light shielding layer and the second light shielding layer;
The number of the contact holes is less than the number of the pixels.   An electronic apparatus comprising the display device according to any one of claims 1 to 10.

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