JP2017073416A - 配線構造体、及び配線構造体の製造方法 - Google Patents
配線構造体、及び配線構造体の製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052796 boron Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 50
- 239000010703 silicon Substances 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 claims description 28
- 238000007747 plating Methods 0.000 claims description 22
- 238000007740 vapor deposition Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 11
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
【解決手段】インターポーザ1は、貫通配線パターン5を含む配線パターン3が設けられた配線構造体である。インターポーザ1は、貫通配線パターン5が配置された貫通孔11を有するシリコン基板10と、少なくとも配線パターン3に沿って、貫通孔11の内面11aを含むシリコン基板10の表面に設けられた絶縁層14と、配線パターン3に沿って絶縁層14上に設けられたボロン層15と、ボロン層15上に設けられた金属層16と、備える。
【選択図】図2
Description
Claims (9)
- 貫通配線パターンを含む配線パターンが設けられた配線構造体であって、
前記貫通配線パターンが配置された貫通孔を有するシリコン基板と、
少なくとも前記配線パターンに沿って、前記貫通孔の内面を含む前記シリコン基板の表面に設けられた絶縁層と、
前記配線パターンに沿って前記絶縁層上に設けられたボロン層と、
前記ボロン層上に設けられた金属層と、備える、配線構造体。 - 前記貫通孔の少なくとも一部の内面は、前記シリコン基板の厚さ方向に沿っている、請求項1記載の配線構造体。
- 前記貫通孔の少なくとも一部の内面は、前記シリコン基板の厚さ方向と交差する一の方向に沿っている、請求項1記載の配線構造体。
- 前記貫通孔の幅は、10μm以上100μm以下である、請求項1〜3のいずれか一項記載の配線構造体。
- 前記金属層は、めっき層である、請求項1〜4のいずれか一項記載の配線構造体。
- 前記シリコン基板は、インターポーザを構成している、請求項1〜5のいずれか一項記載の配線構造体。
- 前記シリコン基板は、半導体装置を構成している、請求項1〜5のいずれか一項記載の配線構造体。
- 貫通配線パターンを含む配線パターンが設けられた配線構造体の製造方法であって、
前記貫通配線パターンが配置される貫通孔をシリコン基板に形成する第1ステップと、
少なくとも前記配線パターンの形成予定領域に沿って、前記貫通孔の内面を含む前記シリコン基板の表面に絶縁層を形成する第2ステップと、
前記形成予定領域に沿って前記絶縁層上にボロン層を形成する第3ステップと、
めっきにより前記ボロン層上に金属層を形成する第4ステップと、を含む、配線構造体の製造方法。 - 前記第3ステップでは、気相成長法により前記絶縁層上に前記ボロン層を等方的に形成し、その後に前記形成予定領域に沿って前記ボロン層をパターニングする、請求項8記載の配線構造体の製造方法。
Priority Applications (6)
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JP2015197520A JP6450296B2 (ja) | 2015-10-05 | 2015-10-05 | 配線構造体、及び配線構造体の製造方法 |
US15/765,536 US10573556B2 (en) | 2015-10-05 | 2016-09-01 | Wiring structure and method for producing wiring structure |
EP16853348.7A EP3361499B1 (en) | 2015-10-05 | 2016-09-01 | Wiring structure and method for producing wiring structure |
PCT/JP2016/075681 WO2017061194A1 (ja) | 2015-10-05 | 2016-09-01 | 配線構造体、及び配線構造体の製造方法 |
CN201680058495.0A CN108140618B (zh) | 2015-10-05 | 2016-09-01 | 配线构造体及配线构造体的制造方法 |
TW105129032A TWI713183B (zh) | 2015-10-05 | 2016-09-08 | 配線構造體及配線構造體之製造方法 |
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US (1) | US10573556B2 (ja) |
EP (1) | EP3361499B1 (ja) |
JP (1) | JP6450296B2 (ja) |
CN (1) | CN108140618B (ja) |
TW (1) | TWI713183B (ja) |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004296488A (ja) * | 2003-03-25 | 2004-10-21 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、及び電子機器 |
JP2007005403A (ja) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | 半導体基板への貫通配線の形成方法 |
JP2010192481A (ja) * | 2009-02-16 | 2010-09-02 | Panasonic Corp | 半導体基板と半導体パッケージおよび半導体基板の製造方法 |
JP2011192884A (ja) * | 2010-03-16 | 2011-09-29 | Toppan Printing Co Ltd | シリコン配線基板 |
JP2013207006A (ja) * | 2012-03-28 | 2013-10-07 | Toppan Printing Co Ltd | 貫通電極付き配線基板及びその製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6331483B1 (en) * | 1998-12-18 | 2001-12-18 | Tokyo Electron Limited | Method of film-forming of tungsten |
JP3599325B2 (ja) * | 2001-02-09 | 2004-12-08 | 株式会社フジクラ | 基板の貫通電極形成方法および貫通電極を有する基板 |
US20040126548A1 (en) * | 2001-05-28 | 2004-07-01 | Waseda University | ULSI wiring and method of manufacturing the same |
CN100514596C (zh) * | 2006-01-13 | 2009-07-15 | 联华电子股份有限公司 | 金属内连线的制作方法与结构 |
US7902069B2 (en) * | 2007-08-02 | 2011-03-08 | International Business Machines Corporation | Small area, robust silicon via structure and process |
WO2011078010A1 (ja) * | 2009-12-25 | 2011-06-30 | 富士フイルム株式会社 | 絶縁基板、絶縁基板の製造方法、配線の形成方法、配線基板および発光素子 |
US8507940B2 (en) * | 2010-04-05 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat dissipation by through silicon plugs |
US8338939B2 (en) * | 2010-07-12 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV formation processes using TSV-last approach |
JP2012119381A (ja) * | 2010-11-29 | 2012-06-21 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2014107304A (ja) * | 2012-11-22 | 2014-06-09 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US8981564B2 (en) * | 2013-05-20 | 2015-03-17 | Invensas Corporation | Metal PVD-free conducting structures |
US9617648B2 (en) * | 2015-03-04 | 2017-04-11 | Lam Research Corporation | Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias |
US11107878B2 (en) * | 2015-03-24 | 2021-08-31 | International Business Machines Corporation | High resistivity iron-based, thermally stable magnetic material for on-chip integrated inductors |
JP6509635B2 (ja) * | 2015-05-29 | 2019-05-08 | 東芝メモリ株式会社 | 半導体装置、及び、半導体装置の製造方法 |
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- 2016-09-01 WO PCT/JP2016/075681 patent/WO2017061194A1/ja unknown
- 2016-09-01 CN CN201680058495.0A patent/CN108140618B/zh active Active
- 2016-09-08 TW TW105129032A patent/TWI713183B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004296488A (ja) * | 2003-03-25 | 2004-10-21 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、及び電子機器 |
JP2007005403A (ja) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | 半導体基板への貫通配線の形成方法 |
JP2010192481A (ja) * | 2009-02-16 | 2010-09-02 | Panasonic Corp | 半導体基板と半導体パッケージおよび半導体基板の製造方法 |
JP2011192884A (ja) * | 2010-03-16 | 2011-09-29 | Toppan Printing Co Ltd | シリコン配線基板 |
JP2013207006A (ja) * | 2012-03-28 | 2013-10-07 | Toppan Printing Co Ltd | 貫通電極付き配線基板及びその製造方法 |
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WO2017061194A1 (ja) | 2017-04-13 |
TWI713183B (zh) | 2020-12-11 |
JP6450296B2 (ja) | 2019-01-09 |
EP3361499A1 (en) | 2018-08-15 |
TW201724438A (zh) | 2017-07-01 |
EP3361499A4 (en) | 2019-05-22 |
CN108140618B (zh) | 2021-03-19 |
US20190080911A1 (en) | 2019-03-14 |
EP3361499B1 (en) | 2020-07-15 |
US10573556B2 (en) | 2020-02-25 |
CN108140618A (zh) | 2018-06-08 |
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