JP2017050346A - Multilayer ceramic capacitor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor which enables the rise in relative dielectric constant and consequently the increase in electrostatic capacitance in a multilayer ceramic capacitor limited in size.SOLUTION: A multilayer ceramic capacitor 10 comprises a laminate 12 having laminated dielectric layers 14 and internal electrode layers 16. The dielectric layers 14 include a perovskite compound including Sr, Ba, Ca, Ti and Zr, provided that Sr is 40-90 mol%, Ba is 0-45 mol%, Ca is 0-20 mol%, Zr is 90-100 mol%, and Ti is 0-10 mol%; (Sr mole number+Ba mole number+Ca mole number)/(Zr mole number+Ti mole number) is 1.00-1.03. The perovskite compound includes rhombic crystal, of which the lattice volume is 275.0 Åor larger.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a multilayer ceramic capacitor, and in particular, a multilayer body having a plurality of laminated dielectric layers and a plurality of internal electrode layers, and formed on an end face of the multilayer body so as to be electrically connected to the internal electrode layers. The present invention relates to a monolithic ceramic capacitor having external electrodes and a method for manufacturing the same.

  The multilayer ceramic capacitor includes an element body in which dielectric layers and internal electrode layers are alternately stacked. The internal electrode layers are formed such that a pair of internal electrode layers are alternately exposed from both end faces of the element body. One internal electrode layer laminated alternately is electrically connected to the inside of the terminal electrode formed so as to cover one end face of the element body. The other internal electrode layer stacked alternately is electrically connected to the inside of the terminal electrode formed so as to cover the other end face of the element body. In this way, a capacitance is formed between the terminal electrodes formed at both ends of the element body (see Patent Document 1).

Japanese Patent Laying-Open No. 2015-62216

  In recent years, with the miniaturization of electronic equipment, further miniaturization has been demanded for multilayer ceramic capacitors mounted on such electronic equipment. Therefore, there is a need for a multilayer ceramic capacitor that is smaller and has a higher capacitance. In general, a multilayer ceramic capacitor made of a perovskite type compound containing a large amount of Sr and Zr in a dielectric layer has a higher capacitance depending on the temperature than a multilayer ceramic capacitor made of a perovskite type compound containing a lot of Ba and Ti. Although the change is small, there is a problem that the capacitance is small. Therefore, in order to increase the capacitance of the multilayer ceramic capacitor, a method of increasing the area of the internal electrode by increasing the number of dielectric layers can be considered, but if the number of dielectric layers is increased, the multilayer ceramic capacitor There is a problem that it is difficult to downsize.

  SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor capable of improving the relative dielectric constant and, as a result, increasing the capacitance in a multilayer ceramic capacitor having a limited size, and a method for manufacturing the same. It is.

The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor including a perovskite type compound containing Sr, Ba, Ca, Ti, Zr.
The multilayer ceramic capacitor includes a multilayer body,
The multilayer body includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked, and further, a first main surface and a second main surface that are opposed to the stacking direction, and a width direction orthogonal to the stacking direction. A first side face and a second side face opposite to each other, and a first end face and a second end face opposite to each other in a length direction perpendicular to the stacking direction and the width direction,
A first external electrode that covers the first end surface, extends from the first end surface, and is disposed to cover the first main surface, the second main surface, the first side surface, and the second side surface;
A second external electrode covering the second end surface and extending from the second end surface and arranged to cover the first main surface, the second main surface, the first side surface and the second side surface. ,
The dielectric layer is
The mole percentage of Sr is given by (number of moles of Sr) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 40% or more and 90% or less,
The mole percentage of Ba is given by (number of moles of Ba) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 45% or less,
The mol% of Ca is given by (number of moles of Ca) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 20% or less,
The mole percentage of Zr is given by (number of moles of Zr) / (number of moles of Zr + number of moles of Ti), and is 90% or more and 100% or less,
The mole percentage of Ti is given by (number of moles of Ti) / (number of moles of Zr + number of moles of Ti), and is 0% or more and 10% or less,
(Number of moles of Sr + number of moles of Ba + number of moles of Ca) / (number of moles of Zr + number of moles of Ti) is 1.00 or more and 1.03 or less,
Crystals contained in the perovskite compound contained in the dielectric layer is orthorhombic, wherein the cell volume is 275.0A ³ or more, a laminated ceramic capacitor.
In the multilayer ceramic capacitor according to the present invention, it is preferable that hydrogen is generated from the multilayer body in a temperature range of 400 ° C. or higher and 900 ° C. or lower by applying heat to the multilayer body at a temperature rising rate of 20 ° C./min.
A method for manufacturing a multilayer ceramic capacitor according to the present invention is such that the multilayer ceramic capacitor according to the present invention has a DC voltage of 25 kV / mm or more and 80 kV / mm or less per dielectric layer thickness in a temperature atmosphere of 100 ° C. or more and 200 ° C. or less. It is a manufacturing method of the multilayer ceramic capacitor characterized by applying for 3 to 3600 minutes.
In the method for producing a multilayer ceramic capacitor according to the present invention, the perovskite compound may be used at a temperature of 600 ° C. to 700 ° C. after forming the external electrode in a weakly oxidizing atmosphere with an oxygen partial pressure of 10 ppm or less for 60 minutes to 4800 minutes. A method for manufacturing a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor is heat-treated.

The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor including a composition of a perovskite type compound containing Sr, Ba, Ca, Ti, and Zr, wherein Ba or Sr having a large ion radius is used as a constituent element in the dielectric layer. In addition, by making the lattice volume 275.0 ³ , hydrogen is easily held in the lattice. Since this hydrogen limits the vibration of Zr contained in the lattice, when hydrogen is contained, the relative dielectric constant decreases, and the hydrogen retained in the lattice of the perovskite type compound of the dielectric layer in the multilayer ceramic capacitor By removing together, it is possible to obtain a multilayer ceramic capacitor in which the dielectric constant is improved and the capacitance can be increased.

  According to the present invention, it is possible to obtain a multilayer ceramic capacitor and a method of manufacturing the same that can improve the relative dielectric constant and, as a result, increase the capacitance in the multilayer ceramic capacitor having a limited size.

  The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

It is a perspective view which shows an example of the multilayer ceramic capacitor concerning this invention. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1.

  As shown in FIGS. 1, 2, and 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12, for example. The stacked body 12 includes a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 that are stacked. Furthermore, the laminate 12 includes a first main surface 12a and a second main surface 12b that are opposed to the lamination direction x, and a first side surface 12c and a second side surface that are opposed to the width direction y orthogonal to the lamination direction x. 12d, and a first end surface 12e and a second end surface 12f that are opposed to a length direction z orthogonal to the stacking direction x and the width direction y. The laminated body 12 is preferably rounded at corners and ridge lines. In addition, a corner | angular part is a part where three adjacent surfaces of a laminated body cross, and a ridgeline part is a part where two adjacent surfaces of a laminated body intersect.

  The number of dielectric layers 14 is preferably 25 or more and 110 or less. The dimension of the dielectric layer 14 in the stacking direction x is preferably 0.8 μm or more and 14.0 μm or less. The dielectric layer 14 includes an outer layer portion 14a and an inner layer portion 14b. The outer layer portion 14a is located on the first main surface 12a side and the second main surface 12b side of the laminate 12, and is formed between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The dielectric layer 14 is located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between both outer layer portions 14a is the inner layer portion 14b. The dimension of the outer layer portion 14a in the stacking direction is preferably 17 μm or more and 300 μm or less.

As shown in FIGS. 2 and 3, the stacked body 12 includes, as the plurality of internal electrode layers 16, for example, a plurality of first internal electrode layers 16 a and a plurality of second internal electrode layers 16 b having a substantially rectangular shape. The plurality of first internal electrode layers 16 a and the plurality of second internal electrode layers 16 b are embedded so as to be alternately arranged at equal intervals along the stacking direction x of the stacked body 12.
On one end side of the first internal electrode layer 16 a, there is an extraction electrode portion 18 a that is extracted to the first end surface 12 e of the multilayer body 12. On one end side of the second internal electrode layer 16b, there is an extraction electrode portion 18b extracted to the second end surface 12f of the multilayer body 12. Specifically, the extraction electrode portion 18 a on one end side of the first internal electrode layer 16 a is exposed on the first end surface 12 e of the multilayer body 12. Further, the lead electrode portion 18 b on one end side of the second internal electrode layer 16 b is exposed on the second end face 12 f of the multilayer body 12.

  The multilayer body 12 includes a counter electrode portion 20a in which the first internal electrode layer 16a and the second internal electrode layer 16b face each other in the inner layer portion 14b of the dielectric layer 14. The stacked body 12 is formed between one end in the width direction y of the counter electrode portion 20a and the first side surface 12c and between the other end in the width direction y of the counter electrode portion 20a and the second side surface 12d. Side part (hereinafter referred to as “W gap”) 20b of the laminate 14. Further, the laminated body 12 is formed between the end portion of the first internal electrode layer 16a opposite to the extraction electrode portion 18a and the second end surface 12f and the extraction electrode portion 18b of the second internal electrode layer 16b. It includes an end portion (hereinafter referred to as “L gap”) 20c of the stacked body 14 formed between the opposite end portion and the first end face 12e. When the L dimension in the length direction z was 3.2 mm, the W dimension in the width direction y was 1.6 mm, and the T dimension in the stacking direction x was 1.6 mm, the L gap was 110 μm and the W gap was 140 μm. When the L dimension in the length direction z was 0.25 mm, the W dimension in the width direction y was 0.125 mm, and the T dimension in the stacking direction x was 0.125 mm, the L gap was 40 μm and the W gap was 20 μm.

The dielectric layer 14 of the stacked body 12 includes a perovskite type compound containing Sr, Ba, Ca, Ti, and Zr. This perovskite type compound is represented by the general formula A _m BO ₃ . Here, the A site is Sr, and may contain at least one selected from the group consisting of Ba and Ca in addition to Sr. The B site is Zr, and may contain at least one selected from the group consisting of Ti in addition to Zr. O is oxygen. m is a perovskite type compound represented by a molar ratio of A site to B site. In this case, each content is
The mole percentage of Sr is given by (number of moles of Sr) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 40% or more and 90% or less,
The mole percentage of Ba is given by (number of moles of Ba) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 45% or less,
The mol% of Ca is given by (number of moles of Ca) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 20% or less,
The mole percentage of Zr is given by (number of moles of Zr) / (number of moles of Zr + number of moles of Ti), and is 90% or more and 100% or less,
The mole percentage of Ti is given by (number of moles of Ti) / (number of moles of Zr + number of moles of Ti), and is 0% or more and 10% or less,
The number of moles of Sr + number of moles of Ba + number of moles of Ca / (number of moles of Zr + number of moles of Ti) is 1.00 or more and 1.03 or less.
The crystal contained in the perovskite compound contained in the dielectric layer 14 is orthorhombic, the lattice volume is 275.0A ³ or more.

The hydrogen content in the perovskite compound, the total amount of hydrogen generated at 400 ° C. or higher 900 ° C. or less, if the lattice volume of the perovskite compound is 275.0A ³ or more, 400 ° C. or higher 900 ° C. or less in the total amount of hydrogen generated, for the case the lattice volume of the perovskite compound is less than 275.0A ^3, 21.5 times 1.0 times.

In addition, the presence form of the subcomponent in the dielectric layer 14 is not ask | required, For example, a subcomponent may exist in the crystal grain of a perovskite type compound.
The content molar part of each element is an amount obtained by ICP analysis after dissolving and treating the laminate 12 with a solvent, and in which part in the laminate 12 the element was present. Does not depend on That is, as another aspect of the multilayer ceramic capacitor 10 of the present invention, there may be mentioned one in which the composition of the multilayer body 12 is determined similarly to the composition of the dielectric layer 14 described above.

  Furthermore, as still another aspect of the multilayer ceramic capacitor 10 of the present invention, the dielectric layer described above is used as the mole part of each element when the mole part of each element is subjected to the dissolution treatment of the multilayer body 12 with a solvent. 14 is the same as the content molar part of each element contained in 14. As a solution processing method, for example, an alkali melting method is used.

  The internal electrode layer 16 contains, for example, a metal such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au. The internal electrode layer 16 may further include dielectric particles having the same composition as the ceramics included in the dielectric layer 14. The number of internal electrode layers 16 is preferably 40 or more and 110 or less. The thickness of the internal electrode layer 16 is preferably 0.6 μm or more and 1.0 μm or less. The ratio of the first internal electrode layer 16a covering the dielectric layer 14 and the ratio of the second internal electrode layer 16b covering the dielectric layer 14 is preferably 75% or more and 95% or less. The first internal electrode layer 16a and the second internal electrode layer 16b are provided with a counter electrode part 20a facing each other and a lead drawn from the counter electrode part 20a to the first end face 12e and the second end face 12f of the multilayer body 12. Electrode portions 18a and 18b are provided.

External electrodes 22 are formed on the first end surface 12 e side and the second end surface 12 f side of the multilayer body 12. The external electrode 22 has a first external electrode 22a and a second external electrode 22b.
A first external electrode 22 a is formed on the first end surface 12 e side of the multilayer body 12. The first external electrode 22a covers the first end surface 12e of the multilayer body 12, extends from the first end surface 12e, and extends from the first main surface 12a, the second main surface 12b, the first side surface 12c, and the first side surface 12c. 2 to cover a part of the side surface 12d. In this case, the first external electrode 22a is electrically connected to the extraction electrode portion 18a of the first internal electrode layer 16a.
A second external electrode 22 b is formed on the second end face 12 f side of the multilayer body 12. The second external electrode 22b covers the second end surface 12f of the multilayer body 12, extends from the second end surface 12f, and extends from the first main surface 12a, the second main surface 12b, the first side surface 12c, and the first side surface 12c. 2 to cover a part of the side surface 12d. In this case, the second external electrode 22b is electrically connected to the extraction electrode portion 18b of the second internal electrode layer 16b.

  In the laminated body 12, the first internal electrode layer 16a and the second internal electrode layer 16b are opposed to each other through the dielectric layer 14 in each counter electrode portion 20a, thereby forming a capacitance. . Therefore, a capacitance can be obtained between the first external electrode 22a to which the first internal electrode layer 16a is connected and the second external electrode 22b to which the second internal electrode layer 16b is connected. . Therefore, the multilayer ceramic electronic component having such a structure functions as a capacitor.

  As shown in FIG. 2 or 3, the first external electrode 22 a includes a base electrode layer 24 a and a plating layer 26 a in order from the laminated body 12 side. Similarly, the second external electrode 22b includes a base electrode layer 24b and a plating layer 26b in this order from the stacked body 12 side.

The base electrode layers 24a and 24b each include at least one selected from a baking layer, a resin layer, a thin film layer, and the like. Here, the base electrode layers 24a and 24b formed of the baking layer will be described.
The baking layer includes glass containing Si and Cu as a metal. The baking layer may be a plurality of layers. The baking layer is obtained by applying a conductive paste containing glass and metal to the laminated body 12 and baking it. The baking layer may be fired at the same time as the dielectric layer 14 and the internal electrode layer 16. The layer 16 may be baked after being baked. The thickness of the thickest portion of the baking layer is preferably 4 μm or more and 100 μm or less.

A resin layer containing conductive particles and a thermosetting resin may be formed on the surface of the baking layer. The resin layer may be directly formed on the laminate 12 without forming a baking layer. The resin layer may be a plurality of layers. The thickness of the thickest portion of the resin layer is preferably 5 μm or more and 100 μm or less.
Further, the thin film layer is a layer of 1 μm or less formed by a thin film forming method such as a sputtering method or a vapor deposition method and deposited with metal particles.

Further, as the plating layers 26a and 26b, for example, at least one metal selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, Bi, Zn, or the like or an alloy containing the metal is used. .
The plating layers 26a and 26b may be formed of a plurality of layers. The plating layers 26a and 26b preferably have a two-layer structure including a first plating layer provided on the surface of the baking layer and a second plating layer provided on the surface of the first plating layer.

  It is preferable to use Ni for the first plating layer. The first plating layer using Ni is used to prevent the base electrode layers 24a and 24b from being eroded by solder when mounting the multilayer ceramic capacitor. When the internal electrode layer 16 contains Ni, it is preferable to use Cu having good bonding properties with Ni as the first plating layer.

Moreover, it is preferable to use Sn or Au for the second plating layer. The second plating layer using Sn or Au is used for improving the wettability of the solder when mounting the multilayer ceramic capacitor so that it can be easily mounted. The second plating layer is formed as necessary, and the external electrode 22 is provided directly on the laminate 12 and is directly connected to the internal electrode layer 16. It may be composed of one plating layer. However, a catalyst may be provided on the laminate 12 as a pretreatment.
The second plating layer may be provided as the outermost layer of the plating layers 26a and 26b, and another plating layer may be provided on the surface of the second plating layer.

  The thickness per plating layer is preferably 1 μm or more and 35 μm or less. Moreover, it is preferable that the plating layers 26a and 26b do not contain glass. Furthermore, it is preferable that the metal ratio per unit volume is 99 volume% or more in the plating layers 26a and 26b. Moreover, the plating layers 26a and 26b are grain-grown along the thickness direction, and are columnar.

The dimension in the length direction z of the multilayer ceramic capacitor 10 including the multilayer body 12, the first external electrode 22a, and the second external electrode 22b is L, and the multilayer body 12, the first external electrode 22a, and the second The dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the outer electrode 22b is defined as T dimension, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the multilayer body 12, the first external electrode 22a, and the second external electrode 22b. Is the W dimension.
The dimension of the multilayer ceramic capacitor 10 is such that the L dimension in the length direction z is 0.25 mm or more and 3.2 mm or less, the W dimension in the width direction y is 0.125 mm or more and 1.6 mm or less, and the T dimension in the lamination direction x is 0. It is 125 mm or more and 1.6 mm or less. The dimensions of the multilayer ceramic capacitor 10 can be measured with a microscope.

  The composition of the perovskite type compound contained in the dielectric layer 14 can be confirmed, for example, as follows. First, the external electrode 22 of the multilayer ceramic capacitor 10 is removed by polishing to obtain the multilayer body 12. And the laminated body 12 from which the external electrode 22 was removed can be solution-processed by an alkali melting method, and this solution can be confirmed by ICP analysis.

  The lattice volume of the perovskite type compound contained in the dielectric layer 14 is measured as follows. First, the external electrode portion of the cross section (hereinafter referred to as “LW plane”) including the length direction z and the width direction y of the multilayer body 12 of the multilayer ceramic capacitor 10 is removed by polishing. The LW surface is measured with a powder X-ray diffractometer, and an orthorhombic lattice volume (a axis × b axis × c axis) is calculated from the obtained diffraction pattern by Rietveld analysis.

Further, the hydrogen content contained in the perovskite type compound is measured as follows. The amount of hydrogen gas generated from the multilayer ceramic capacitor 10 is measured by a temperature programmed desorption gas analyzer. First, heating is performed with infrared rays at a heating rate of 20 ° C./min under vacuum. Next, the ion current value of the generated hydrogen is measured. And when the ion current value lattice volume of the perovskite-type compound is less than 275.0A ^3, in the case of 275.0A ³ or more, integrated in a range of 400 ° C. or higher 900 ° C. or less, to calculate the ratio.

  Further, the average thickness of each of the plurality of internal electrode layers and the plurality of dielectric layers is measured as follows. First, the multilayer ceramic capacitor 10 is polished so that a cross section including the length direction z and the stack direction x of the multilayer body (hereinafter referred to as “LT cross section”) is exposed. By observing this LT cross section with a scanning electron microscope, the thickness of each part is observed. In this case, the thickness on a total of five lines is measured, which is the center line passing through the center of the cross section of the stacked body 12 and extending along the stacking direction x and two lines drawn from the center line on both sides. The average value of these five measured values is the average thickness of each part. In order to obtain a more accurate average thickness, the above five measurement values are obtained for each of the upper part, the center part, and the lower part in the stacking direction x, and the average value of these measurement values is taken as the average thickness of each part.

The multilayer ceramic capacitor 10 shown in FIG. 1 includes Ba or Sr having a large ionic radius as a constituent element in the dielectric layer 14 and has a lattice volume of 275.0 ³ , whereby hydrogen is easily retained in the lattice. Since this hydrogen limits the vibration of Zr contained in the lattice, the relative dielectric constant is reduced when hydrogen is contained. However, by removing collectively the hydrogen retained in the lattice of the perovskite type compound of the dielectric layer 14 in the multilayer ceramic capacitor 10 shown in FIG. 1, the relative permittivity can be improved and the capacitance can be increased. A ceramic capacitor can be obtained.

Further, in the multilayer ceramic capacitor 10 shown in FIG. 1, when the lattice volume of the perovskite type compound is 275.0% ³ or more, when the temperature rise rate is increased at 20 ° C./min, hydrogen is generated at 400 ° C. or more and 900 ° C. or less. Occur. In this case, since the relative permittivity is further improved, it is possible to obtain the multilayer ceramic capacitor 10 having further improved capacitance. When the lattice volume of the perovskite compound is less than 275.0 ³ , hydrogen is hardly generated, but when it is 275.0 ³ or more, it is 1.0 to 21.5 times compared to the case where it is less than 275.0 ^3. It is preferable that hydrogen is generated.

Next, a method for manufacturing this multilayer ceramic capacitor will be described.
First, SrCO ₃ , BaCO ₃ , CaCO ₃ , ZrO ₂ , and TiO ₂ having a purity of 99% or more, which are raw material powders, are prepared as materials constituting the main component of the dielectric layer 14. Each of these materials is weighed and then wet mixed by a ball mill. Then, it is dried and crushed. The powder thus obtained is calcined at 1100 ° C. or higher and 1300 ° C. or lower for 2 hours in the air, and then pulverized to obtain a first main component powder. In addition, the manufacturing method of a main component is not specifically limited, such as a solid-phase method and a hydrothermal method, and a raw material is not specifically limited, such as carbonate, an oxide, a hydroxide, a chloride. Further, inevitable impurities such as HfO ₂ may be contained.

Subsequently, SiO ₂ , MnCO ₃ , and Al ₂ O ₃ powders are prepared as additive materials. After the main component powder and these additive materials are weighed, they are wet mixed by a ball mill, and then dried and crushed. As a result, raw material powder is obtained. CaCO ₃ , SrCO ₃ , BaCO ₃ , ZrO ₂ , and TiO ₂ may be added at this stage for adjusting the molar ratio.

  To the obtained raw material powder, a polyvinyl butyral binder and an organic solvent such as toluene and ethanol are added and wet-mixed with a ball mill to prepare a slurry. Using the slurry thus obtained, a sheet can be formed by a doctor blade method and cut to obtain a rectangular ceramic green sheet.

Next, the ceramic green sheet and the conductive paste for internal electrodes obtained in this way are prepared. The ceramic green sheet and the conductive paste for internal electrodes include a binder and a solvent, and a known organic binder or organic solvent can be used.
On the ceramic green sheet, a conductive paste for internal electrodes is printed in a predetermined pattern by, for example, screen printing or gravure printing, thereby forming an internal electrode pattern.
Further, a predetermined number of ceramic green sheets for outer layers on which no internal electrode pattern is formed are laminated, ceramic green sheets on which internal electrode patterns are formed are sequentially laminated thereon, and ceramic green sheets for outer layers are formed thereon. A predetermined number of sheets are laminated to produce a laminated sheet. At this time, a plurality of ceramic green sheets on which the internal electrode patterns are formed are laminated so that the sides from which the internal electrode patterns are drawn are staggered.

And the lamination block is produced by pressing the obtained lamination sheet in the lamination direction by means, such as a hydrostatic pressure press.
Next, the laminated block is cut into a predetermined size, and the laminated chip is cut out. At this time, the corners and ridge lines of the multilayer chip may be rounded by barrel polishing or the like. Further, after heating the laminated chip to 250 ° C. in the atmosphere and burning the binder, the temperature rising rate was 3.33 ° C./min to 200 ° C./min, the top temperature was 1200 ° C. to 1300 ° C., log P _O2 = −9.0. The laminated body 12 is produced by baking at ˜-11.0 MPa.

A conductive paste for an external electrode is applied to both end faces of the obtained laminate 12 and baked in a reducing atmosphere at a top temperature of 800 ° C., thereby forming a baked layer of the external electrode.
Furthermore, if necessary, the surface of the baking layer of the conductive paste for the external electrode is plated to obtain the multilayer ceramic capacitor 10.

  In the method for manufacturing a multilayer ceramic capacitor according to this embodiment, as described below, hydrogen contained in the multilayer body 12 is removed by a voltage application process or a heat treatment in a weak oxidizing atmosphere. Any of these treatment methods for removing hydrogen can be used.

First, the voltage application processing method will be described.
The voltage application process is performed on the obtained multilayer ceramic capacitor. In the voltage application treatment, a DC voltage of 25 kV / mm or more and 80 kV / mm or less is applied for 10 minutes or more and 3600 minutes or less per thickness of the dielectric layer in the temperature atmosphere of 100 ° C. or more and 200 ° C. or less. This is the process.

Next, a heat treatment method in a weak oxidizing atmosphere will be described.
When the perovskite type compound contained in the laminate 12 in which the baking layer is formed is subjected to heat treatment in a weakly oxidizing atmosphere, if plating is performed after the baking layer is formed, the plating is performed before the plating. This is a treatment in which heat treatment is performed for 60 minutes or more and 4800 minutes or less in a weakly oxidizing atmosphere at a temperature of not less than 700 ° C. and not more than 700 ° C. and an oxygen partial pressure of not more than 10 ppm.

  In this method of manufacturing a multilayer ceramic capacitor, hydrogen held in the lattice can be removed by applying a predetermined DC voltage in a temperature atmosphere of 100 ° C. or higher and 200 ° C. or lower for a certain period of time. As a result, the capacitance of the multilayer ceramic capacitor 10 can be increased in a short time.

  Further, in this method of manufacturing a multilayer ceramic capacitor, the relative dielectric constant is improved because the hydrogen held in the lattice is oxidized and discharged by processing in a weakly oxidizing atmosphere in which the external electrodes are not oxidized. An increase in the capacitance of the capacitor 10 can be realized.

  The effects as described above will become clear from the following experimental example.

(Experimental example)
A multilayer ceramic capacitor was produced using the manufacturing method as described above. Here, each material and additive material constituting the main component of the dielectric layer were weighed so as to have the charged values shown in Tables 1 to 3. In the table, those marked with * or ** are outside the scope of the present invention. And when the obtained raw material powder was analyzed by ICP, it was confirmed that it was almost the same as the preparation composition shown in Tables 1 to 3.
Further, as the conductive paste for the internal electrode, a paste containing 100 parts by weight of Ni powder as a metal powder, 7 parts by weight of ethyl cellulose as an organic vehicle, and terpineol as a solvent was used.
Further, when firing the laminated chip, after heating the binder to a temperature of 250 ° C. in the air and burning the binder, the temperature rising rate is 3.33 to 200 ° C./min, the maximum temperature is 1200 to 1300 ° C., the oxygen content is Firing was performed at a pressure log P _O2 = −9.0 to −11.0 MPa to obtain a ceramic sintered body. When the obtained sintered body was analyzed by ICP, it was confirmed that it was almost the same as the preparation composition shown in Tables 1 to 3.
The sintered body was barreled to expose the internal electrode from the end face, and an external electrode paste containing Cu was applied thereto. After the external electrode paste containing Cu was dried, the baking layer of the external electrode was baked at a maximum temperature of 800 ° C. in a reducing atmosphere. Subsequently, a first plating layer using Ni was formed on the surface of the baking layer by a barrel plating method, and then a second plating layer using Sn was similarly formed on the surface of the first plating layer.
When the XRD structure analysis of the obtained laminate was performed, it was revealed that the main component has a perovskite type structure based on barium titanate. In the samples 1 to 48, the L dimension in the length direction z is 3.2 mm, the W dimension in the width direction y is 1.6 mm, and the T dimension in the stacking direction x is 1.6 mm. Sample 49 to sample 52 have an L dimension in the length direction z of 0.25 mm, a W dimension in the width direction y of 0.125 mm, and a T dimension in the stacking direction x of 0.125 mm.

The multilayer ceramic capacitor thus obtained was evaluated as follows.
-Method for confirming the rate of increase in capacitance (a) Voltage application treatment The capacitance of a multilayer ceramic capacitor with n = 20 samples was measured with an LCR meter. The measurement frequency was 1 kHz. After the measurement, the conditions for the voltage application treatment were the temperature, DC voltage, and application time shown in Tables 1 and 2. The capacitance of the multilayer ceramic capacitor with n = 20 samples after voltage treatment was measured with an LCR meter in the same manner as before voltage treatment. The rate of change in capacitance before and after voltage treatment was calculated using the following formula. Further, the amount of hydrogen gas generated from the multilayer ceramic capacitor was measured with a temperature programmed desorption gas analyzer. First, heating is performed with infrared rays at a heating rate of 20 ° C./min under vacuum. Next, the ion current value of the generated hydrogen is measured. And when the ion current value lattice volume of the perovskite-type compound is less than 275.0A ^3, in the case of 275.0A ³ or more, integrated in a range of 400 ° C. or higher 900 ° C. or less, and calculate the magnification. Tables 1 and 2 show the average value of n = 20. The sample numbers in the table marked with ** are the results when left for 2 weeks without voltage application. Further, except for Sample No. 6 and Sample No. 14, crystals contained in the perovskite type compound contained in the dielectric layer were orthorhombic.

Change rate of capacitance = ((capacitance after voltage processing) − (capacitance before voltage processing)) / (capacitance before voltage processing) * 100

(B) Heat treatment in weak oxidizing atmosphere The capacitance of the multilayer ceramic capacitor having the number of samples n = 20 was measured with an LCR meter. The measurement frequency was 1 kHz. After the measurement, the heat treatment was performed under the conditions of temperature, oxygen partial pressure, and treatment time shown in Table 3 as conditions for heat treatment in a weak oxidizing atmosphere. The capacitance of the multilayer ceramic capacitor with n = 20 samples after the heat treatment was measured with an LCR meter in the same manner as before the heat treatment. The change rate of the capacitance before and after the heat treatment was calculated by the following formula. Table 3 shows the average value of n = 20. In all of sample numbers 1 to 4, the crystals contained in the perovskite type compound contained in the dielectric layer were orthorhombic.

Change rate of capacitance = ((capacitance after heat treatment) − (capacitance before heat treatment)) / (capacitance before heat treatment) * 100

Here, the external electrode of the multilayer ceramic capacitor was removed by polishing, the obtained multilayer body was subjected to a solution treatment by an alkali melting method, and ICP analysis was performed on this solution. These were confirmed to be almost the same as the preparation compositions shown in Tables 1 to 3.

Tables 1 and 2 show the evaluation results based on the change in the capacitance of the multilayer ceramic capacitor when the voltage application treatment is performed.
Table 3 shows the evaluation results based on the change in the capacitance of the multilayer ceramic capacitor when the heat treatment is performed in a weak oxidizing atmosphere.

(Evaluation results)
From the results shown in Table 1 and Table 2, for the dielectric layer of the multilayer ceramic capacitor, the mole% of Sr is given by (number of moles of Sr) / (number of moles of Sr + number of moles of Ba + number of moles of Ca). 40% or more and 90% or less, and the mole percentage of Ba is given by (number of moles of Ba) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 45% or less, The mole percentage of Ca is given by (number of moles of Ca) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 20% or less, and the mole percentage of Zr is (mol of Zr). Number) / (number of moles of Zr + number of moles of Ti), which is 90% or more and 100% or less, and the mole percentage of Ti is (number of moles of Ti) / (number of moles of Zr + number of moles of Ti). 0% or more and 10% or less, (number of moles of Sr + number of moles of Ba + The number of moles of a) / (number of moles of Zr + number of moles of Ti) is 1.00 or more and 1.03 or less, and the crystals contained in the perovskite type compound contained in the dielectric layer are orthorhombic. For a multilayer ceramic capacitor having a lattice volume of 275.0 mm ³ or more, a DC voltage of 25 kV / mm or more and 80 kV / mm or less per thickness of the dielectric layer in a temperature atmosphere of 100 ° C. or more and 200 ° C. or less, which is a voltage application process. As a result, a multilayer ceramic capacitor having a predetermined increased capacitance was obtained. Further, the sample is within the scope of the present invention, when the lattice volume of the perovskite compound is 275.0A ³ or more, the total amount of hydrogen generated at 400 ° C. or higher 900 ° C. or less, the lattice volume of the perovskite-type compound It was confirmed that it was 1.0 to 21.5 times compared to the case of less than 275.0 cm ³ .

From the results shown in Table 3, for the dielectric layer of the multilayer ceramic capacitor, the mole percentage of Sr is given by (number of moles of Sr) / (number of moles of Sr + number of moles of Ba + number of moles of Ca). 40% or more and 90% or less, and the mol% of Ba is given by (number of moles of Ba) / (number of moles of Sr + number of moles of Ba + number of moles of Ca). % Of mol of Ca is given by (number of moles of Ca) / (number of moles of Sr + number of moles of Ba + number of moles of Ca) of 0% or more and 20% or less, and the mole percentage of Zr is (number of moles of Zr). ) / (Number of moles of Zr + number of moles of Ti), and 90% or more and 100% or less, and the mole percentage of Ti is given by (number of moles of Ti) / (number of moles of Zr + number of moles of Ti). 0% or more and 10% or less, (number of moles of Sr + number of moles of Ba + Ca The number of moles) / (number of moles of Zr + number of moles of Ti) is 1.00 or more and 1.03 or less, and the crystals contained in the perovskite type compound contained in the dielectric layer are orthorhombic and have a lattice volume. the laminated ceramic capacitor but is 275.0A ³ or more, a heat treatment in a weak oxidizing atmosphere, the heat treatment conditions for the perovskite-type compound, a temperature of 600 ° C. or higher 700 ° C. or less, the oxygen partial pressure of 10 ppm, A sample subjected to a heat treatment for 60 minutes or more and 4800 minutes or less obtained a multilayer ceramic capacitor having a predetermined increased capacitance.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is carried out within the range of the summary.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 12 Laminated body 12a 1st main surface 12b 2nd main surface 12c 1st side surface 12d 2nd side surface 12e 1st end surface 12f 2nd end surface 14 Dielectric layer 14a Outer layer part 14b Inner layer part 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a, 18b Lead electrode portion 20a Counter electrode portion 20b W gap 20c L gap 22 External electrode 22a First external electrode 22b Second external electrode 24a, 24b Base electrode layer 26a, 26b Plating layer

Claims (4)

In a multilayer ceramic capacitor including a perovskite type compound containing Sr, Ba, Ca, Ti, Zr,
The multilayer ceramic capacitor includes a multilayer body,
The stacked body includes a plurality of stacked dielectric layers and a plurality of internal electrode layers, and further, a first main surface and a second main surface facing the stacking direction are orthogonal to the stacking direction. A first side surface and a second side surface opposed to the width direction; a first end surface and a second end surface opposed to the stacking direction and a length direction perpendicular to the width direction;
A first covering the first end surface and extending from the first end surface and covering the first main surface, the second main surface, the first side surface and the second side surface External electrodes,
A second end surface covering the second end surface and extending from the second end surface and covering the first main surface, the second main surface, the first side surface and the second side surface; With external electrodes,
The dielectric layer is
The mole percentage of Sr is given by (number of moles of Sr) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 40% or more and 90% or less,
The mole percentage of Ba is given by (number of moles of Ba) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 45% or less,
The mol% of Ca is given by (number of moles of Ca) / (number of moles of Sr + number of moles of Ba + number of moles of Ca), and is 0% or more and 20% or less,
The mole percentage of Zr is given by (number of moles of Zr) / (number of moles of Zr + number of moles of Ti), and is 90% or more and 100% or less,
The mole percentage of Ti is given by (number of moles of Ti) / (number of moles of Zr + number of moles of Ti), and is 0% or more and 10% or less,
(Number of moles of Sr + number of moles of Ba + number of moles of Ca) / (number of moles of Zr + number of moles of Ti) is 1.00 or more and 1.03 or less,
The crystals contained in the perovskite compound contained in the dielectric layer is orthorhombic, wherein the cell volume is 275.0A ³ or more, the multilayer ceramic capacitor.   2. The laminate according to claim 1, wherein heat is applied to the laminate at a heating rate of 20 ° C./min, and hydrogen is generated from the laminate in a temperature range of 400 ° C. or more and 900 ° C. or less. Ceramic capacitor.   The multilayer ceramic capacitor according to claim 1, wherein a DC voltage of 25 kV / mm or more and 80 kV / mm or less is applied for 10 minutes or more and 3600 minutes or less per thickness of the dielectric layer in a temperature atmosphere of 100 ° C. or more and 200 ° C. or less. A method for producing a multilayer ceramic capacitor, comprising:   The perovskite compound according to claim 1 is heat-treated at a temperature of 600 ° C. to 700 ° C. in a weakly oxidizing atmosphere having an oxygen partial pressure of 10 ppm or less for 60 minutes to 4800 minutes after forming the external electrode. , Manufacturing method of multilayer ceramic capacitor.

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