JP2017044597A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device that can conduct current testing with high accuracy and in short time when a logic circuit works.CONSTITUTION: A PLL circuit is configured to multiply a low-speed clock signal to generate an internal high-speed clock signal, and an analog-to-digital converter is configured to convert input analog information data to digital information data. A test circuit includes a first selection circuit that selects any one of the internal high-speed clock signal and an external high-speed clock signal supplied from an outside of a semiconductor device on the basis of a test mode setting signal, and a second selection circuit that selects any one of the digital information data and digital test data on the basis of the test mode setting signal. A logic circuit is configured to conduct demodulation processing of the digital information data or the digital test data on the basis of the internal high-speed clock signal or the external high-speed clock signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device including a PLL circuit and an analog-digital converter.

  As a wireless communication device that receives a radio signal such as a radio frequency (RF) signal and demodulates it to obtain received data, for example, a PLL (Phase Locked Loop) circuit, an analog digital converter (ADC) and logic A semiconductor device provided with a circuit is known (for example, Patent Document 1). Such a semiconductor device operates by receiving a low-speed clock signal and analog data from an RF receiving circuit, for example. The PLL circuit multiplies the low-speed clock signal to generate a high-speed clock signal. The logic circuit generates a control signal for turning on the power supply of the ADC based on the high-speed clock signal. The ADC receives a control signal from the logic circuit and converts analog data into digital data based on the high-speed clock signal generated by the PLL circuit. The logic circuit demodulates the digital data converted in the ADC to obtain received data.

JP 2009-296310 A

  In the semiconductor device as described above, in order to determine the performance of the logic circuit and the presence / absence of a failure, a so-called operation current test is performed in which a current flowing during operation is measured and compared with an expected value. When performing an operating current test, for example, digital data generated by an ADC is supplied to a logic circuit, and the logic circuit is operated to measure current. Therefore, for example, when there is some malfunction in the ADC, digital data is not stably supplied to the logic circuit. Even if there is no malfunction in the ADC, the digital data output from the ADC is affected by the power supply and ground of the semiconductor device, so that the supply of digital data to the logic circuit becomes unstable. For this reason, even if the same analog data is input to the ADC each time for each test, the same digital data is not always supplied to the logic circuit, and there is a problem that the accuracy of the current test during operation is lowered. . Furthermore, since the low-speed clock signal input to the PLL circuit and the high-speed clock signal output from the PLL circuit are asynchronous, there is a problem that the output of the logic circuit varies.

  In addition, a waiting time occurs between the time when the power supply of the semiconductor device is turned on and the time when the operation of each unit is stabilized. For example, a waiting time for stabilizing the operation of the PLL circuit occurs after the low-speed clock signal is input to the PLL circuit until the high-speed clock signal is stably output. Further, since the logic circuit enables the ADC control signal after the analog data is stably supplied from the RF receiving circuit, a waiting time for the stable supply of analog data is required. Furthermore, a waiting time also occurs after the control signal is enabled and before the ADC is turned on. As described above, since the operating current test is started after many waiting times, the operating current test takes time.

  In order to solve the above-described problems, an object of the present invention is to provide a semiconductor device capable of performing an operation current test of a logic circuit with high accuracy in a short time.

  A semiconductor device according to the present invention includes a PLL circuit that multiplies a low-speed clock signal to generate an internal high-speed clock signal, an analog-digital converter that converts input analog information data into digital information data, and a test mode setting signal. A first selection circuit for selecting one of the internal high-speed clock signal and an external high-speed clock signal supplied from the outside, and the digital information data and the digital test data based on the test mode setting signal A test circuit having a second selection circuit for selecting one of them, and a logic circuit that performs demodulation processing of the digital information data or the digital test data based on the internal high-speed clock signal or the external high-speed clock signal It is characterized by including these.

  According to the present invention, it is possible to accurately perform a current test during operation of a logic circuit in a short time.

1 is a block diagram illustrating a configuration of a semiconductor device 10 according to a first embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor device 20 which concerns on Example 2 of this invention. FIG. 6 is a block diagram illustrating a configuration of a logic circuit 21 according to a second embodiment. It is a block diagram which shows the structure of the semiconductor device 30 which concerns on Example 3 of this invention. It is a block diagram which shows the structure of the semiconductor device 40 which concerns on Example 4 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the present invention. The semiconductor device 10 includes a PLL (Phase Locked Loop) circuit 11, an ADC (Analog Digital Converter) 12, a test circuit 13, and a logic circuit 18. The semiconductor device 10 receives a low-speed clock signal LCK and analog information data AD from an RF (Radio Frequency) receiving circuit (not shown).

  The PLL circuit 11 multiplies the low-speed clock signal LCK supplied from the RF reception circuit to generate an internal high-speed clock signal HCK.

  The ADC 12 performs analog-to-digital conversion on the analog information data AD input from the RF receiving circuit to obtain digital information data DD. The ADC 12 is controlled to be turned on by a selection control signal SCS supplied from a third selection circuit 16 described later. The ADC 12 performs the analog-digital conversion process in synchronization with the selection clock signal SCK supplied from the first selection circuit 14.

  The test circuit 13 is provided in the semiconductor device 10 in order to perform a test (hereinafter referred to as an operation current test) for measuring a current flowing during operation of the ADC 12 and the logic circuit 18 and comparing the measurement result with an expected value. Circuit. The test circuit 13 includes a first selection circuit 14, a second selection circuit 15, and a third selection circuit 16.

  A test enable signal TE is supplied to the first selection circuit 14, the second selection circuit 15, and the third selection circuit 16 from the outside of the semiconductor device 10.

  The test enable signal TE is a test mode setting signal for setting the test circuit 13 to a mode for performing an operation current test (hereinafter referred to as a test mode). For example, the test enable signal TE has a signal value “0” or “1”. It consists of a value signal. In the test mode, the test enable signal TE of “ON” (for example, signal value “1”) is supplied to the test circuit 13. On the other hand, in the normal operation mode that is not the test mode, the test enable signal TE of “OFF” (for example, signal value “0”) is supplied to the test circuit 13. That is, in the test mode, the test mode setting signal indicates enable, and in the normal operation mode that is not the test mode, the test mode setting signal indicates disable.

  An external high-speed clock signal ECK is supplied to the first selection circuit 14 from the outside of the semiconductor device 10. The external high-speed clock signal ECK is a clock signal corresponding to the operation current test.

  External digital data ED is supplied to the second selection circuit 15 from the outside of the semiconductor device 10. The external digital data ED is digital test data for use in an operation current test.

  The first selection circuit 14 selects one of the internal high-speed clock signal HCK supplied from the PLL circuit 11 and the external high-speed clock signal ECK supplied from the outside according to the test enable signal TE, and serves as the selection clock signal SCK. The logic circuit 18 and the ADC 12 are supplied. Specifically, when the test enable signal TE is on, the first selection circuit 14 selects the external high-speed clock signal ECK as the selection clock signal SCK and supplies it to the logic circuit 18 and the ADC 12. On the other hand, when the test enable signal TE is off, the first selection circuit 14 selects the internal high-speed clock signal HCK as the selection clock signal SCK and supplies it to the logic circuit 18 and the ADC 12.

  The second selection circuit 15 selects one of the digital information data DD supplied from the ADC 12 and the external digital data ED supplied from the outside according to the test enable signal TE, and supplies it to the logic circuit 18 as selection data SD. To do. Specifically, when the test enable signal TE is on, the second selection circuit 15 selects the external digital data ED as selection data SD and supplies it to the logic circuit 18. When the test enable signal TE is off, the second selection circuit 15 selects the digital information data DD as the selection data SD and supplies it to the logic circuit 18.

  The third selection circuit 16 includes a storage unit 17. The storage unit 17 stores a fixed value FV that is a signal value of a control signal for controlling the ADC 12 to be turned on. The third selection circuit 16 selects either the internal control signal CS supplied from the logic circuit 18 or a fixed signal having a fixed value FV according to the test enable signal TE, and supplies the selected signal to the ADC 12 as the selection control signal SCS. . Specifically, when the test enable signal TE is on, the third selection circuit 16 selects a fixed signal having a fixed value FV as the signal value of the selection control signal SCS and supplies it to the ADC 12. When the test enable signal TE is off, the third selection circuit 16 selects the internal control signal CS as the selection control signal SCS and supplies it to the ADC 12.

  Both the internal control signal CS and the fixed signal having the fixed value FV are control signals for controlling the power supply of the ADC 12 to be turned on. That is, the third selection circuit 16 is a power supply control circuit for the ADC 12.

  The logic circuit 18 supplies the internal control signal CS to the third selection circuit 16 in response to the supply of the selection clock signal SCK from the first selection circuit 14. The logic circuit 18 performs demodulation processing, decoding processing, and the like on the selection data SD supplied from the second selection circuit 15 in synchronization with the selection clock signal SCK, and obtains a logic circuit output LO.

  As described above, the test enable signal TE that is on (signal value “1”) is supplied to the first selection circuit 14, the second selection circuit 15, and the third selection circuit 16 in the test mode. Therefore, in the test mode, the first selection circuit 14 selects the external high-speed clock signal ECK and supplies it to the logic circuit 18. The second selection circuit 15 selects the external digital data ED and supplies it to the logic circuit 18. The logic circuit 18 performs demodulation processing and decoding processing on the external digital data ED in synchronization with the external high-speed clock signal ECK.

  As described above, the semiconductor device 10 of this embodiment includes the first selection circuit 14 that supplies the external high-speed clock signal ECK to the logic circuit 18 in the test mode. Therefore, the logic circuit 18 can perform operations such as demodulation processing and decoding processing in synchronization with an external clock signal (external high-speed clock signal ECK) without waiting for stabilization of the operation of the PLL circuit 11.

  In addition, the semiconductor device 10 of the present embodiment includes a second selection circuit 15 that supplies the external digital data ED to the logic circuit 18 in the test mode. Therefore, the logic circuit 18 can perform operations such as demodulation processing and decoding processing on external digital data (external digital data ED) without waiting for stabilization of the operation of the ADC 12.

  Therefore, in the test mode, the logic circuit 18 can be operated at an arbitrary timing regardless of the states of the PLL circuit 11 and the ADC 12, so that the operation current test of the logic circuit 18 can be performed in a short time.

  In addition, the semiconductor device 10 of the present embodiment includes a first selection circuit 14 that selects a signal having a signal value of the fixed value FV and supplies the signal to the ADC 12 in the test mode. Therefore, the power of the ADC 12 can be turned on at an arbitrary timing in the test mode. This makes it possible to perform an operation current test of the ADC 12 in a short time.

  In addition, the logic circuit 18 performs demodulation processing and decoding processing in synchronization with the external digital data ED that does not undergo analog-digital conversion by the ADC 12. Therefore, for example, even when the ADC 12 has a problem or when the output of the ADC 12 fluctuates due to the influence of the power source, the ground, or the like of the semiconductor device 10, the demodulation process is not affected by this. And a decoding process can be performed. Therefore, the operation current test of the logic circuit 18 can be accurately performed. Further, the operation current test of the ADC 12 and the operation current test of the logic circuit 18 can be performed separately.

  The logic circuit 18 performs demodulation processing and decoding processing in synchronization with the external high-speed clock signal ECK that does not undergo clock signal multiplication processing by the PLL circuit 11. Therefore, demodulation processing and decoding processing can be performed regardless of the state of the PLL circuit 11. Therefore, the operation current test of the logic circuit 18 can be accurately performed.

  FIG. 2 is a block diagram illustrating a configuration of the semiconductor device 20 according to the second embodiment. Hereinafter, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 20 is a device that is provided, for example, in a terrestrial digital broadcast receiver and performs demodulation processing and decoding processing on an OFDM (Orthogonal Frequency Division Multiplexing) modulated wave. The semiconductor device 20 includes a PLL circuit 11, an ADC 12, a test circuit 13, and a logic circuit 21.

  FIG. 3 is a block diagram showing a configuration of the logic circuit 21. The logic circuit 21 is supplied with a test enable signal TE, selection data SD from the second selection circuit 15, and an external timing signal ES from the outside of the apparatus. The logic circuit 21 includes a demodulator 22, a decoder 23, and a TS (Transport Stream) converter 27. The decoding unit 23 includes a synchronization detection block 24, a fourth selection circuit 25, and a decoding and error correction block 26.

  The demodulation unit 22 performs demodulation processing on the selection data SD supplied from the second selection circuit 15 to obtain demodulation data FD. The demodulation unit 22 supplies the demodulated data FD to the synchronization detection block 24 and the decoding and error correction block 26 of the decoding unit 23.

  The synchronization detection block 24 detects synchronization by detecting a synchronization pattern included in the demodulated data FD, and generates an internal timing signal IS. For example, the synchronization detection block 24 detects synchronization by detecting a unique word included in the head portion of the packet in the demodulated data FD (hereinafter referred to as unique word detection). The synchronization detection block 24 performs synchronization detection by decoding a transmission multiplexing control signal (TMCC: Transmission and Multiplexing Configuration and Control) included in the demodulated data FD (hereinafter referred to as TMCC decoding detection).

  An external timing signal ES is supplied to the fourth selection circuit 25 from the outside of the semiconductor device 20. The fourth selection circuit 25 selects one of the external timing signal ES and the internal timing signal IS supplied from the synchronization detection block 24 and supplies the selected timing signal SS to the decoding and error correction block 26. Specifically, when the test enable signal TE is on, the fourth selection circuit 25 selects the external timing signal ES as the selection timing signal SS and supplies it to the decoding and error correction block 26. On the other hand, when the test enable signal TE is off, the fourth selection circuit 25 selects the internal timing signal IS as the selection timing signal SS and supplies it to the decoding and error correction block 26.

  The decoding and error correction block 26 performs a decoding process on the demodulated data FD in synchronization with the selection timing signal SS supplied from the fourth selection circuit 25. The decoding and error correction block 26 performs error detection and error correction processing using parity bits, CRC (Cyclic Redundancy Code), and the like. The decoding and error correction block 26 supplies the data subjected to the decoding process and the error correction process to the TS conversion unit 27 as decoded data GD.

  The TS converter 27 converts the decoded data GD into a TS (Transport Stream) method, and obtains a logic circuit output LO.

  In the semiconductor device 20 configured as described above, the test enable signal TE that is on (signal value “1”) is supplied to the fourth selection circuit 25 in the test mode. Accordingly, the fourth selection circuit 25 selects the external timing signal ES and supplies it to the decoding and error correction block 26. The decoding and error correction block 26 performs decoding processing and error correction processing on the demodulated data FD in synchronization with the external timing signal ES. Therefore, the decoding and error correction block 26 can perform the decoding process and the error correction process at an arbitrary timing regardless of the synchronization detection timing in the synchronization detection block 24.

  That is, in synchronization detection by unique word detection, for example, when demodulated data FD is input to the synchronization detection block 24 from the end of the unique word, synchronization detection is performed until the beginning of the next unique word is input. Can not. In addition, since the demodulation data FD for one OFDM frame is necessary for the TMCC decoding determination, the synchronization detection cannot be performed until the demodulation data FD for one OFDM frame is supplied to the synchronization detection block 24. Therefore, since synchronization detection in the synchronization detection block 24 takes a time of at least one OFDM frame, when performing decoding processing and error correction processing in synchronization with the internal timing signal IS, the decoding and error correction block 26 immediately performs processing. Can not do. However, according to the logic circuit 21 of this embodiment, in the test mode, the decoding and error correction block 26 performs processing in synchronization with the external timing signal ES, so that a waiting time for synchronization detection in the synchronization detection block 24 is required. Therefore, the decoding process and the error correction process can be performed.

  Therefore, according to the semiconductor device 20 of the present embodiment, the decoding unit 23 can be operated at an arbitrary timing in the test mode, so that the operation current test of the logic circuit 21 can be performed in a short time.

  FIG. 4 is a block diagram illustrating a configuration of the semiconductor device 30 according to the third embodiment. The semiconductor device 30 of this embodiment is different from that of the first embodiment in that digital test data is generated inside the device without receiving external digital data ED from outside the device. Hereinafter, the same components as those of the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 30 includes a PLL circuit 11, an ADC 12, a test circuit 31, and a logic circuit 18.

  The test circuit 31 includes a first selection circuit 32, a digital data generation circuit 33, a second selection circuit 34, and a third selection circuit 35.

  The first selection circuit 32 selects one of the internal high-speed clock signal HCK supplied from the PLL circuit 11 and the external high-speed clock signal ECK supplied from the outside in accordance with the test enable signal TE, and serves as the selection clock signal SCK. This is supplied to the logic circuit 18, the ADC 12 and the digital data generation circuit 33. Similar to the first selection circuit 14 of the first embodiment, the first selection circuit 32 is configured such that the external high-speed clock signal ECK when the test enable signal TE is on and the internal high-speed clock when the test enable signal TE is off. The signal HCK is selected as the selected clock signal SCK.

  The digital data generation circuit 33 receives the supply of the selection clock signal SCK from the first selection circuit 21, generates digital test data corresponding to the clock pattern of the selection clock signal SCK, and supplies it to the second selection circuit 34 as test data TD. Supply.

  The second selection circuit 34 selects one of the digital information data DD supplied from the ADC 12 and the test data TD supplied from the digital data generation circuit 33 according to the test enable signal TE, and selects a logic circuit as selection data SD. 18 is supplied. Specifically, when the test enable signal TE is on, the second selection circuit 34 selects the test data TD as the selection data SD and supplies it to the logic circuit 18. When the test enable signal TE is off, the second selection circuit 34 selects the digital information data DD as the selection data SD and supplies it to the logic circuit 18.

  Similar to the third selection circuit 16 of the first embodiment, the third selection circuit 35 includes a storage unit 36 that stores a fixed value FV. The third selection circuit 35 selects one of the internal control signal CS supplied from the logic circuit 18 and the fixed value FV stored in the storage unit 36 according to the test enable signal TE, and serves as the selection control signal SCS. Supply to ADC12. The third selection circuit 35 selects the fixed value FV when the test enable signal TE is on and the internal control signal CS as the selection control signal SCS when the test enable signal TE is off, and supplies the selection control signal SCS to the ADC 12. Supply.

  As described above, the test circuit 31 of the semiconductor device 30 of this embodiment includes the digital data generation circuit 33 that generates the test data TD in synchronization with the test enable signal TE and the external high-speed clock signal ECK. Therefore, the digital test data can be generated inside the apparatus without being supplied with the external digital data ED as in the first embodiment. Therefore, the number of terminals for receiving external signal input can be reduced.

  Further, according to the test circuit 31 of the semiconductor device 30 of the present embodiment, it is possible to reduce the memory capacity used in the operation current test. That is, in the conventional semiconductor device of the wireless communication device that does not have the test circuit 31, a complex pattern of analog information data is input as a test pattern in order to operate the entire semiconductor device during an operation current test. Capacity is required. On the other hand, in the semiconductor device 30 of this embodiment, digital test data is obtained using the test enable signal TE having the signal value “1” and the external high-speed clock signal ES formed by repeating the signal values “0” and “1”. Since the generated current test is performed, it is possible to perform the current test while suppressing the memory capacity to be used.

  FIG. 5 is a block diagram illustrating a configuration of the semiconductor device 40 according to the fourth embodiment. The semiconductor device 40 of the present embodiment is different from the first embodiment in that the test enable signal TE is not supplied from the outside of the device and the test enable signal TE is generated inside the device. Hereinafter, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 40 includes a PLL circuit 11, an ADC 12, a test circuit 41, and a logic circuit 18.

  The test circuit 41 includes a first selection circuit 14, a second selection circuit 15, a third selection circuit 16, and a digital data decoding circuit 42.

  In the present embodiment, the external digital data ED supplied from the outside of the semiconductor device 40 includes an encoded test enable signal TE (that is, an encoded test mode setting signal). The external digital data ED is supplied to the second selection circuit 15 and the digital data decoding circuit 42.

  The digital data decoding circuit 42 decodes the encoded test enable signal TE included in the external digital data ED in synchronization with the external high-speed clock signal ECK to obtain the test enable signal TE. That is, the digital data decoding circuit 42 is a test mode setting signal decoding circuit that decodes the digital test data and obtains a test mode setting signal. The digital data decoding circuit 42 supplies the generated test enable signal TE to the first selection circuit 14, the second selection circuit 15, and the third selection circuit 16.

  As described above, the test circuit 41 of the semiconductor device 40 according to this embodiment includes the digital data decoding circuit 42 that decodes the encoded test enable signal TE included in the external digital data ED to obtain the test enable signal TE. . As a result, it is not necessary to supply the test enable signal TE from the outside of the apparatus separately from the external digital data ED, so that the number of terminals for receiving a signal input from the outside of the apparatus can be reduced.

  As described above, the semiconductor device of the present invention includes the test circuit, and in the test mode, the clock signal (ECK) independent of the operation of the PLL circuit 11 and the digital data (ED, TD) independent of the operation of the ADC 12 are obtained. , Supply to the logic circuit. Therefore, the operation current test can be started without waiting for stabilization of the operation of the PLL circuit 11 and the ADC 12, and the test can be performed in a short time.

  In addition, since the logic circuit is operated by supplying digital data not subjected to analog-digital conversion by the ADC 12 to the logic circuit, it is influenced by the state of the ADC 12 (the influence of the output of the ADC 12 from the power supply or the ground, the malfunction of the ADC 12, etc.). Therefore, a highly accurate operation current test can be performed. In addition, the ADC 12 operating current test and the logic circuit operating current test can be performed separately.

  In addition, the above-described Examples 1 to 4 can be applied in combination as appropriate.

  The present invention is not limited to the above embodiment. For example, in the first to third embodiments, the configuration in which the test enable signal TE is supplied from the outside of the semiconductor device has been described as an example. However, the present invention is not limited to this. For example, a register is set in the semiconductor device by I2C (Inter-Integrated Circuit) communication or SPI (Serial Peripheral Interface) communication using an asynchronous interface, and the test circuit is controlled to the test mode. There may be.

  In the second embodiment, an example in which the semiconductor device of the present invention is provided in a terrestrial digital broadcast receiver has been described. However, the present invention is not limited to this, and the present invention can be widely used for other reception methods for performing synchronization detection. In addition to the second embodiment, the semiconductor devices of the first, third, and fourth embodiments may be used for terrestrial digital broadcasting and other receivers.

  In the first to fourth embodiments, a timer may be provided inside the semiconductor device, and the test enable signal TE may be switched from on to off when a predetermined time elapses after the operation current test is started. For example, by setting the time until the operations of the PLL circuit 11 and the ADC 12 are stabilized as a predetermined time of the timer, the logic circuit 18 can calculate the internal high-speed clock signal HCK multiplied by the PLL circuit 11 after the predetermined time has elapsed. Demodulation processing and decoding processing can be performed using the digital information data DD analog-digital converted by the ADC 12. Further, for example, in the second embodiment, by setting the predetermined time of the timer to a time corresponding to one OFDM frame (for example, 204 msec), the decoding and error correction block 26 is synchronized after the synchronization detection in the synchronization detection block 24. Decoding processing and error correction processing can be performed in synchronization with the internal timing signal IS generated by the detection block 24.

  In short, a semiconductor device (10) according to the present invention includes a PLL circuit (11) that multiplies a low-speed clock signal to generate an internal high-speed clock signal, and analog-to-digital conversion that converts input analog information data into digital information data. A first selection circuit (14) for selecting one of an internal high-speed clock signal and an external high-speed clock signal supplied from the outside based on the test mode setting signal, and a test mode setting signal A test circuit (13) having a second selection circuit (15) for selecting either digital information data or digital test data based on the internal high-speed clock signal or the external high-speed clock signal. And a logic circuit (18) for demodulating information data or digital test data. It is intended.

10, 20, 30, 40 Semiconductor device 11 PLL circuit 12 ADC
13, 31, 41 Test circuit 14, 32 First selection circuit 15, 34 Second selection circuit 16, 35 Third selection circuit 17, 36 Storage unit 18, 21 Logic circuit 22 Demodulation unit 23 Decoding unit 24 Synchronization detection block 25 First 4 selection circuit 26 decoding and error correction block 27 TS converter 33 digital data generation circuit 42 digital data decoding circuit

Claims (9)

A PLL circuit that multiplies the low-speed clock signal to generate an internal high-speed clock signal;
An analog-digital converter that converts the input analog information data into digital information data;
A first selection circuit for selecting one of the internal high-speed clock signal and an external high-speed clock signal supplied from outside based on a test mode setting signal; and the digital information data based on the test mode setting signal A second selection circuit that selects any one of the digital test data; and a test circuit having:
A logic circuit that performs demodulation processing of the digital information data or the digital test data based on the internal high-speed clock signal or the external high-speed clock signal;
A semiconductor device comprising: When the test mode setting signal indicates enable, the first selection circuit selects the external high-speed clock signal and supplies it to the logic circuit.
2. The semiconductor device according to claim 1, wherein the second selection circuit selects the digital test data and supplies the digital test data to the logic circuit when the test mode setting signal indicates enable.   The semiconductor device according to claim 1, wherein the test circuit further includes a power supply control circuit that turns on the power supply of the analog-digital converter when the test mode setting signal indicates enable.   4. The semiconductor device according to claim 1, wherein the test mode setting signal is supplied from outside the semiconductor device, and the digital test data is supplied from outside the semiconductor device. The logic circuit is
A demodulator that performs demodulation processing to obtain demodulated data;
A decoding and error correction unit for performing decoding processing and error correction processing on the demodulated data;
A synchronization detector that performs synchronization detection based on the demodulated data and generates an internal timing signal;
A fourth selection circuit that selects one of the internal timing signal and an external timing signal supplied from the outside of the semiconductor device based on the test mode setting signal and supplies the selected timing signal to the decoding and error correction unit When,
Including
2. The decoding and error correction unit performs the decoding process and the error correction process in synchronization with the internal timing signal or the external timing signal supplied from the fourth selection circuit. 5. A semiconductor device according to any one of 4 to 4.   The test circuit further includes a digital data generation circuit that generates the digital test data in synchronization with a signal selected from the internal high-speed clock signal or the external high-speed clock signal by the first selection circuit. The semiconductor device according to claim 1. The digital test data includes encoded data obtained by encoding the test mode setting signal,
The test circuit further includes a test mode setting signal decoding circuit that obtains the test mode setting signal by decoding the encoded data included in the digital test data in synchronization with the external high-speed clock signal. The semiconductor device according to claim 1. The PLL circuit is supplied with the low-speed clock signal from a receiving circuit that receives a radio signal,
The semiconductor device according to claim 1, wherein the analog-digital converter receives the analog information data from the receiving circuit.   The semiconductor device according to claim 8, wherein the wireless signal is an OFDM signal.