JP2016225603A - Multilayer ceramic capacitor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor capable of suppressing occurrence of a short circuit between inner electrodes, and a method of manufacturing the same.SOLUTION: A multilayer ceramic capacitor having a laminated body 16 and a side margin portion 21 includes an off-set portion 24. The laminated body 16 includes inner electrodes 12, 13 and a dielectric layer 17 which are alternately laminated. The side margin portion 21 is composed of a dielectric body and is provided so as to cover a side surface S of the laminated body 16. The off-set portion 24 is made of an amorphous region or a void region. The off-set portion 24 is formed between the inner electrodes 12, 13 and the side margin portion 21 in a manner such that end portions 22, 23 of the inner electrodes 12, 13 at the side of the side surface S are offset from the side surface in the inside direction of the laminated body 16.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a monolithic ceramic capacitor that can be reduced in size and increased in capacity, and a method for manufacturing the same.

  In recent years, with the downsizing and high performance of electronic devices, there is an increasing demand for downsizing and increasing the capacity of multilayer ceramic capacitors used in electronic devices. In order to increase the capacitance while keeping the size of the multilayer ceramic capacitor small, it is effective to increase the intersection area of the internal electrodes of the multilayer ceramic capacitor (the area of the overlapping portion of the opposing internal electrodes) as much as possible.

  As a technique for increasing the crossing area of the internal electrodes, the side surface portion of the multilayer chip is cut off to expose the internal electrodes to the cut surface, and then the insulation around the internal electrodes is secured on the cut surface. For this reason, a technique for forming a side margin portion for the purpose of retrofitting has been developed. With this technique, the side margin can be formed thin, and the crossing area of the internal electrodes can be made relatively large.

  When the side surface portion of the multilayer chip is cut off, there is a possibility that the cut surface is scratched or a foreign matter such as a cut piece (sludge) is attached. In the state where the internal electrodes are exposed on the cut surface, if scratches or foreign matters are attached to the cut surface, there is a high probability that the upper and lower internal electrodes are electrically connected to each other and short-circuited.

  In order to solve such a problem, attempts are being made to suppress damage to the cut surface and adhesion of foreign matter. For example, Patent Document 1 discloses a method of making a short circuit between internal electrodes less likely to occur by cutting the laminated body along the extending direction of the internal electrodes than when the laminated body is cut along the laminated direction. Has been. Further, Patent Document 2 prevents the adhesive sheet holding the laminate from being cut by cutting the laminate from the upper surface side to the middle in the lamination direction and cutting the remaining portion from the lower surface side. A method for suppressing the generation of adhesive waste is disclosed.

JP 2013-162037 A JP 2014-143357 A

  However, even when improvements are made in the cutting process as in Patent Document 1 and Patent Document 2, for example, the extension of the internal electrode at the time of cutting, the generation of cut pieces, etc. are completely suppressed. Can not. For this reason, when the interval between the internal electrodes becomes narrow as the monolithic ceramic capacitor becomes smaller, a short circuit is likely to occur between the ends of the internal electrodes exposed on the cut surface. Further, it is necessary to prevent scratches and deposits on the cut surface until the side margin portion is formed after the cutting step.

  In view of the circumstances as described above, an object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the occurrence of a short circuit between internal electrodes and a method for manufacturing the same.

In order to achieve the above object, a multilayer ceramic capacitor according to an embodiment of the present invention includes an offset portion in a multilayer ceramic capacitor having a multilayer body and a side margin portion.
The laminate includes internal electrodes and dielectric layers that are alternately laminated.
The side margin portion is made of a dielectric and is provided so as to cover the side surface of the stacked body.
The offset portion is composed of an amorphous region or a void region. The offset portion is formed between the internal electrode and the side margin portion so as to offset an end portion on the side surface of the internal electrode from the side surface toward the inner side of the stacked body.

  In this configuration, the end portion of the internal electrode on the side surface side of the multilayer body is offset in the inner direction of the multilayer body. For this reason, the end portions of the internal electrodes are insulated from each other by the dielectric layer. Therefore, even if there are scratches or deposits on the side surface of the laminate before the side margin portion is provided in the manufacturing process, it is possible to prevent the internal electrodes from conducting on the side surface. Thereby, generation | occurrence | production of the short between internal electrodes can be suppressed.

The offset portion may have a width of 0.1 μm or more.
By setting the width of the offset portion to 0.1 μm or more, the possibility that the internal electrodes on the side surface of the multilayer body are electrically connected can be reduced.

A method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention includes manufacturing a multilayer body in which ceramic sheets constituting a dielectric layer and conductors constituting internal electrodes are alternately laminated.
The side surface of the laminate is cut so that the conductor is exposed.
Etching is performed on the exposed conductor on the side surface of the laminate.
A side margin portion made of ceramic is provided so as to cover the side surface of the stacked body after the etching process, and a capacitor body is manufactured.
The capacitor body is fired.

  In the method of forming the side margin portion by retrofitting from the state in which the conductor is exposed on the side surface by cutting the laminated body, the conductor exposed on the side surface is elongated at the time of cutting so that the internal electrodes can contact each other. May cause scratches or deposits on the sides. On the other hand, in the above manufacturing method, the etching process is performed before the side margin portion is provided in the stacked body. Thereby, the part exposed to the side surface of a laminated body among the conductors which comprise an internal electrode can be removed, and the edge part of each internal electrode can be offset to the inner side of a laminated body. Therefore, it is possible to manufacture a multilayer ceramic capacitor in which the crossing area of the internal electrodes is increased without being affected by the extension of the internal electrodes on the side surfaces of the multilayer body, scratches on the side surfaces, or deposits that may occur during the manufacturing process.

  In the present specification, in this description of the production method, unless otherwise specified, the unfired laminated body and the fired laminated body are collectively referred to as “laminated body”. Therefore, the etching treatment may be performed on an unfired stacked body or may be performed on a fired stacked body. In the case where the etching process is performed on the fired stacked body, a firing process may be performed again after providing a side margin portion in the stacked body to form a capacitor body.

The etching process may be a process by acid, ion bombardment or laser irradiation.
Thereby, the edge part of the conductor exposed from the side surface can be removed, and the conductor can be offset in the inner direction of the stacked body.

For example, the etching process may be a process using nitric acid.
Thereby, the conductor containing a metal can be melted, and the etching process can be selectively performed from the side surface of the stacked body.
Further, the etching process may be a process using concentrated nitric acid.
By using concentrated nitric acid, the etching of the internal electrode can be made more uniform.

In the etching treatment, laser irradiation may be performed using a laser under a condition for selectively removing the conductor.
Thereby, a conductor can be etched appropriately and a conductor can be preferentially etched rather than a ceramic sheet.
As a laser that satisfies such conditions, for example, a green laser or a UV (Ultra Violet) laser can be used.

In the etching process, laser irradiation may be performed using a nanosecond pulse laser, a picosecond pulse laser, or a femtosecond pulse laser.
By using such a laser, the conductor can be appropriately removed.

Specifically, in the etching process, laser irradiation may be performed using a green laser having a wavelength of 532 nm, a UV (Ultra Violet) laser having a wavelength of 355 nm, or an infrared laser having a wavelength of 1064 nm.
Thereby, a conductor can be etched more appropriately and a conductor can be preferentially etched rather than a ceramic sheet.

  It is possible to provide a multilayer ceramic capacitor and a method for manufacturing the same that can suppress the occurrence of a short circuit between internal electrodes.

1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. It is sectional drawing along the AA 'line of the said multilayer ceramic capacitor. It is sectional drawing along the BB 'line of the said multilayer ceramic capacitor. It is a figure which expands and shows a part of sectional drawing shown in FIG. It is a flowchart which shows the manufacturing method of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a flowchart which shows other embodiment of the manufacturing method of the said multilayer ceramic capacitor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the drawing, an X axis, a Y axis, and a Z axis that are orthogonal to each other are shown as appropriate. The X axis, Y axis, and Z axis are common in all drawings.

[Configuration of Multilayer Ceramic Capacitor 10]
1 to 3 are views showing a multilayer ceramic capacitor 10 according to an embodiment of the present invention. FIG. 1 is a perspective view of a multilayer ceramic capacitor 10. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line AA ′ of FIG. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line BB ′.

  The multilayer ceramic capacitor 10 includes an element body 11, a first external electrode 14, and a second external electrode 15. The element body 11 has a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13. The external electrodes 14 and 15 cover both end faces of the element body 11 in the X-axis direction. The first external electrode 14 is connected to the first internal electrode 12, and the second external electrode 15 is connected to the second internal electrode 13.

  The element body 11 includes a stacked body 16, a first cover layer 18, a second cover layer 19, a first side margin portion 20, a second side margin portion 21, and an offset portion 24.

  The multilayer body 16 is made of a dielectric, and has a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13 therein. The first internal electrode 12 and the second internal electrode 13 have a flat plate shape extending along the XY plane, and are alternately stacked in the Z-axis direction. Thereby, the dielectric layer 17 is formed between the first internal electrode 12 and the second internal electrode 13. That is, the laminated body 16 is obtained by alternately laminating the internal electrodes 12 and 13 and the dielectric layers 17.

  In the laminated body 16, the thickness of the dielectric layer is not particularly limited, and examples thereof include those within a range of 0.5 μm to 2.0 μm. The thickness of the internal electrode is also not particularly limited, and examples thereof include those in the range of 0.5 μm to 2.0 μm. For example, a dielectric layer and an internal electrode having a thickness of about 1.0 μm can be used. The number of stacked layers of these dielectric layers and internal electrodes can be arbitrarily set. For example, the number of layers can be several tens to several hundreds, and more than 1,000 layers. For example, the number of dielectric layers and the number of internal electrodes may be 300, but the present invention is not limited to this.

  The internal electrodes 12 and 13 are each made of a conductive material and function as internal electrodes of the multilayer ceramic capacitor 10 configured in a flat plate shape. As the conductive material, for example, a metal material containing nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or an alloy thereof is used.

A ceramic material is used as the dielectric constituting the dielectric layer 17. As the ceramic material, for example, a material having a perovskite structure including barium (Ba) and titanium (Ti) typified by barium titanate (BaTiO ₃ ) can be used. In addition to the barium titanate system, the ceramic material constituting the dielectric layer 17 includes strontium titanate (SrTiO ₃ ) system, calcium titanate (CaTiO ₃ ) system, magnesium titanate (MgTiO ₃ ) system, zirconic acid system A calcium (CaZrO ₃ ) system, a calcium zirconate titanate (PCZT) system, a barium zirconate (BaZrO ₃ ) system, a titanium oxide (TiO ₂ ) system, and the like may be used.

The cover layers 18 and 19 have a flat plate shape extending along the XY plane. The first cover layer 18 covers the upper surface of the stacked body 16 in the Z-axis direction, and the second cover layer 19 covers the lower surface of the stacked body 16 in the Z-axis direction.
The side margin portions 20 and 21 have a flat plate shape extending along the XZ plane. The first side margin portion 20 covers the side surface of the multilayer body 16 facing the Y-axis direction, and the second side margin portion 21 covers the side surface of the multilayer body 16 opposite to the first side margin portion 20.
The cover layers 18 and 19 and the side margin portions 20 and 21 mainly have a function of protecting the multilayer body 16 and ensuring insulation around the multilayer body 16.

  The cover layers 18 and 19 and the side margin portions 20 and 21 are also formed of ceramic which is a dielectric. The material for forming the cover layers 18 and 19 and the side margin portions 20 and 21 may be any material having an insulating property. However, by using a material similar to that of the dielectric layer 17, internal stress in the element body 11 is suppressed. The

  FIG. 4 is an enlarged view of a part of the cross-sectional view shown in FIG. As shown in FIGS. 3 and 4, the offset portion 24 is provided between each internal electrode 12, 13 and the first side margin portion 20, and between each internal electrode 12, 13 and the second side margin portion 21. Each is formed. FIG. 4 shows an offset portion 24 formed between each internal electrode 12, 13 and the second side margin portion 21. Of the side surfaces of the multilayer body 16, when the side surface covered with the second side margin portion 21 is a side surface S, each internal electrode 12, 13 Have.

  Although illustration and description are omitted, the structures of the internal electrodes 12 and 13 and the offset portion 24 on the side surface on the first side margin portion 20 side of the multilayer body 16 are also on the side surface S on the second side margin portion 21 side. Is substantially the same.

  The offset portion 24 is a gap provided so as to offset the end portions 22 and 23 of the internal electrodes 12 and 13 from the side surface S of the multilayer body 16 toward the inner side of the multilayer body 16. The offset portion 24 may be a void area (air gap). Alternatively, the offset portion 24 may be an amorphous region. The amorphous region is a region made of a material having no crystal structure, and is made of, for example, glass. Examples of vitreous materials include silicon oxides containing metal elements such as Ba, Ni, and manganese (Mn).

  The offset width W of the offset portion 24 is not particularly limited, but is preferably 0.1 μm or more. In the present embodiment, the offset width W is a distance from the side surface S of the multilayer body 16 to the end portions 22 and 23 of the internal electrodes 12 and 13.

  With the above configuration, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a plurality of pieces between the first internal electrode 12 and the second internal electrode 13 are provided. A voltage is applied to the dielectric layer 17. Thereby, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 are stored in the plurality of dielectric layers 17.

[Method of Manufacturing Multilayer Ceramic Capacitor 10]
FIG. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. 6 to 10 are diagrams illustrating a manufacturing process of the multilayer ceramic capacitor 10. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 will be described along FIG. 5 with reference to FIGS.

(Step ST11: Ceramic sheet preparation process)
In step ST11, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the dielectric layer 17 of the multilayer body 16 and a third ceramic sheet 103 for forming the cover layers 18 and 19 are prepared. . The ceramic sheets 101, 102, 103 are configured as unfired dielectric green sheets, and are formed into a sheet shape using, for example, a roll coater or a doctor blade.

  FIG. 6 is a plan view of the ceramic sheets 101, 102, 103. At this stage, the ceramic sheets 101, 102, 103 are not cut for each multilayer ceramic capacitor 10. FIG. 6 shows cutting lines Lx and Ly when cutting each multilayer ceramic capacitor 10. The cutting line Lx is parallel to the X axis, and the cutting line Ly is parallel to the Y axis.

  As shown in FIG. 6, the first ceramic sheet 101 is formed with unfired first internal electrodes 112 corresponding to the first internal electrodes 12, and the second ceramic sheet 102 is not yet formed corresponding to the second internal electrodes 13. A fired second internal electrode 113 is formed. Note that no internal electrode is formed on the third ceramic sheet 103 corresponding to the cover layers 18 and 19.

  The unfired internal electrodes 112 and 113 correspond to a conductor constituting the internal electrode in the present invention. The internal electrodes 112 and 113 can be formed using any conductive paste. For example, a screen printing method can be used to form the internal electrodes 112 and 113 using the conductive paste.

  The internal electrodes 112 and 113 are disposed over two regions adjacent to each other in the X-axis direction that are partitioned by the cutting line Ly, and extend in a band shape in the Y-axis direction. The first internal electrode 112 and the second internal electrode 113 are shifted in the X-axis direction by one row of regions partitioned by the cutting line Ly. That is, the cutting line Ly passing through the center of the first internal electrode 112 passes through the region between the second internal electrodes 113, and the cutting line Ly passing through the center of the second internal electrode 113 passes through the region between the first internal electrodes 112. Passing through.

  The conductive paste typically includes a metal material, an organic binder, and a solvent. These materials are not particularly limited. In addition, when etching with an acid is performed in the internal electrode etching step (ST14) described later, the organic binder contained in the conductive paste is more soluble in the acid than the binder contained in the ceramic sheets 101, 102, and 103. It is preferable to employ an easy one. Examples of such an organic binder include ethyl cellulose (EC).

(Step ST12: Lamination process)
In step ST12, the unfired laminated body 104 is produced by laminating the ceramic sheets 101, 102, 103 prepared in step ST11.

  FIG. 7 is a perspective view of the laminate 104 obtained in step ST12. In FIG. 7, for convenience of explanation, the ceramic sheets 101, 102, and 103 are shown in an exploded manner. However, in the actual laminate 104, the ceramic sheets 101, 102, 103 are integrated by thermocompression bonding or the like.

  In the laminated body 104, the first ceramic sheets 101 and the second ceramic sheets 102 corresponding to the dielectric layers 17 of the laminated body 16 are alternately laminated in the Z-axis direction. Thereby, the unsintered laminated body 104 is obtained by alternately laminating the ceramic sheets constituting the dielectric layer 17 and the conductors constituting the internal electrodes 12 and 13.

  In the laminated body 104, the third ceramic sheets 103 corresponding to the cover layers 18 and 19 are laminated on the upper and lower surfaces in the Z-axis direction of the alternately laminated ceramic sheets 101 and 102. In the example shown in FIG. 7, three third ceramic sheets 103 are laminated, but the number of the third ceramic sheets 103 can be changed as appropriate.

(Step ST13: Cutting process)
In step ST13, the laminated body 105 obtained in step ST12 is cut to produce a laminated chip 105.

  FIG. 8 is a plan view of the laminate 104 after step ST13. The laminated body 104 is cut along the cutting lines Lx and Ly while being attached to a cut tape C such as a foam tape. Thereby, the laminated body 104 is separated into pieces and the laminated chip 105 is obtained.

  FIG. 9 is a perspective view of the multilayer chip 105 obtained in step ST13. On the multilayer chip 105, unfired internal electrodes 112 and 113, an unfired dielectric layer 117, a first cover layer 118, and a second cover layer 119 are formed. In the multilayer chip 105, unfired internal electrodes 112 and 113 are exposed on both side surfaces S1 and S2 facing the Y-axis direction, which is a cut surface.

  The cutting process of step ST13 described above corresponds to the process of cutting the side surface of the multilayer body so as to expose the conductor in the present invention.

(Step ST14: Internal electrode etching process)
In step ST14, the unfired internal electrodes 112 and 113 exposed on the side surfaces of the multilayer chip 105 obtained in step ST13 are etched on the side surfaces S1 and S2 facing the Y-axis direction, which are the cut surfaces. Apply.

  The etching process can be performed, for example, by immersing the side surfaces S1, S2 from which the unfired internal electrodes 112, 113 are exposed in an acid for a predetermined time. In this etching process, the offset width W (see FIG. 4) of the offset portion 24 can be controlled by the immersion time, and a desired offset width W can be easily obtained.

  The acid used for the etching process may be any acid that can dissolve the conductors constituting the internal electrodes 112 and 113. As the acid, for example, nitric acid, more preferably concentrated nitric acid can be used. Thereby, since it is possible to melt the conductor containing metal, the internal electrodes 112 and 113 and the metal deposits derived from the internal electrodes 112 and 113 are selectively etched from the side surfaces S1 and S2 of the multilayer chip 105. be able to. Further, by using concentrated nitric acid, the etching of the internal electrodes 112 and 113 can be made more uniform. Concentrated nitric acid refers to an aqueous solution of nitric acid having a mass percent concentration of 60% or more, for example.

  In addition, each end surface of the multilayer chip 105 facing the X-axis direction, that is, an end portion on the first external electrode 14 side of the first internal electrode 112 and an end portion on the second external electrode 15 side of the second internal electrode 113 are etched. In order to avoid this, it is preferable to immerse only the side portions (S1, S2) facing the Y-axis direction described above. Alternatively, the laminated chip 105 may be immersed by masking the end face of the laminated chip 105 facing the X-axis direction.

  The etching process in step ST14 is not limited to the method of immersing in the acid described above. As a method other than the above, for example, a method of performing ion bombardment processing on the internal electrodes 112 and 113 can be cited.

Alternatively, the etching process in step ST14 may be a process by laser irradiation. For example, a YAG laser can be used as the laser. By irradiating the side surfaces S1 and S2 with laser using a laser irradiation apparatus, the end portions exposed from the side surfaces S1 and S2 of the internal electrodes 112 and 113 can be removed. Thereby, as will be described later, the offset width W can be controlled more finely.
In this case, laser irradiation can be performed using a laser under a condition for selectively removing the internal electrodes 112 and 113. As a laser that satisfies such conditions, a green laser having a wavelength of 532 nm (second harmonic), a UV laser having a wavelength of 355 nm (third harmonic), an infrared laser having a wavelength of 1064 nm (fundamental wavelength), or the like may be used. For example, when the internal electrodes 112 and 113 contain Ni, a green laser can be particularly preferably used. By using such a laser, the internal electrodes 112 and 113 can be appropriately etched, and the internal electrodes 112 and 113 can be preferentially etched over the ceramic sheets 101 and 102. In this step, a semiconductor laser, a fiber laser, or the like can be used in addition to the YAG laser.
In this step, laser irradiation can be performed using a nanosecond pulse laser, a picosecond pulse laser, or a femtosecond pulse laser. That is, as the laser irradiation device, a nanosecond laser device having a pulse width of a nanosecond region, a picosecond laser device having a picosecond region, or a femtosecond laser device having a femtosecond can be used. By using a pulse laser device having a short pulse width in this way, the internal electrodes 112 and 113 can be appropriately removed.

(Step ST15: Side margin portion forming step)
In step ST15, the unfired first side margin part 120 and the second side margin part 121 are provided on the side surface of the unfired laminated chip 105 after the etching process obtained in step ST14, and the unfired element body 111 is thus formed. Is made. The side margin portions 120 and 121 are formed by immersing the side surfaces S1 and S2 of the laminated chip 105 after the etching process in a paste material made of the same ceramic material as the dielectric layer 117 and the cover layers 118 and 119, for example. It can be formed by pulling up (dip method). As a result, the side surfaces S1 and S2 facing the Y-axis direction of the multilayer chip 105 are covered by the side margin portions 120 and 121, respectively, and insulation around the internal electrodes 112 and 113 is ensured.

  Note that the method of forming the side margin portions 120 and 121 in step ST15 is not limited to the above-described dipping method, and other methods may be used. For example, the side margin portions 120 and 121 may be formed by applying ceramic slurry to the side surfaces of the laminated chip 105 after the etching process.

  FIG. 10 is a perspective view of the unfired element body 111 obtained in step ST15. By performing step ST15 after step ST14, between the internal electrodes 112, 113 of the unfired element body 111 and the first side margin portion 120 and between the internal electrodes 112, 113 and the second side margin portion 121. Between the two, gaps serving as offset portions 24 are formed.

(Step ST16: Firing step)
In step ST16, the unfired element body 111 obtained in step ST15 is fired to produce the element body 11 of the multilayer ceramic capacitor 10 shown in FIGS. Firing can be performed, for example, in a reducing atmosphere or in a low oxygen partial pressure atmosphere.

Depending on the firing atmosphere, liquid phase glass containing the Si component contained in the dielectric layer 17 and the side margin portion 21 may flow into the gap formed by the etching process. At this time, metal elements such as Ba, Ni, and Mn contained in the side margin portion 21 and the internal electrodes 112 and 113 may diffuse into the glassy material. Thereby, the offset portion 24 made of an amorphous region is formed.
In the case where an amorphous region is not formed in the void, an offset portion 24 composed of the void region is formed.

(Step ST17: External electrode forming step)
In step ST17, external electrodes 14 and 15 are formed on the element body 11 obtained in step ST16, whereby the multilayer ceramic capacitor 10 shown in FIGS.

  In step ST17, first, an unfired electrode material is applied so as to cover one X-axis direction end face of the element body 11, and an unfired electrode material is applied so as to cover the other X-axis direction end face of the element body 11. To do. The applied unfired electrode material is baked, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere to form a base film on the element body 11. Then, an intermediate film and a surface film are formed on the base film baked on the element body 11 by a plating process such as electroplating, thereby completing the external electrodes 14 and 15.

  As described above, in the method for manufacturing the multilayer ceramic capacitor 10 according to the present embodiment, since the side margin portions 120 and 121 are retrofitted, the internal electrodes 12 and 13 are secured widely, and the intersection area between the internal electrodes 12 and 13 is increased. Can be bigger.

Here, in the manufacturing method in which the side margin portion is retrofitted from the state in which the unfired laminated body is cut and the conductor is exposed to the side surface, the conductor exposed on the side surface is elongated at the time of cutting, and the internal electrodes are May come into contact with each other, or scratches or deposits may be generated on the sides. For this reason, it is conceivable that a short circuit is likely to occur between the end portions of the internal electrodes at the boundary portion between the cut surface and the side margin portion.
Furthermore, such structural defects such as scratches and deposits may cause a reduction in product life and withstand voltage of the multilayer ceramic capacitor.

On the other hand, in the method for manufacturing the multilayer ceramic capacitor 10 according to this embodiment, as described above, the internal electrodes 112 and 113 are formed from the side surfaces S1 and S2 of the multilayer chip 105 before the side margin portions 120 and 121 are provided. Etching is performed on the edge. Thereby, portions exposed to the side surfaces S1 and S2 of the conductors constituting the internal electrodes 112 and 113 can be removed, and the end portions of the internal electrodes 112 and 113 can be offset toward the inner side of the multilayer chip 105.
Further, when there are deposits derived from the internal electrodes 112 and 113 due to the cutting on the side surfaces S1 and S2, such deposits can be removed by an etching process.

  Thereby, the insulation between the adjacent internal electrodes 112 and 113 can be ensured. Therefore, according to the present embodiment, a short circuit between the internal electrodes or the multilayer ceramic capacitor 10 can be obtained without being affected by the extension of the internal electrodes on the side surface of the multilayer body, scratches on the side surface, or deposits that may occur during the manufacturing process. It can prevent the product life and withstand voltage from decreasing.

  In particular, when the offset width W is 0.1 μm or more, the end portions 22 and 23 of the internal electrodes 12 and 13 are sufficiently retracted from the side surface S of the multilayer body 16. It becomes difficult to be affected by the adhesion of foreign matter to the end surfaces of the 16 side surfaces S. That is, the possibility that the internal electrodes 12 and 13 on the side surface S are conducted can be further reduced.

  The effect of this embodiment can also be explained as follows. When scratches occur on the side surfaces S1 and S2 of the dielectric layer 117, the dielectric breakdown voltage of the dielectric layer 117 may be reduced at that location, but by offsetting the internal electrodes 112 and 113, the dielectric layer 117 Since the predetermined regions on the side surfaces S1 and S2 are not sandwiched between the internal electrodes 112 and 113, dielectric breakdown is unlikely to occur. This also prevents the product life and breakdown voltage of the multilayer ceramic capacitor 10 from decreasing.

  Examples of the present invention will be described. As an example of the present invention, a multilayer ceramic capacitor 10 (hereinafter referred to as an experimental chip) by the above-described manufacturing method was manufactured with the following configuration.

Configuration of experimental chip:
Chip dimensions (vertical x horizontal x height) 1.0 mm x 0.5 mm x 0.5 mm (including external electrodes)
Dielectric layer thickness 0.7μm
Number of dielectric layers 315 Internal electrode layer thickness 0.7μm
Number of internal electrode layers 315 layers Cover layer thickness 35 μm
Side margin thickness 30μm
External electrode thickness (including plating) 30μm
End margin thickness 50μm
The end margin thickness is the minimum value of the distance between the external electrode side edge from which the internal electrode is not drawn and the external electrode in the internal electrode layer (for example, the internal electrode 12 and the external electrode in FIG. 2). The distance from the electrode 15).

  The offset portion of each experimental chip is set to a size different from 0.5 μm, 1 μm, and 10 μm in the amount of offset of the internal electrode (offset width W in FIG. 4) from the side surface of the stacked body before the side margin portion is retrofitted. It was provided by etching with concentrated nitric acid. For comparison, an experimental chip corresponding to a multilayer ceramic capacitor without an offset portion, in which a side margin portion is retrofitted without performing an etching process after cutting the side surface of the multilayer body (with an internal electrode offset amount of 0 μm). ) Was also produced.

  As described above, 100 experimental chips of each type of multilayer ceramic capacitor with only the offset amount of the internal electrodes varied were produced, and the number of shorts between the internal electrodes was examined. Table 1 is a table showing the offset amount of the internal electrode and the number of shorts in the experimental chip of the multilayer ceramic capacitor according to the example of the present invention.

  As shown in Table 1, in each type of experimental chip in which the offset portion is provided so that the offset amount of the internal electrode is 0.1 μm or more, compared to the experimental chip in which the offset portion is not provided, the short-circuited The number of occurrences has decreased. As a result, in the multilayer ceramic capacitor having the offset portion, it is possible to prevent the internal electrodes from conducting on the side surface by offsetting the internal electrode from the side surface of the multilayer body, and the occurrence of a short circuit between the internal electrodes. It is thought that it was possible to suppress this.

  Furthermore, as another example, an experiment chip was prepared in which etching of the internal electrode was performed by laser irradiation instead of concentrated nitric acid, and a similar experiment was performed. As a result, the offset amount of the internal electrode can be further reduced. Specifically, the short-circuit occurrence rate was 0 in the experimental chip having the offset amount of 0.1 μm or more and 0.5 μm or less. From this result, it was found that even when the internal electrodes were offset by laser irradiation, it was possible to satisfactorily suppress the occurrence of shorts between the internal electrodes and to reduce the number of shorts even with a smaller offset amount. . Therefore, the crossing area between the internal electrodes can be ensured more reliably by laser etching.

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.

For example, in the above-described embodiment, it has been described that the etching process is a process using an acid. Alternatively, as the etching process, a wet etching process using an etching solution other than an acid may be applied, or a dry etching process may be applied.
Further, the etching process may be a laser irradiation process using a laser.

  In the embodiment according to the method for manufacturing a multilayer ceramic capacitor described above, the etching process for forming the offset portion and the step for forming the side margin portion are performed before firing each multilayer chip (laminate). However, the timing of the etching process and the formation of the side margin portion is not limited to this, and may be after, for example, firing each multilayer chip. Specifically, as shown in FIG. 11, after performing the process (step ST13) of cutting the side surface of the unfired laminated body so as to expose the conductor among the above-described processes, each laminated chip. Is fired to obtain a laminate (step ST24), and then an etching process can be performed on the internal electrodes exposed on the side surfaces of the laminate (step ST25). Thereafter, for example, an unfired side margin portion is retrofitted to the side surface of the etched laminate by the same method as described above (step 26), and the obtained capacitor element body is fired to complete the side margin portion (step 26). 27) An external electrode can be formed as described above (step 28). Thus, during the manufacturing process of the multilayer ceramic capacitor, the same effect as described above can be obtained by offsetting the end of each internal electrode inward from the side surface of the multilayer body.

DESCRIPTION OF SYMBOLS 10 ... Multilayer ceramic capacitor 12, 13 ... Internal electrode 16 ... Laminated body 17 ... Dielectric layer 20, 21 ... Side margin part 22, 23 ... End part 24 ... Offset part 101, 102 ... Unbaked ceramic sheet 104 ... Unbaked Laminated body 105: unsintered laminated chip (laminated body)
111: Unfired element (capacitor element)
112, 113 ... Unfired internal electrode (conductor)
117: Unfired dielectric layers 120, 121 ... Unfired side margin portions S, S1, S2 ... Side surface W ... Offset width

Claims (9)

A laminate in which internal electrodes and dielectric layers are alternately laminated;
A side margin portion made of a dielectric material and provided to cover the side surface of the laminate;
In a multilayer ceramic capacitor having
It consists of an amorphous region or a void region formed between the internal electrode and the side margin so as to offset the end of the internal electrode on the side surface from the side surface toward the inside of the stacked body. Multilayer ceramic capacitor with offset part. The multilayer ceramic capacitor according to claim 1,
A width of the offset portion is 0.1 μm or more. Multilayer ceramic capacitor. Fabricate a laminate in which the ceramic sheet constituting the dielectric layer and the conductor constituting the internal electrode are alternately laminated,
Cutting the side surface of the laminate to expose the conductor;
Etching the exposed conductor on the side surface of the laminate,
A capacitor body is prepared by providing a side margin portion made of ceramic so as to cover the side surface of the stacked body after the etching process,
A method for producing a multilayer ceramic capacitor, comprising firing the capacitor body. It is a manufacturing method of the multilayer ceramic capacitor according to claim 3,
The method for manufacturing a multilayer ceramic capacitor, wherein the etching treatment is treatment by acid, ion bombardment or laser irradiation. It is a manufacturing method of the multilayer ceramic capacitor according to claim 4,
The etching process is a process using nitric acid. It is a manufacturing method of the multilayer ceramic capacitor according to claim 5,
The etching process is a process using concentrated nitric acid. It is a manufacturing method of the multilayer ceramic capacitor according to claim 4,
In the etching process, a method of manufacturing a multilayer ceramic capacitor in which laser irradiation is performed using a laser under a condition for selectively removing the conductor. A method for producing a multilayer ceramic capacitor according to claim 4 or 7,
In the etching process, a multilayer ceramic capacitor is manufactured by performing laser irradiation using a nanosecond pulse laser, a picosecond pulse laser, or a femtosecond pulse laser. A method for producing a multilayer ceramic capacitor according to claim 4, 7 or 8,
In the etching process, a multilayer ceramic capacitor manufacturing method in which laser irradiation is performed using a green laser having a wavelength of 532 nm, a UV (Ultra Violet) laser having a wavelength of 355 nm, and an infrared laser having a wavelength of 1064 nm.

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