JP2016206938A - Information processing system, memory control method for information processing system, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform erasure processing for a specified specific region on a semiconductor memory in a short time.SOLUTION: In an information processing system including a host and semiconductor memory, when a command is issued to a semiconductor memory, it is determined whether the issued command is a command for erasing a specified memory region on the semiconductor memory; where if it is determined that it is the command for erasing the specified memory region, erasure processing is performed for the specified memory region.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an information processing system, a memory control method for the information processing system, and a program.

  2. Description of the Related Art Conventionally, as a storage device provided in an information processing apparatus, there is an apparatus using an SSD (solid state drive). Here, the SSD cannot overwrite data on a block in which data is written. For this reason, it is necessary to read the block to be rewritten into the buffer, rewrite the data in the buffer, erase the corresponding block, and then write back the contents of the buffer to the block. Therefore, there has been a problem that the writing speed is remarkably reduced when the number of empty blocks is reduced.

  Therefore, in order to improve the decrease in the writing speed, a Trim command has been devised, in which an OS (Operating System) notifies the SSD of an unnecessary data block to the SSD, and an unnecessary area in the block is released to make an empty block. It was done.

  In addition, when there is no longer a data writable area, there is a case where garbage collection is performed to erase the entire contents of the data area once in order to secure a place to write data (see, for example, Patent Document 1). .

JP 2001-184255 A

However, in the prior art, when the Trim command is executed, garbage collection is executed for all blocks in which unnecessary data exists, and therefore processing time is required when a large amount of unnecessary data exists.
For this reason, the processing capacity of the entire SSD is reduced. Further, when garbage collection is executed to erase the entire contents of the data area, further processing time is required, and the processing capacity of the entire SSD is significantly reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a mechanism capable of performing an erasing process in a short time on a specified specific area on a semiconductor memory. .

An information processing system of the present invention that achieves the above object has the following configuration.
An information processing system including a host and a semiconductor memory, wherein issuance means for issuing a command to the semiconductor memory, and whether the issued command is a command for erasing a specified memory area of the semiconductor memory First determining means for determining whether or not and a erasing means for erasing the specified memory area when it is determined that the command is for erasing the specified memory area.

  According to the present invention, an erasing process can be performed in a short time for a specified specific area on a semiconductor memory.

1 is a block diagram illustrating a configuration of an information processing system. It is a figure which shows an example of a Trim command format. It is a figure which shows the memory map of SSD. It is a figure which shows an example of UI screen displayed on a host. It is a flowchart explaining the memory control method of an information processing system. It is a flowchart explaining the memory control method of an information processing system. It is a figure which shows the block information of SSD shown in FIG. It is a flowchart explaining the memory control method of an information processing system.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
<Description of system configuration>
[First Embodiment]

  FIG. 1 is a block diagram showing the configuration of the information processing system according to the present embodiment. In this example, an SSD (solid state drive) used as a semiconductor memory and a host are used as one information processing system. It should be noted that the present invention can be applied to a single device or a system composed of a plurality of devices as long as the functions of the present invention are executed unless otherwise specified.

In FIG. 1, reference numeral 101 denotes a host that writes and reads data to and from the SSD 102, and transmits a command and receives the status of the SSD 102 to control the SSD 102. For this reason, the host 101 includes a system bus including a CPU, memory, data bus, and control bus (not shown).
An SSD 102 writes data received from the host 101 to the internal NAND flash memory 105. Further, data is read from the internal NAND flash memory 105 and transmitted to the host 101. In addition, it sets itself based on the command received from the host 101 and transmits its own status to the host 101.

  A SATA I / F unit 103 communicates between the host 101 and the controller 104. A controller unit 104 controls the entire SSD. A NAND flash memory 105 stores and reads data according to instructions from the controller 104. Reference numeral 106 denotes a work memory, which functions as a temporary data buffer for storing programs executed by the controller 104 and various reference data necessary for control.

FIG. 2 is a diagram showing an example of a Trim command format issued by the host 101 shown in FIG. Here, the Trim command is a command for notifying the SSD 102 of a logical address that may be physically erased in advance.
In FIG. 2, reference numeral 201 denotes a Trim field of the Trim command format. When “1” is set, Trim is enabled, and when “0” is set, Trim is disabled.
Reference numeral 202 denotes a logical address field for specifying the start position in the Trim command format. When the Trim field 201 is “1”, the Trim command is executed from the logical address described here.
Reference numeral 203 denotes a size field of the Trim command format. When the Trim field 201 is “1”, the Trim command is applied to the area from the logical address described in the start logical address field 202 to the size described here. Execute. The Trim command is defined by the ATA (AT Attachment) interface standard, and is transmitted from the host 101 to the SSD 102. The SSD 102 is received via the SATA I / F 103 and is interpreted and executed by the controller 104.

  Table 1 below shows an example of conversion between a logical address and a physical address that specify the start position. In Table 1 shown in the table format, the logical address is an address when the storage area of the SSD 102 is viewed from the host 101. The physical address is an address of a block which is a storage area (memory area) of the NAND flash memory 105 in the SSD 102, and is associated with the logical address 202 on a one-to-one basis. This information is stored in the work memory 106 and is managed by the controller 104. Even when the physical address in which data is written is changed by garbage collection or the like, it is sequentially updated and the association with the logical address is maintained.

FIG. 3 is a diagram showing a memory map of the SSD 102 shown in FIG.
In FIG. 3, reference numeral 301 denotes an area of the SSD 102 viewed from the host 101. A spool area 302 is provided in a part of the SSD 102 according to an instruction from the host 101 or the user. This area stores temporary data, and is used, for example, to temporarily record job data of the multifunction peripheral.

FIG. 4 is a diagram showing an example of a UI screen displayed on the host 101 shown in FIG.
In FIG. 4, 401 is an example of a UI (User Interface) that issues a Trim command in the host 101, and is displayed on a PC (Personal Computer) monitor, an operation panel of a multi-function peripheral, etc. Accept. Reference numeral 402 denotes a Trim command execution button, which accepts a Trim command execution instruction from the user.

  FIG. 5 is a flowchart for explaining a memory control method of the information processing system according to the present embodiment. This example corresponds to the Trim command execution processing procedure of the host 101 shown in FIG. Each step is realized by executing a control program stored in the control unit of the host 101. A predetermined OS is installed in the host 101, and various systems (including a file system) execute data processing under the management of the OS.

When the host 101 detects that the user has pressed the execute button 402 on the UI screen shown in FIG. 4 (S501), the host 101 deletes the spool area 302 of the SSD 102 using a file system managed by the OS (not shown) (S502). ). Note that erasure by the file system continues to exist on the block only by replacing the data of the block with unnecessary data.
Subsequently, the host 101 acquires the logical address and size of the spool area 302 from the OS (S504), and sets “1” in the Trim field 201 of the ATA command. Further, the logical address acquired in S504 is set in the start logical address field 202, the size acquired in S504 is set in the size field 203 (S505), the Trim command is transmitted to the SSD 102 (S506), and the process is terminated. To do.

FIG. 6 is a flowchart for explaining a memory control method of the information processing system according to the present embodiment. This corresponds to the Trim command execution processing procedure received by the SSD 102 from the host 101 in this embodiment. Each step is realized by executing a control program stored in the controller 104.
When the controller 104 of the SSD 102 receives an ATA command from the host 101 (S601), it determines whether or not the received command is a Trim command (S602). If the controller 104 determines that the command is not a Trim command, the controller 104 executes the corresponding command (S603) and ends the process.

  On the other hand, when the controller 104 determines that the command is a Trim command, the controller 104 determines whether or not the SSD 102 has an area designation option (S604). When the controller 104 determines that there is an area designation option, the controller 104 acquires a physical address associated with the logical address indicated by the start logical address field 202 from Table 1 (S605). Subsequently, the controller 104 searches for an empty block in which no data is written (S607), and the controller 104 waits for a timing suitable for processing (S608).

Here, the timing suitable for processing is, for example, when there are few accesses from the host 101 or when a predetermined time has elapsed.
When the timing suitable for processing comes in this way, the controller 104 of the SSD 102 copies valid data written in one block in the designated area to an empty block (S609), and the controller 104 subsequently copies. The original old block is erased to create a free block (S610).

  On the other hand, when the controller 104 determines that there is no designated area option in S604, the controller 104 searches for an empty block in which no data is written as normal Trim command processing (S612). Then, the controller 104 waits for a timing suitable for processing (S613). Here, when the timing suitable for processing arrives, the controller 104 copies valid data written in one block in the entire area to an empty block (S614), and then the controller 104 copies the copy source. The old block is deleted to create an empty block (S615), and the process returns to S611.

FIG. 7 is a diagram showing block information of the SSD 102 shown in FIG.
In FIG. 7A, reference numeral 701 denotes a block, which is an erase unit of the SSD 102. Reference numeral 702 denotes valid data written in the SSD 102. Reference numeral 703 denotes an empty block, which indicates a state in which new data can be written. Reference numeral 704 denotes unnecessary data, which is data erased by the file system. Reference numeral 705 denotes an area of the SSD 102 corresponding to the spool area 302, which is unnecessary data. Here, the blocks are represented as continuous blocks, but depending on the association between logical addresses and physical addresses, there may be a discontinuous block collection.

In FIG. 7B, reference numerals 701 to 704 are the same as those in FIG. Reference numeral 706 denotes an area of the SSD 102 corresponding to the spool area 302, and shows a state after the area designation Trim command is executed in the area 705 of FIG. 7A by the method of the present invention. The area designated portion is replaced with an empty block 706. As described above, garbage collection is performed in block units for the area designated area, which is high speed.
According to the present embodiment, unnecessary data can be erased only for a part of areas designated in units of blocks, so that there is an empty space faster than executing a Trim command or erasing for all areas. The process of securing the area can be finished.

[Second Embodiment]
FIG. 8 is a flowchart for explaining a memory control method of the information processing system according to the present embodiment. This example corresponds to the Trim command execution processing procedure of the host 101 shown in FIG. Each step is realized by executing a control program stored in the control unit of the host 101. A predetermined OS is installed in the host 101, and various systems (including a file system) execute data processing under the management of the OS. S502 to S506 are the same as those in FIG.

  When the host 101 detects that the processing using the job data temporarily stored in the spool area 302 is completed (S511), the spool area 302 of the SSD 102 is erased by the file system as in the first embodiment (S502). .

Subsequently, the host 101 acquires the logical address and size of the spool area 302 from the OS (S504), and the host 101 sets “1” in the Trim field 201 of the ATA command. Further, the host 101 sets the logical address acquired in S504 in the start logical address field 202 and the size acquired in S504 in the size field 203 (S505), and the host 101 transmits a Trim command to the SSD 102 ( S506).
As a result, the host 101 can promptly send a region-designated Trim command to the SSD 102 without waiting for an instruction from the user.
Thereby, the execution timing of the Trim command issued from the host 101 can be started when the execution of the predetermined job is completed. Therefore, the data processing burden on the controller 104 of the SSD 102 during job processing can be reduced.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101 Host 102 SSD
103 SATA I / F
104 controller 105 NAND flash memory 106 work memory

Claims (10)

An information processing system including a host and a semiconductor memory,
Issuing means for issuing commands to the semiconductor memory;
First determination means for determining whether the issued command is a command for erasing a specified memory area of the semiconductor memory;
If it is determined that the command is for erasing the specified memory area, erasing means for erasing the specified memory area;
An information processing system comprising: A second judging means for judging whether or not the designated memory area is a free area;
2. The information processing system according to claim 1, wherein when it is determined that the designated memory area is an empty area, the erasing unit erases the designated memory area.   The information processing system according to claim 1, wherein the erasing unit erases the designated memory area in units of blocks.   2. The information processing system according to claim 1, wherein the command includes a logical address specifying a start position of an area to be erased and a size to be erased in the semiconductor memory.   2. The information processing system according to claim 1, wherein the erasing unit erases a designated memory area in response to completion of a predetermined job. A table that associates the logical address with the physical address of the semiconductor memory;
6. The information processing system according to claim 1, wherein the erasing unit specifies a physical address to be erased in the semiconductor memory with reference to the table.   The information processing system according to claim 1, further comprising accepting means for accepting an erase instruction for the semiconductor memory.   8. The information processing system according to claim 1, wherein the semiconductor memory is a solid state drive. A memory control method for an information processing system including a host and a semiconductor memory,
An issuing process for issuing commands to the semiconductor memory;
A determination step of determining whether the issued command is a command for erasing a specified memory area of the semiconductor memory;
If it is determined that the command is for erasing the specified memory area, an erasing process for erasing the specified memory area;
A memory control method for an information processing system.   A program for causing a computer to execute the memory control method of the information processing system according to claim 9.

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