JP2016127116A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can prevent semiconductor chips from being out of alignment in a process of division into a plurality of semiconductor chips and a process of increasing intervals among the plurality of semiconductor chips.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming trenches W5 with a cutting depth shallower than a thickness of a semiconductor wafer W on a first surface W1 of the semiconductor wafer W; a process of attaching a first adhesive sheet 10 to a first surface W1 where the trenches W5 are formed; a process of grinding a second surface W6 of the semiconductor wafer W to decrease a thickness of the semiconductor wafer W and dividing the semiconductor wafer W into a plurality of semiconductor chips CP; a process of attaching a second adhesive sheet to a third surface W3 exposed by grinding of the second surface W6; a process of removing the first adhesive sheet 10; and a process of stretching the second adhesive sheet to increase intervals among a plurality of semiconductor chips CP.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device.

In recent years, electronic devices have been reduced in size, weight, and functionality. Semiconductor devices mounted on electronic devices are also required to be smaller, thinner, and higher in density. A method for thinning a semiconductor chip used in a semiconductor device has been developed.
For example, Patent Document 1 discloses a step of forming a bottomed groove in accordance with a pellet division planned boundary line on the front side of a silicon substrate, and grinding the back side of the substrate until the bottom of the groove is opened and a pellet is formed. The manufacturing method of the pellet which comprises a process is described. According to Patent Document 1, it is described that the substrate can be prevented from cracking when the thickness of the silicon substrate after back grinding is thin. The manufacturing method described in Patent Document 1 may be referred to as “first dicing method” or “DBG (Dicing Before Grinding) process”.

  A semiconductor chip may be mounted in a package close to its size. Such a package may be referred to as a semiconductor chip scale package (CSP). As one of the CSPs, there is a semiconductor wafer level package (WLP). In WLP, before dicing into individual pieces, external electrodes and the like are formed on the semiconductor wafer. Finally, the semiconductor wafer is diced into individual pieces. Examples of WLP include a fan-in type and a fan-out type. In a fan-out type WLP (hereinafter sometimes abbreviated as FO-WLP), a semiconductor chip sealing body is formed by covering a semiconductor chip with a sealing member so as to be an area larger than the semiconductor chip size. Then, the rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.

  For example, in Patent Document 2, an extended semiconductor wafer is formed by enclosing a plurality of semiconductor chips separated from a semiconductor wafer, leaving a circuit formation surface thereof, and surrounding with a mold member. Describes a method of manufacturing a semiconductor package formed by extending a rewiring pattern. In the manufacturing method described in Patent Document 2, before a plurality of separated semiconductor chips are surrounded by a mold member, the semiconductor wafer mount tape for expansion is attached to the semiconductor chip, and the semiconductor wafer mount tape is extended to be a plurality of semiconductor chips. The distance between the chips is increased. Patent Document 2 also describes an embodiment in which a DBG process is applied.

JP-A-5-335411 International Publication No. 2010/058646

  In the manufacturing method described in Patent Document 2, since a method of dividing into pieces by dicing is adopted, the alignment state of a plurality of silicon semiconductor chips may be disturbed. In addition, when the DBG process is applied in the manufacturing method of Patent Document 2, a tape material having both surface protection characteristics during back grinding and expandability during expansion is required. However, Patent Document 2 does not specifically disclose any tape material having such characteristics. Furthermore, since the tape that protects the circuit surface of the semiconductor wafer during back grinding is generally the same size as the outer shape of the semiconductor wafer, it is difficult to stretch the tape. Therefore, in the method employing the DBG process described in Patent Document 2, it is difficult to increase the interval between the plurality of semiconductor chips.

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent the disorder of the alignment state and widen the interval between the plurality of semiconductor chips in the step of dividing into a plurality of semiconductor chips.

  According to one aspect of the present invention, a step of forming a groove having a depth of cut shallower than the thickness of the semiconductor wafer on the first surface of the semiconductor wafer, and a first surface on the first surface where the groove is formed. A step of affixing the adhesive sheet and a second surface opposite to the first surface to which the first adhesive sheet is affixed to reduce the thickness of the semiconductor wafer, A step of dividing the second adhesive sheet into a plurality of semiconductor chips, a step of pasting the second adhesive sheet on the third surface that appears by grinding the second surface, a step of peeling the first adhesive sheet, And a step of extending the second pressure-sensitive adhesive sheet to widen the intervals between the plurality of semiconductor chips.

  According to this aspect of the present invention, since the semiconductor wafer is divided into a plurality of semiconductor chips by a so-called tip dicing method, disorder of the alignment state of the semiconductor chips during dicing can be prevented. Furthermore, according to one aspect of the present invention, the plurality of semiconductor chips separated by the first dicing method are attached to the second adhesive sheet, the second adhesive sheet is stretched, and the plurality of semiconductor chips are connected to each other. Can be widened.

1 aspect of this invention WHEREIN: Before forming the said groove | channel on said 1st surface, it further includes the process of sticking a 3rd adhesive sheet on said 1st surface, cutting | disconnecting said 3rd adhesive sheet, Preferably, the groove is formed on the first surface, and the first pressure-sensitive adhesive sheet is attached to the cut third pressure-sensitive adhesive sheet.
According to such an aspect, since the groove is formed in a state where the first surface is protected by the third pressure-sensitive adhesive sheet, contamination and breakage of the first surface due to cutting waste can be prevented.

In one aspect of the present invention, it is preferable that a plurality of circuits are formed on the first surface, and the grooves are formed so as to partition the circuits.
According to such an aspect, it can be separated into a plurality of semiconductor chip units.

1 aspect of this invention WHEREIN: It is preferable that said 2nd adhesive sheet has a tensile elasticity modulus smaller than said 1st adhesive sheet.
According to this aspect, in the expanding process of extending the second pressure-sensitive adhesive sheet, it becomes easy to greatly increase the interval between the plurality of semiconductor chips.

In one embodiment of the present invention, it is preferable that the method further includes a step of covering the plurality of semiconductor chips with a sealing member while leaving the first surface after increasing the interval between the plurality of semiconductor chips.
According to this aspect, it is possible to cover the plurality of semiconductor chips with the sealing member after greatly increasing the interval between the plurality of semiconductor chips without disturbing the alignment state of the plurality of semiconductor chips. Moreover, according to this aspect, the separated semiconductor chips can be sealed one by one with the sealing member without being rearranged by pick and place from the first adhesive sheet to another adhesive sheet or support. Can be covered. Therefore, according to this aspect, the steps of the WLP manufacturing process can be simplified.

Sectional drawing explaining the manufacturing method which concerns on 1st embodiment. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. Sectional drawing explaining the manufacturing method which concerns on 2nd embodiment.

[First embodiment]
Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.

FIG. 1A shows a semiconductor wafer W adhered to a protective sheet 30 as a third adhesive sheet. The semiconductor wafer W has a circuit surface W1 as a first surface, and a circuit W2 is formed on the circuit surface W1. The protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W. The protection sheet 30 protects the circuit surface W1 and the circuit W2.
The semiconductor wafer W may be, for example, a silicon semiconductor wafer or a compound semiconductor wafer such as gallium / arsenic. Examples of a method for forming the circuit W2 on the circuit surface W1 include a widely used method, such as an etching method and a lift-off method.

The protective sheet 30 has a third base film 31 and a third pressure-sensitive adhesive layer 32. The third pressure-sensitive adhesive layer 32 is laminated on the third base film 31.
The material of the third base film 31 is not particularly limited. Examples of the material of the third base film 31 include polyvinyl chloride resin, polyester resin (polyethylene terephthalate, etc.), acrylic resin, polycarbonate resin, polyethylene resin, polypropylene resin, acrylonitrile / butadiene / styrene resin, polyimide resin, and polyurethane resin. Examples thereof include resins and polystyrene resins.

  The pressure-sensitive adhesive contained in the third pressure-sensitive adhesive layer 32 is not particularly limited and can be widely applied. Examples of the pressure-sensitive adhesive contained in the third pressure-sensitive adhesive layer 32 include rubber-based, acrylic-based, silicone-based, polyester-based, and urethane-based adhesives. In addition, the kind of adhesive is selected in consideration of the use, the kind of adherend to be attached, and the like.

  When the energy ray polymerizable compound is blended in the third pressure-sensitive adhesive layer 32, the third pressure-sensitive adhesive layer 32 is irradiated with energy rays from the third base film 31 side, and the energy ray polymerizable compound is irradiated. Is cured. When the energy ray polymerizable compound is cured, the cohesive force of the third pressure-sensitive adhesive layer 32 is increased, and the pressure-sensitive adhesive force between the third pressure-sensitive adhesive layer 32 and the semiconductor wafer W can be reduced or eliminated. Examples of the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.

[Groove formation process]
FIG. 1B shows a diagram for explaining a step of forming a groove having a predetermined depth from the circuit surface W1 side of the semiconductor wafer W (sometimes referred to as a groove forming step).
In the groove forming step, the semiconductor wafer is cut from the protective sheet 30 side using a dicing blade of a dicing apparatus or the like. At that time, the protective sheet 30 is completely cut, and a groove W5 is formed by making a cut with a depth shallower than the thickness of the semiconductor wafer W from the circuit surface W1 of the semiconductor wafer W. The groove W5 is formed so as to partition a plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W. The depth of the groove W5 is not particularly limited as long as it is a little deeper than the thickness of the target semiconductor chip. When the groove W5 is formed, cutting waste from the semiconductor wafer W is generated. In the present embodiment, since the groove W5 is formed in a state where the circuit surface W1 is protected by the protective sheet 30, contamination and breakage of the circuit surface W1 and the circuit W2 due to cutting waste can be prevented.

[Grinding process]
FIG. 1C shows a diagram for explaining a process of grinding the back surface W6 as the second surface of the semiconductor wafer W after forming the groove W5 (sometimes referred to as a grinding process). .
In this embodiment, before grinding, the 1st adhesive sheet 10 is stuck on the protection sheet 30 side. After adhering the first adhesive sheet 10, the semiconductor wafer W is ground from the back surface W 6 side using the grinder 50. By grinding, the thickness of the semiconductor wafer W is reduced and finally divided into a plurality of semiconductor chips CP. Grinding is performed from the back surface W6 side until the bottom of the groove W5 is removed, and the semiconductor wafer W is separated into pieces for each circuit W2. Thereafter, back grinding is further performed as necessary to obtain a semiconductor chip CP having a predetermined thickness. In this embodiment, grinding is performed until the back surface W3 as the third surface is exposed.
FIG. 1D shows a state where a plurality of divided semiconductor chips CP are held by the protective sheet 30 and the first adhesive sheet 10.

The first pressure-sensitive adhesive sheet 10 has a first base film 11 and a first pressure-sensitive adhesive layer 12. The first pressure-sensitive adhesive layer 12 is laminated on the first base film 11.
The material of the first base film 11 is not particularly limited. Examples of the material of the first base film 11 include the same materials as those exemplified for the third base film 31.

  The pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 12 is not particularly limited and can be widely applied. As an adhesive contained in the 1st adhesive layer 12, the adhesive similar to the adhesive demonstrated about the 3rd adhesive layer 32 is mentioned, for example. In addition, the kind of adhesive is selected in consideration of the use, the kind of adherend to be attached, and the like. The first pressure-sensitive adhesive layer 12 may also contain an energy ray polymerizable compound.

  The first pressure-sensitive adhesive sheet 10 may be cut in advance so as to have substantially the same shape as the semiconductor wafer W, or a first pressure-sensitive adhesive sheet 10 larger than the semiconductor wafer W is prepared. After being attached to the semiconductor wafer W, it may be cut into the same shape as the semiconductor wafer W.

  In the present embodiment, the first pressure-sensitive adhesive layer 12 contains a relatively strong pressure-sensitive adhesive so that it can be peeled off along with the cut protective sheet 30 in a later step. Is preferred. The first base film 11 is preferably relatively rigid like polyethylene terephthalate so that it does not stretch when it is peeled off.

[Attaching process (second adhesive sheet)]
FIG. 2 (A) shows a diagram for explaining a step of sticking the second adhesive sheet 20 to a plurality of semiconductor chips CP (sometimes referred to as a sticking step) after the grinding step.
The second adhesive sheet 20 is attached to the back surface W3 of the semiconductor chip CP. The second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22.
The material of the second base film 21 is not particularly limited. Examples of the material of the second base film 21 include the same materials as those exemplified for the third base film 31.

  The second pressure-sensitive adhesive layer 22 is laminated on the second base film 21. The pressure-sensitive adhesive contained in the second pressure-sensitive adhesive layer 22 is not particularly limited and can be widely applied. As an adhesive contained in the 2nd adhesive layer 22, the adhesive similar to the adhesive demonstrated about the 3rd adhesive layer 32 is mentioned, for example. In addition, the kind of adhesive is selected in consideration of the use, the kind of adherend to be attached, and the like. The second pressure-sensitive adhesive layer 22 may also contain an energy ray polymerizable compound.

  The second pressure-sensitive adhesive sheet 20 preferably has a smaller tensile elastic modulus than the first pressure-sensitive adhesive sheet 10. The tensile modulus of the second pressure-sensitive adhesive sheet 20 is preferably 10 MPa or more and 2000 MPa or less. The breaking elongation of the second pressure-sensitive adhesive sheet 20 is also preferably 50% or more.

  In the present embodiment, the adhesive force of the second adhesive layer 22 to the semiconductor wafer W is preferably larger than the adhesive force of the third adhesive layer 32 to the semiconductor wafer W. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 and the protective sheet 30 can be easily peeled off.

  The second adhesive sheet 20 may be attached to the plurality of semiconductor chips CP and the ring frame. In this case, a ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and this is lightly pressed and fixed. Thereafter, the second adhesive layer 22 exposed inside the ring shape of the ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second adhesive sheet 20.

[Peeling process (first adhesive sheet)]
FIG. 2B shows a diagram for explaining a process of peeling the first pressure-sensitive adhesive sheet 10 and the protective sheet 30 (sometimes referred to as a peeling process) after the second pressure-sensitive adhesive sheet 20 has been attached. ing.
In the present embodiment, as described above, the first pressure-sensitive adhesive sheet 10 is adhered to the protective sheet 30. When the first pressure-sensitive adhesive sheet 10 is peeled off, the cut protective sheet 30 is accompanied and peeled off. When the protective sheet 30 is peeled off, the circuit surfaces W1 of the plurality of semiconductor chips CP are exposed. In the present embodiment, as shown in FIG. 2B, the distance between the semiconductor chips CP divided by the prior dicing method is D1. The distance D1 is preferably 15 μm or more and 110 μm or less, for example.

[Expanding process]
FIG. 2C shows a diagram illustrating a process of extending the second adhesive sheet 20 that holds a plurality of semiconductor chips CP (sometimes referred to as an expanding process).
In the expanding process, the interval between the plurality of semiconductor chips CP is further expanded. The method for extending the second pressure-sensitive adhesive sheet 20 in the expanding step is not particularly limited. Examples of the method of stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like. For example, a method of grabbing and stretching.

  In the present embodiment, as shown in FIG. 2C, the distance between the semiconductor chips CP after the expanding process is D2. The distance D2 is larger than the distance D1. For example, the distance D2 is preferably 200 μm or more and 5000 μm or less.

[Sealing process]
FIG. 3 is a diagram illustrating a process of sealing a plurality of semiconductor chips CP using the sealing member 60 (sometimes referred to as a sealing process).
FIG. 3 (A) shows a diagram illustrating a step of attaching a surface protective sheet 40 as a fourth adhesive sheet to a plurality of semiconductor chips CP after the expanding step.
After extending the second pressure-sensitive adhesive sheet 20 to increase the distance between the plurality of semiconductor chips CP to the distance D2, the surface protection sheet 40 is attached to the circuit surface W1 of the semiconductor chip CP. The surface protection sheet 40 includes a fourth base film 41 and a fourth pressure-sensitive adhesive layer 42. It is preferable that the surface protection sheet 40 is stuck so that the circuit surface W1 may be covered with the fourth pressure-sensitive adhesive layer 42.

The material of the surface protection sheet 40 is not particularly limited. Examples of the material of the fourth base film 41 include the same materials as those exemplified for the third base film 31.
The fourth pressure-sensitive adhesive layer 42 is laminated on the fourth base film 41. The pressure-sensitive adhesive contained in the fourth pressure-sensitive adhesive layer 42 is not particularly limited and can be widely applied. As an adhesive contained in the 4th adhesive layer 42, the adhesive similar to the adhesive demonstrated about the 3rd adhesive layer 32 is mentioned, for example. In addition, the kind of adhesive is selected in consideration of the use, the kind of adherend to be attached, and the like. The fourth pressure-sensitive adhesive layer 42 may also contain an energy ray polymerizable compound.

  The adhesive force of the fourth adhesive layer 42 to the semiconductor wafer W is preferably larger than the adhesive force of the second adhesive layer 22 to the semiconductor wafer W. If the adhesive force of the fourth pressure-sensitive adhesive layer 42 is larger, the second pressure-sensitive adhesive sheet 20 can be easily peeled after the plurality of semiconductor chips CP are transferred to the surface protective sheet 40.

  The surface protective sheet 40 preferably has heat resistance. When the sealing member to be described later is a thermosetting resin, for example, the curing temperature is about 120 ° C. to 180 ° C., and the heating time is about 30 minutes to 2 hours. The surface protective sheet 40 preferably has heat resistance so that wrinkles do not occur when the sealing member is thermally cured. Moreover, it is preferable that the surface protection sheet 40 is comprised with the material which can peel from the semiconductor chip CP after a thermosetting process.

  The surface protection sheet 40 may be attached to the plurality of semiconductor chips CP and the second ring frame. In this case, the second ring frame is placed on the fourth pressure-sensitive adhesive layer 42 of the surface protection sheet 40, and this is lightly pressed and fixed. Thereafter, the fourth adhesive layer 42 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor chip CP and fixed.

  After the surface protective sheet 40 is adhered, when the second pressure-sensitive adhesive sheet 20 is peeled off, the back surfaces W3 of the plurality of semiconductor chips CP are exposed. Even after the second adhesive sheet 20 is peeled off, it is preferable that the distance D2 between the plurality of semiconductor chips CP expanded in the expanding process is maintained. When the energy ray polymerizable compound is blended in the second pressure-sensitive adhesive layer 22, the second pressure-sensitive adhesive layer 22 is irradiated with energy rays from the second base film 21 side, and the energy ray polymerizable compound is irradiated. It is preferable to peel the second pressure-sensitive adhesive sheet 20 after curing.

FIG. 3B shows a diagram illustrating a process of sealing a plurality of semiconductor chips CP held by the surface protection sheet 40.
The sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1. The sealing member 60 is also filled between the plurality of semiconductor chips CP. In this embodiment, since the circuit surface W1 and the circuit W2 are covered with the surface protection sheet 40, it is possible to prevent the circuit surface W1 from being covered with the sealing member 60.

By the sealing process, the sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in the sealing member is obtained. In the sealing step, the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.
The method for covering the plurality of semiconductor chips CP with the sealing member 60 is not particularly limited. For example, a method of accommodating a plurality of semiconductor chips CP while covering the circuit surface W1 with the fourth surface protection sheet 40 in a mold, injecting a fluid resin material into the mold, and curing the resin material May be adopted. Further, a method of embedding the plurality of semiconductor chips CP in the sealing resin by placing the sheet-shaped sealing resin so as to cover the back surfaces W3 of the plurality of semiconductor chips CP and heating the sealing resin is adopted. May be. Examples of the material of the sealing member 60 include an epoxy resin. The epoxy resin used as the sealing member 60 may contain, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like.

  After the sealing step, when the surface protective sheet 40 is peeled off, the surface 3S that has been in contact with the circuit surface W1 of the semiconductor chip CP and the surface protective sheet 40 of the sealing body 3 is exposed.

[Semiconductor package manufacturing process]
4 and 5 are diagrams for explaining a manufacturing process of a semiconductor package using a plurality of semiconductor chips CP. The present embodiment preferably includes a manufacturing process of such a semiconductor package.

[Rewiring layer formation process]
FIG. 4A shows a cross-sectional view of the sealing body 3 after the surface protective sheet 40 is peeled off. In this embodiment, it is preferable to further include a rewiring layer forming step of forming a rewiring layer on the sealing body 3 after the surface protective sheet 40 is peeled off. In the rewiring layer forming step, rewirings connected to the circuits W2 of the plurality of exposed semiconductor chips CP are formed on the circuit surface W1 and the surface 3S of the sealing body 3. In forming the rewiring, first, an insulating layer is formed on the sealing body 3.

  FIG. 4B is a cross-sectional view illustrating a process of forming the first insulating layer 61 on the circuit surface W1 of the semiconductor chip CP and the surface 3S of the sealing body 3. A first insulating layer 61 including an insulating resin is formed on the circuit surface W1 and the surface 3S so as to expose the circuit W2 or the internal terminal electrode W4 of the circuit W2. Examples of the insulating resin include polyimide resin, polybenzoxazole resin, and silicone resin. The material of the internal terminal electrode W4 is not limited as long as it is a conductive material, and examples thereof include gold, silver, metals such as copper and aluminum, and alloys.

  FIG. 4C is a cross-sectional view illustrating a process of forming the rewiring 5 that is electrically connected to the semiconductor chip CP sealed in the sealing body 3. In the present embodiment, the rewiring 5 is formed following the formation of the first insulating layer 61. The material of the rewiring 5 is not limited as long as it is a conductive material, and examples thereof include gold, silver, metals such as copper and aluminum, and alloys. The rewiring 5 can be formed by a known method.

  FIG. 5A is a cross-sectional view illustrating a process of forming the second insulating layer 62 that covers the rewiring 5. The rewiring 5 has external electrode pads 5A for external terminal electrodes. An opening or the like is provided in the second insulating layer 62 to expose the external electrode pad 5A for the external terminal electrode. In the present embodiment, the external electrode pad 5A is exposed in the region of the semiconductor chip CP of the sealing body 3 (region corresponding to the circuit surface W1) and outside the region (region corresponding to the surface 3S on the sealing member 60). I am letting. The rewiring 5 is formed on the surface 3S of the sealing body 3 so that the external electrode pads 5A are arranged in an array. In the present embodiment, since the external electrode pad 5A is exposed outside the region of the semiconductor chip CP of the sealing body 3, a fan-out type WLP can be obtained.

[Connection process with external terminal electrode]
FIG. 5B is a cross-sectional view illustrating a process of connecting the external terminal electrode to the external electrode pad 5A of the sealing body 3. An external terminal electrode 7 such as a solder ball is placed on the external electrode pad 5A exposed from the second insulating layer 62, and the external terminal electrode 7 and the external electrode pad 5A are electrically connected by solder bonding or the like. The material of the solder ball is not particularly limited, and examples thereof include lead-containing solder and lead-free solder.

[Second dicing process]
FIG. 5C shows a cross-sectional view for explaining a process of separating the sealing body 3 to which the external terminal electrode 7 is connected (sometimes referred to as a second dicing process). In the second dicing process, the sealing body 3 is separated into individual semiconductor chips CP. The method for dividing the sealing body 3 into individual pieces is not particularly limited. For example, the sealing body 3 can be separated into pieces by adopting a method similar to the method of dicing the semiconductor wafer W described above. The step of dividing the sealing body 3 into pieces may be performed by sticking the sealing body 3 to an adhesive sheet such as a dicing sheet.

  By separating the sealing body 3 into pieces, the semiconductor package 1 in units of the semiconductor chip CP is manufactured. As described above, the semiconductor package 1 in which the external terminal electrode 7 is connected to the external electrode pad 5A fanned out outside the region of the semiconductor chip CP is manufactured as a fan-out type wafer level package (FO-WLP).

[Mounting process]
In the present embodiment, it is also preferable to include a step of mounting the separated semiconductor package 1 on a printed wiring board or the like.

  According to the present embodiment, since the semiconductor wafer W is divided into a plurality of semiconductor chips CP by a so-called tip dicing method, disorder of the alignment state of the semiconductor chips CP during dicing can be prevented. Furthermore, according to the present embodiment, a plurality of semiconductor chips CP separated by the tip dicing method are attached to the second pressure-sensitive adhesive sheet 20, and the second pressure-sensitive adhesive sheet 20 is stretched to form a plurality of semiconductor chips CP. The distance between each other can be increased. Also in the expanding process, it is possible to prevent disorder of the alignment state of the plurality of semiconductor chips CP.

  The method according to the present embodiment is excellent in adaptability to the process of manufacturing the FO-WLP type semiconductor package 1. Specifically, according to the present embodiment, the uniformity and accuracy of the chip interval in the FO-WLP type semiconductor package 1 can be improved.

[Second Embodiment]
2nd embodiment is different from 1st embodiment regarding the process from the process of peeling the 1st adhesive sheet 10 in 1st embodiment to the rewiring layer formation process. Since the second embodiment is the same as the first embodiment in other points, the description is omitted or simplified.

The figure explaining the process of peeling the 1st adhesive sheet 10 in this embodiment is shown by FIG. 6 (A).
In this embodiment, after the 2nd adhesive sheet 20 is stuck on the back surface W3 of semiconductor chip CP, the process of peeling only the 1st adhesive sheet 10 is included. That is, in the first embodiment, when the first pressure-sensitive adhesive sheet 10 is peeled off, the cut protective sheet 30 is accompanied and peeled off. In the present embodiment, the protective sheet 30 is attached to the circuit of the semiconductor chip CP. The first pressure-sensitive adhesive sheet 10 is peeled off while remaining on the surface W1.

  When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 12, the first pressure-sensitive adhesive layer 12 is irradiated with energy rays from the first base film 11 side, and the energy ray polymerizable compound is irradiated. Is cured. When the energy beam polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer is increased, and the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 12 and the protective sheet 30 can be reduced or eliminated. At this time, it is preferable to irradiate energy rays so that the adhesive strength of the third adhesive layer 32 of the protective sheet 30 is not reduced or lost. Examples of the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.

  In the present embodiment, the adhesive force of the second adhesive layer 22 to the semiconductor wafer W is preferably larger than the adhesive force of the first adhesive layer 12 to the third base film 31. Furthermore, the adhesive force of the first adhesive layer 12 to the third base film 31 is preferably smaller than the adhesive force of the third adhesive layer 32 to the semiconductor wafer W. In the present embodiment, only the first pressure-sensitive adhesive sheet 10 is peeled first from the state where the first pressure-sensitive adhesive sheet 10, the second pressure-sensitive adhesive sheet 20, and the protective sheet 30 are adhered to the semiconductor chip CP. Therefore, if the adhesive force of the first pressure-sensitive adhesive layer 12 is low, it is easy to peel off while leaving the divided protective sheet 30 on the semiconductor chip CP.

FIG. 6B shows a diagram for explaining an expanding process of extending the second pressure-sensitive adhesive sheet 20 after peeling the first pressure-sensitive adhesive sheet 10.
The second adhesive sheet 20 holds a plurality of semiconductor chips CP whose circuit surface W1 is covered with the protective sheet 30. In the expanding process of the present embodiment, the second pressure-sensitive adhesive sheet 20 is stretched in such a state, and the space between the plurality of semiconductor chips CP is expanded to the distance D2.

FIG. 6C shows a diagram illustrating a process of sealing a plurality of semiconductor chips CP after the expansion process is performed.
In the first embodiment, the surface protection sheet 40 is adhered to the circuit surface W1, the second adhesive sheet 20 is peeled off, and the semiconductor chip CP is sealed using the sealing member 60, whereas this embodiment is described. Then, since the protective sheet 30 has already been adhered to the circuit surface W1, the surface protective sheet 40 need not be adhered, and the second adhesive sheet is still adhered to the back surface W3 of the semiconductor chip CP. Can be sealed. The sealing body 3A is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1. It is preferable that the surface 3S of the sealing body 3A and the circuit surface W1 of the semiconductor chip CP are the same surface.

  In the present embodiment, as shown in FIG. 6C, a sealing member 60 is filled between and around the plurality of semiconductor chips CP. In this embodiment, since the circuit surface W1 and the circuit W2 are covered with the protective sheet 30, it is possible to prevent the circuit surface W1 from being covered with the sealing member 60. In the sealing step, the second pressure-sensitive adhesive sheet is adhered to the back surface W3 of the semiconductor chip CP. Therefore, the back surface W3 of the semiconductor chip CP is not covered with the sealing member 60, and the thickness of the sealing body 3A can be reduced.

  By the sealing process of the present embodiment, a sealing body 3A in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in the sealing member 60 is obtained. In the sealing step, the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.

  After the sealing step, the protective sheet 30 and the second pressure-sensitive adhesive sheet 20 are peeled off. The order of peeling these is not particularly limited. When peeling off the protective sheet 30, it is preferable to use an adhesive tape, for example. An adhesive tape is stuck on the surface of the third base film 31 of the protective sheet 30, and the protective sheet 30 can be peeled off using this adhesive tape as a base point. The adhesive tape may be an adhesive tape or a heat seal tape. When the second adhesive sheet 20 is peeled off, the back surface W3 of the semiconductor chip CP is exposed.

  Using the sealing body 3A, a semiconductor package or a semiconductor device can be manufactured through the same steps as in the first embodiment.

  According to the manufacturing method according to the present embodiment, disorder of the alignment state of the plurality of semiconductor chips CP can be prevented as in the first embodiment. The method according to the present embodiment is also excellent in adaptability to a process of manufacturing a FO-WLP type semiconductor package, and can manufacture a thinner semiconductor package.

[Third embodiment]
3rd embodiment is the same as that of 1st embodiment regarding the process until it implements the 2nd expanding process in 1st embodiment. Therefore, the description of the same points is omitted or simplified. Hereafter, the point which concerns on difference with 1st embodiment among 3rd embodiment is demonstrated.

  The third embodiment includes a step of picking up each of the plurality of semiconductor chips CP without performing the sealing step after performing the expanding step and expanding the interval between the plurality of semiconductor chips CP. As the pickup, a pickup device that has been conventionally used can be used. In the present embodiment, it is preferable that the picked-up semiconductor chip CP further includes a step of mounting on a printed wiring board or the like. The mounted semiconductor chip CP is sealed and packaged with a sealing member or the like, for example.

  According to the present embodiment, the semiconductor chip CP can be picked up after greatly increasing the interval between the plurality of semiconductor chips CP while preventing the disorder of the alignment state of the semiconductor chips CP. Therefore, when picking up, it becomes easy to prevent the semiconductor chip CP gripped by the pickup device from coming into contact with another semiconductor chip or the pickup device from coming into contact with another semiconductor chip.

[Modification of Embodiment]
The present invention is not limited to the above-described embodiment. The present invention includes a modification of the above-described embodiment as long as the object of the present invention can be achieved.

  For example, a circuit or the like in a semiconductor wafer or a semiconductor chip is not limited to the illustrated arrangement or shape. The connection structure with the external terminal electrode in the semiconductor package is not limited to the mode described in the above embodiment. In the above-described embodiment, the aspect of manufacturing the FO-WLP type semiconductor package has been described as an example. However, the present invention can also be applied to an aspect of manufacturing other semiconductor packages such as a fan-in type WLP.

  For example, in the above-described embodiment, a mode in which the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W and the groove forming step is performed is illustrated, but the present invention is not limited to such a mode. For example, without applying the protective sheet 30 to the circuit surface W1, the groove forming step is performed with the circuit surface W1 exposed, and after the groove is formed, the first adhesive sheet 10 is applied to the circuit surface W1 to perform the grinding step. Embodiments to be implemented are also included in the present invention. Further, a passivation film that covers the circuit surface W1 may be formed before the groove forming step. The passivation film preferably has a shape that exposes the internal terminal electrode W4 of the circuit W2. The passivation film is preferably formed using, for example, silicon nitride, silicon oxide, polyimide, or the like.

  For example, in the above-described embodiment, an example in which the second adhesive sheet 20 is extended to widen the intervals between the plurality of semiconductor chips CP has been described as an example. However, the expanding process may be performed a plurality of times. . When carrying out a plurality of expanding steps, the plurality of semiconductor chips CP held on the second adhesive sheet 20 are transferred to another expanding sheet while maintaining the expanded spacing, and the expanding sheet is stretched, Furthermore, the interval between the plurality of semiconductor chips CP can be increased. For example, after attaching the surface protection sheet 40 in the first embodiment, the surface protection sheet 40 may be extended to further increase the interval between the plurality of semiconductor chips CP.

  For example, in the above-described embodiment, the semiconductor device manufacturing method including the step of forming a groove having a depth of cut shallower than the thickness of the semiconductor wafer has been described as an example. However, the semiconductor wafer in which the groove is formed in advance is described. May be used.

  The present invention can be used as a method for manufacturing a semiconductor device.

  DESCRIPTION OF SYMBOLS 10 ... 1st adhesive sheet, 20 ... 2nd adhesive sheet, 30 ... Protection sheet (3rd adhesive sheet), 60 ... Sealing member, CP ... Semiconductor chip, W ... Semiconductor wafer, W1 ... Circuit surface (1st One surface), W3 ... back surface (third surface), W5 ... groove, W6 ... back surface (second surface).

Claims (5)

Forming a groove having a depth of cut shallower than the thickness of the semiconductor wafer on the first surface of the semiconductor wafer;
Attaching the first pressure-sensitive adhesive sheet to the first surface on which the groove is formed;
A step of grinding a second surface opposite to the first surface to which the first adhesive sheet is affixed to reduce the thickness of the semiconductor wafer and dividing the semiconductor wafer into a plurality of semiconductor chips When,
A step of affixing a second adhesive sheet on the third surface that appears after grinding the second surface;
Peeling the first pressure-sensitive adhesive sheet;
Extending the second pressure-sensitive adhesive sheet to widen the interval between the plurality of semiconductor chips. A method for manufacturing a semiconductor device. Before forming the groove on the first surface, further comprising a step of attaching a third adhesive sheet to the first surface;
Cutting the third adhesive sheet to form the groove on the first surface;
Affixing the first pressure-sensitive adhesive sheet to the cut third pressure-sensitive adhesive sheet,
A method for manufacturing a semiconductor device according to claim 1. A plurality of circuits are formed on the first surface,
The groove is formed so as to partition the circuit.
A method for manufacturing a semiconductor device according to claim 1. The second adhesive sheet has a smaller tensile elastic modulus than the first adhesive sheet,
The method for manufacturing a semiconductor device according to claim 1. And further comprising a step of covering the plurality of semiconductor chips with a sealing member leaving the first surface after expanding the interval between the plurality of semiconductor chips.
The method for manufacturing a semiconductor device according to claim 1.

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