JP2016115154A - Master device and electric apparatus for performing synchronous serial data communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a master device to avoid an error due to the delay of data transferred from a slave device to the master device if synchronous serial data communication is performed between the master device and the slave device.SOLUTION: A master device 204D for performing synchronous serial data communication with a slave device on the basis of a clock includes: transmission preparation determination means (SPI control unit) 204D(1) for determining whether or not the slave device has prepared a data line (SI) for data transmission corresponding to a command from the master device 204D; and clock stop control means 204D(6) that stops the clock when the transmission preparation determination means 204D(1) has determined that the preparation of the data line (SI) is not completed, and resumes the supply of the clock when it has determined that the preparation of the data line (SI) is completed.SELECTED DRAWING: Figure 11

Description

  The present invention relates to a master device used in synchronous serial data communication for transferring data between a master device and a slave device, and an electric apparatus including the master device and the slave device.

Some electrical devices such as information processing apparatuses are mounted with custom electronic parts manufactured using a process that has not been used (referred to as an old process).
Some of these custom electronic components have been in use for over 10 years.
However, since the manufacture of custom electronic parts using the old process is not profitable, the parts manufacturer may suspend (disconnect) the manufacture of custom electronic parts using the old process.

When a parts manufacturer stops producing custom electronic components, electrical equipment manufacturers usually respond by procuring electronic parts that can replace custom electronic parts. The
In that case, manufacturers of electrical equipment respond by using a microcomputer (hereinafter referred to as a microcomputer).

However, simply replacing the custom electronic component with a microcomputer may cause an error in the processing of the electrical device.
When a slave device in an electric device is replaced with a microcomputer and connected to, for example, an SPI (Serial Peripheral Interface) used for synchronous serial data communication between the master device and the slave device, the master device makes a read request to the slave device. The processing speed of the microcomputer may not be in time.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to delay data transfer to a master device of a slave device when performing synchronous serial data communication between a master device and a slave device. This is to avoid an error caused by the master device.

  The present invention is a master device that performs serial data communication with a slave device based on a clock, and whether the slave device is ready for a data line for data transmission corresponding to a command from the master device. Transmission preparation determining means for determining whether or not the transmission preparation determining means stops the clock when the data line preparation is determined to be incomplete, and supplies the clock when the data line preparation is determined to be complete. A master device for performing synchronous serial data communication, comprising: a clock stop control means for restarting.

  According to the master device of the present invention, when synchronous serial data communication is performed between a master device and a slave device, errors due to a delay in data transfer to the master device of the slave device can be avoided in the master device. .

2 is a block diagram of an image forming apparatus in which an operation control unit of an operation unit connected to an SPI is configured by an ASIC. FIG. It is a block diagram which shows roughly the structure of the controller connected to SPI. It is a block diagram of an operation unit which is a slave device connected to the SPI. It is a block diagram of an SPI master device. FIG. 4 is a timing chart when data is written to an SPI slave device in the SPI master device. FIG. 4 is a timing chart when reading data from an SPI slave device in an SPI master device. FIG. 4 is a timing chart at the time of reading data in the SPI master device when the operation control unit of the operation unit shown in FIG. 3 is replaced from an ASIC to a microcomputer. 1 is a block diagram of an image forming apparatus having an SPI master device according to an embodiment of the present invention. It is a block diagram of a controller provided with an SPI master device according to an embodiment of the present invention. It is a block diagram of an operation part. It is a block diagram of the SPI master device of a controller. FIG. 5 is a timing chart at the time of reading read data transferred from an SPI slave device in an SPI master device. FIG. 6 is a block diagram of an SPI master device according to another embodiment of the present invention. FIG. 10 is a timing chart at the time of reading data in an SPI master device according to another embodiment of the present invention. It is a timing diagram at the time of reading data when additional information such as address information is not transferred.

  Hereinafter, an embodiment of the present invention will be described. Here, as a premise of the present invention, a control unit of an electric device is a master device and an operation unit is a slave device, and both devices are connected by SPI to synchronize serial. In the case of performing data communication, processing related to data writing and reading when the operation control unit of the operation unit is configured by an ASIC will be described with reference to FIGS. Subsequently, when the ASIC is based on an old process, a problem when the microcomputer is replaced with a microcomputer and a master device according to an embodiment of the present invention relating to a solution to the problem will be described with reference to FIG. 7 and subsequent drawings.

The present invention relates to data transfer between a master device and a slave device. An electrical device including a master device and a slave device that performs synchronous serial communication is, for example, an information processing apparatus, an image forming apparatus, or the like. Here, the image forming apparatus will be described as an example.
FIG. 1 is a block diagram of an image forming apparatus in which an operation control unit of an operation unit connected to an SPI is configured by an ASIC.
The image forming apparatus 100 includes a switch (SW) 10, a PSU (Power Supply Unit) 14, a plotter unit 12, a scanner unit 16, a controller 20, and an operation unit 30 as illustrated.

Here, the controller 20 and the operation unit 30 are connected by an SPI.
As shown in FIG. 4 described later, the SPI includes a chip select (CS) signal line, a clock (CLK) signal line, a data output (SO) signal line, It consists of four signal lines, data input (SI) signal lines.

The switch 10 is a power switch. When the switch 10 is turned on, power is supplied to the PSU 14.
The PSU 14 is a power supply unit of the image forming apparatus 100 and supplies power to the plotter unit 12, the scanner unit 16, the controller 20, and the operation unit 30.
The plotter unit 12 outputs an image formed inside the image forming apparatus 100.
The scanner unit 16 scans a document image, for example.
The controller 20 is a control unit of the image forming apparatus 100, receives a command (operation) from the operation unit 30, a network, and a USB (Universal Serial Bus), and executes control according to the command.
The operation unit 30 is a unit for setting (commanding) various operations to the image forming apparatus 100.

FIG. 2 is a block diagram schematically showing the structure of the controller 20 connected to the SPI.
The controller 20 includes a clock generation unit 201, a CPU (Central Processing Unit) 202, a ROM (Read Only Memory) 203, an ASIC (Application Specific Integrated Circuit) 204, a DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) 205, A PHY 206 and a PHY clock generation unit 207 are included.

The clock generation unit 201 generates a clock signal used inside the controller 20 and supplies the generated clock signal CLK to each unit of the controller 20.
The CPU 202 is an arithmetic processing device that controls the entire controller 20.
The ROM 203 is a nonvolatile memory, and stores programs executed by the CPU 202 and various data.

The ASIC 204 is an integrated circuit for image data processing.
As shown in FIG. 2, the ASIC 204 includes a CPU I / F (interface) 204a, ROM I / F 204b, USB I / F 204c, SPI device 204d, PCI (Peripheral Component Interconnect) I / F 204e, and MEM (Memory Module) I / F. F204f and MAC (Media Access Control) 204g.

The CPU I / F 204a is an interface with the CPU 202.
The ROM I / F 204b is an interface with the ROM 203.
The USB I / F 204c is an interface for executing data communication with a PC (Personal Computer) or the like.

The SPI device 204d is an interface with the operation unit 30 and functions as a master device. Hereinafter, for convenience of explanation, the SPI device is referred to as an SPI master device 204d.
The CPU 202 controls to regularly transfer a command for scanning the key 302a of the operation unit 30 from the SPI master device 204d to the SPI slave device 301a (FIG. 3) of the operation unit 30 which is a slave device. The CPU 202 recognizes the read data transferred from the SPI slave device 301 a and determines the operation content of the key 302 a pressed on the operation unit 30.
The CPU 202 executes control of the image forming apparatus 100 based on the operation content (operation information) of the key 302 a pressed on the operation unit 30.

  For example, when the “COPY key” is pressed by the user in the operation unit 30, the CPU 202 recognizes that the “COPY key” is pressed from the data transferred from the SPI slave device 301 a. Based on this recognition, the CPU 202 controls the scanner unit 16 to scan a document image and the plotter unit 12 to output an image based on the image data transferred from the scanner unit 16.

The PCI I / F 204 e is an interface with the plotter unit 12 and the scanner unit 16.
The MEM I / F 204f is a memory interface with the DDR SDRAM 205.
The MAC 204g functions as a data link layer in the network and is connected to the PHY 206.

The DDR SDRAM 205 is a volatile memory and temporarily stores various data.
The PHY 206 functions as a physical layer in the network.
The PHY clock generation unit 207 generates a clock signal and supplies the clock signal to the PHY 206.

FIG. 3 is a block diagram of the operation unit 30 which is a slave device connected to the SPI.
The operation unit 30 includes an operation control unit 301, a key 302a, a key control unit 302, an LCD (Liquid Crystal Display) 303a, an LCD driver 303b, an LCD control unit 303, an LED (Light Emitting Diode) 304a, and an LED control unit 304.
In FIG. 3, as described above, the operation control unit 301 of the operation unit 30 is configured by an ASIC.

The operation control unit 301 includes an SPI device 301a and a command control unit 301b.
The SPI device 301a is an interface with the controller 20 and functions as a slave device. Hereinafter, for convenience of explanation, the SPI device is referred to as an SPI slave device 301a.
The command control unit 301b recognizes the command transferred from the SPI master device 204d, and executes various controls in the operation unit 30 based on the command.
The commands include an LED ON / OFF command (write command), an LCD control command (write command), a key sense command (read command), and the like.

The key 302a is a key input receiving unit that receives a key input on the operation panel.
The key control unit 302 receives the key sense command, detects the presence or absence of key input, and transmits the state (contents) of the key 302 a to the operation control unit 301.
The LCD 303a is a first display means, and is a liquid crystal display provided with a backlight or the like.
The LCD driver 303b supplies power to the LCD 303a and causes the LCD 303a to display data designated by the LCD control unit 303.
The LCD control unit 303 converts the data designated as a display target into data that can be displayed on the LCD 303a, and controls the LCD 303a. The LCD control unit 303 controls, for example, a backlight of the LCD 303a.
The LED 304a is a second display unit and is a light emitting diode.
The LED control unit 304 receives a command (LED ON / OFF) related to the LED 304a, and turns on or off the LED 304a designated by the command.

FIG. 4 is a block diagram of the SPI master device 204d.
The SPI master device 204d includes an SPI control unit 204d (1), a CS generation unit 204d (2), a CLK generation unit 204d (3), a parallel / serial conversion unit 204d (4), and a serial / parallel conversion unit 204d (5). Have.
The SPI control unit 204d (1) is a component (i.e., CS generation unit 204d (2), CLK generation unit 204d (3), parallel / serial conversion unit 204d (4), serial / parallel conversion) constituting the SPI master device 204d. Part 204d (5)).

The CS generation unit 204d (2) generates and outputs a chip select (CS) signal.
The CLK generator 204d (3) generates a clock signal CLK from the internal clock signal iCLK. The internal clock signal iCLK is generated by the clock generation unit 201 and supplied to the SPI master device 204d.
The parallel / serial conversion unit 204d (4) converts the parallel data transferred from the SPI master device 204d into serial data and outputs it as a data output (SO) signal.
The serial / parallel converter 204d (5) converts serial data input from SI (data input terminal) into parallel data, and transfers the parallel data to the PCI bus.

FIG. 5 is a timing chart when the SPI master device 204d writes data to the SPI slave device 301a.
In the timing chart shown in FIG. 5, the internal clock signal iCLK, the chip select signal CS, the clock signal CLK, the data output signal SO, and the data input signal SI are shown.
The clock signal CLK is a common synchronization signal in the processing of the SPI master device 204d and the SPI slave device 301a. In FIG. 6, FIG. 7, FIG. 12, FIG. 14, and FIG. 15, which will be described later, the signals shown in FIG.

When data is written from the controller 20 (master) to the operation unit 30 (slave), the CPU 202 of the controller 20 transfers a write command, an address, and write data to the parallel / serial conversion unit 204d (4) of the SPI master device 204d.
Upon receiving a transfer start command from the CPU 202, the parallel / serial conversion unit 204d (4) converts the transferred write command, address, and write data from parallel data to serial data.

The SPI control unit 204d (1) of the SPI master device 204d controls the chip select signal CS from the High level to the Low level and outputs the clock signal CLK in order to output the converted serial data.
In other words, the SPI control unit 204d (1) synchronizes with the falling edge (negative edge) of the clock signal CLK, and uses the write command signal (8 bits) and the address signal (8 bits) as the data output signal SO to generate the SPI of the operation unit 30. Transfer to the slave device 301a.

The SPI control unit 204d (1) further writes (writes) data to the SPI slave device 301a. Therefore, as shown in FIG. 5, the SPI slave device starts from the falling edge of the fifteenth clock following the transfer of the address signal. Write data is transferred to 301a.
The SPI control unit 204d (1) controls the CLK generation unit 204d (3) to output the clock signal CLK until the write data is output, and when the output of the write data is completed (timing of the falling edge of the 22nd clock). ), The clock signal CLK is controlled to high level (that is, stopped).
The SPI control unit 204d (1) controls the clock signal CLK to the high level, and simultaneously controls the chip select signal CS to the high level because the output of the serial data is stopped.

The SPI slave device 301a recognizes the content of the command from the write command signal and the data write designation location from the address signal, and further writes the write data transferred from the SPI master device 204d to the designated location.
In this case, the data input signal SI input to the SPI master device 204d does not change in the High state.

FIG. 6 is a timing chart at the time of reading data from the SPI slave device 301a in the SPI master device 204d.
When the controller 20 (master) reads data from the operation unit 30 (slave), the CPU 202 of the controller 20 transfers a read command and an address to the parallel / serial conversion unit 204d (4) of the SPI master device 204d.
When receiving a transfer start command from the CPU 202, the parallel / serial conversion unit 204d (4) converts the transferred read command and address from parallel data to serial data.

In order to output the converted serial data, the SPI control unit 204d (1) controls the chip select signal CS from the high level to the low level and outputs the clock signal CLK in the same manner as when writing data. The CLK generation unit 204d (3) is controlled.
Next, the SPI control unit 204d (1) transfers the read command signal (8 bits) and the address signal (8 bits) as data output signals to the SPI slave device 301a in synchronization with the falling edge of the clock signal.

In this case, the SPI slave device 301a recognizes the content of the command from the read command signal and the data reading designated location from the address signal, and reads the data from the designated location.
The SPI slave device 301a transfers the read data to the SPI master device 204d at the falling edge of the 15th clock of the clock signal CLK in FIG.

  The SPI control unit 204d (1) transfers the input data signal SI (read data (8 bits)) transferred from the SPI slave device 301a to the clock signal CLK by the serial / parallel conversion unit 204d (5). Control is performed so that the data is converted into parallel data at the timing of each rising edge from the 16th rising edge.

The SPI control unit 204d (1) controls the clock signal CLK to a high level (stop) when 8-bit read data is input to the serial / parallel conversion unit 204d (5).
In addition, the SPI control unit 204d (1) controls the clock signal CLK to the high level, and simultaneously controls the chip select signal CS to the high level since the input of the read data is completed.

The data transfer between the SPI master device 204d and the SPI slave device 301a when the operation control unit 301 of the operation unit 30 connected to the SPI is configured with an ASIC has been described above.
Next, assuming that the ASIC of the operation control unit 301 described above is manufactured by an old process and has already been stopped, the SPI master device 204d and the SPI slave device are replaced when the ASIC is replaced with a microcomputer. An error that occurs in the data transfer process between 301a will be described.

Here, the microcomputer is a computer that operates with a program (that is, software) that is generally configured by combining several thousand or more instructions. For this reason, an ordinary microcomputer may not be able to determine all of a plurality of instructions within one clock cycle period at a predetermined frequency.
For example, in the processing of the image forming apparatus 100, the microcomputer may not be able to determine commands related to the LCD 303a, LED 304a, and key 302a transferred from the SPI master device 204d in one clock. Also, the microcomputer may require thousands of clocks depending on the contents of processing, such as when detecting the state of the key 302a.
Therefore, simply replacing a part of the data processing member in an electrical apparatus, for example, an image forming apparatus, from the ASIC to the microcomputer does not take into account the processing delay of the microcomputer, and an error may occur in the processing.

FIG. 7 is a timing chart at the time of data reading in the SPI master device 204d when the operation control unit 301 of the operation unit 30 shown in FIG. 3 is replaced with an microcomputer from the ASIC. The case where an error occurs in the signal transfer process, here, the read process in the SPI master device 204d is shown.
FIG. 7 shows a case where one clock cycle is required for the microcomputer to interpret the contents of the command.

When the controller 20 instructs the operation unit 30 to transfer data, first, the SPI control unit 204d (1) of the controller 20 converts the SPI slave device 301a in the parallel / serial conversion unit 204d (4). Output the serial data. For this purpose, the SPI control unit 204d (1) controls the chip select signal CS generated by the CS generation unit 204d (2) from the high level to the low level, as shown in FIG. In step 3), control is performed to output the clock signal CLK.
Next, the SPI control unit 204d (1) transfers the read command signal (8 bits) and the address signal (8 bits) to the SPI slave device 301a as data output signals in synchronization with the falling edge of the clock signal CLK.

In this case, the microcomputer configuring the SPI slave device 301a starts interpretation on the content of the command at the time of the last bit of the address data, that is, the rising edge of the 15th clock of the clock signal CLK.
The microcomputer interprets that the content of the command is data reading after the lapse of one clock period from the start of the interpretation regarding the content of the command. Based on this interpretation, the microcomputer recognizes the data reading designated portion from the address signal transferred from the SPI master device 204d, and reads the data from the designated portion.
When reading the data, the microcomputer transfers the read data (read data (8 bits)) to the controller 20 (SPI master device 204d) at the falling edge of the 16th clock of the clock signal CLK.

On the other hand, the SPI control unit 204d (1) transfers the data input signal SI (read data (8 bits)) transferred from the SPI slave device 301a and input to the data input terminal from the rising edge of the 16th clock of the clock signal CLK. The serial / parallel converter 204d (5) is controlled to convert the data into parallel data.
Therefore, the SPI control unit 204d (1) reads data that has been shifted (delayed) by one clock as read data, and cannot read accurate data. That is, an error occurs in the read data reading process.

As described above, when the operation control unit 301 is configured by a microcomputer, a processing delay occurs.
Therefore, the SPI master device according to the embodiment of the present invention controls the clock signal CLK used for synchronization control of the SPI master device 204d according to the processing delay caused by configuring the SPI slave device with a microcomputer. To solve this problem.
Hereinafter, an SPI master device according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 8 is a block diagram of an image forming apparatus having an SPI master device according to an embodiment of the present invention.
The image forming apparatus 100 is the same as that illustrated in FIG. 1 except that the operation control unit 301 (FIG. 3) of the operation unit 30 is configured by a microcomputer.
That is, the image forming apparatus 100 includes a switch 10, a PSU 14, a plotter unit 12, a scanner unit 16, a controller 20, and an operation unit 30.
In addition, the controller 20 and the operation unit 30 are connected by SPI, and the signal lines constituting the SPI are four signal lines (the signal lines of the chip select signal CS, the clock signal CLK, the data output signal SO, and the data input signal SI). ).

FIG. 9 is a block diagram of the controller 20 including the SPI master device according to the embodiment of the present invention.
The controller 20 includes a clock generation unit 201, a CPU 202, a ROM 203, an ASIC 204, a DDR SDRAM 205, a PHY 206, and a PHY clock generation unit 207, as shown in FIG.
With respect to each part constituting the controller 20, functions other than the SPI master device 204D of the ASIC 204 have the same functions as those shown in FIG.
Here, the SPI device is described as the SPI master device 204D. The SPI master device 204D will be described later with reference to FIGS.

FIG. 10 is a block diagram of the operation unit 30A.
As illustrated in FIG. 10, the operation unit 30A includes an operation control unit 301A, a key 302a, an LCD driver 303b, an LCD 303a, and an LED 304a.
Here, the operation control unit 301A is configured by a microcomputer as described above.
Not only the SPI device 301A (1) and the command control unit 301A (2) but also the key control unit 301A (3), the LCD control unit 301A (4), and the LED control unit 301A (5) are configured by a microcomputer.
Also here, as in the case shown in FIG. 3, the SPI device will be described as SPI slave device 301A (1).

FIG. 11 is a block diagram of the SPI master device 204D of the controller 20.
The SPI master device 204D includes an SPI control unit 204D (1), a CS generation unit 204D (2), a CLK generation unit 204D (3), a parallel / serial conversion unit 204D (4), a serial / parallel conversion unit 204D (5), It has a CLK stop control unit 204D (6).
Each block constituting the SPI master device 204D other than the CLK stop control unit 204D (6) has the same function as that shown in FIG.

The CLK stop control unit 204D (6) has a delay register that stores (sets) a delay amount of processing in the microcomputer.
The CLK stop control unit 204D (6) stops (invalidates) the clock CLK at a predetermined timing in the data reading operation according to the delay amount stored in the delay register (corresponding to a preset period in the present invention). To control.

FIG. 12 is a timing chart at the time of reading the read data transferred from the SPI slave device 301a in the SPI master device 204D.
FIG. 12 shows a case where the transfer of the read data from the SPI slave device 204D is delayed by two clock periods as compared with the case where the operation control unit 301A is configured by the ASIC 204.
That is, FIG. 12 shows a case where the delay amount related to data transfer from the SPI slave device 301a is known.

In starting communication with the SPI slave device 301a, first, the SPI control unit 204D (1) of the SPI master device 204D controls the chip select signal CS from the High level to the Low level, and then the CLK generation unit 204D ( 3) controls to output the clock signal CLK.
The SPI control unit 204D (1) transfers the read command signal (8 bits) and the address signal (8 bits) to the SPI slave device 301a as the data output signal SO in synchronization with the falling edge of the clock signal.

When the command transmitted from the CPU 202 is interpreted as a read command, the SPI control unit 204D (1) uses a preset period, that is, a delay amount (a delay amount corresponding to a period of two clock cycles) as the falling edge of the seventh clock. At the timing, it is set in the delay register of the CLK stop control unit 204D (6).
When the SPI control unit 204D (1) completes the output of the address signal as the data output signal SO, in this case, the CLK stop control unit 204D (6) corresponding to the transmission preparation determination unit of the present invention delays the delay register. Since the amount is set, it is determined that the preparation of the data line (SI signal transfer line) connected from the SPI slave device 301A (1) to the serial / parallel converter 204D (5) is not completed. When the CLK stop control unit 204D (6) determines that the preparation of the data line is not completed, that is, it is not completed, the control is performed so that the clock signal is stopped (fixed to High) from the point A in FIG. At that time (A in FIG. 12), the countdown of the delay amount (for two clock periods) of the delay register of the CLK stop control unit 204D (6) is started.

When the delay register countdown ends, that is, when two clocks have elapsed (B in FIG. 12), the CLK stop control unit 204D (6) determines that the preparation of the data line is completed, and the clock signal CLK Release the stop.
When the stop of the clock signal CLK is released, the clock signal CLK changes from High to Low as shown in FIG. 12, and the SPI slave device 301A (1) transfers the read data to the SPI master device 204D.

When the clock signal CLK is supplied from the clock generation unit 201 along with the cancellation of the stop of the clock signal CLK, the SPI control unit 204D (1) controls the serial / parallel conversion unit 204D (5) to set the 16th clock signal CLK. Serial data is converted into parallel data from the rising edge of the clock.
When the SPI control unit 204D (1) recognizes the last data at the rising edge of the 23rd clock of the clock signal CLK, it transfers the read data converted into parallel data to the CPU 202 via the SPI bus.

As shown in FIG. 12, the SPI control unit 204D (1) controls the clock signal CLK to High level after the 23rd clock rise of the clock signal CLK.
Further, when the SPI control unit 204D (1) controls the clock signal to the high level, the chip select signal CS is also controlled to the high level.

As described above, when the processing delay amount in the microcomputer is known, the delay amount is set in the register, and the clock signal CLK is controlled to stop according to the delay amount, so that the SPI master device 204D It is possible to avoid errors when reading data.
As described above, if the delay amount is converted into the clock cycle and set in the delay register of the SPI master device 204D, an error at the time of reading data in the SPI master device 204D can be avoided.
In FIG. 12, the processing related to data reading has been described. However, the processing related to data writing is the same as that shown in FIG. 5. At the time of data writing, the CLK stop control unit 204D (6) performs clock operation. Stop control is not executed.

Next, with reference to FIG. 13 and FIG. 14, a description will be given of clock control for error avoidance when the processing delay amount in the microcomputer is not known (when it is unknown or when it fluctuates).
FIG. 13 is a block diagram of an SPI master device 204D according to another embodiment of the present invention.
The SPI master device 204D includes an SPI control unit 204D (1), a CS generation unit 204D (2), a CLK generation unit 204D (3), a parallel / serial conversion unit 204D (4), a serial / parallel conversion unit 204D (5), A CLK stop control unit 204D (6a) is included.
Each block constituting the SPI master device 204D other than the CLK stop control unit 204D (6a) has the same function as that shown in FIG.

Further, as shown in FIG. 13, the data input signal SI is input not only to the serial / parallel converter 204D (5) but also to the CLK stop controller 204D (6a).
That is, the CLK stop control unit 204D (6a) uses the data input signal SI as a ready signal for determining whether the transfer preparation of the SPI slave device 301A (1) is completed, and the ready signal level (High or CLK is controlled according to (Low).
Hereinafter, the control in the CLK stop control unit 204D (6a) will be described with reference to the timing chart of FIG.

FIG. 14 is a timing chart at the time of reading data in the SPI master device 204D according to another embodiment of the present invention.
The SPI control unit 204D (1) controls the chip select signal CS from the high level to the low level in order to transfer read command data and the like to the SPI slave device 301A (1), similar to that shown in FIG. Further, a clock signal CLK is output.
Next, the SPI control unit 204D (1) transfers the read command signal (8 bits) as the data output signal SO to the SPI slave device 301A (1) in synchronization with the falling edge of the clock signal CLK.
When the SPI slave device 301A (1) receives the read command signal (that is, at the rising edge of the seventh clock of the clock signal CLK in FIG. 14), the SPI slave device 301A (1) recognizes that the read data cannot be transferred. The data input signal SI transferred to the SPI master device 204D is controlled from Low to High at the falling edge of the clock.

The SPI control unit 204D (1) transfers the address signal (8 bits) as a data output signal to the SPI slave device 301A (1) following the read command signal (8 bits).
The CLK stop control unit 204D (6a) monitors the level of the data input signal SI, and confirms that the level of the data input signal SI is High at the rising edge of the 15th clock, and sets the clock signal CLK to High level. Stop control.
The CLK stop control unit 204D (6a) monitors the data input signal SI using the internal clock signal iCLK even after the stop control of the clock signal to High.

Then, the SPI slave device 301A (1) controls the data input signal SI input to the SPI master device 204D from High to Low when read data transfer preparation is completed.
When the CLK stop control unit 204D (6a) confirms that the data input signal has transitioned from High to Low, the CLK stop control unit 204D (6a) cancels the stop control of the clock signal CLK (ie, enables the clock).
The SPI slave device 301A (1) transfers the read data to the SPI master device 204D simultaneously with the fall of the 15th clock.

The SPI control unit 204D (1) reads the read data transferred from the SPI slave device 301A (1) from the rising edge of the 16th clock.
The processing after the 16th clock is the same as that shown in FIG.

  As described above, according to the present embodiment, the SPI control unit 204D (1) stops the clock operation until the CLK slave control unit 204D (6a) completes the transfer preparation in the SPI slave device 301A (1). Control to do. Therefore, even when the delay amount related to the data transfer from the SPI slave device 301A (1) is unknown or fluctuates, an error at the time of reading data in the SPI master device 204D can be avoided.

Next, a case in which additional information such as address information is not ready to be transferred during data reading processing, and data is not transferred from the SPI master device 204D to the SPI slave device 301A (1) will be described with reference to FIG. .
In this case, the SPI control unit 204D (1) transfers the data input signal by the CLK stop control unit 204D (6a) when transferring the last bit of the read command signal (that is, at the rising edge of the seventh clock of the clock signal CLK). SI is monitored and it is confirmed whether transfer preparation is completed in the SPI slave device 301A (1) (that is, whether or not the data input signal SI is Low).

In the example shown in FIG. 15, the additional data such as address information is not ready for transfer even after the rising edge of the seventh clock, so the data input signal SI is High. Therefore, the CLK stop control unit 204D (6a) controls to stop the clock signal CLK to High.
After that, the CLK stop control unit 204D (6a) cancels the stop control of the clock signal CLK when it is confirmed by the internal clock signal iCLK that data transfer is ready and the data input signal SI has transitioned from High to Low. To do.
The SPI control unit 204D (1) reads the read data from the rising edge of the eighth clock.

  5, 6, 7, 12, 14, and 15, the command signal, the address signal, and the data signal (that is, write data and read data) to be transferred as data output signals are all 8 bits. Although it is configured with a length, a length other than the 8-bit length can be similarly handled (processed).

As described above, in the SPI communication system that performs data transfer between the SPI master device and the SPI slave device according to the embodiment of the present invention, when the data transfer from the SPI slave device is delayed, the SPI master device side Thus, with a simple configuration for monitoring input data indicating completion of data transfer preparation from the SPI slave device, it is possible to prevent a signal reading error due to a delay in data transfer.
Therefore, for example, when the SPI slave device is composed of an ASIC manufactured by an old process, there is a problem of delay in data transfer from the SPI slave device to the SPI master device, which is expected when the SPI slave device is replaced with a microcomputer. Can be eliminated.

  204D ... SPI master device, 204D (1) ... SPI control unit, 204D (2) ... CS generation unit, 204D (3) ... CLK generation unit, 204D (4) ... parallel / serial conversion unit, 204D (5) ... serial Parallel conversion unit, 204D (6)... CLK stop control unit.

Claims (8)

A master device that performs serial data communication with a slave device based on a clock,
Transmission preparation determination means for determining whether the slave device is ready for a data line for data transmission corresponding to a command from the master device;
A clock stop control means for stopping the clock when the transmission preparation determination means determines that the preparation of the data line is incomplete, and restarting the supply of the clock when it is determined that the preparation of the data line is complete;
A master device for performing synchronous serial data communication. The master device according to claim 1,
The transmission preparation determination means determines whether a preset period has elapsed after the clock is stopped,
The master device for performing synchronous serial data communication, wherein the clock stop control means restarts the supply of the clock when the transmission preparation determination means determines that the set period has elapsed. The master device according to claim 1,
The clock stop control means, on condition that the transfer of the data including the command from the master device to the slave device is completed and the transmission preparation determination means determines that the data line preparation of the slave device is incomplete. A master device for performing synchronous serial data communication, wherein the clock signal is stopped and the clock line is released and the clock supply is resumed on the condition that it is determined that the preparation of the data line of the slave device is completed . The master device according to claim 3,
The transmission preparation determining means determines whether the preparation of the data line is completed or not based on a signal indicating completion or uncompleted preparation of the data line transferred from the slave device. Master device for serial data communication. The master device according to claim 4, wherein
A master device for performing synchronous serial data communication, wherein a signal indicating completion or incomplete of preparation of the data line is a data input signal of the master device transferred on the data line. The master device according to any one of claims 3 to 5,
The transmission preparation determination means determines whether the preparation of the data line from the slave device is complete or incomplete at the transfer timing of the last bit of the data transfer request composed of a plurality of bits from the master device to the slave device. A master device for performing synchronous serial data communication characterized by determining. The master device according to any one of claims 1 to 6,
A master device for performing synchronous serial data communication, wherein the command for clock synchronous serial data communication is a command for the master device to read data from a slave device.   An electric apparatus comprising the master device and the slave device that perform synchronous serial data communication according to any one of claims 1 to 7.

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