JP2016187024A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which enables a stable operation in high-frequency operation and has favorable high-frequency properties.SOLUTION: A semiconductor device has: a buffer layer 21 provided on a substrate 10; a semiconductor layer which is provided on the buffer layer 21 and includes a co-doped region 22 and a high-resistance region 23; a carrier transit layer 31 provided on the semiconductor layer; a carrier supply layer 32 provided on the carrier transit layer 31; and a gate electrode 41, a source electrode 42 and a drain electrode 43 which are provided on the carrier supply layer 32. The co-doped region 22 is formed in a region between the gate electrode 41 and drain electrode 43 in plan view, and Si and at least one impurity element selected from Fe and C are doped. The high-resistance region 23 is formed in a region just below the gate electrode 41 and either of Fe of C is doped as an impurity element.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN that is a nitride semiconductor is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, a nitride semiconductor such as GaN is extremely promising as a material for a semiconductor device for power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), an HEMT made of AlGaN / GaN using GaN as an electron transit layer and AlGaN as an electron supply layer has attracted attention. In the HEMT composed of AlGaN / GaN, strain caused by the difference in lattice constant between GaN and AlGaN occurs in AlGaN. High-density 2DEG (Two-Dimensional Electron Gas) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization difference of AlGaN. Therefore, it is expected as a high-efficiency power device for high-efficiency switching elements, electric vehicles and the like.

JP 2002-359256 A JP 2010-232503 A

  In the semiconductor device using the nitride semiconductor described above, there is a demand for a semiconductor device with good high frequency characteristics capable of stable operation during high frequency operation.

  According to one aspect of the present embodiment, a nitride semiconductor buffer layer provided above a substrate, and a nitride semiconductor including a co-doped region and a high resistance region provided above the buffer layer. A nitride semiconductor layer, a nitride semiconductor carrier travel layer provided above the nitride semiconductor layer, a nitride semiconductor carrier supply layer provided above the carrier travel layer, and the carrier supply A gate electrode, a source electrode, and a drain electrode provided above the layer, and the co-doped region is formed in a region between the gate electrode and the drain electrode in a plan view, and Fe and At least one impurity element selected from C and Si are doped, and the high resistance region is formed in a region immediately below the gate electrode, and the impurity element and Fe, one of C is characterized in that it is doped with Te.

  According to the disclosed semiconductor device, high frequency characteristics can be improved in a semiconductor device using a nitride semiconductor.

Structural diagram of a semiconductor device with a high resistance layer Explanatory diagram of characteristics of semiconductor device shown in FIG. 1 (1) Explanatory diagram of characteristics of the semiconductor device shown in FIG. 1 (2) Structure diagram of the semiconductor device in the first embodiment Explanatory drawing (1) of the characteristic of the semiconductor device in 1st Embodiment Explanatory drawing (2) of the characteristic of the semiconductor device in 1st Embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Structure diagram of semiconductor device according to second embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Structure diagram of semiconductor device according to third embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (3) Structure diagram of semiconductor device according to fourth embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 4th Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 4th Embodiment Process drawing of the manufacturing method of the semiconductor device in 4th Embodiment (3) Explanatory diagram of a discretely packaged semiconductor device according to the fifth embodiment Circuit diagram of power supply device according to fifth embodiment Structure diagram of high-power amplifier according to fifth embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
First, a field effect transistor using a nitride semiconductor as a semiconductor device using a nitride semiconductor will be described with reference to FIG. This field effect transistor has a structure in which a high resistance layer is provided between the buffer layer and the electron transit layer in order to suppress a leakage current in the buffer layer. As shown in FIG. 1, the field effect transistor includes a nucleation layer (not shown), a buffer layer 921, a high resistance layer 922, an electron transit layer 931, an electron supply layer 932, and a cap layer 933 on a substrate 910. Are sequentially stacked. A gate electrode 941 is formed on the cap layer 933, a source electrode 942 and a drain electrode 943 are formed on the electron supply layer 932, and the surface of the cap layer 933 is exposed. Is covered with a protective film 950.

  In the field effect transistor that is the semiconductor device shown in FIG. 1, the substrate 910 is a SiC substrate, and the nucleation layer (not shown) is made of AlN or the like. The buffer layer 921 is made of AlGaN or the like, and the high resistance layer 922 is made of GaN doped with Fe to increase the resistance. The electron transit layer 931 is made of GaN, the electron supply layer 932 is made of AlGaN, and the cap layer 933 is made of GaN. As a result, 2DEG 931 a is generated in the electron transit layer 931 in the vicinity of the interface between the electron transit layer 931 and the electron supply layer 932. The protective film 950 is made of SiN or the like.

  In the field effect transistor shown in FIG. 1, by providing a high resistance layer 922 made of GaN doped with Fe between the buffer layer 921 and the electron transit layer 931, a leakage current flowing through the buffer layer 921 is obtained. Can be suppressed. However, since Fe-doped GaN forming the high-resistance layer 922 has many levels, when a voltage is applied between the source and the drain, electrons are trapped in the level and high frequency characteristics are obtained. Will fall.

For example, consider the case where a pulse voltage as shown in FIG. 2A is applied to the field effect transistor shown in FIG. Specifically, after applying a gate voltage (Vg) for turning off and a voltage pulse (PH state) of a drain voltage (Vd) of 150 V, a gate voltage at which the drain current (Id) becomes Idsq is set to 50 V Let us consider a case where the drain voltage is lowered (PL state). In this case, after applying a voltage pulse, a drain current of Idsq (for example, 20 mA / mm ² ) flows, but as shown in FIG. 2B, the drain current of Idsq is applied by applying a voltage pulse. After ending, it starts flowing with a delay. If the delay time when such a drain current starts to flow is long, the high frequency characteristics deteriorate. The reason why the time when the drain current begins to flow is delayed is that when a high drain voltage is applied to the semiconductor device shown in FIG. 1, electrons are trapped in the high resistance layer 922 in which Fe is doped in GaN. However, even if the drain voltage is lowered, trapped electrons are not immediately emitted from the high resistance layer 922, and it takes time for the electrons to be emitted. For this reason, it is assumed that a sufficient drain current does not flow while electrons are trapped in the high resistance layer 922.

  FIG. 3 shows an IV characteristic by DC measurement obtained by applying a DC voltage to the semiconductor device and an IV characteristic by pulse application measurement obtained by applying a predetermined voltage pulse. As a result, even with the same drain voltage, the drain current is lower in the pulse application measurement than in the DC measurement, and the on-resistance is increased. Since pulse application measurement corresponds to the case where the semiconductor device is operated at a high frequency, FIG. 3 means that the on-resistance is increased when the semiconductor device is operated at a high frequency. This is because electrons trapped in the high resistance layer 922 are not immediately emitted from the high resistance layer 922 even if the drain voltage is lowered, and it takes time to be emitted. In this pulse application measurement, after applying a pulse of a gate voltage (Vg) for turning off and a drain voltage (Vd) of 150 V, the pulse voltage is returned to a predetermined gate voltage, and whenever a voltage pulse is applied, The measurement was performed by gradually increasing the drain voltage.

  Therefore, a semiconductor device using a nitride semiconductor is required to have a high frequency characteristic.

(Semiconductor device)
Next, the semiconductor device in this embodiment will be described. As shown in FIG. 4, the semiconductor device in the present embodiment is formed by sequentially stacking a nucleation layer (not shown) and a buffer layer 21 on a substrate 10. On the buffer layer 21, a co-doped region 22 is formed between a gate electrode 41 and a drain electrode 43, which will be described later, and between the gate electrode 41 and the source electrode 42 immediately below and between the gate electrode 41 and the source electrode 42. A high resistance region 23 is formed. The co-doped region 22 and the high resistance region 23 formed on the buffer layer 21 are formed with the same thickness. On the co-doped region 22 and the high resistance region 23, an electron transit layer 31 and an electron supply layer 32 are formed. The cap layer 33 is formed by laminating in order. A gate electrode 41 is formed on the cap layer 33, and a source electrode 42 and a drain electrode 43 are formed on the electron supply layer 32. The region where the surface of the cap layer 33 is exposed is covered with the protective film 50.

  In the present embodiment, a SiC substrate is used as the substrate 10, and a nucleation layer (not shown) is formed of an AlN film having a thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 21 is formed of an AlGaN film having a thickness of 1 nm to 1000 nm, for example, 600 nm. The co-doped region 22 and the high-resistance region 23 are formed with the same film thickness. The co-doped region 22 is doped with both Fe and Si as impurity elements in GaN, and the high-resistance region 23 has impurities in GaN. Only Fe is doped as an element.

In the present embodiment, the concentration of the impurity element in the co-doped region 22 is doped so that Si is higher than Fe. Specifically, the concentration of Fe doped in the co-doped region 22 is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁷ cm ⁻³ . . Further, the concentration of Si doped in the co-doped region 22 is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, for example, 5 × 10 ¹⁸ cm ⁻³ . Further, the high resistance region 23 is doped with Fe having the same concentration as that of Fe doped in the co-doped region 22. As an impurity element doped in the co-doped region 22 and the high resistance region 23, C or the like may be used instead of Fe.

The electron transit layer 31 is formed of an i-GaN film having a thickness of 3 μm, the electron supply layer 32 is formed of an AlGaN film having a thickness of 30 nm, and the cap layer 33 is formed of a film having a thickness of 5 nm. It is made of GaN. The electron supply layer 32 may be formed of an n-AlGaN film. In this case, Si is doped as an impurity element at a concentration of 5 × 10 ¹⁸ cm ⁻³ . Further, an i-AlGaN film having a thickness of 5 nm may be formed as a spacer layer (not shown) between the electron transit layer 31 and the electron supply layer 32. As a result, 2DEG 31 a is generated in the electron transit layer 31 in the vicinity of the interface between the electron transit layer 31 and the electron supply layer 32. The protective film 50 is formed of SiN having a film thickness of 10 nm or more and 700 nm or less.

  In the present embodiment, the co-doped region 22 is formed in the region between the gate electrode 41 and the drain electrode 43 between the buffer layer 21 and the electron transit layer 31. In the co-doped region 22, since GaN is doped with Si, even if Fe is doped, trapped electrons are emitted in a short time, and high-frequency characteristics can be improved. Further, since the high resistance region 23 is formed between the buffer layer 21 and the electron transit layer 31, immediately below the gate electrode 41 and between the gate electrode 41 and the source electrode 42, the buffer layer 21. It is possible to suppress the occurrence of leakage current in Therefore, in the semiconductor device in the present embodiment, it is possible to suppress the occurrence of leakage current in the buffer layer 21 and to improve the high frequency characteristics.

  FIG. 5 shows the result of measuring the delay time for the semiconductor device shown in FIG. 1 and the semiconductor device in the present embodiment shown in FIG. 4 by the same method as shown in FIG. 5A is the characteristic in the semiconductor device shown in FIG. 1, which is the same as that shown in FIG. 2B, and 5B is the characteristic of the semiconductor device in the present embodiment shown in FIG. . As shown in FIG. 5, the semiconductor device in this embodiment can have a shorter delay time than the semiconductor device shown in FIG. 1, and can improve high-frequency characteristics.

  FIG. 6 shows the results of pulse application measurement on the semiconductor device shown in FIG. 1 and the semiconductor device in the present embodiment shown in FIG. 6A is the result of pulse application measurement of the semiconductor device shown in FIG. 1, which is the same as that shown in FIG. 3, and 6B is the result of pulse application measurement of the semiconductor device in the present embodiment shown in FIG. It is. As shown in FIG. 6, in the pulse application measurement, the semiconductor device in this embodiment can have a higher drain current than the semiconductor device shown in FIG. Can be lowered. Thereby, a high frequency characteristic can be improved.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS. The nitride semiconductor formed on the substrate 10 is formed by epitaxial growth by MOVPE (Metal-Organic Vapor Phase Epitaxy). When growing a nitride semiconductor by MOVPE, TMA (trimethylaluminum) is used as the Al source gas, TMG (trimethylgallium) is used as the Ga source gas, and NH ₃ is used as the N source gas. (Ammonia) is used. When doping Fe, cyclopentanedienyl iron (CP2Fe) is supplied as a source gas.

First, as shown in FIG. 7A, a nucleation layer (not shown), a buffer layer 21, and a high resistance film 23a are sequentially formed on the substrate 10 by MOVPE. In the present embodiment, a SiC substrate is used as the substrate 10, and a nucleation layer (not shown) is formed of an AlN film having a thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 21 is formed of an AlGaN film having a thickness of 1 nm to 1000 nm, for example, 600 nm. The high resistance film 23a is a film in which Fe is doped as an impurity element in GaN, and the concentration of Fe doped as an impurity element is, for example, 1 × 10 ¹⁷ cm ⁻³ .

  Next, as shown in FIG. 7B, a resist pattern 61 having an opening 61a in the region where the co-doped region 22 is formed is formed on the high resistance film 23a. Specifically, a photoresist is applied on the high resistance film 23a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern 61 having an opening 61a in a region where the co-doped region 22 is formed.

Next, as shown in FIG. 7C, a co-doped region 22 is formed by ion implantation of Si into the high resistance film 23a in the region where the resist pattern 61 is not formed. The concentration of Si ion-implanted into the co-doped region 22 is, for example, 5 × 10 ¹⁸ cm ⁻³ . Thereby, in the high resistance film 23a, the co-doped region 22 is formed in the region where the Si ions are implanted, the resist pattern 61 is formed, and the region where the Si ions are not implanted is the high resistance region 23. Become.

Next, as illustrated in FIG. 8A, the electron transit layer 31, the electron supply layer 32, and the cap layer 33 are sequentially stacked on the co-doped region 22 and the high resistance region 23. The electron transit layer 31 is formed of an i-GaN film having a thickness of about 3.0 μm. The electron supply layer 32 is formed of n-AlGaN having a film thickness of about 30 nm, and Si is doped so as to have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ as an n-type impurity element. The cap layer 33 is made of GaN having a thickness of about 5 nm. Note that an i-AlGaN film having a thickness of 5 nm may be formed as a spacer layer (not shown) between the electron transit layer 31 and the electron supply layer 32. As a result, 2DEG 31 a is generated in the electron transit layer 31 in the vicinity of the interface between the electron transit layer 31 and the electron supply layer 32. Thereafter, in order to activate Si doped as an impurity element, heat treatment is performed at a temperature of 800 ° C. to 1100 ° C., for example, 900 ° C.

  Next, as illustrated in FIG. 8B, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 32. Specifically, a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the cap layer 33 and performing exposure and development with an exposure apparatus. Form. Thereafter, the cap layer 33 or the like in the region where the resist pattern is not formed is removed by RIE (Reactive Ion Etching) or the like, and further, the resist pattern (not shown) is removed by an organic solvent or the like. After that, again, a photoresist is applied on the cap layer 33 and the electron supply layer 32, and exposure and development are performed by an exposure apparatus so that an opening is formed in a region where the source electrode 42 and the drain electrode 43 are formed. A resist pattern (not shown) is formed. Thereafter, after a metal film containing Al is formed by vacuum deposition, the metal film on the resist pattern is removed together with the resist pattern by lift-off by being immersed in an organic solvent or the like. Thereby, the source electrode 42 and the drain electrode 43 are formed by the remaining metal film. Thereafter, a heat treatment is further performed at a temperature of 400 ° C. to 1000 ° C., for example, 550 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 42 and the drain electrode 43.

  Next, as shown in FIG. 8C, the gate electrode 41 is formed on the cap layer 33. Specifically, a photoresist is applied on the cap layer 33, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 41 is formed. Thereafter, a metal laminated film of Ni / Au is formed by vacuum vapor deposition, and then immersed in an organic solvent or the like to remove the metal laminated film on the resist pattern together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal laminated film.

  Next, as shown in FIG. 9, a protective film 50 is formed on the cap layer 33 where the gate electrode 41, the source electrode 42, and the drain electrode 43 are not formed. Specifically, it is formed by forming a SiN film having a film thickness of 10 nm or more and 700 nm or less by MOCVD (Metal Organic Chemical Vapor Deposition).

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

[Second Embodiment]
(Semiconductor device)
Next, a semiconductor device according to the second embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 10, a nucleation layer (not shown) and a buffer layer 21 are sequentially stacked on a substrate 10. On the buffer layer 21, a co-doped region 22 is formed between a gate electrode 41 and a drain electrode 43 described later, and a co-doped region 122 is formed between the gate electrode 41 and the source electrode 42. ing. A high resistance region 123 is formed immediately below the gate electrode 41. The co-doped regions 22 and 122 and the high-resistance region 123 formed on the buffer layer 21 are formed with the same thickness. On the co-doped regions 22 and 122 and the high-resistance region 123, the electron transit layer 31, An electron supply layer 32 and a cap layer 33 are stacked in order. A gate electrode 41 is formed on the cap layer 33, and a source electrode 42 and a drain electrode 43 are formed on the electron supply layer 32. The region where the surface of the cap layer 33 is exposed is covered with the protective film 50.

  In the present embodiment, the co-doped regions 22 and 122 are doped with both Fe and Si as impurity elements in GaN, and the high resistance region 123 is doped with only Fe as an impurity element in GaN.

The concentration of the impurity element in the co-doped regions 22 and 122 is doped so that Si is higher than Fe. Specifically, the concentration of Fe doped in the co-doped regions 22 and 122 is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁷ cm ^−3. It is. The concentration of Si doped in the co-doped regions 22 and 122 is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, for example, 5 × 10 ¹⁸ cm ⁻³ . The high resistance region 123 is doped with Fe having the same concentration as that of Fe doped in the co-doped regions 22 and 122. As the impurity element doped in the co-doped regions 22 and 122 and the high resistance region 123, C or the like may be used instead of Fe.

The electron transit layer 31 is formed of an i-GaN film having a thickness of 3 μm, the electron supply layer 32 is formed of an AlGaN film having a thickness of 30 nm, and the cap layer 33 is formed of a film having a thickness of 5 nm. It is made of GaN. The electron supply layer 32 may be formed of an n-AlGaN film. In this case, Si is doped as an impurity element at a concentration of 5 × 10 ¹⁸ cm ⁻³ . Further, an i-AlGaN film having a thickness of 5 nm may be formed as a spacer layer (not shown) between the electron transit layer 31 and the electron supply layer 32. As a result, 2DEG 31 a is generated in the electron transit layer 31 in the vicinity of the interface between the electron transit layer 31 and the electron supply layer 32. The protective film 50 is formed of SiN having a film thickness of 10 nm or more and 700 nm or less.

  In the present embodiment, the co-doped region 22 is formed in the region between the gate electrode 41 and the drain electrode 43 between the buffer layer 21 and the electron transit layer 31, and the gate electrode 41, the source electrode 42, A co-doped region 122 is formed in the region between. In the co-doped regions 22 and 122, since GaN is doped with Si, even when Fe is doped, trapped electrons are emitted in a short time, and the high-frequency characteristics are further improved as compared with the first embodiment. can do. In addition, since the high resistance region 123 is formed in the region immediately below the gate electrode 41 between the buffer layer 21 and the electron transit layer 31, it is possible to suppress the occurrence of leakage current in the buffer layer 21. . Therefore, in the semiconductor device in the present embodiment, it is possible to suppress the occurrence of leakage current in the buffer layer 21 and to improve the high frequency characteristics.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS. The nitride semiconductor formed on the substrate 10 is formed by epitaxial growth by MOVPE.

First, as shown in FIG. 11A, a nucleation layer (not shown), a buffer layer 21, and a high resistance film 23a are sequentially formed on the substrate 10 by MOVPE. In the present embodiment, a SiC substrate is used as the substrate 10, and a nucleation layer (not shown) is formed of an AlN film having a thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 21 is formed of an AlGaN film having a thickness of 1 nm to 1000 nm, for example, 600 nm. The high resistance film 23a is a film in which Fe is doped as an impurity element in GaN, and the concentration of Fe doped as an impurity element is, for example, 1 × 10 ¹⁷ cm ⁻³ .

  Next, as shown in FIG. 11B, a resist pattern 161 having openings 161a and 161b in the regions where the co-doped regions 22 and 122 are formed is formed on the high resistance film 23a. Specifically, a resist pattern 161 having openings 161a and 161b in regions where the co-doped regions 22 and 122 are formed by applying a photoresist on the high resistance film 23a and performing exposure and development by an exposure apparatus. Form.

Next, as shown in FIG. 11C, co-doped regions 22 and 122 are formed by ion implantation of Si into the high resistance film 23a in the region where the resist pattern 161 is not formed. The concentration of Si ion-implanted into the co-doped regions 22 and 122 is, for example, 5 × 10 ¹⁸ cm ⁻³ . Thus, in the high resistance film 23a, the co-doped regions 22 and 122 are formed in the region where the Si ions are implanted, the resist pattern 161 is formed, and the region where the Si ions are not implanted is the high resistance region. 123.

Next, as illustrated in FIG. 12A, the electron transit layer 31, the electron supply layer 32, and the cap layer 33 are sequentially stacked on the co-doped regions 22 and 122 and the high resistance region 123. The electron transit layer 31 is formed of an i-GaN film having a thickness of about 3.0 μm. The electron supply layer 32 is formed of n-AlGaN having a film thickness of about 30 nm, and Si is doped so as to have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ as an n-type impurity element. The cap layer 33 is made of GaN having a thickness of about 5 nm. Note that an i-AlGaN film having a thickness of 5 nm may be formed as a spacer layer (not shown) between the electron transit layer 31 and the electron supply layer 32. As a result, 2DEG 31 a is generated in the electron transit layer 31 in the vicinity of the interface between the electron transit layer 31 and the electron supply layer 32. Thereafter, in order to activate Si doped as an impurity element, heat treatment is performed at a temperature of 800 ° C. to 1100 ° C., for example, 900 ° C.

  Next, as shown in FIG. 12B, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 32. Specifically, a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the cap layer 33 and performing exposure and development with an exposure apparatus. Form. Thereafter, the cap layer 33 and the like in the region where the resist pattern is not formed are removed by RIE and the resist pattern (not shown) is removed by an organic solvent or the like. After that, again, a photoresist is applied on the cap layer 33 and the electron supply layer 32, and exposure and development are performed by an exposure apparatus so that an opening is formed in a region where the source electrode 42 and the drain electrode 43 are formed. A resist pattern (not shown) is formed. Thereafter, after a metal film containing Al is formed by vacuum deposition, the metal film on the resist pattern is removed together with the resist pattern by lift-off by being immersed in an organic solvent or the like. Thereby, the source electrode 42 and the drain electrode 43 are formed by the remaining metal film. Thereafter, a heat treatment is further performed at a temperature of 400 ° C. to 1000 ° C., for example, 550 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 42 and the drain electrode 43.

  Next, as shown in FIG. 12C, the gate electrode 41 is formed on the cap layer 33. Specifically, a photoresist is applied on the cap layer 33, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 41 is formed. Thereafter, a metal laminated film of Ni / Au is formed by vacuum vapor deposition, and then immersed in an organic solvent or the like to remove the metal laminated film on the resist pattern together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal laminated film.

  Next, as shown in FIG. 13, a protective film 50 is formed on the cap layer 33 in which the gate electrode 41, the source electrode 42, and the drain electrode 43 are not formed. Specifically, an SiN film having a thickness of 10 nm to 700 nm is formed by MOCVD.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

  The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
(Semiconductor device)
Next, a semiconductor device according to a third embodiment will be described. In the semiconductor device in this embodiment, the impurity element doped in the co-doped region and the high resistance region is doped with C instead of Fe. In the semiconductor device according to the present embodiment, as shown in FIG. 14, a nucleation layer (not shown) and a buffer layer 21 are sequentially stacked on a substrate 10. A co-doped region 222 is formed on the buffer layer 21 between a gate electrode 41 and a drain electrode 43, which will be described later. Between the gate electrode 41 and between the gate electrode 41 and the source electrode 42, A high resistance region 223 is formed. The co-doped region 222 and the high resistance region 223 formed on the buffer layer 21 are formed with the same thickness, and the electron transit layer 31 and the electron supply layer 32 are formed on the co-doped region 222 and the high resistance region 223. The cap layer 33 is formed by laminating in order. A gate electrode 41 is formed on the cap layer 33, and a source electrode 42 and a drain electrode 43 are formed on the electron supply layer 32. The region where the surface of the cap layer 33 is exposed is covered with the protective film 50.

  In the present embodiment, the co-doped region 222 is doped with both C and Si as impurity elements in GaN, and the high resistance region 223 is doped with only C as an impurity element in GaN.

The concentration of the impurity element in the co-doped region 222 is doped so that Si is higher than C. Specifically, the concentration of C doped in the co-doped region 222 is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁷ cm ⁻³ . . Further, the concentration of Si doped in the co-doped region 222 is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, for example, 5 × 10 ¹⁸ cm ⁻³ . The high resistance region 223 is doped with C having the same concentration as that of C doped in the co-doped region 222.

  In the present embodiment, a co-doped region 222 is formed in a region between the gate electrode 41 and the drain electrode 43 between the buffer layer 21 and the electron transit layer 31. In the co-doped region 222, since GaN is doped with Si, even if Fe is doped, trapped electrons are emitted in a short time, and high-frequency characteristics can be improved. In addition, since the high resistance region 223 is formed between the buffer layer 21 and the electron transit layer 31 immediately below the gate electrode 41 and between the gate electrode 41 and the source electrode 42, the buffer layer 21 It is possible to suppress the occurrence of leakage current in Therefore, in the semiconductor device in the present embodiment, it is possible to suppress the occurrence of leakage current in the buffer layer 21 and to improve the high frequency characteristics.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 15A, a nucleation layer (not shown), a buffer layer 21 and a high resistance film 223a are sequentially formed on the substrate 10 by MOVPE. In the present embodiment, a SiC substrate is used as the substrate 10, and a nucleation layer (not shown) is formed of an AlN film having a thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 21 is formed of an AlGaN film having a thickness of 1 nm to 1000 nm, for example, 600 nm. The high resistance film 223a is a film in which GaN is doped with C as an impurity element, and the concentration of C doped as the impurity element is, for example, 1 × 10 ¹⁷ cm ⁻³ .

  Next, as shown in FIG. 15B, a resist pattern 61 having an opening 61a in a region where the co-doped region 222 is formed is formed on the high resistance film 223a. Specifically, a photoresist is applied on the high resistance film 223a, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern 61 having an opening 61a in a region where the co-doped region 222 is formed.

Next, as shown in FIG. 15C, a co-doped region 222 is formed by ion implantation of Si into the high resistance film 223a in the region where the resist pattern 61 is not formed. The concentration of Si ion-implanted into the co-doped region 222 is, for example, 5 × 10 ¹⁸ cm ⁻³ . Thereby, in the high resistance film 223a, the co-doped region 222 is formed in the region where the Si ions are implanted, the resist pattern 61 is formed, and the region where the Si ions are not implanted is the high resistance region 223. Become.

Next, as shown in FIG. 16A, the electron transit layer 31, the electron supply layer 32, and the cap layer 33 are sequentially stacked on the co-doped region 222 and the high resistance region 223. The electron transit layer 31 is formed of an i-GaN film having a thickness of about 3.0 μm. The electron supply layer 32 is formed of n-AlGaN having a film thickness of about 30 nm, and Si is doped so as to have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ as an n-type impurity element. The cap layer 33 is made of GaN having a thickness of about 5 nm. Note that an i-AlGaN film having a thickness of 5 nm may be formed as a spacer layer (not shown) between the electron transit layer 31 and the electron supply layer 32. As a result, 2DEG 31 a is generated in the electron transit layer 31 in the vicinity of the interface between the electron transit layer 31 and the electron supply layer 32. Thereafter, in order to activate Si doped as an impurity element, heat treatment is performed at a temperature of 800 ° C. to 1100 ° C., for example, 900 ° C.

  Next, as illustrated in FIG. 16B, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 32. Specifically, a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the cap layer 33 and performing exposure and development with an exposure apparatus. Form. Thereafter, the cap layer 33 and the like in the region where the resist pattern is not formed are removed by RIE and the resist pattern (not shown) is removed by an organic solvent or the like. After that, again, a photoresist is applied on the cap layer 33 and the electron supply layer 32, and exposure and development are performed by an exposure apparatus so that an opening is formed in a region where the source electrode 42 and the drain electrode 43 are formed. A resist pattern (not shown) is formed. Thereafter, after a metal film containing Al is formed by vacuum deposition, the metal film on the resist pattern is removed together with the resist pattern by lift-off by being immersed in an organic solvent or the like. Thereby, the source electrode 42 and the drain electrode 43 are formed by the remaining metal film. Thereafter, a heat treatment is further performed at a temperature of 400 ° C. to 1000 ° C., for example, 550 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 42 and the drain electrode 43.

  Next, as illustrated in FIG. 16C, the gate electrode 41 is formed on the cap layer 33. Specifically, a photoresist is applied on the cap layer 33, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 41 is formed. Thereafter, a metal laminated film of Ni / Au is formed by vacuum vapor deposition, and then immersed in an organic solvent or the like to remove the metal laminated film on the resist pattern together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal laminated film.

  Next, as shown in FIG. 17, a protective film 50 is formed on the cap layer 33 where the gate electrode 41, the source electrode 42, and the drain electrode 43 are not formed. Specifically, an SiN film having a thickness of 10 nm to 700 nm is formed by MOCVD.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

  The contents other than the above are the same as in the first embodiment.

[Fourth Embodiment]
(Semiconductor device)
Next, a semiconductor device according to a fourth embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 18, a nucleation layer (not shown) and a buffer layer 21 are sequentially stacked on a substrate 10. On the buffer layer 21, a co-doped region 222 is formed between a gate electrode 41 and a drain electrode 43 described later, and a co-doped region 322 is formed between the gate electrode 41 and the source electrode 42. ing. A high resistance region 323 is formed immediately below the gate electrode 41. The co-doped regions 222 and 322 and the high resistance region 323 formed on the buffer layer 21 are formed to have the same thickness. On the co-doped regions 222 and 322 and the high resistance region 323, the electron transit layer 31, An electron supply layer 32 and a cap layer 33 are stacked in order. A gate electrode 41 is formed on the cap layer 33, and a source electrode 42 and a drain electrode 43 are formed on the electron supply layer 32. The region where the surface of the cap layer 33 is exposed is covered with the protective film 50.

  In the present embodiment, the co-doped regions 222 and 322 are doped with both C and Si as impurity elements in GaN, and the high resistance region 323 is doped with only C as an impurity element in GaN.

The concentration of the impurity element in the co-doped regions 222 and 322 is doped so that Si is higher than C. Specifically, the concentration of C doped in the co-doped regions 222 and 322 is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, for example, 1 × 10 ¹⁷ cm ^−3. It is. The concentration of Si doped in the co-doped regions 222 and 322 is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, for example, 5 × 10 ¹⁸ cm ⁻³ . The high resistance region 323 is doped with C having the same concentration as that of C doped in the co-doped regions 222 and 322.

  In the present embodiment, a co-doped region 222 is formed in a region between the gate electrode 41 and the drain electrode 43 between the buffer layer 21 and the electron transit layer 31, and the gate electrode 41, the source electrode 42, A co-doped region 322 is formed in the region between. In the co-doped regions 222 and 322, since GaN is doped with Si, even if Fe is doped, trapped electrons are emitted in a short time, and the high-frequency characteristics are further improved as compared with the third embodiment. can do. In addition, since the high resistance region 323 is formed in the region immediately below the gate electrode 41 between the buffer layer 21 and the electron transit layer 31, it is possible to suppress the occurrence of leakage current in the buffer layer 21. . Therefore, in the semiconductor device in the present embodiment, it is possible to suppress the occurrence of leakage current in the buffer layer 21 and to improve the high frequency characteristics.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS. The nitride semiconductor formed on the substrate 10 is formed by epitaxial growth by MOVPE.

First, as shown in FIG. 19A, a nucleation layer (not shown), a buffer layer 21, and a high resistance film 223a are sequentially formed on the substrate 10 by MOVPE. In the present embodiment, a SiC substrate is used as the substrate 10, and a nucleation layer (not shown) is formed of an AlN film having a thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 21 is formed of an AlGaN film having a thickness of 1 nm to 1000 nm, for example, 600 nm. The high resistance film 223a is a film in which GaN is doped with C as an impurity element, and the concentration of C doped as the impurity element is, for example, 1 × 10 ¹⁷ cm ⁻³ .

  Next, as shown in FIG. 19B, a resist pattern 161 having openings 161a and 161b is formed on the high resistance film 223a in the region where the co-doped regions 222 and 322 are to be formed. More specifically, a resist pattern 161 having openings 161a and 161b in regions where the co-doped regions 222 and 322 are formed by applying a photoresist on the high resistance film 223a and performing exposure and development by an exposure apparatus. Form.

Next, as shown in FIG. 19C, co-doped regions 222 and 322 are formed by ion implantation of Si into the high resistance film 223a in the region where the resist pattern 161 is not formed. The concentration of Si ion-implanted into the co-doped regions 222 and 322 is, for example, 5 × 10 ¹⁸ cm ⁻³ . Thus, in the high resistance film 223a, the co-doped regions 222 and 322 are formed in the region where the Si ions are implanted, the resist pattern 161 is formed, and the region where the Si ions are not implanted is the high resistance region. 323.

Next, as illustrated in FIG. 20A, the electron transit layer 31, the electron supply layer 32, and the cap layer 33 are sequentially stacked on the co-doped regions 222 and 322 and the high resistance region 323. The electron transit layer 31 is formed of an i-GaN film having a thickness of about 3.0 μm. The electron supply layer 32 is formed of n-AlGaN having a film thickness of about 30 nm, and Si is doped so as to have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ as an n-type impurity element. The cap layer 33 is made of GaN having a thickness of about 5 nm. Note that an i-AlGaN film having a thickness of 5 nm may be formed as a spacer layer (not shown) between the electron transit layer 31 and the electron supply layer 32. As a result, 2DEG 31 a is generated in the electron transit layer 31 in the vicinity of the interface between the electron transit layer 31 and the electron supply layer 32. Thereafter, in order to activate Si doped as an impurity element, heat treatment is performed at a temperature of 800 ° C. to 1100 ° C., for example, 900 ° C.

  Next, as illustrated in FIG. 20B, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 32. Specifically, a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the cap layer 33 and performing exposure and development with an exposure apparatus. Form. Thereafter, the cap layer 33 and the like in the region where the resist pattern is not formed are removed by RIE and the resist pattern (not shown) is removed by an organic solvent or the like. After that, again, a photoresist is applied on the cap layer 33 and the electron supply layer 32, and exposure and development are performed by an exposure apparatus so that an opening is formed in a region where the source electrode 42 and the drain electrode 43 are formed. A resist pattern (not shown) is formed. Thereafter, after a metal film containing Al is formed by vacuum deposition, the metal film on the resist pattern is removed together with the resist pattern by lift-off by being immersed in an organic solvent or the like. Thereby, the source electrode 42 and the drain electrode 43 are formed by the remaining metal film. Thereafter, a heat treatment is further performed at a temperature of 400 ° C. to 1000 ° C., for example, 550 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 42 and the drain electrode 43.

  Next, as shown in FIG. 20C, the gate electrode 41 is formed on the cap layer 33. Specifically, a photoresist is applied on the cap layer 33, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 41 is formed. Thereafter, a metal laminated film of Ni / Au is formed by vacuum vapor deposition, and then immersed in an organic solvent or the like to remove the metal laminated film on the resist pattern together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal laminated film.

  Next, as shown in FIG. 21, a protective film 50 is formed on the cap layer 33 on which the gate electrode 41, the source electrode 42, and the drain electrode 43 are not formed. Specifically, an SiN film having a thickness of 10 nm to 700 nm is formed by MOCVD.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

  The contents other than the above are the same as those in the second embodiment.

[Fifth Embodiment]
Next, a fifth embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-frequency amplifier.

  The semiconductor device in the present embodiment is a discrete package of any of the semiconductor devices in the first to fourth embodiments. The semiconductor device thus discretely packaged will be described with reference to FIG. FIG. 22 schematically shows the inside of a discretely packaged semiconductor device. The arrangement of electrodes and the like are different from those shown in the first to fourth embodiments. Yes.

  First, the semiconductor device manufactured in the first to fourth embodiments is cut by dicing or the like to form a HEMT semiconductor chip 410 made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die attach agent 430 such as solder. The semiconductor chip 410 corresponds to the semiconductor device in the first to fourth embodiments.

  Next, the gate electrode 411 is connected to the gate lead 421 by a bonding wire 431, the source electrode 412 is connected to the source lead 422 by a bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by a bonding wire 433. The bonding wires 431, 432, and 433 are made of a metal material such as Al. In the present embodiment, the gate electrode 411 is a gate electrode pad, and is connected to the gate electrode 41 of the semiconductor device according to the first to fourth embodiments. The source electrode 412 is a source electrode pad, and is connected to the source electrode 42 of the semiconductor device according to the first to fourth embodiments. The drain electrode 413 is a drain electrode pad, and is connected to the drain electrode 43 of the semiconductor device according to the first to fourth embodiments.

  Next, resin sealing with a mold resin 440 is performed by a transfer molding method. In this way, a HEMT discrete packaged semiconductor device using a GaN-based semiconductor material can be manufactured.

  Next, a power supply device and a high frequency amplifier in the present embodiment will be described. The power supply device and the high-frequency amplifier in the present embodiment are a power supply device and a high-frequency amplifier using any one of the semiconductor devices in the first to fourth embodiments.

  First, the power supply device according to the present embodiment will be described with reference to FIG. The power supply device 460 in this embodiment includes a high-voltage primary circuit 461, a low-voltage secondary circuit 462, and a transformer 463 disposed between the primary circuit 461 and the secondary circuit 462. The primary circuit 461 includes an AC power supply 464, a so-called bridge rectifier circuit 465, a plurality of switching elements (four in the example shown in FIG. 23) 466, a switching element 467, and the like. The secondary side circuit 462 includes a plurality of switching elements (three in the example shown in FIG. 23) 468. In the example shown in FIG. 23, the semiconductor device according to the first to fourth embodiments is used as the switching elements 466 and 467 of the primary circuit 461. Note that the switching elements 466 and 467 of the primary circuit 461 are preferably normally-off semiconductor devices. The switching element 468 used in the secondary circuit 462 uses a normal MISFET (metal insulator semiconductor field effect transistor) formed of silicon.

  Next, based on FIG. 24, the high frequency amplifier in this Embodiment is demonstrated. The high frequency amplifier 470 in the present embodiment may be applied to, for example, a power amplifier for a base station of a mobile phone. The high frequency amplifier 470 includes a digital predistortion circuit 471, a mixer 472, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixer 472 mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the example shown in FIG. 24, the power amplifier 473 includes any one of the semiconductor devices in the first to fourth embodiments. The directional coupler 474 performs monitoring of input signals and output signals. In the circuit shown in FIG. 24, for example, the output signal can be mixed with the AC signal by the mixer 472 and sent to the digital predistortion circuit 471 by switching the switch.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A nitride semiconductor buffer layer provided above the substrate;
A nitride semiconductor layer including a co-doped region and a high-resistance region provided above the buffer layer;
A nitride semiconductor carrier travel layer provided above the nitride semiconductor layer;
A nitride semiconductor carrier supply layer provided above the carrier travel layer;
A gate electrode, a source electrode, and a drain electrode provided above the carrier supply layer;
Have
The co-doped region is formed in a region between the gate electrode and the drain electrode in a plan view, and is doped with at least one impurity element selected from Fe and C and Si. And
The high resistance region is formed in a region immediately below the gate electrode, and is doped with either Fe or C as an impurity element.
(Appendix 2)
The semiconductor device according to appendix 1, wherein the high resistance region is also formed in a region between the gate electrode and the source electrode in plan view.
(Appendix 3)
The semiconductor device according to appendix 1, wherein the co-doped region is also formed in a region between the gate electrode and the source electrode in plan view.
(Appendix 4)
4. The semiconductor device according to any one of appendices 1 to 3, wherein in the co-doped region, the concentration of Si is higher than any one of Fe and C.
(Appendix 5)
The concentration of any one of the Fe and C doped in the co-doped region is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, and the concentration of Si is 1 × The semiconductor device according to any one of appendices 1 to 4, wherein the semiconductor device is 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.
(Appendix 6)
The supplementary note 5, wherein the concentration of any one of the Fe and C doped in the high resistance region is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. Semiconductor device.
(Appendix 7)
The semiconductor device according to any one of appendices 1 to 6, wherein the co-doped region and the high-resistance region are formed of a material containing GaN.
(Appendix 8)
The carrier traveling layer is formed of a material containing GaN,
The semiconductor device according to any one of appendices 1 to 7, wherein the carrier supply layer is formed of a material containing AlGaN.
(Appendix 9)
Forming a buffer layer above the substrate;
Forming a nitride semiconductor layer of a nitride semiconductor doped with at least one impurity element selected from Fe and C above the buffer layer;
Si is ion-implanted into a part of the nitride semiconductor layer to form a co-doped region in which the Si is ion-implanted and a high resistance region in which the Si is not doped in the nitride semiconductor layer,
Forming a nitride semiconductor carrier travel layer above the nitride semiconductor layer;
Forming a nitride semiconductor carrier supply layer above the carrier travel layer,
Forming a gate electrode, a source electrode, and a drain electrode above the carrier supply layer;
The co-doped region is formed in a region between the gate electrode and the drain electrode in plan view,
The method of manufacturing a semiconductor device, wherein the high resistance region is formed in a region immediately below the gate electrode.
(Appendix 10)
The method for manufacturing a semiconductor device according to appendix 9, wherein the high resistance region is also formed in a region between the gate electrode and the source electrode in plan view.
(Appendix 11)
The method for manufacturing a semiconductor device according to appendix 9, wherein the co-doped region is also formed in a region between the gate electrode and the source electrode in plan view.
(Appendix 12)
12. The method for manufacturing a semiconductor device according to any one of appendices 9 to 11, wherein the concentration of Si in the co-doped region is higher than the concentration of any one of Fe and C.
(Appendix 13)
The concentration of any one of the Fe and C doped in the co-doped region is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, and the concentration of Si is 1 × The method for manufacturing a semiconductor device according to any one of appendices 9 to 12, wherein the manufacturing method is 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.
(Appendix 14)
Item 13. The supplementary note 13, wherein the concentration of any one of the Fe and C doped in the high resistance region is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. Semiconductor device manufacturing method.
(Appendix 15)
15. The method of manufacturing a semiconductor device according to any one of appendices 9 to 14, wherein the co-doped region and the high resistance region are formed of a material containing GaN.
(Appendix 16)
The carrier traveling layer is formed of a material containing GaN,
16. The method for manufacturing a semiconductor device according to any one of appendices 9 to 15, wherein the carrier supply layer is formed of a material containing AlGaN.
(Appendix 17)
A power supply device comprising the semiconductor device according to any one of appendices 1 to 8.
(Appendix 18)
An amplifier comprising the semiconductor device according to any one of appendices 1 to 8.

10 substrate 21 buffer layer 22 co-doped region 23 high resistance region 31 electron transit layer 31a 2DEG
32 Electron supply layer 33 Cap layer 41 Gate electrode 42 Source electrode 43 Drain electrode

Claims (8)

A nitride semiconductor buffer layer provided above the substrate;
A nitride semiconductor layer including a co-doped region and a high-resistance region provided above the buffer layer;
A nitride semiconductor carrier travel layer provided above the nitride semiconductor layer;
A nitride semiconductor carrier supply layer provided above the carrier travel layer;
A gate electrode, a source electrode, and a drain electrode provided above the carrier supply layer;
Have
The co-doped region is formed in a region between the gate electrode and the drain electrode in a plan view, and is doped with at least one impurity element selected from Fe and C and Si. And
The high resistance region is formed in a region immediately below the gate electrode, and is doped with either Fe or C as an impurity element.   The semiconductor device according to claim 1, wherein the high resistance region is also formed in a region between the gate electrode and the source electrode in plan view.   The semiconductor device according to claim 1, wherein the co-doped region is also formed in a region between the gate electrode and the source electrode in plan view.   4. The semiconductor device according to claim 1, wherein a concentration of the Si in the co-doped region is higher than a concentration of any one of the Fe and C. 5. The concentration of any one of the Fe and C doped in the co-doped region is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, and the concentration of Si is 1 × 5. The semiconductor device according to claim 1, wherein the semiconductor device is 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. Forming a buffer layer above the substrate;
Forming a nitride semiconductor layer of a nitride semiconductor doped with at least one impurity element selected from Fe and C above the buffer layer;
Si is ion-implanted into a part of the nitride semiconductor layer to form a co-doped region in which the Si is ion-implanted and a high resistance region in which the Si is not doped in the nitride semiconductor layer,
Forming a nitride semiconductor carrier travel layer above the nitride semiconductor layer;
Forming a nitride semiconductor carrier supply layer above the carrier travel layer,
Forming a gate electrode, a source electrode, and a drain electrode above the carrier supply layer;
The co-doped region is formed in a region between the gate electrode and the drain electrode in plan view,
The method of manufacturing a semiconductor device, wherein the high resistance region is formed in a region immediately below the gate electrode.   The method of manufacturing a semiconductor device according to claim 6, wherein the high resistance region is also formed in a region between the gate electrode and the source electrode in a plan view.   The method of manufacturing a semiconductor device according to claim 6, wherein the co-doped region is also formed in a region between the gate electrode and the source electrode in a plan view.

Images