JP2016144233A - Signal generation circuit, voltage conversion device and signal generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal generation circuit in which a minimum increment of a value to be set to a generation part that periodically generates a PWM signal corresponding to a preset value, can be made substantially smaller than an actual increment with a relatively small processing load, a voltage conversion device and a signal generation method.SOLUTION: A CPU 11 identifies a setting value U that is closest to a target value X that should be set to a PWM circuit 15, and a setting value Z that is closest secondly, every N (=3) cycles of a PWM signal generated by a PWM signal generation part 153 included in the PWM circuit 15. In accordance with a result of comparing magnitudes of the identified Y and Z with a magnitude of X, Y and Z are combined, such that N pieces of setting values are determined and set to the PWM circuit 15 one by one in each cycle of the PWM signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a signal generation circuit and a voltage conversion device including a generation unit that generates a signal having a duty according to a set value, and a control unit that sets a value that can be set in the generation unit according to a target value. And a signal generation method.

  Conventionally, a voltage converter that converts a voltage by driving a switching element with a PWM signal has been widely used. In this PWM control type voltage conversion device, for example, a voltage command value is calculated based on a voltage target value, and a value corresponding to the calculated voltage command value is set in a PWM signal generator, thereby setting the set value. A PWM signal having a duty corresponding to the frequency is generated. Thus, by changing the duty of the PWM signal for driving the switching element in accordance with the target value of voltage, an output voltage corresponding to the target value of voltage can be obtained.

  Here, when the minimum increment (that is, the minimum unit) of a value that can be set in the PWM signal generation unit (hereinafter referred to as a settable value) is relatively large, the duty of the PWM signal is smoothed with respect to a change in the target value. Therefore, the output voltage changes stepwise. Further, for example, when the target value to be set in the PWM signal generation unit is calculated as the operation amount by the PWM control, when the minimum increment of the settable value is larger than the minimum increment of the target value, The duty of the PWM signal cannot be smoothly changed with respect to the change of the target value and the load fluctuation, and an error occurs in the output voltage.

  On the other hand, in Patent Document 1, when the on / off time of the PWM signal is calculated for each cycle of PWM control, the remainder of the division with the voltage command value as the dividend is rounded down to calculate on / off. A PWM inverter that calculates time and outputs a PWM pulse based on the calculation result is disclosed. The remainder generated by the above calculation corresponds to a voltage command value that is truncated without being reflected in the on / off time.

  In this PWM inverter, the remainder that is not reflected in the on / off time in the previous computation is newly added to the next computation by adding the rounded down remainder to the voltage command value in the computation after the next cycle. / It is reflected in the off time, and it is repeated that the remainder at that time is further reflected in the next calculation. For this reason, the average value of the on / off time set for the PWM signal generation unit can be brought close to the target on / off time to be originally set. That is, the minimum increment of the value set in the generation unit can be made smaller than the actual increment on average.

JP-A-3-98470

  However, in the technique disclosed in Patent Document 1, since an operation including division is performed for each cycle of PWM control to determine the on / off time of the PWM signal, a large processing load is generated for each cycle. . For this reason, an inexpensive microcomputer with low processing capability executes the above arithmetic processing and other processing such as communication in parallel and stably even when the change in the target value is relatively small. There was a possibility that it could not be done.

  The present invention has been made in view of such circumstances, and the object of the present invention is to reduce the minimum increment of the value set in the generator that periodically generates a signal having a duty corresponding to the set value. Another object of the present invention is to provide a signal generation circuit, a voltage conversion device, and a signal generation method that can be made substantially smaller than an actual increment with a relatively small processing load.

  The signal generation circuit according to the present invention includes a generation unit that periodically generates a signal having a duty corresponding to a set value, and a settable value that can be set in the generation unit according to a predetermined value. A signal generation circuit including a control unit that is set for each period, the control unit is configured to set a value that is closest to the predetermined value and a second value every N cycles (N is a natural number of 2 or more) of the signal. N setstable values out of the two settable values are determined based on the means for specifying a settable value close to, the two settable values specified by the means and the size of each of the predetermined values. And determining means for determining to be set in the generating section.

  In the signal generation circuit according to the present invention, the determining means may determine the N settable values and an average value of M settable values (M is a natural number satisfying 2 ≦ M ≦ N) as the predetermined value. It is characterized in that it is determined sequentially so as to be closest to the value.

  In the signal generation circuit according to the present invention, the determining means determines the N settable values such that an average value of each settable value is closest to the predetermined value. It is characterized by that.

  The signal generation circuit according to the present invention includes a storage unit that stores a correspondence between a predetermined value and N settable values, and the storage unit generates N settable values as an average of each settable value. A predetermined value is determined in advance so as to be closest to the corresponding predetermined value, and the determining means obtains N settable values corresponding to the predetermined value from the storage information of the storage unit. It is characterized by being determined.

  In the signal generation circuit according to the present invention, the control unit sequentially reads out N settable values determined by the determination unit from the storage unit for each cycle of the signal and sets the values in the generation unit. It is characterized by being.

  The voltage conversion device according to the present invention detects the voltage converted by the voltage conversion circuit, the voltage conversion circuit converting the voltage by switching according to the duty of the signal generated by the signal generation circuit, and the voltage conversion circuit The control unit included in the signal generation circuit includes means for calculating the predetermined value by PWM control based on the voltage detected by the detection unit. To do.

  The signal generation method according to the present invention includes a generation unit that periodically generates a signal having a duty corresponding to a set value, and a settable value that can be set in the generation unit according to a predetermined value. In a method of generating the signal by a signal generation circuit including a control unit that sets every cycle, a settable value closest to the predetermined value for every N cycles (N is a natural number of 2 or more) of the signal, and The second settable value is specified, and N settable values are selected from the two settable values based on the two specified settable values and the size of the predetermined value. It is characterized by determining to set to.

In the present invention, the predetermined value is a target value to be set in the generation unit, and the control unit determines and sets a settable value that can be set in the generation unit according to the target value. Specifically, the control unit identifies the settable value closest to the target value and the second settable value for each N cycles of the signal generated by the generation unit, and sets the two specified settable values. Based on the result of comparison between the magnitude and the target value, N settable values are determined from the two specified settable values, and set in the setting unit one by one for each period of the signal. .
Accordingly, the ratio of the settable value closest to the target value and the settable value closest to the second value is appropriately determined for the N settable values determined by the control unit, and thus the average of the N settable values is determined. Value is finer-tuned than the smallest increment of the settable value.

In the present invention, for the N settable values determined by the control unit, the settable value closest to the target value is determined as the first settable value, and the first to Mth (2 The determination of the Mth settable value is repeated N−1 times so that the average value of the settable values up to ≦ M ≦ N) is closest to the target value.
Thereby, in any period of N periods of the signal, the average value of the settable values set in the generation unit from the first period to the period becomes closest to the target value.

In the present invention, for the N settable values determined by the control unit, N settable values are determined so that the average value of all the N settable values is closest to the target value. .
As a result, the average value of the N settable values set in the generation unit is closest to the target value for the entire N period of the signal.

In the present invention, the correspondence between the N settable values calculated in advance so that the average value is closest to the target value and the target value is stored in the storage unit. The control unit determines N settable values corresponding to the target value to be set in the generation unit from the storage information in the storage unit.
Thereby, N settable values to be determined according to the target value are easily determined when the control unit executes the control.

In the present invention, the control unit sequentially reads N settable values from the storage unit and sets them in the generation unit.
Thereby, the storage information of the storage unit is sequentially set in the generation unit.

In the present invention, the voltage conversion circuit converts the voltage by switching according to the duty of the signal generated by the signal generation circuit described above, and the control unit of the signal generation circuit is generated by PWM control based on the converted voltage. The target value to be set for the part is calculated.
As a result, a signal generation circuit capable of making the minimum increment of the value set in the generator that periodically generates a signal substantially smaller than the actual increment with a relatively small processing load is provided in the voltage converter. Applied, the accuracy of the output voltage is improved.

According to the present invention, for the N settable values determined by the control unit, the ratio of the settable value closest to the target value and the second closest settable value is appropriately determined. Is adjusted more finely than the smallest increment of the settable value.
Therefore, the minimum increment of the value set in the generator that periodically generates a signal having a duty corresponding to the set value can be made substantially smaller than the actual increment with a relatively small processing load. It becomes.

It is a block diagram which shows the structural example of a voltage converter provided with the signal generation circuit which concerns on Embodiment 1 of this invention. FIG. 3 is a timing diagram for explaining the operation of the signal generation circuit according to the first embodiment of the present invention. It is explanatory drawing for demonstrating the operation | movement in which the average duty of a PWM signal is decided by N setting values. It is explanatory drawing for demonstrating the method of determining N setting values in the signal generation circuit which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of CPU which performs a PWM interruption process in the signal generation circuit which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of CPU which concerns on the setting value determination subroutine in Embodiment 1 of this invention. It is a graph which shows the list of N setting values determined according to the target value in the signal generation circuit which concerns on Embodiment 1 of this invention. It is explanatory drawing for demonstrating the method of determining N setting values in the signal generation circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows the process sequence of CPU which concerns on the subroutine of the setting value determination in Embodiment 2 of this invention. It is a graph which shows the list of the N setting values determined according to the target value in the signal generation circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structural example of a voltage converter provided with the signal generation circuit which concerns on Embodiment 3 of this invention. It is a flowchart which shows the process sequence of CPU which performs a PWM interruption process with the signal generation circuit which concerns on Embodiment 3 of this invention.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a voltage conversion apparatus including a signal generation circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 1a denotes a signal generation circuit. The signal generation circuit 1a generates a PWM signal whose duty changes and supplies the PWM signal to the voltage conversion circuit 2. The voltage conversion circuit 2 converts the voltage of the external battery 3 and supplies it to the external load 4. Although the voltage conversion circuit 2 steps down the voltage of the battery 3 here, the voltage conversion circuit 2 may step up or step up or step down the voltage of the battery 3.

  The signal generation circuit 1a is composed of a microcomputer having a CPU 11. The CPU 11 includes a ROM 12a for storing information such as a program, a RAM 13a for storing temporarily generated information, an A / D converter 14 (corresponding to a detection unit) for converting an analog voltage into a digital voltage value, and a PWM signal. A generated PWM circuit (corresponding to a generation unit) 15 and an interrupt controller 16 for processing a plurality of interrupt requests are connected to each other by a bus. Of the signal generation circuit 1a, the control unit 10a is obtained by removing the PWM circuit 15. However, the PWM circuit 15 may be included in the control unit 10a.

  The RAM 13a includes a duty data table 131 in which a plurality of data to be transferred to the register buffer 151 included in the PWM circuit 15 is stored. Data stored in the duty data table 131 is sequentially set in the register buffer 151 by an interrupt process described later controlled by the interrupt controller 16.

  The PWM circuit 15 includes a duty register 152 in which the contents of the register buffer 151 are periodically loaded, and a PWM signal generation unit 153 that generates a PWM signal having a duty corresponding to the contents of the duty register 152. The PWM signal generation unit 153 gives a load signal for loading the contents of the register buffer 151 to the duty register 152.

  The PWM signal generation unit 153 generates a PWM signal having an on time that is an integral multiple of the period of the internal clock, based on an internal clock (not shown) and the contents of the duty register 152. The PWM signal generated by the PWM signal generation unit 153 is supplied to the voltage conversion circuit 2 and also to the interrupt controller 16 as one of interrupt requests.

  The interrupt controller 16 is configured to accept a plurality of interrupt requests. When any interrupt request is accepted, the interrupt controller 16 gives a signal (so-called INT signal) for requesting an interrupt to the CPU 11. When an acknowledge signal (so-called INTA signal) is given, an interrupt vector corresponding to each interrupt request is sent to the bus. When the interrupt vector sent to the bus is read by the CPU 11, the CPU 11 executes an interrupt process corresponding to each interrupt request.

  In the voltage conversion circuit 2, the drain and source are connected to an N-channel MOSFET (hereinafter simply referred to as FET) 21 whose drain is connected to the positive terminal of the battery 3, and the source of the FET 21 and the negative terminal of the battery 3, respectively. FET 22 and a drive circuit 26 for supplying a drive signal to the gates of the FET 21 and FET 22 based on the PWM signal supplied from the PWM signal generation unit 153 of the PWM circuit 15.

  A load 4 is connected between the drain and source of the FET 22 via a series circuit of an inductor 23 and a resistor 24. A capacitor 25 is connected to the load 4 in parallel. The voltage at the connection point between the resistor 24 and the capacitor 25 is supplied to the A / D converter 14. A current detector 27 is connected to both ends of the resistor 24, and a detection voltage of the current detector 27 is applied to the A / D converter 14.

  In the above configuration, the CPU 11 of the signal generation circuit 1a controls the voltage supplied to the load 4 by, for example, a current mode control method in which voltage loop control and current loop control are executed in parallel. In the voltage loop control, the CPU 11 performs the target in the subsequent current loop control based on the deviation obtained by subtracting the digital voltage value obtained by converting the output voltage supplied to the load 4 by the A / D converter 14 from the target voltage value. The operation amount that becomes the current value of is calculated. In this voltage loop control, the voltage output from the voltage conversion circuit 2 is the control amount.

  In the current loop control, the CPU 11 performs PWM based on a deviation obtained by subtracting the digital current value obtained by converting the detection voltage of the current detector 27 by the A / D converter 14 from the target current value from the previous voltage loop control. An operation amount for the circuit 15 is calculated. Further, the CPU 11 determines a settable value (hereinafter simply referred to as a set value) that can be set in the PWM circuit 15 in accordance with the calculated operation amount (corresponding to a predetermined value: hereinafter referred to as a target value). The PWM circuit 15 generates a PWM signal having a duty corresponding to the set value when the determined set value is set. In this current loop control, the current output from the voltage conversion circuit 2 is the control amount.

  Here, when the output voltage and output current of the voltage conversion device fluctuate relatively gently in time, the control cycle of the voltage loop control and the current mode control is N times the PWM cycle (N is a natural number of 2 or more). It can be said that it is sufficient to go with a period of. In the first embodiment, therefore, N set values for the PWM circuit 15 are determined and stored in the duty data table 131 for every N cycles of the PWM cycle, and the interrupt processing generated in the PWM cycle is performed. One set value is set in the PWM circuit 15 for each cycle. In the following, N = 3 for simplicity.

Next, a mechanism in which the PWM signal generation unit 153 generates a PWM signal corresponding to the contents of the duty register 152 will be described.
FIG. 2 is a timing diagram for explaining the operation of the signal generation circuit 1a according to the first embodiment of the present invention. The five timing charts shown in FIG. 2 all have the same time axis as the horizontal axis, and the vertical axis indicates the interrupt signal level and the interrupt processing executed at the PWM cycle from the top of the figure. , The contents of the register buffer 151, the on / off state of the load signal for loading the contents of the register buffer 151 into the duty register 152, and the contents of the duty register 152 are shown.

  The PWM signal includes the first period, the second period, and the third period in N periods (N = 3) from time t21 to t22, from time t22 to t23, and from time t23 to t31. The on-time when the level is H (high) is times T21, T22, and T23, respectively. From time t13 to t21 is the third period in the previous N period, and the on-time is time T13. The fall when the signal level in each cycle of the PWM signal changes from H to L is accepted as an interrupt request to the interrupt controller 16 and the interrupt process is executed once.

  Specifically, the interrupt process is executed only once when the times T13, T21, T22, and T23 have elapsed from the times t13, t21, t22, and t23, respectively. Of these, the interrupt processing in the third cycle is longer in execution time than the interrupt processing in the first cycle and the second cycle by the time for collectively calculating the set values for the next N cycles. Become. The calculated set values are stored in the continuous storage area from the first address to the third address in the duty data table 131 as the first set value, the second set value, and the third set value, respectively.

  The first set value, the second set value, and the third set value stored in the duty data table 131 are the interrupt process in the third period when each set value is stored, and the first set value in the next N period. Data are sequentially read out by interrupt processing in each of the period and the second period, and set in the register buffer 151. Thereby, in the interrupt processing in each of the first period, the second period, and the third period, the contents of the register buffer 151 are changed to the second set value, the third set value, and the first set value for the next N period. Rewritten.

  On the other hand, at the rise when the signal level of the PWM signal changes from L to H, that is, at times t13, t21, t22, t23, and t31, the contents of the register buffer 151 are transferred from the PWM signal generation unit 153 to the duty register 152. A load signal for loading is provided. Thereby, the contents of the duty register 152 are held at the first set value, the second set value, and the third set value during the first period, the second period, and the third period, respectively. The content determines the on-time of the PWM signal in each of the first period, the second period, and the third period, and determines the duty.

  In the example shown in FIG. 2, three set values for the next N cycle are calculated within the third cycle of the previous N cycle. However, when this calculation is not completed within the third cycle, The duty data table 131 may be a double buffer so that writing and reading to the duty data table 131 do not compete. Specifically, three set values are calculated and written to one buffer during the third period, the first period, and the second period, and the subsequent third period, the first period, and the second period In the meantime, the next three set values are calculated and written to the other buffer, and the three set values previously calculated from one buffer in the interrupt processing in each cycle may be read sequentially.

Next, a specific example in which the set value corresponding to the target value is set in the PWM circuit 15 will be described.
FIG. 3 is an explanatory diagram for explaining an operation in which the average duty of the PWM signal is determined by N set values. In the figure, the horizontal axis represents time, and the vertical axis represents the signal level of the PWM signal. FIG. 3 shows how the PWM signals in the first period, the second period, and the third period of the PWM period change on / off for each of three consecutive N (= 3) periods. The PWM signal in each PWM cycle is on in the first half and off in the second half.

In the first embodiment, the period of the PWM signal generated by the PWM circuit 15 is 10 μs, the minimum increment of the value that can be set in the PWM circuit 15 is 1, and 1 of this increment is the duty of the PWM signal. Corresponds to 3%. In other words, the duty of the PWM signal generated by the PWM circuit 15 can be set in units of 3%. On the other hand, it is assumed that the minimum increment of the result calculated by the CPU 11 as the target value to be set in the PWM circuit 15 is 0.1 or less. This calculation is, for example, a PID calculation, and examples of the timing at which the calculation is performed and the timing at which the set value is set in the PWM circuit 15 are as shown in FIG.
When the target duty is calculated by PID calculation, the minimum increment of the calculated duty% value is set to 0.3%, and the value obtained by multiplying the calculated duty by 100/3 is set as the target value. Then, the same result as above can be obtained.

  At the timing shown in FIG. 3, the result of the PID calculation in the first N cycles is 19.4 (corresponding to 19.4 × 3 = 58.2% in terms of duty: hereinafter, only the corresponding% value is shown in parentheses. ), The first set value, the second set value, and the third set value are determined as 19 (57%), 20 (60%), and 19 (57%), respectively. Since the increment 1 of the set value corresponds to 3% of the duty and 1% of the duty corresponds to 0.1 μs, the ON time of each PWM signal generated in the next N cycles by each set value is 5. 7 μs, 6.0 μs, and 5.7 μs, and the average on-time is 5.8 μs. This indicates that the average duty is 58%.

  Similarly, when the result of the PID calculation in the second N cycle is 19.6 (58.8%), each of the first set value, the second set value, and the third set value is 19 (57 %), 20 (60%) and 20 (60%). As a result, the ON time of each PWM signal generated in the next N period depending on each set value is 5.7 μs, 6.0 μs, and 6.0 μs, respectively, and the average on time is 5.9 μs. This indicates that the average duty is 59%. As described above, the average duty of the PWM signal in N cycles can be set in increments of 1%.

Next, a method for determining the first set value, the second set value, and the third set value corresponding to the target value will be described.
FIG. 4 is an explanatory diagram for explaining a method of determining N set values in the signal generation circuit 1a according to the first embodiment of the present invention. In the figure, “◯” represents N (N = 3) set values, and “●” represents an average value of M (2 ≦ M ≦ N) set values. Since the average value has no meaning for the first set value, the number of “●” is one less than the number of “◯”.

  For the target value X, first, the closest setting value Y and the second closest setting value Z are specified. In the example of FIG. 4, Y that is larger than X and not larger than ½ or more than X is first identified, and Z is identified as Y−1. Unlike the case shown in FIG. 4, when Y that is smaller than X and not smaller than ½ or less than X is first identified (not shown), Z is identified as Y + 1.

  In the first embodiment, N set values are sequentially determined from Y and Y-1. At this time, the Mth set value is determined such that the average value from the first set value to the Mth (2 ≦ M ≦ N) set value is the closest value to the target value X. Since the first set value is determined before the second set value in anticipation of the average value of the first and second set values being closest to the target value X, the first set value is always Y is determined. In the case of FIG. 4, the candidate value for the second setting value is Y or Y-1.

  When the second set value is determined, it is determined which of the two set values of the second set value and the average value of the first set value is closer to X. In this case, since the two candidate values are Y or Y-1 and the first set value is Y, Y which is the average value of Y and Y and Y-1 which is the average value of Y-1 and Y / 2 is compared to determine which is closer to X. In the case of FIG. 4, since Y−1 / 2 is closer to X than Y, the second set value is determined to be Y−1.

  When the third set value is determined, it is determined which of the two candidate values of the third set value, the average value of the second set value and the first set value, is closer to X. In this case, since the two candidate values of the third set value are Y or Y-1, the second set value is Y-1, and the first set value is Y, Y, Y-1 and Y It is determined which of Y-1 / 3 as an average value and Y-2 / 3 as an average value of Y-1, Y-1 and Y is closer to X. In the case of FIG. 2, since Y-1 / 3 is closer to X than Y-2 / 3, the third set value is determined to be Y-1 / 3.

2, 3 and 4, the case where N is 3 has been described, but the same applies to the case where N is 2 or 4 or more. Hereinafter, the operation of the signal generation circuit 1a for determining the N set values described above will be described with reference to a flowchart showing the operation. The following processing is executed by the CPU 11 according to a control program stored in advance in the ROM 12a.
FIG. 5 is a flowchart showing a processing procedure of the CPU 11 that executes the PWM interrupt processing in the signal generation circuit 1a according to the first embodiment of the present invention, and FIG. 6 shows the setting value determination in the first embodiment of the present invention. It is a flowchart which shows the process sequence of CPU11 which concerns on this subroutine.

  The loop counter J in FIG. 5, the target value X in FIG. 6, the value Y closest to the target value, the second closest value Z, the loop counter M, the total value S of the M set values, the value Ay and the value Az is stored in the RAM 13a. The initial value of the loop counter J is N. The first, second, and third set values determined in the process of FIG. 6 are stored in the duty data table 131 in the order of addresses.

  When the interruption of the PWM cycle occurs and the control of the CPU 11 shifts to the processing of FIG. 5, the CPU 11 determines whether or not the loop counter J is N (here, 3) (S10). In the case (S10: YES), J is set to 1 (S11). Thereafter, the CPU 11 takes in a digital output voltage value obtained by converting the output voltage supplied to the load 4 by the A / D converter 14 (S12), and executes an operation related to voltage loop control based on the taken-in output voltage value. In step S13, a target current value is calculated as the operation amount.

  Thereafter, the CPU 11 captures a digital output current value obtained by converting the detection voltage of the current detector 27 by the A / D converter 14 (S14), and executes a calculation related to current loop control based on the captured output current value. (S15) A target value X to be set in the PWM circuit 15 as an operation amount is calculated and stored in the RAM 13a. In order to omit the current loop control, steps S14 and S15 may not be executed. Next, the CPU 11 calls and executes a subroutine relating to setting value determination (S16).

When returning from the subroutine related to setting value determination, the CPU 11 reads the J-th setting value among the N setting values from the duty data table 131 (S17), and sets the read J-th setting value in the register buffer 151. (S18), the process returns to the interrupted routine.
On the other hand, if J is not N in step S10 (S10: NO), the CPU 11 increments J by 1 (S19), and then moves the process to step S17 to set the Jth set value in the register buffer 151. .

  Moving to FIG. 6, when a subroutine related to setting value determination is called from the PWM interrupt processing, the CPU 11 specifies the setting value Y closest to the target value X stored in the RAM 13a (S21) and 2 The set value Z closest to the second is identified (S22), and the first set value is determined as Y (S23). At this point, Z is specified as either Y + 1 or Y-1. Next, the CPU 11 sets the loop counter M to 1 (S24), and sets the total value S of the M set values to Y (S25).

  Thereafter, the CPU 11 determines whether or not M is N (S26). If N is N (S26: YES), the CPU 11 returns to the called routine. When M is not N (S26: NO), the CPU 11 increments M by 1 (S27), and then calculates (S + Y) / M value Ay (S28) and (S + Z) / M value Az. Is calculated (S29). Ay and Az calculated here are two candidate values that can be an average value of M set values.

  Next, the CPU 11 determines whether or not | Ay-X | is equal to or smaller than | Az-X | (S30). The determination here is to determine which of the two candidate values is close to the target value X. When | Ay−X | is equal to or smaller than | Az−X | (S30: YES), the CPU 11 determines the Mth set value as Y (S31), and replaces the total value S of the M set values with S + Y. (S32), the process proceeds to step S26. On the other hand, when | Ay−X | is larger than | Az−X | (S30: NO), the CPU 11 determines the Mth set value as Z (S33), and sets the total value S of the M set values to S + Z. After the replacement (S34), the process proceeds to step S26.

  In the above-described flowchart, the setting value Z closest to the target value X and the setting value Z closest to the second are specified first, and the value of Z (Y + 1 or Y-1) is stored in the RAM 13a. It is not limited. For example, when determining the Mth set value, an average value from the first set value to the M-1th set value is calculated, and the magnitude relationship between this average value and the target value X is determined. , It may be specified each time whether Z is Y + 1 or Y-1.

Next, a plurality of examples of the N set values determined as described above will be described.
FIG. 7 is a chart showing a list of N set values determined according to the target value in the signal generation circuit 1a according to the first embodiment of the present invention. The target value is represented by a numerical value with two decimal places. For example, when the target value is in the range of 0.00 to 0.17, the first, second, and third set values are determined as 0, 0, and 0, respectively. In this case, the average value of the N set values is 0.00, the average value of the duty of the PWM signal thereby becomes 0%, and the ON time is 0.0 μs. When the target value is in the range of 0.17 to 0.50, the first, second and third set values are determined as 0, 1 and 0, respectively, and the average value of the N set values is rounded off. Therefore, the average value of the duty of the PWM signal is 1%, and the ON time is 0.1 μs.

  When the target value is in the range of 0.50 to 0.83, the first, second, and third set values are determined as 0, 1, and 1, respectively, and the average value of the N set values is 0. The average value of the duty of the PWM signal is 2%, and the ON time is 0.2 μs. When the target value is in the range of 0.83 to 1.17, the first, second, and third set values are determined as 1, 1, and 1, respectively, and the average value of the N set values is 1 The average value of the duty of the PWM signal is 3%, and the ON time is 0.3 μs. Similarly, every time the target value increases by 1, the N set values and their average values increase by 1, the average duty value increases by 3%, and the on-time average value becomes 0.3 μs. Only get longer.

  Particularly in the case corresponding to FIG. 3, when the target value is in the range of 19.17 to 19.50, the first, second, and third set values are determined as 19, 20, and 19, respectively. The average value of the N set values is 19.33, the average value of the duty of the PWM signal is 58%, and the ON time is 5.8 μs. When the target value is in the range of 19.50 to 19.83, the first, second, and third set values are determined as 19, 20, and 20, respectively, and an average value of N set values Is 19.66, the average value of the duty of the PWM signal is 59%, and the ON time is 5.9 μs.

As described above, according to the first embodiment, the CPU 11 functioning as the center of the control unit 10a determines a set value that can be set in the PWM circuit 15 according to the target value X that should be set in the PWM circuit 15. To set. Specifically, the CPU 11 sets the setting value Y closest to the target value X and the setting value closest to the second for every N (= 3) periods of the PWM signal generated by the PWM signal generation unit 153 included in the PWM circuit 15. Z is specified, and N setting values are determined from Y and Z according to the result of comparing the specified Y and Z sizes with the X size, and one is set for each period of the PWM signal. The PWM circuit 15 is set.
Thereby, since the ratio of the setting value Y closest to the target value X and the setting value Z closest to the second among the N setting values determined by the CPU 11 is appropriately specified, the average value of the N setting values Is adjusted more finely than the smallest increment of values that can be set in the PWM circuit 15.
Accordingly, the minimum increment of the value set in the PWM circuit (generator) 15 that periodically generates a signal having a duty corresponding to the set value is substantially smaller than the actual increment with a relatively small processing load. It can be made smaller.

Further, according to the first embodiment, for the N set values determined by the CPU 11, the set value Y closest to the target value X is determined as the first set value, and the first set value to the Mth set value ( The determination of the Mth set value is repeated N−1 times so that the average value up to 2 ≦ M ≦ N) is closest to the target value X.
Therefore, the average value of the set values set in the PWM circuit 15 from the first cycle to the cycle is set to the value closest to the target value X in any cycle of the N cycles of the PWM signal. Is possible.

(Embodiment 2)
While the first embodiment is a mode in which the first set value and the Mth set value (2 ≦ M ≦ N) are directly and sequentially determined, the second embodiment has a target among the M set values. In this embodiment, the N setting values are indirectly determined by calculating the number of setting values that are second closest to the value.
Since the configuration of the voltage conversion device in the second embodiment is the same as that shown in FIG. 1 in the first embodiment, portions corresponding to those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. .

  FIG. 8 is an explanatory diagram for explaining a method of determining N set values in the signal generation circuit 1a according to the second embodiment of the present invention. For the target value X, first, the closest setting value Y and the second closest setting value Z are specified. In the example of FIG. 8, Y that is smaller than X and not smaller than ½ or less than X is first identified, and Z is identified as Y + 1.

  Assuming that all of the first set value to the Nth set value are determined as Y, the average value of all the set values is Y. Next, if only one of the N setting values is determined to be Z (Y + 1 in the case of FIG. 8) instead of Y, the average value of all the setting values increases / decreases by 1 / N from Y. (In the case of FIG. 8, it increases). Similarly, every time the setting value determined as Z increases by 1, the average value of all the setting values increases / decreases by 1 / N (in the case of FIG. 8 increases).

  Considering that the relationship between the number of set values determined as Z and the average value of all the set values is as described above, the number of set values determined as Z is determined from Y to Z. The magnitude relationship between X and the value increased or decreased by 1 / N in each direction may be determined each time. More specifically, when the magnitude relationship is reversed by increasing / decreasing K times by 1 / N, it is determined which is closer to X between the value ya increased / decreased K times and the value yb increased / decreased K−1 times. The closer number of times (K or K-1) may be the number of set values determined as Z.

  More specifically, the magnitude relationship between the value yc increased or decreased by 1 / 2N from the value yb increased or decreased K-1 times and X may be determined. In the case of FIG. 8, since K = 2 and it is determined that yc is greater than X, the value of K−1 is the number of setting values determined as Z.

  If the above-mentioned algorithm is viewed from the X side, 1 / N is repeatedly subtracted from the difference x between X and Y, and if the subtraction result xa becomes negative when subtracting K times, 1 / N from x The number of setting values determined as Z may be determined by whether or not a value xc obtained by further subtracting 1 / 2N from a value xb obtained by subtracting K-1 times is negative. In the example of FIG. 8, since K = 2 and xc becomes negative, the number of Z is determined to be 1. If xc is positive, the number of Z is determined to be 2.

  Note that 1 / 2N is first subtracted from the difference x between X and Y, and Z is determined depending on how many times 1 / N is subtracted from the subtraction result and the subtraction result becomes negative. The number of values may be determined. If the subtraction result when 1 / 2N is subtracted is negative, the number of Z is determined as 0. If the subtraction result when 1 / N is subtracted K times is negative, the number of Z is determined as K. The This algorithm will be described in the flowchart described later. In the example of FIG. 8, since the subtraction result becomes negative when 1 / N is subtracted once from the result of subtracting 1 / 2N from x, the number of Z is determined to be 1.

Below, operation | movement of the signal generation circuit 1a mentioned above is demonstrated using the flowchart which shows it. The following processing is executed by the CPU 11 according to a control program stored in advance in the ROM 12a.
FIG. 9 is a flowchart showing the processing procedure of the CPU 11 according to the set value determination subroutine in the second embodiment of the present invention. The number K of set values in FIG. 9 and the difference x between X and Y are stored in the RAM 13a. Since the processing procedure of the CPU 11 related to the PWM interrupt processing is the same as that shown in FIG. 5 in the first embodiment, illustration and description thereof are omitted.

  When a subroutine related to setting value determination is called from the PWM interrupt processing, the CPU 11 specifies the setting value Y closest to the target value X stored in the RAM 13a (S40) and the setting value Z closest to the second. (S41), and the number K of set values determined to be Z is set to 0 (S42). Thereafter, the CPU 11 calculates a difference x between X and Y (S43), and newly sets a value obtained by subtracting 1 / 2N from the calculated x (S44).

  Next, the CPU 11 determines whether or not x is negative (S45). If negative (S45: YES), the process proceeds to step S49 described later. When x is not negative (S45: NO), the CPU 11 increments the value of K by 1 (S46), and newly sets a value obtained by subtracting 1 / N from x (S47).

Next, the CPU 11 determines whether or not x is negative (S48). If not negative (S48: NO), the process proceeds to step S46. If x is negative (S48: YES), the CPU 11 at this point in time has NK set values determined to be Y (value) and K set values determined to be Z (value). Are stored in the duty data table 131 (S49), and the process returns to the called routine.
In steps S45 and S48, it is determined whether or not x is negative. However, an equal sign may be included in the determination to determine whether x is 0 or less.

Next, a plurality of examples of the N set values determined as described above will be described.
FIG. 10 is a chart showing a list of N set values determined according to the target value in the signal generation circuit 1a according to the second embodiment of the present invention. In FIG. 10, the first setting value, the second setting value, and the third setting value included in the N setting values are arranged in ascending order of numerical values. However, the present invention is not limited to this, and may be arranged in descending order. , They may be arranged in any order.

  The target value and the N set values shown in FIG. 10 are partly in the order of arrangement of the first set value, the second set value, and the third set value, compared to that shown in FIG. 7 in the first embodiment. They are only different, and there is no difference in the numbers themselves in the chart. The average value of the N set values is exactly the same as the value shown in FIG.

  Specifically, if the target value is in the range of 0.17 to 0.50, the first, second, and third set values are determined as 0, 0, and 1, respectively. Is within the range of 1.17 to 0.50, the first, second, and third set values are determined as 1, 1, and 2, respectively. When the target value is within the range of 19.17 to 19.50, the first, second, and third set values are determined to be 19, 19, and 20, respectively.

As described above, according to the second embodiment, for the N set values determined by the control unit 10a, the N set values are set so that the average value of all the N set values is closest to the target value. Determine the setting value.
Thereby, the average value of the N set values set in the generation unit is closest to the target value for the entire N cycles of the signal.

(Embodiment 3)
In the first embodiment, the determined N setting values are once written in the duty data table 131 included in the RAM 13a and then sequentially read out in the PWM cycle. N set values are determined from the contents stored in advance in a duty data table included in the ROM, and are sequentially read out in a PWM cycle.
FIG. 11 is a block diagram illustrating a configuration example of a voltage conversion apparatus including the signal generation circuit 1b according to Embodiment 3 of the present invention.

  The signal generation circuit 1b is composed of a microcomputer having a CPU 11. The CPU 11 is bus-connected to a ROM 12b that stores information such as programs, a RAM 13b that stores temporarily generated information, an A / D converter 14, a PWM circuit 15, and an interrupt controller 16. Of the signal generation circuit 1b, the control unit 10b is the one excluding the PWM circuit 15, but the PWM circuit 15 may be included in the control unit 10b.

  The ROM 12b includes a duty data table (corresponding to a storage unit) 121. The duty data table 121 includes N set values respectively associated with each range of target values shown in FIG. 10 in the second embodiment. Are stored in advance. The duty data table 121 may be included in another memory outside the control unit 10b. From a plurality of sets of N set values stored in the duty data table 121, one set of the first set value, the second set value, and the third set value is determined by an interrupt process every N cycles. .

Unlike the RAM 13a according to the first embodiment, the RAM 13b does not include the duty data table 131. The timing chart for explaining the operation of the signal generation circuit 1b is the same as that shown in FIG. 2 of the first embodiment.
In addition, the same code | symbol is attached | subjected to the location corresponding to Embodiment 1, and the description is abbreviate | omitted.

  The first setting value, the second setting value, and the third setting value determined from the contents stored in the duty data table 121 are the interrupt processing in the third period when each setting value is determined, and The data are sequentially read out by the interrupt process in each of the first period and the second period in the N period and set in the register buffer 151.

Hereinafter, the operation of the signal generation circuit 1b for determining the N set values described above will be described with reference to a flowchart showing the operation. The following processing is executed by the CPU 11 according to a control program stored in advance in the ROM 12b.
FIG. 12 is a flowchart showing a processing procedure of the CPU 11 that executes the PWM interrupt processing in the signal generation circuit 1b according to the third embodiment of the present invention. The loop counter J and the target value X in FIG. 12 are stored in the RAM 13b. The initial value of the loop counter J is N.

  Of the processes from step S50 to S58, processes other than step S56 are the same as the processes from step S10 to S18 shown in FIG.

  When the interruption of the PWM period occurs and the control of the CPU 11 shifts to the processing of FIG. 12, the CPU 11 determines whether or not the loop counter J is N (here, 3) (S50). In the case (S50: YES), J is set to 1 (S51). Thereafter, the CPU 11 performs a calculation related to the voltage loop control based on the output voltage and the current loop control based on the output current (S52 to S55).

  Next, the CPU 11 collates the contents of the duty data table 121, that is, each range of target values stored in the table with the target value X calculated by the above-described calculation (S56). As a result of the collation, the N set values stored in the duty data table 121 corresponding to the range including the target value X are determined set values.

  Next, the CPU 11 reads the Jth set value from the duty data table 121 (S57), sets the read Jth set value in the register buffer 151 (S58), and returns to the interrupted routine. ,

As described above, according to the third embodiment, there is a correspondence relationship between the N set values calculated in advance so that the average value is closest to the target value X and the range of the target value. It is stored in the ROM 12b. The CPU 11 determines N set values corresponding to the target value X to be set in the PWM circuit 15 from the stored information in the ROM 12b.
Therefore, N setting values to be determined according to the target value X can be easily determined when the CPU 11 executes the control.

Further, according to the third embodiment, the CPU 11 included in the control unit 10b sequentially reads N set values from the ROM 12b and sets them in the PWM circuit 15 by an interrupt process.
Therefore, the contents of the ROM 12b can be sequentially set in the PWM circuit 15.

Furthermore, according to the first, second, or third embodiment, the voltage conversion circuit 2 converts the voltage by switching according to the duty of the PWM signal generated by the signal generation circuit 1a or 1b, and is based on the converted voltage. By the PWM control, the CPU 11 of the signal generation circuit 1a or 1b calculates a target value to be set in the PWM circuit 15.
Therefore, the signal generation circuit 1a or 1b that can make the minimum increment of the value set in the PWM circuit 15 that periodically generates the PWM signal substantially smaller than the actual increment with a relatively small processing load. When applied to a voltage converter, the accuracy of the output voltage can be improved.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, the technical features described in each embodiment can be combined with each other.

1a, 1b Signal generation circuit 10a, 10b Control unit 11 CPU (identifying means, determining means)
12a, 12b ROM
121 Duty data table (storage unit)
13a, 13b RAM
131 Duty data table 14 A / D converter 15 PWM circuit (generator)
151 Register Buffer 152 Duty Register 153 PWM Signal Generation Unit 16 Interrupt Controller 2 Voltage Conversion Circuit 26 Drive Circuit 27 Current Detector 3 Battery 4 Load

The present invention relates to a signal generation circuit, a voltage conversion device, and a signal including a generation unit that generates a PWM signal according to a set value and a control unit that sets a value that can be set in the generation unit according to a target value. It relates to the generation method.

  Conventionally, a voltage converter that converts a voltage by driving a switching element with a PWM signal has been widely used. In this PWM control type voltage conversion device, for example, a voltage command value is calculated based on a voltage target value, and a value corresponding to the calculated voltage command value is set in a PWM signal generator, thereby setting the set value. A PWM signal having a duty corresponding to the frequency is generated. Thus, by changing the duty of the PWM signal for driving the switching element in accordance with the target value of voltage, an output voltage corresponding to the target value of voltage can be obtained.

Here, when the minimum increment (that is, the minimum unit) of a value that can be set in the PWM signal generation unit (hereinafter referred to as a settable value) is relatively large, the duty of the PWM signal is smoothed with respect to a change in the target value. Therefore, the output voltage changes stepwise. Further, for example, when the target value to be set in the PWM signal generation unit is calculated as the operation amount by the PWM control, when the minimum increment of the settable value is larger than the minimum increment of the target value, The duty of the PWM signal cannot be smoothly changed with respect to the change of the target value and the load fluctuation, and an error occurs in the output voltage.

In contrast, Patent Document 1, when calculating the on / off times of the PWM signal for each periodic in PWM control, ON / OFF by operation truncates remainder of the division of the dividend a voltage command value A PWM inverter that calculates time and outputs a PWM pulse based on the calculation result is disclosed. The remainder generated by the above calculation corresponds to a voltage command value that is truncated without being reflected in the on / off time.

  In this PWM inverter, the remainder that is not reflected in the on / off time in the previous computation is newly added to the next computation by adding the rounded down remainder to the voltage command value in the computation after the next cycle. / It is reflected in the off time, and it is repeated that the remainder at that time is further reflected in the next calculation. For this reason, the average value of the on / off time set for the PWM signal generation unit can be brought close to the target on / off time to be originally set. That is, the minimum increment of the value set in the generation unit can be made smaller than the actual increment on average.

JP-A-3-98470

However, with the technique disclosed in Patent Document 1, for determining the on / off times of the PWM signal by performing the operation including a division for each periodic in PWM control, great processing load is generated every periodic . For this reason, an inexpensive microcomputer with low processing capability executes the above arithmetic processing and other processing such as communication in parallel and stably even when the change in the target value is relatively small. There was a possibility that it could not be done.

The present invention has been made in view of such circumstances, and an object of the present invention is to compare a minimum increment of a value set in a generation unit that periodically generates a PWM signal according to a set value. It is an object of the present invention to provide a signal generation circuit, a voltage converter, and a signal generation method that can be made substantially smaller than an actual increment with a small processing load.

Signal generating circuit according to an embodiment of the present invention includes a generation unit for the PWM signal generated periodically according to the set value, in accordance with a target value, for each periodic prior SL signal to the generator A control unit that sets a settable value that can be set in the generation unit, and the generation unit generates a PWM signal for an external voltage conversion circuit and performs PWM control on the voltage conversion circuit. in the signal generating circuit Ru is converted, said control unit, N periods of the signal (N is a natural number of 2 or more) each time, the specific configurable value close to the nearest settable value and the second the value of the target And N settable values obtained by combining the two settable values are set in the generating unit based on the means for performing the setting, the two settable values specified by the means, and the target values. And a determination means for determining as much as possible. That.

In the signal generation circuit according to an aspect of the present invention, the determining unit may determine the N settable values as M average values of M settable values (M is a natural number satisfying 2 ≦ M ≦ N). characterized in that you have to be determine to be closest to the value of the target.

In the signal generation circuit according to one aspect of the present invention, the determining unit determines the N settable values such that an average value of each settable value is closest to the target value. It is characterized by that.

A signal generation circuit according to an aspect of the present invention includes a storage unit that stores a correspondence relationship between a target value and N settable values, and the storage unit stores N settable values for each settable value. Are determined in advance so as to be closest to the corresponding target value, and the determining means stores N settable values corresponding to the target value in the storage unit. It is determined from the stored information.

Signal generating circuit according to an embodiment of the present invention, the control unit sets the determination means of N configurable value determined within the generator every periodic sequentially reads from the storage unit of the signal It is characterized by the above.

A voltage conversion device according to one embodiment of the present invention includes the above-described signal generation circuit, a voltage conversion circuit that converts voltage by switching according to the duty of a signal generated by the signal generation circuit, and the voltage conversion circuit A voltage conversion device including a detection unit for detecting a voltage, wherein the control unit included in the signal generation circuit includes means for calculating the target value by PWM control based on the voltage detected by the detection unit. It is characterized by.

Signal generation method according to an embodiment of the present invention includes a generation unit for the PWM signal generated periodically according to the set value, in accordance with a target value, for each periodic prior SL signal to the generator A control unit that sets a settable value that can be set in the generation unit, and the generation unit generates a PWM signal for an external voltage conversion circuit and performs PWM control on the voltage conversion circuit. a method for generating the signal by the signal generating circuit Ru to convert the, for each N period of the signal (N is a natural number of 2 or more), closest to the value of the targetable value and the second near settable value And N setstable values obtained by combining the two settable values are determined to be set in the generation unit based on the two specified settable values and the size of the target value. It is characterized by that.

In the present embodiment, control section sets to determine the settable settable value in the generator in accordance with the target value. Specifically, the control unit identifies the settable value closest to the target value and the second settable value for each N cycles of the signal generated by the generation unit, and sets the two specified settable values. the results of comparing the magnitude of the magnitude and the target value, to determine N number of possible values by combining two configurable values identified, set one by one generator each periodic in the signal To do.
Accordingly, the ratio of the settable value closest to the target value and the settable value closest to the second value is appropriately determined for the N settable values determined by the control unit, and thus the average of the N settable values is determined. Value is finer-tuned than the smallest increment of the settable value.

In this aspect , for the N settable values determined by the control unit, the settable value closest to the target value is determined as the first settable value, and the first to Mth (2 The determination of the Mth settable value is repeated N −1 times so that the average value of the settable values up to ≦ M ≦ N) is closest to the target value.
Thereby, in any period of N periods of the signal, the average value of the settable values set in the generation unit from the first period to the period becomes closest to the target value.

In this aspect , for the N settable values determined by the control unit, N settable values are determined such that the average value of all N settable values is closest to the target value. .
As a result, the average value of the N settable values set in the generation unit is closest to the target value for the entire N period of the signal.

In this mode , the correspondence between the N settable values determined in advance so that the average value is closest to the target value and the target value is stored in the storage unit. Control unit determines the N number of possible values-out set all the generator in response to the target value from the information stored in the storage unit.
Thereby, N settable values to be determined according to the target value are easily determined when the control unit executes the control.

In this aspect , the control unit sequentially reads N settable values from the storage unit and sets them in the generation unit.
Thereby, the storage information of the storage unit is sequentially set in the generation unit.

In this aspect , the voltage conversion circuit converts the voltage by switching according to the duty of the signal generated by the signal generation circuit, and the control unit of the signal generation circuit generates by PWM control based on the converted voltage. The target value to be set for the part is calculated.
As a result, a signal generation circuit capable of making the minimum increment of the value set in the generator that periodically generates a signal substantially smaller than the actual increment with a relatively small processing load is provided in the voltage converter. Applied, the accuracy of the output voltage is improved.

According to the above , for the N settable values determined by the control unit, the ratio of the settable value closest to the target value and the second closest settable value is appropriately determined. The average value is adjusted more finely than the smallest settable value increment.
Therefore, the minimum increment of the value set in the generator that periodically generates the PWM signal corresponding to the set value can be made substantially smaller than the actual increment with a relatively small processing load. .

It is a block diagram which shows the structural example of a voltage converter provided with the signal generation circuit which concerns on Embodiment 1 of this invention. FIG. 3 is a timing diagram for explaining the operation of the signal generation circuit according to the first embodiment of the present invention. It is a timing diagram for explaining the operation in which the average duty of the PWM signal is determined by N set values. It is explanatory drawing for demonstrating the method of determining N setting values in the signal generation circuit which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of CPU which performs a PWM interruption process in the signal generation circuit which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of CPU which concerns on the setting value determination subroutine in Embodiment 1 of this invention. It is a graph which shows the list of N setting values determined according to the target value in the signal generation circuit which concerns on Embodiment 1 of this invention. It is explanatory drawing for demonstrating the method of determining N setting values in the signal generation circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows the process sequence of CPU which concerns on the subroutine of the setting value determination in Embodiment 2 of this invention. It is a graph which shows the list of the N setting values determined according to the target value in the signal generation circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structural example of a voltage converter provided with the signal generation circuit which concerns on Embodiment 3 of this invention. It is a flowchart which shows the process sequence of CPU which performs a PWM interruption process with the signal generation circuit which concerns on Embodiment 3 of this invention.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a voltage conversion apparatus including a signal generation circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 1a denotes a signal generation circuit. The signal generation circuit 1a generates a PWM signal whose duty changes and supplies the PWM signal to the voltage conversion circuit 2. The voltage conversion circuit 2 converts the voltage of the external battery 3 and supplies it to the external load 4. Although the voltage conversion circuit 2 steps down the voltage of the battery 3 here, the voltage conversion circuit 2 may step up or step up or step down the voltage of the battery 3.

Signal generating circuit 1a is a microcomputer having a CPU 11. CPU11 is, ROM 12a for storing information such as programs, temporarily RAM13a for storing the generated information, PWM circuit for generating an A / D converter 14, PWM signal converting an analog voltage to a digital value (generator 15) and an interrupt controller 16 for processing a plurality of interrupt requests. Of the signal generation circuit 1a, the control unit 10a is obtained by removing the PWM circuit 15. However, the PWM circuit 15 may be included in the control unit 10a.

The RAM 13a includes a duty data table 131 in which a plurality of data to be set for the register buffer 151 included in the PWM circuit 15 is stored. Data stored in the duty data table 131 in the interrupt processing to be described later interrupt controller 16 arbitrates, and is sequentially set in the register buffer 151.

  The PWM circuit 15 includes a duty register 152 in which the contents of the register buffer 151 are periodically loaded, and a PWM signal generation unit 153 that generates a PWM signal having a duty corresponding to the contents of the duty register 152. The PWM signal generation unit 153 gives a load signal for loading the contents of the register buffer 151 to the duty register 152.

  The PWM signal generation unit 153 generates a PWM signal having an on time that is an integral multiple of the period of the internal clock, based on an internal clock (not shown) and the contents of the duty register 152. The PWM signal generated by the PWM signal generation unit 153 is supplied to the voltage conversion circuit 2 and also to the interrupt controller 16 as one of interrupt requests.

  The interrupt controller 16 is configured to accept a plurality of interrupt requests. When any interrupt request is accepted, the interrupt controller 16 gives a signal (so-called INT signal) for requesting an interrupt to the CPU 11. When an acknowledge signal (so-called INTA signal) is given, an interrupt vector corresponding to each interrupt request is sent to the bus. When the interrupt vector sent to the bus is read by the CPU 11, the CPU 11 executes an interrupt process corresponding to each interrupt request.

In the voltage conversion circuit 2, the drain and source are connected to an N-channel MOSFET (hereinafter simply referred to as FET) 21 whose drain is connected to the positive terminal of the battery 3, and the source of the FET 21 and the negative terminal of the battery 3, respectively. The synchronous rectification FET 22, and a drive circuit 26 that supplies a drive signal to the gates of the FET 21 and the FET 22 based on the PWM signal supplied from the PWM signal generation unit 153 of the PWM circuit 15.

  A load 4 is connected between the drain and source of the FET 22 via a series circuit of an inductor 23 and a resistor 24. A capacitor 25 is connected to the load 4 in parallel. The voltage at the connection point between the resistor 24 and the capacitor 25 is supplied to the A / D converter 14. A current detector 27 is connected to both ends of the resistor 24, and a detection voltage of the current detector 27 is applied to the A / D converter 14.

In the above configuration, the CPU 11 of the signal generation circuit 1a controls the voltage supplied to the load 4 by, for example, a current mode control method in which voltage loop control and current loop control are executed in parallel. In the voltage-loop control, CPU 11 is a digital value converted by the A / D converter 14 the output voltage supplied to the load 4, based on the deviation obtained by subtracting from the voltage value of the target, the target in the subsequent stage of the current loop control The operation amount that becomes the current value is calculated. In this voltage loop control, the voltage output from the voltage conversion circuit 2 is the control amount.

In the current loop control, CPU 11 is based on the detection voltage of the current detector 27 to digital values converted by the A / D converter 14, the deviation obtained by subtracting from the current value of the target from the previous stage of the voltage loop control, PWM circuit The operation amount for 15 is calculated. CPU11 further calculated manipulated variable settable settable value to the PWM circuit 15 in accordance with (hereinafter, referred to as target value) (hereinafter, simply referred to as setting value) is determined. The PWM circuit 15 generates a PWM signal having a duty corresponding to the set value when the determined set value is set. In this current loop control, the current output from the voltage conversion circuit 2 is the control amount.

Here, when the output voltage and the output current of the voltage conversion device fluctuate relatively gently in time, the control cycle of the voltage loop control and the current loop control is N times the PWM cycle (N is a natural number of 2 or more). It can be said that it is sufficient to go with a period of. Therefore in the first embodiment, is stored in the duty data table 131 to determine together the N set value for the PWM circuit 15 every N cycle of the PWM period, hand interrupt processing that occurs in the PWM cycle one setting value set in the PWM circuit 15 for each periodic. In the following, N = 3 for simplicity.

Next, a mechanism in which the PWM signal generation unit 153 generates a PWM signal corresponding to the contents of the duty register 152 will be described.
FIG. 2 is a timing diagram for explaining the operation of the signal generation circuit 1a according to the first embodiment of the present invention. The five timing charts shown in FIG. 2 all have the same time axis as the horizontal axis, and the vertical axis indicates the interrupt signal level and the interrupt processing executed at the PWM cycle from the top of the figure. , The contents of the register buffer 151, the on / off state of the load signal for loading the contents of the register buffer 151 into the duty register 152, and the contents of the duty register 152 are shown.

  The PWM signal includes the first period, the second period, and the third period in N periods (N = 3) from time t21 to t22, from time t22 to t23, and from time t23 to t31. The on-time when the level is H (high) is times T21, T22, and T23, respectively. From time t13 to t21 is the third period in the previous N period, and the on-time is time T13. The fall when the signal level in each cycle of the PWM signal changes from H to L is accepted as an interrupt request to the interrupt controller 16 and the interrupt process is executed once.

Specifically, the interrupt process is executed only once when the times T13, T21, T22, and T23 have elapsed from the times t13, t21, t22, and t23, respectively. Among these, the interrupt process in the third period is longer in execution time than the interrupt process in the first period and the second period by the time for collectively determining the set values for the next N period. Become. The determined setting values are stored in the continuous storage area from the first address to the third address in the duty data table 131 as the first setting value, the second setting value, and the third setting value, respectively.

  The first set value, the second set value, and the third set value stored in the duty data table 131 are the interrupt process in the third period when each set value is stored, and the first set value in the next N period. Data are sequentially read out by interrupt processing in each of the period and the second period, and set in the register buffer 151. Thereby, in the interrupt processing in each of the first period, the second period, and the third period, the contents of the register buffer 151 are changed to the second set value, the third set value, and the first set value for the next N period. Rewritten.

  On the other hand, at the rise when the signal level of the PWM signal changes from L to H, that is, at times t13, t21, t22, t23, and t31, the contents of the register buffer 151 are transferred from the PWM signal generation unit 153 to the duty register 152. A load signal for loading is provided. Thereby, the contents of the duty register 152 are held at the first set value, the second set value, and the third set value during the first period, the second period, and the third period, respectively. The content determines the on-time of the PWM signal in each of the first period, the second period, and the third period, and determines the duty.

In the example shown in FIG. 2, three set values for the next N cycle are determined within the third cycle of the previous N cycle, but this determination is not completed within the third cycle. The duty data table 131 may be a double buffer so that writing and reading to the duty data table 131 do not compete. Specifically, three setting values are determined and written to one buffer during the third period, the first period, and the second period, and the subsequent third period, the first period, and the second period In the meantime, the next three set values are determined and written to the other buffer, and the previously determined three set values are sequentially read from one buffer in the interrupt processing in each cycle.

Next, a specific example in which the set value corresponding to the target value is set in the PWM circuit 15 will be described.
FIG. 3 is a timing chart for explaining an operation in which the average duty of the PWM signal is determined by N set values. In the figure, the horizontal axis represents time, and the vertical axis represents the signal level of the PWM signal. FIG. 3 shows how the PWM signals in the first period, the second period, and the third period of the PWM period change on / off for each of three consecutive N (= 3) periods. The PWM signal in each PWM cycle is on in the first half and off in the second half.

In the first embodiment, the period of the PWM signal generated by the PWM circuit 15 is 10 μs, the minimum increment of the value that can be set in the PWM circuit 15 is 1, and 1 of this increment is the duty of the PWM signal. Corresponds to 3%. In other words, the duty of the PWM signal generated by the PWM circuit 15 can be set in units of 3%. On the other hand, it is assumed that the minimum increment of the result calculated by the CPU 11 as the target value to be set in the PWM circuit 15 is 0.1 or less. This calculation is, for example, a PID calculation, and examples of the timing at which the calculation is performed and the timing at which the set value is set in the PWM circuit 15 are as shown in FIG.
When the target duty is calculated by PID calculation, the minimum increment of the calculated duty% value is set to 0.3%, and the value obtained by multiplying the calculated duty by 100/3 is set as the target value. Then, the same result as above can be obtained.

  At the timing shown in FIG. 3, the result of the PID calculation in the first N cycles is 19.4 (corresponding to 19.4 × 3 = 58.2% in terms of duty: hereinafter, only the corresponding% value is shown in parentheses. ), The first set value, the second set value, and the third set value are determined as 19 (57%), 20 (60%), and 19 (57%), respectively. Since the increment 1 of the set value corresponds to 3% of the duty and 1% of the duty corresponds to 0.1 μs, the ON time of each PWM signal generated in the next N cycles by each set value is 5. 7 μs, 6.0 μs, and 5.7 μs, and the average on-time is 5.8 μs. This indicates that the average duty is 58%.

  Similarly, when the result of the PID calculation in the second N cycle is 19.6 (58.8%), each of the first set value, the second set value, and the third set value is 19 (57 %), 20 (60%) and 20 (60%). As a result, the ON time of each PWM signal generated in the next N period depending on each set value is 5.7 μs, 6.0 μs, and 6.0 μs, respectively, and the average on time is 5.9 μs. This indicates that the average duty is 59%. As described above, the average duty of the PWM signal in N cycles can be set in increments of 1%.

Next, a method for determining the first set value, the second set value, and the third set value corresponding to the target value will be described.
FIG. 4 is an explanatory diagram for explaining a method of determining N set values in the signal generation circuit 1a according to the first embodiment of the present invention. In the figure, “◯” represents N (N = 3) set values, and “●” represents an average value of M (2 ≦ M ≦ N) set values. Since the average value has no meaning for the first set value, the number of “●” is one less than the number of “◯”.

  For the target value X, first, the closest setting value Y and the second closest setting value Z are specified. In the example of FIG. 4, Y that is larger than X and not larger than ½ or more than X is first identified, and Z is identified as Y−1. Unlike the case shown in FIG. 4, when Y that is smaller than X and not smaller than ½ or less than X is first identified (not shown), Z is identified as Y + 1.

In the first embodiment, N set values are sequentially determined from Y and Z (= Y−1 ) . At that time, the M-th set value is sequentially determined so that the average value from the first set value to the M-th (2 ≦ M ≦ N) set value becomes a value closest to the target value X. Since the first set value is determined before the second set value in anticipation of the average value of the first and second set values being closest to the target value X, the first set value is always Y is determined. In the case of FIG. 4, the candidate value for the second setting value is Y or Z.

When the second set value is determined, it is determined which of the two set values of the second set value and the average value of the first set value is closer to X. In this case, two candidate values are Y or Z (= Y-1), average from the first set value is Y, which is the average value of Y and Y Y, and the Y-1 and Y The value Y-1 / 2 is compared to determine which is closer to X. In the case of FIG. 4, since Y−1 / 2 is closer to X than Y, the second setting value is determined to be Z.

When the third set value is determined, it is determined which of the two candidate values of the third set value, the average value of the second set value and the first set value, is closer to X. In this case, two candidate values of the third set value is Y or Z (= Y-1), the second set value is Z, from the first set value is a Y, Y and Y-1 and is the average value of the Y Y-1/3, and both Y-1 and Y-1 and of the Y-2/3 is an average value of the Y is either closer to X is determined. In the case of FIG. 2, since Y-1 / 3 is closer to X than Y-2 / 3, the third setting value is determined to be Y.

2, 3 and 4, the case where N is 3 has been described, but the same applies to the case where N is 2 or 4 or more. Hereinafter, the operation of the signal generation circuit 1a for determining the N set values described above will be described with reference to a flowchart showing the operation. The following processing is executed by the CPU 11 according to a control program stored in advance in the ROM 12a.
FIG. 5 is a flowchart showing a processing procedure of the CPU 11 that executes the PWM interrupt processing in the signal generation circuit 1a according to the first embodiment of the present invention, and FIG. 6 shows the setting value determination in the first embodiment of the present invention. It is a flowchart which shows the process sequence of CPU11 which concerns on this subroutine.

The loop counter J in FIG. 5, the target value X in FIG. 6, the value Y closest to the target value X , the second closest value Z, the loop counter M, the total value S of M set values, the value Ay, The value Az is stored in the RAM 13a. The initial value of the loop counter J is N. First determined in the processing in FIG. 6, the second and third set values are sequential stored in consecutive addresses in the duty data table 131.

When the interruption of the PWM cycle occurs and the control of the CPU 11 shifts to the processing of FIG. 5, the CPU 11 determines whether or not the loop counter J is N (here, 3) (S10). In the case (S10: YES), J is set to 1 (S11). Then, CPU 11 is the output voltage supplied to the load 4 A / D converter takes in the output voltage value converted by the (detection corresponding to unit) 14 (S12), a voltage based on the output voltage value fetched loop A calculation related to the control is executed (S13), and a target current value is calculated as an operation amount.

Then, CPU 11 may detect the voltage uptake the output current value converted by the A / D converter 14 (S14) of the current detector 27, performs operations according to the current loop control based on the output current value taken (S15) A target value X to be set in the PWM circuit 15 as an operation amount is calculated and stored in the RAM 13a. In order to omit the current loop control, steps S14 and S15 may not be executed. Next, the CPU 11 calls and executes a subroutine relating to setting value determination (S16).

When returning from the subroutine related to setting value determination, the CPU 11 reads the J-th setting value among the N setting values from the duty data table 131 (S17), and sets the read J-th setting value in the register buffer 151. (S18), the process returns to the interrupted routine.
On the other hand, if J is not N in step S10 (S10: NO), the CPU 11 increments J by 1 (S19), and then moves the process to step S17 to set the Jth set value in the register buffer 151. .

Turning to FIG. 6, when a subroutine related to setting value determination is called from the PWM interrupt processing, the CPU 11 specifies the setting value Y closest to the target value X stored in the RAM 13a (S21 : specifying means). And the second closest setting value Z is identified (S22 : corresponding to the identifying means ), and the first setting value is determined to be Y (S23 : corresponding to the determining means ). At this point, Z is specified as either Y + 1 or Y-1. Next, the CPU 11 sets the loop counter M to 1 (S24), and sets the total value S of the M set values to Y (S25).

  Thereafter, the CPU 11 determines whether or not M is N (S26). If N is N (S26: YES), the CPU 11 returns to the called routine. When M is not N (S26: NO), the CPU 11 increments M by 1 (S27), and then calculates (S + Y) / M value Ay (S28) and (S + Z) / M value Az. Is calculated (S29). Ay and Az calculated here are two candidate values that can be an average value of M set values.

Next, the CPU 11 determines whether or not | Ay-X | is equal to or smaller than | Az-X | (S30). Determination here is one of the two candidate values, one is intended to determine whether the close to the target value X. When | Ay−X | is equal to or smaller than | Az−X | (S30: YES), the CPU 11 determines the Mth set value as Y (S31 : equivalent to a determination unit ), and the total value of the M set values. After replacing S with S + Y (S32), the process proceeds to step S26. On the other hand, when | Ay−X | is larger than | Az−X | (S30: NO), the CPU 11 determines the Mth set value as Z (S33 : equivalent to a determination unit ), and sums the M set values. After the value S is replaced with S + Z (S34), the process proceeds to step S26.

In the above-described flowchart, the setting value Z closest to the target value X and the setting value Z closest to the second are specified first, and the value of Z (Y + 1 or Y-1) is stored in the RAM 13a. It is not limited. For example, when determining the Mth set value, an average value from the first set value to the M-1th set value is calculated, and the magnitude relationship between this average value and the target value X is determined. The setting value Y closest to the target value X may be specified each time, and it may be specified each time whether the second closest setting value Z is Y + 1 or Y-1.

Next, a plurality of examples of the N set values determined as described above will be described.
FIG. 7 is a chart showing a list of N set values determined according to the target value in the signal generation circuit 1a according to the first embodiment of the present invention. The target value is represented by a numerical value with two decimal places. Hereinafter, N set values will be listed and described with respect to typical target value ranges. For example, when the target value is in the range of 0.00 to 0.17, the first, second, and third set values are determined as 0, 0, and 0, respectively. In this case, the average value of the N set values is 0.00, the average value of the duty of the PWM signal thereby becomes 0%, and the ON time is 0.0 μs. When the target value is in the range of 0.17 to 0.50, the first, second and third set values are determined as 0, 1 and 0, respectively, and the average value of the N set values is rounded off. Therefore, the average value of the duty of the PWM signal is 1%, and the ON time is 0.1 μs.

When the target value is in the range of 0.50 to 0.83, the first, second, and third set values are determined as 0, 1, and 1, respectively, and the average value of the N set values is 0. The average value of the duty of the PWM signal is 2%, and the ON time is 0.2 μs. When the target value is in the range of 0.83 to 1.17, the first, second, and third set values are determined as 1, 1, and 1, respectively, and the average value of the N set values is 1 The average value of the duty of the PWM signal is 3%, and the ON time is 0.3 μs. Similarly, for each of the three ranges included in the range of the target value from 1.17 to 2.17 , every time the lower limit and upper limit of the target value range are increased by 1, N set value and the average value thereof is determined so that Do increased by 1, increases the average value of the duty is only 3%, the average value of the oN time becomes longer by 0.3 microsecond.

  Particularly in the case corresponding to FIG. 3, when the target value is in the range of 19.17 to 19.50, the first, second, and third set values are determined as 19, 20, and 19, respectively. The average value of the N set values is 19.33, the average value of the duty of the PWM signal is 58%, and the ON time is 5.8 μs. When the target value is in the range of 19.50 to 19.83, the first, second, and third set values are determined as 19, 20, and 20, respectively, and an average value of N set values Is 19.66, the average value of the duty of the PWM signal is 59%, and the ON time is 5.9 μs.

As described above, according to the first embodiment, the CPU 11 functioning as the center of the control unit 10a determines a set value that can be set in the PWM circuit 15 according to the target value X that should be set in the PWM circuit 15. To set. Specifically, the CPU 11 sets the setting value Y closest to the target value X and the setting value closest to the second for every N (= 3) periods of the PWM signal generated by the PWM signal generation unit 153 included in the PWM circuit 15. identify Z, as a result of comparing the magnitude of the size and X of the specified Y and Z, to determine N number of set values by combining Y and Z, 1 single per circumferential phase of the PWM signal Each is set in the PWM circuit 15.
As a result, the ratio of the setting value Y closest to the target value X and the setting value Z closest to the second among the N setting values determined by the CPU 11 is appropriately determined, and thus the average value of the N setting values However, the minimum increment of the value that can be set in the PWM circuit 15 is finely adjusted.
Accordingly, the minimum increment of the value set in the PWM circuit (generator) 15 that periodically generates the PWM signal corresponding to the set value is made substantially smaller than the actual increment with a relatively small processing load. It becomes possible.

Further, according to the first embodiment, for the N set values determined by the CPU 11, the set value Y closest to the target value X is determined as the first set value, and the first set value to the Mth set value ( The determination of the Mth set value is repeated N−1 times so that the average value up to 2 ≦ M ≦ N) is closest to the target value X.
Therefore, the average value of the set values set in the PWM circuit 15 from the first cycle to the cycle is set to the value closest to the target value X in any cycle of the N cycles of the PWM signal. Is possible.

(Embodiment 2)
The first embodiment, while the first set value and the M set value (2 ≦ M ≦ N) is in the form of sequential decision, the second embodiment, the target value of the M setpoint In this mode, N setting values are determined collectively by calculating the number of setting values that are the second closest to the number of setting values.
Since the configuration of the voltage conversion device in the second embodiment is the same as that shown in FIG. 1 in the first embodiment, portions corresponding to those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. .

  FIG. 8 is an explanatory diagram for explaining a method of determining N set values in the signal generation circuit 1a according to the second embodiment of the present invention. For the target value X, first, the closest setting value Y and the second closest setting value Z are specified. In the example of FIG. 8, Y that is smaller than X and not smaller than ½ or less than X is first identified, and Z is identified as Y + 1.

Assuming that all of the first set value to the Nth set value are determined as Y, the average value of all the set values is Y. Next, when only one of the N setting values is determined to be Z (Y + 1 in the case of FIG. 8) instead of Y, the average value of all the setting values is 1 / N with respect to Y. to increase only (or decrease less) (in the case of FIG. 8 increases). Similarly, set value determined as Z is the average value of all the set value 1 / N by increasing (or decreasing low) to every increase by one (in the case of FIG. 8 increases).

Considering that the relationship between the number of set values determined as Z and the average value of all the set values is as described above, the number of set values determined as Z is determined from Y to Z. The magnitude relationship between X and the value obtained by adding (or subtracting) by 1 / N in each direction may be determined each time. More specifically, if the magnitude relationship between X and the value obtained by adding (or subtracting) 1 / N K times to Y is reversed, the value ya added (or subtracted) K times and K−1 What is closer to X is determined by the value yb added (or subtracted) times, and the closer number (K or K-1) may be set as the number of set values determined as Z.

For Specifically, FIG. 8, the magnitude relation between the 1 / N the K-1 times adding (or subtracting) adds further 1 / 2N the value yb (or subtracting) value yc and X with respect to Y What is necessary is just to judge. In the case of FIG. 8 (see the left half of FIG. 8) , K = 2, and it is determined that yc is greater than X. Therefore, the value K−1 (= 1) is determined to be Z. It becomes the number of.

If the above algorithm is viewed from the X side (see the right half of FIG. 8) , the subtraction result xa becomes negative when 1 / N is repeatedly subtracted from the difference x between X and Y and subtracted K times. If the value xc obtained by subtracting 1 / 2N from the value xb obtained by subtracting 1 / N from K-1 times from x is negative, the number of set values determined as Z may be determined. . In the example of FIG. 8, since K = 2 and xc becomes negative, the number of Z is determined to be 1. If xc is positive, the number of Z is determined to be 2.

Note that 1 / 2N is first subtracted from the difference x between X and Y, and Z is determined depending on how many times 1 / N is subtracted from the subtraction result, and the subtraction result becomes negative. The number of values may be determined. If the subtraction result when 1 / 2N is subtracted is negative, the number of Z is determined as 0. If the subtraction result when 1 / N is subtracted K times is negative, the number of Z is determined as K. The This algorithm will be described in the flowchart described later. In the example of FIG. 8, since the subtraction result becomes negative when 1 / N is subtracted once from the result of subtracting 1 / 2N from x, the number of Z is determined to be 1.

Below, operation | movement of the signal generation circuit 1a mentioned above is demonstrated using the flowchart which shows it. The following processing is executed by the CPU 11 according to a control program stored in advance in the ROM 12a.
FIG. 9 is a flowchart showing the processing procedure of the CPU 11 according to the set value determination subroutine in the second embodiment of the present invention. The number K of set values in FIG. 9 and the difference x between X and Y are stored in the RAM 13a. Since the processing procedure of the CPU 11 related to the PWM interrupt processing is the same as that shown in FIG. 5 in the first embodiment, illustration and description thereof are omitted.

When a subroutine related to setting value determination is called from the PWM interrupt processing, the CPU 11 specifies the setting value Y closest to the target value X stored in the RAM 13a (S40 : equivalent to specifying means ) and 2 The set value Z closest to the second is specified (S41 : corresponding to specifying means ), and the number K of set values determined as Z is set to 0 (S42). Thereafter, the CPU 11 calculates a difference x between X and Y (S43), and newly sets a value obtained by subtracting 1 / 2N from the calculated x (S44).

  Next, the CPU 11 determines whether or not x is negative (S45). If negative (S45: YES), the process proceeds to step S49 described later. When x is not negative (S45: NO), the CPU 11 increments the value of K by 1 (S46), and newly sets a value obtained by subtracting 1 / N from x (S47).

Next, the CPU 11 determines whether or not x is negative (S48). If not negative (S48: NO), the process proceeds to step S46. When x is negative (S48: YES) , the CPU 11 is determined to have (value) Y at this time ( corresponding to the determining means), NK set values, and (value) Z. (Corresponding to the determining means) The K set values are stored in the duty data table 131 (S49), and the process returns to the called routine.
In steps S45 and S48, it is determined whether or not x is negative. However, an equal sign may be included in the determination to determine whether x is 0 or less.

Next, a plurality of examples of the N set values determined as described above will be described.
FIG. 10 is a chart showing a list of N set values determined according to the target value in the signal generation circuit 1a according to the second embodiment of the present invention. In FIG. 10, the first setting value, the second setting value, and the third setting value included in the N setting values are arranged in ascending order of numerical values. However, the present invention is not limited to this, and may be arranged in descending order. , They may be arranged in any order.

  The target value and the N set values shown in FIG. 10 are partly in the order of arrangement of the first set value, the second set value, and the third set value, compared to that shown in FIG. 7 in the first embodiment. They are only different, and there is no difference in the numbers themselves in the chart. The average value of the N set values is exactly the same as the value shown in FIG.

  Specifically, if the target value is in the range of 0.17 to 0.50, the first, second, and third set values are determined as 0, 0, and 1, respectively. Is within the range of 1.17 to 0.50, the first, second, and third set values are determined as 1, 1, and 2, respectively. When the target value is within the range of 19.17 to 19.50, the first, second, and third set values are determined to be 19, 19, and 20, respectively.

As described above, according to the second embodiment, for the N set values determined by the control unit 10a, the N set values are set so that the average value of all the N set values is closest to the target value. Determine the setting value.
Therefore, the entire N periods of the signal, it is possible to most value close to the average value of the target value of the set of N set value to the PWM circuit 15.

(Embodiment 3)
In the first embodiment, the N setting values sequentially determined every N cycles are once written in the duty data table 131 included in the RAM 13a and then sequentially read in the PWM cycle. In the third mode, N set values are selected from the contents stored in advance in the duty data table included in the ROM, so that they are determined in batches every N cycles and sequentially read out in the PWM cycle. It is.
FIG. 11 is a block diagram illustrating a configuration example of a voltage conversion apparatus including the signal generation circuit 1b according to Embodiment 3 of the present invention.

Signal generating circuit 1b, Ru microcomputer der having a CPU 11. The CPU 11 is bus-connected to a ROM 12b that stores information such as programs, a RAM 13b that stores temporarily generated information, an A / D converter 14, a PWM circuit 15, and an interrupt controller 16. Of the signal generation circuit 1b, the control unit 10b is the one excluding the PWM circuit 15, but the PWM circuit 15 may be included in the control unit 10b.

  The ROM 12b includes a duty data table (corresponding to a storage unit) 121. The duty data table 121 includes N set values respectively associated with each range of target values shown in FIG. 10 in the second embodiment. Are stored in advance. The duty data table 121 may be included in another memory outside the control unit 10b. From a plurality of sets of N set values stored in the duty data table 121, one set of the first set value, the second set value, and the third set value is determined by an interrupt process every N cycles. .

Unlike the RAM 13a according to the first embodiment, the RAM 13b does not include the duty data table 131. The timing chart for explaining the operation of the signal generation circuit 1b is the same as that shown in FIG. 2 of the first embodiment.
In addition, the same code | symbol is attached | subjected to the location corresponding to Embodiment 1, and the description is abbreviate | omitted.

N set values are determined, for example, in the third period in N periods (N = 3). The first setting value, the second setting value, and the third setting value determined from the contents stored in the duty data table 121 are the interrupt processing in the third period when each setting value is determined, and The data are sequentially read out by the interrupt process in each of the first period and the second period in the N period and set in the register buffer 151.

Hereinafter, the operation of the signal generation circuit 1b for determining the N set values described above will be described with reference to a flowchart showing the operation. The following processing is executed by the CPU 11 according to a control program stored in advance in the ROM 12b.
FIG. 12 is a flowchart showing a processing procedure of the CPU 11 that executes the PWM interrupt processing in the signal generation circuit 1b according to the third embodiment of the present invention. The loop counter J and the target value X in FIG. 12 are stored in the RAM 13b. The initial value of the loop counter J is N.

  Of the processes from step S50 to S58, processes other than step S56 are the same as the processes from step S10 to S18 shown in FIG.

When the interruption of the PWM period occurs and the control of the CPU 11 shifts to the processing of FIG. 12, the CPU 11 determines whether or not the loop counter J is N (here, 3) (S50). In the case (S50: YES), J is set to 1 (S51) . Thereafter, the CPU 11 performs a calculation related to the voltage loop control based on the output voltage and the current loop control based on the output current (S52 to S55).

Next, the CPU 11 collates the contents of the duty data table 121, that is, each range of target values stored in the table with the target value X calculated by the above-described calculation (S56). As a result of the collation, N set values stored in the duty data table 121 corresponding to the range in which the target value X is included are determined set values (corresponding to a determination unit) .

  Next, the CPU 11 reads the Jth set value from the duty data table 121 (S57), sets the read Jth set value in the register buffer 151 (S58), and returns to the interrupted routine.

As described above, according to the third embodiment, the correspondence relationship between the N set values determined in advance so that the average value is closest to the target value X and the range of the target value is as follows. It is stored in the duty data table 121 of the ROM 12b. CPU11, corresponding to the target value X set all-out N pieces of set values to the PWM circuit 15 sequentially reads determined from the duty data table 121 in the interrupt processing.
Therefore, N setting values to be determined according to the target value X can be easily determined when the CPU 11 executes the control.

Further, according to the third embodiment, the CPU 11 included in the control unit 10b sequentially reads N set values from the duty data table 121 and sets them in the PWM circuit 15 by interrupt processing.
Therefore, the contents of the duty data table 121 can be sequentially set in the PWM circuit 15.

Furthermore, according to the first, second, or third embodiment, the voltage conversion circuit 2 converts the voltage by switching according to the duty of the PWM signal generated by the signal generation circuit 1a or 1b, and is based on the converted voltage. By the PWM control, the CPU 11 of the signal generation circuit 1a or 1b calculates a target value to be set in the PWM circuit 15.
Therefore, the signal generation circuit 1a or 1b that can make the minimum increment of the value set in the PWM circuit 15 that periodically generates the PWM signal substantially smaller than the actual increment with a relatively small processing load. When applied to a voltage converter, the accuracy of the output voltage can be improved.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, the technical features described in each embodiment can be combined with each other.

1a, 1b Signal generation circuit 10a, 10b Control unit 11 CPU (identifying means, determining means)
12a, 12b ROM
121 Duty data table (storage unit)
13a, 13b RAM
131 Duty data table 14 A / D converter (detector)
15 PWM circuit (generator)
151 Register Buffer 152 Duty Register 153 PWM Signal Generation Unit 16 Interrupt Controller 2 Voltage Conversion Circuit 26 Drive Circuit 27 Current Detector 3 Battery 4 Load

Claims (7)

A generator that periodically generates a signal having a duty corresponding to a set value; and a controller that sets a settable value that can be set in the generator according to a predetermined value for each cycle of the signal; In a signal generation circuit comprising:
The controller is
Means for specifying a settable value closest to the predetermined value and a settable value closest to the second value every N periods (N is a natural number of 2 or more) of the signal;
Determination means for determining N settable values from among the two settable values to be set in the generation unit based on the two settable values specified by the means and the magnitudes of the predetermined values. A signal generation circuit comprising: and.   The determining means sequentially determines the N settable values so that an average value of M settable values (M is a natural number satisfying 2 ≦ M ≦ N) is closest to the predetermined value. 2. The signal generating circuit according to claim 1, wherein the signal generating circuit is configured as described above.   2. The determination unit according to claim 1, wherein the determination unit determines the N settable values such that an average value of each settable value is closest to the predetermined value. The signal generation circuit described. A storage unit for storing a correspondence between a predetermined value and N settable values;
The storage unit stores N settable values in advance so that an average value of each settable value is closest to a corresponding predetermined value;
The signal generation circuit according to claim 1, wherein the determination unit determines N settable values corresponding to the predetermined value from stored information in the storage unit.   5. The control unit is configured to sequentially read N settable values determined by the determination unit from the storage unit for each period of the signal and set the values in the generation unit. The signal generation circuit described in 1. 6. The signal generation circuit according to claim 1, a voltage conversion circuit for converting a voltage by switching according to a duty of a signal generated by the signal generation circuit, and a voltage converted by the voltage conversion circuit A voltage conversion device comprising a detection unit for detecting
The control unit provided in the signal generation circuit includes a means for calculating the predetermined value by PWM control based on the voltage detected by the detection unit. A generator that periodically generates a signal having a duty corresponding to a set value; and a controller that sets a settable value that can be set in the generator according to a predetermined value for each cycle of the signal; In a method for generating the signal in a signal generation circuit comprising:
For each N periods (N is a natural number of 2 or more) of the signal, a settable value closest to the predetermined value and a settable value closest to the second value are specified,
Based on the two specified settable values and the size of each of the predetermined values, N settable values are determined to be set in the generation unit from the two settable values. Signal generation method.

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