JP2016036180A - Wireless communication device - Google Patents

Abstract

An inverting amplifier circuit capable of outputting a highly accurate amplification result is provided. According to one embodiment, an inverting amplifier circuit 1 amplifies a differential voltage between an input voltage supplied to an inverting input terminal and a reference voltage supplied to a non-inverting input terminal, and outputs an amplified signal. An operational amplifier OPA, a feedback resistor RFBT that negatively feeds back the amplified signal to the inverting input terminal of the operational amplifier OPA, and a first resistance value corresponding to the control signal between the external input terminal INT and the inverting input terminal of the operational amplifier OPA. A variable resistance unit PVIC1 that sets a current path and sets a first bypass path of a second resistance value according to a control signal between a node on the current path and a reference voltage terminal GND to which a reference voltage is supplied; Is provided. [Selection] Figure 3

Description

  The present invention relates to a wireless communication apparatus.

  An amplifier circuit having a function as a filter is provided in the wireless communication terminal. For example, Non-Patent Document 1 discloses an apparatus including an amplifier circuit.

H.-H.Nguyen et al, "84 dB 5.2 mA digitally-controlled variable gain amplifier", Electronics Letters, 2008, Vol.44, No.5, pp.344-345 Aarno Parssinen, "DIRECT CONVERSION RECEIVERS IN WIDE-BAND SYSTEMS", Kluwer Academic Publishers, pp.76-103

  The inventors of the present application have found various problems in developing a semiconductor integrated circuit used for a wireless communication terminal or the like. Each embodiment disclosed in the present application provides, for example, a semiconductor integrated circuit suitable for a wireless communication terminal. Further detailed features will become apparent from the description of the present specification and the accompanying drawings.

  One aspect disclosed in this specification includes a semiconductor integrated circuit, and the semiconductor integrated circuit includes a variable resistance unit that sets a current path and a bypass path in accordance with a control signal.

  According to the embodiment, it is possible to provide a high-quality semiconductor integrated circuit and a wireless communication terminal including the same.

1 is an external view illustrating an example of a wireless communication terminal according to a first embodiment; 1 is an external view illustrating an example of a wireless communication terminal according to a first embodiment; 1 is a block diagram illustrating an example of an internal configuration of a wireless communication terminal according to a first embodiment; 1 is a block diagram illustrating a configuration example of an inverting amplifier circuit according to a first embodiment; 3 is a circuit diagram illustrating a configuration example of a programmable voltage-current converter PVIC1 according to the first embodiment; FIG. It is a figure which shows the relationship between each conduction | electrical_connection state of the some switch element provided in programmable voltage-current converter PVIC1 concerning Embodiment 1, and the voltage gain of an inverting amplifier circuit. FIG. 3 is a block diagram illustrating a configuration example of an inverting amplifier circuit according to a second embodiment; It is a circuit diagram which shows the structural example of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a circuit diagram which shows a T-type resistance attenuator. It is a circuit diagram showing a π-type resistance attenuator. It is a figure which shows the relationship between each conduction | electrical_connection state of the several switch element provided in programmable voltage-current converter PVIC2 concerning Embodiment 2, and the voltage gain of an inverting amplifier circuit. It is a figure which shows the equivalent circuit of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a figure which shows the equivalent circuit of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a figure which shows the equivalent circuit of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a figure which shows the equivalent circuit of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a figure which shows the equivalent circuit of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a figure which shows the equivalent circuit of programmable voltage-current converter PVIC2 concerning Embodiment 2. FIG. It is a figure for demonstrating the effect of the programmable voltage current converter PVIC2 concerning Embodiment 2. FIG. FIG. 6 is a block diagram illustrating a configuration example of an inverting amplifier circuit according to a third embodiment; It is a circuit diagram which shows the structural example of programmable voltage-current converter PVIC3 concerning Embodiment 3. FIG. FIG. 6 is a block diagram illustrating a configuration example of an inverting amplifier circuit according to a fourth embodiment; It is a circuit diagram which shows the structural example of programmable voltage-current converter PVIC4 concerning Embodiment 4. FIG. It is a figure which shows the structural example of the inverting amplifier circuit 10 concerning the concept before reaching embodiment. It is a figure which shows the structural example of the inverting amplifier circuit 20 concerning the concept before reaching embodiment. It is a figure which shows the relationship between each conduction | electrical_connection state of the several switch element provided in programmable voltage-current converter PVIC20, and the voltage gain of an inverting amplifier circuit.

<Preliminary examination by the inventors>
Prior to the description of the embodiments, the contents examined in advance by the present inventors will be described.

  In the past, in wireless signal processing circuits mounted on wireless communication terminals, etc., a plurality of functional blocks (amplifier for amplifying signals, mixer for converting signal frequency, filter for passing only a desired band of signals, etc.) are individually provided. It was provided as a part. However, due to recent improvements in semiconductor technology, it has become possible to incorporate many of the plurality of functional blocks constituting the wireless signal processing circuit in one semiconductor chip. Furthermore, wireless signal processing circuits that can support a plurality of wireless access systems have become common for mobile phones and the like. Such a radio signal processing circuit built into one or several semiconductor chips is capable of receiving high-frequency signals received from an antenna with high quality (low noise, high linearity, suppressing signals in bands other than desired, etc.). Convert to low frequency band signal.

  In order to realize the wireless signal processing circuit at a low cost, it is necessary to incorporate many of the plurality of functional blocks constituting the wireless signal processing circuit in one semiconductor chip. One of the obstacles to this purpose is the incorporation of a filter circuit that suppresses signals in a band other than the desired band into a semiconductor chip. In general, this filter circuit is configured using a SAW (Surface Acoustic Wave) filter, a dielectric filter, or the like, and suppresses signals present in bands other than the desired band. However, the SAW filter and the dielectric filter cannot be built in the semiconductor chip due to their configurations.

  A radio signal processing circuit made up of individual components is configured by a superheterodyne system and requires a SAW filter or a dielectric filter, but these cannot be built in a semiconductor chip. Therefore, when a radio signal processing circuit manufactured by a semiconductor is configured by a superheterodyne method, a SAW filter or a dielectric filter is externally attached to the outside of the semiconductor chip. As a result, the number of parts and the mounting area increase.

  Therefore, although the absolute values of the component constants between semiconductor chips vary, the advantage of the semiconductor circuit that the relative values of the component constants within one semiconductor chip match with high precision is required, and a SAW filter or dielectric filter is required. A wireless signal processing circuit system that does not have been proposed has been proposed. Examples of this method include a zero IF method and a low IF method. Neither method requires an external SAW filter or dielectric filter, and suppression of signals existing in a band other than the desired band is performed by a filter that can be incorporated in a semiconductor. However, some filters may need to be externally attached depending on the radio system or system requirements.

  For basic principles such as the zero IF method and the low IF method, see, for example, Non-Patent Document 2. The zero IF method and the low IF method have a common operational characteristic in that one signal is decomposed and processed into two components, an I component and a Q component. By inputting two local oscillation signals (local signals) having the same frequency and a 90-degree phase difference and a radio signal received by an antenna or the like to an orthogonal mixer, the radio signal received by the antenna or the like becomes I Decomposed into component and Q component.

  The radio signal processing circuit is an amplifier circuit that amplifies the output result of the quadrature mixer after the quadrature mixer, and operates the amplifier circuit within the linear operation range by attenuating the output signal of the amplifier circuit. At least an attenuator (attenuator) and a channel filter that passes only a desired channel band are provided.

  With reference to such semiconductor technology, the circuits shown in FIGS. 22 and 23 were studied. FIG. 22 is a diagram illustrating a configuration example of the inverting amplifier circuit (semiconductor integrated circuit) 10 according to the concept prior to the embodiment. FIG. 23 is a diagram illustrating a configuration example of the inverting amplifier circuit (semiconductor integrated circuit) 20 according to the concept before reaching the embodiment. These inverting amplifier circuits 10 and 20 are used as part of the radio signal processing circuit.

<Inverting Amplifying Circuit 10 According to the Concept Prior to the Embodiment>
First, the inverting amplifier circuit 10 shown in FIG. 22 will be described. The inverting amplifier circuit 10 is a circuit that amplifies the output result Vin of a mixer (not shown) supplied to the input terminals INT and INB and outputs the amplified result Vout from the output terminals OUTT and OUTB.

  The inverting amplifier circuit 10 shown in FIG. 22 includes an operational amplifier (amplifier circuit) OPA, feedback resistors RFBT and RFBB, and a voltage / current converter PVIC10.

  The input terminals IT and IB of the voltage / current converter PVIC10 are connected to the input terminals INT and INB of the inverting amplifier circuit 10, respectively. The output terminals OT and OB of the voltage / current converter PVIC10 are connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier OPA, respectively. The non-inverting output terminal and the inverting output terminal of the operational amplifier OPA are connected to the output terminals OUTT and OUTB of the inverting amplifier circuit 10, respectively. The feedback resistor RFBT is provided between the non-inverting output terminal and the inverting input terminal of the operational amplifier OPA. The feedback resistor RFBB is provided between the inverting output terminal and the non-inverting input terminal of the operational amplifier OPA.

  The voltage / current converter PVIC10 includes resistance elements R101T and R101B. In the voltage-current converter PVIC10, the resistance element R101T is provided between the input terminal IT and the output terminal OT. The resistance element R101B is provided between the input terminal IB and the output terminal OB.

In the following, the resistance element R101T, the resistance values of R101B is described as an example case where _{R 1.}

  Next, the detailed operation of the inverting amplifier circuit 10 shown in FIG. 22 will be described.

  The output terminals OT and OB of the voltage / current converter PVIC10 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA to which negative feedback is applied by the feedback resistors RFBT and RFBB, respectively. Therefore, the output terminals OT and OB of the voltage / current converter PVIC10 show the same potential.

  At this time, the output current Iin10 of the voltage / current converter PVIC10 is represented by the following equation (1), where the current flowing from the voltage / current converter PVIC10 toward the operational amplifier OPA is a positive current.

_{Iin10 = I OT -I OB = (} V INT -V INB) / R 1 ··· (1)

I _OT and I _OB indicate currents flowing through the output terminals OT and OB of the voltage / current converter PVIC10, respectively. V _INT and V _INB indicate the potentials of the input terminals INT and INB of the inverting amplifier circuit 10, respectively.

  This current Iin10 is converted into a voltage by feedback resistors RFBT and RFBB, and then output from output terminals OUTT and OUTB. Therefore, the voltage gain G10 of the inverting amplifier circuit 10 including the voltage-current converter PVIC10 is expressed as the following formula (2).

G10 = (V _OUTT −V _OUTB ) / (V _INT −V _INB )
= −Iin10 × R ₂ / (V _INT −V _INB )
= −R ₂ / R ₁ (2)

V _OUTT and V _OUTB indicate the potentials of the output terminals OUTT and OUTB, respectively.

<Inverting Amplifying Circuit 20 According to the Concept Prior to the Embodiment>
Next, the inverting amplifier circuit 20 shown in FIG. 23 will be described. The inverting amplifier circuit 20 includes a programmable voltage-current converter (variable resistance unit) PVIC 20 instead of the voltage-current converter PVIC 10 as compared with the inverting amplifier circuit 10 shown in FIG. Since the other circuit configuration and operation of the inverting amplifier circuit 20 are the same as those of the inverting amplifier circuit 10, description thereof is omitted.

  The programmable voltage-current converter PVIC20 controls the voltage gain of the inverting amplifier circuit 20 in a programmable manner. For example, the programmable voltage-current converter PVIC 20 programmableally attenuates the amplification result Vout of the inverting amplifier circuit 20 and operates the inverting amplifier circuit 20 within the linear operation range.

  The programmable voltage-current converter PVIC20 includes resistance elements R201T to R204T, R201B to R204B, and switch elements S201T to S204T, R201B to R204B.

  In the programmable voltage-current converter PVIC20, the resistance elements R201T to R204T are provided in parallel between the input terminal IT and the output terminal OT. Switch elements S201T to S204 are connected in series to resistance elements R201T to R204T, respectively. The resistive elements R201B to R201B are provided in parallel between the input terminal IB and the output terminal OB. Switch elements S201B to S204B are connected in series to resistance elements R201B to R204B, respectively.

In the following, the resistance element R201T, the resistance values of R201B is _{R 1,} the resistance element R202T, 2R ₁ is the resistance values of R202B, resistive element R203T, the resistance values of R203B is 4R _1, the resistance element R204T , the resistance values of R204B is described an example where a 8R _1.

  Programmable voltage-current converter PVIC20 controls each conduction | electrical_connection state of switch element S201T-S204T, S201B-S204B based on the control signal from a control circuit (not shown), and is input terminal IT and output terminal OT. And the combined resistance between the input terminal IB and the output terminal OB are controlled in a programmable manner. As a result, the inverting amplifier circuit 20 can amplify the input voltage Vin with a desired voltage gain and output it as an amplification result Vout. As a result, the inverting amplifier circuit 20 can operate within the linear operation range with the amplification result Vout attenuated, for example.

  Next, the detailed operation of the inverting amplifier circuit 20 shown in FIG. 23 will be described.

  Each switch element S201T-S204T, S201B-S204B is comprised by FET (Field Effect Transistor), such as MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) and JFET (Junction Field Effect Transistor), for example. Therefore, it is preferable that the on-resistances of the switch elements S201T to S204T and S201B to S204B are adjusted so as to satisfy the following expression (3). Thereby, the influence of element variation, temperature characteristics, etc. is reduced.

  RS204 = 2 × RS203 = 4 × RS202 = 8 × RS201 (3)

  RS201 to RS204 indicate on-resistances of the switch elements S201T to S204T, respectively, and indicate on-resistances of the switch elements S201B to S204B, respectively.

  FIG. 24 is a diagram illustrating the relationship between the conduction state of each of the plurality of switch elements provided in the programmable voltage-current converter PVIC 20 and the voltage gain of the inverting amplifier circuit 20.

First, when the switch elements S201T and S201B are on and the other switch elements are off, the voltage-current conversion gain gm20 of the programmable voltage-current converter PVIC20 is the voltage-current converter shown in FIG. It becomes 1 / R ₁ which is the same as the voltage-current conversion gain gm10 of the PVIC ₁₀ . At this time, the voltage gain G20 of the inverting amplifier circuit 20 is 20 × log10 (| G20 |) dB, which is the same as the voltage gain G10 of the inverting amplifier circuit 10.

Next, when the switch elements S202T and S202B are on and the other switch elements are off, the voltage-current conversion gain gm20 of the programmable voltage-current converter PVIC20 is 1 / (2R ₁ ). . That is, the voltage / current conversion gain gm20 is ½ of the voltage / current conversion gain gm10. At this time, the voltage gain G20 of the inverting amplifier circuit 20 is 20 × log10 (| G20 | / 2) dB. That is, the voltage gain G20 of the inverting amplifier circuit 20 at this time is attenuated by about 6 dB from the voltage gain G10 of the inverting amplifier circuit 10.

Next, when the switch elements S203T and S203B are on and the other switch elements are off, the voltage-current conversion gain gm20 of the programmable voltage-current converter PVIC20 is 1 / (4R ₁ ). . That is, the voltage-current conversion gain gm20 is 1/4 of the voltage-current conversion gain gm10. At this time, the voltage gain G20 of the inverting amplifier circuit 20 is 20 × log10 (| G20 | / 4) dB. That is, the voltage gain G20 of the inverting amplifier circuit 20 at this time is attenuated by about 12 dB from the voltage gain G10 of the inverting amplifier circuit 10.

Next, when the switch elements S204T and S204B are on and the other switch elements are off, the voltage-current conversion gain gm20 of the programmable voltage-current converter PVIC20 is 1 / (8R ₁ ). . That is, the voltage / current conversion gain gm20 is 1/8 of the voltage / current conversion gain gm10. At this time, the voltage gain G20 of the inverting amplifier circuit 20 is 20 × log10 (| G20 | / 8) dB. That is, the voltage gain G20 of the inverting amplifier circuit 20 at this time is attenuated by about 18 dB from the voltage gain G10 of the inverting amplifier circuit 10.

  Thus, the inverting amplifier circuit 20 including the programmable voltage-current converter PVIC 20 can control the voltage gain in a programmable manner.

  However, in the inverting amplifier circuit 20 shown in FIG. 23, the programmable voltage-current converter PVIC20 is connected from both input terminals of the operational amplifier OPA in accordance with the switching of the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC20. Impedance changes as seen. Therefore, the inverting amplifier circuit 20 shown in FIG. 23 has a problem that the frequency characteristic of the amplification result Vout changes unintentionally due to the phase rotation of the feedback signal. Further, the inverting amplifier circuit 20 shown in FIG. 23 has a problem that the voltage gain of the amplifier circuit in the preceding stage changes unintentionally due to a change in impedance viewed from the amplifier circuit (not shown) in the preceding stage.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
First, with reference to FIG. 1A and FIG. 1B, an outline of a radio communication terminal suitable as an electronic apparatus to which the inverting amplifier circuit (semiconductor integrated circuit) according to the present embodiment is applied will be described. 1A and 1B are external views showing a configuration example of a wireless communication terminal 500. FIG. 1A and 1B show a case where the wireless communication terminal 500 is a smartphone. However, the wireless communication terminal 500 may be another wireless communication terminal such as a future phone (for example, a foldable mobile phone terminal), a mobile game terminal, a tablet PC (Personal Computer), or a notebook PC. As a matter of course, the inverting amplifier circuit (semiconductor integrated circuit) according to the present embodiment can also be applied to devices other than wireless communication terminals.

  FIG. 1A shows one main surface (front surface) of a housing 501 forming the wireless communication terminal 500. A display device 502, a touch panel 503, some operation buttons 504, and a camera device 505 are disposed on the front surface of the housing 501. On the other hand, FIG. 1B shows the other main surface (back surface) of the housing 501. A camera device 506 is disposed on the back surface of the housing 501.

  The display device 502 is an LCD (Liquid Crystal Display), an OLED (Organic Light-Emitting Diode) display, or the like, and is arranged such that its display surface is positioned on the front surface of the housing 501. The touch panel 503 is disposed so as to cover the display surface of the display device 502 or is disposed on the back surface side of the display device 502, and detects a contact position on the display surface by the user. That is, the user can intuitively operate the wireless communication terminal 500 by touching the display surface of the display device 502 with a finger or a dedicated pen (generally called a stylus). The operation button 504 is used for an auxiliary operation on the wireless communication terminal 500. Note that such operation buttons may not be provided depending on the wireless communication terminal.

  The camera device 506 is a main camera arranged so that its lens unit is located on the back surface of the housing 501. On the other hand, the camera device 505 is a sub camera arranged so that its lens unit is located on the front surface of the housing 501. Depending on the wireless communication terminal, such a sub camera may not be provided.

  Next, with reference to FIG. 2, an internal configuration of radio communication terminal 500 according to the present embodiment will be described. FIG. 2 is a block diagram illustrating an example of an internal configuration of the wireless communication terminal 500 according to the present embodiment. As illustrated in FIG. 2, the wireless communication terminal 500 includes an application processor 601, a baseband processor 602, an RF (Radio Frequency) subsystem 603, a memory 604, a battery 605, a power management integrated circuit (PMIC) 606, A display unit 607, a camera unit 608, an operation input unit 609, an audio IC 610, a microphone 611, and a speaker 612 are included.

  The application processor 601 reads a program stored in the memory 604 and performs processing for realizing various functions of the wireless communication terminal 500. For example, the application processor 601 executes an OS (Operating System) program from the memory 604 and also executes an application program using the OS program as an operation board.

  The baseband processor 602 performs baseband processing including coding (for example, error correction coding such as convolutional code and turbo code) processing or decoding processing on data transmitted and received by the wireless communication terminal 500. More specifically, the baseband processor 602 receives transmission data from the application processor 601, performs encoding processing on the received transmission data, and transmits it to the RF subsystem 603. In addition, the baseband processor 602 receives received data from the RF subsystem 603, performs a decoding process on the received received data, and transmits it to the application processor 601.

  The RF subsystem 603 performs modulation processing or demodulation processing on data transmitted and received by the wireless communication terminal 500. More specifically, the RF subsystem 603 modulates transmission data received from the baseband processor 602 with a carrier wave to generate a transmission signal, and outputs the transmission signal via an antenna. The RF subsystem 603 receives a reception signal via an antenna, demodulates the reception signal with a carrier wave to generate reception data, and transmits the reception data to the baseband processor 602.

  The memory 604 stores programs and data used by the application processor 601. The memory 604 includes a non-volatile memory that retains stored data even when the power is turned off, and a volatile memory that clears stored data when the power is turned off.

  The battery 605 is a battery and is used when the wireless communication terminal 500 operates without using an external power source. Note that the wireless communication terminal 500 may use the power source of the battery 605 even when an external power source is connected. As the battery 605, a secondary battery is preferably used.

  The power management IC 606 generates an internal power supply from the battery 605 or an external power supply. This internal power supply is given to each block of the wireless communication terminal 500. At this time, the power management IC 606 controls the voltage of the internal power supply for each block that receives the supply of the internal power supply. The power management IC 606 performs voltage control of the internal power supply based on an instruction from the application processor 601. Further, the power management IC 606 can control supply and interruption of internal power for each block. The power management IC 606 also controls charging to the battery 605 when external power is supplied.

  The display unit 607 is, for example, a liquid crystal display device, and displays various images according to processing in the application processor 601. The image displayed on the display unit 607 represents a user interface image, a camera image, a moving image, or the like that gives an operation instruction to the wireless communication terminal 500 by the user.

  The camera unit 608 acquires an image in accordance with an instruction from the application processor. The operation input unit 609 is a user interface that is operated by a user to give an operation instruction to the wireless communication terminal 500. The audio IC 610 decodes the audio data transmitted from the application processor 601 to drive the speaker 612, encodes audio information obtained from the microphone 611, generates audio data, and outputs the audio data to the application processor 601. To do.

<Configuration Example of Inversion Amplifier Circuit 1 According to First Embodiment>
FIG. 3 is a diagram illustrating a configuration example of the inverting amplifier circuit (semiconductor integrated circuit) 1 according to the first embodiment. The inverting amplifier circuit 1 according to the present embodiment sets a current path through which a current having a desired voltage-current conversion gain flows by switching the conduction states of the plurality of switch elements in a programmable manner, and the voltage-current conversion gain. And a programmable voltage-current converter for setting a detour path for detouring the current that is no longer necessary based on the above. Thus, the inverting amplifier circuit 1 according to the present embodiment can output a highly accurate amplification result Vout while suppressing fluctuations in the input / output impedance of the programmable voltage-current converter. This will be specifically described below. Note that the inverting amplifier circuit 1 shown in FIG. 3 is applied to, for example, the RF subsystem 603 in the wireless communication terminal 500 shown in FIG.

  The inverting amplifier circuit 1 shown in FIG. 3 includes an operational amplifier (amplifier circuit) OPA, a feedback resistor (first feedback resistor) RFBT, a feedback resistor (second feedback resistor) RFBB, and a programmable voltage-current converter (variable resistor unit). PVIC1 is provided.

  The inverting amplifier circuit 1 amplifies an output result Vin of a mixer (not shown) supplied to input terminals (first and second external input terminals) INT and INB, and outputs an amplification result (differential amplified signal) Vout as an output terminal. Output from OUTT and OUTB. The programmable voltage-current converter PVIC1 controls the voltage gain of the inverting amplifier circuit 1 by switching the internal combined resistance in a programmable manner. Thereby, for example, the programmable voltage-current converter PVIC1 programmableally attenuates the amplification result Vout of the inverting amplifier circuit 1 and operates the inverting amplifier circuit 1 within the linear operation range.

  The input terminals IT and IB of the programmable voltage-current converter PVIC1 are connected to the input terminals INT and INB of the inverting amplifier circuit 1, respectively. The output terminals OT and OB of the programmable voltage-current converter PVIC1 are connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier OPA, respectively. The non-inverting output terminal and the inverting output terminal of the operational amplifier OPA are connected to the output terminals OUTT and OUTB of the inverting amplifier circuit 1, respectively. The feedback resistor RFBT is provided between the non-inverting output terminal and the inverting input terminal of the operational amplifier OPA. The feedback resistor RFBB is provided between the inverting output terminal and the non-inverting input terminal of the operational amplifier OPA.

In the present embodiment, a case where the resistance values of the feedback resistors RFBT and RFBB are R ₂ will be described as an example.

  FIG. 4 is a circuit diagram illustrating a specific configuration example of the programmable voltage-current converter PVIC1. The programmable voltage-current converter PVIC1 includes resistance elements (first resistance elements) R11T to R14T, resistance elements (second resistance elements) R11B to R14B, resistance elements (third resistance elements) R21T to R23T, R21B to R23B, switch elements. (First switch elements) S11T to S14T, switch elements (second switch elements) S11B to S14B, and switch elements (third switch elements) S21T to S23T, S21B to S23B.

  One end of each of the resistance elements R11T to R14T is connected to the input terminal IT. The other ends of the resistor elements R11T to R14T are connected to the first terminals of the switch elements S11T to S14T, respectively. The second terminals of the switch elements S11T to S14T are connected to the output terminal OT via the node N11T. The third terminals of the switch elements S11T to S13T are connected to a node (common node) N12. One end of each of the resistance elements R11B to R14B is connected to the input terminal IB. The other ends of the resistance elements R11B to R14B are connected to the first terminals of the switching elements S11B to S14B, respectively. The second terminals of the switch elements S11B to S14B are connected to the output terminal OB via the node N11B. The third terminals of the switch elements S11B to S13B are connected to a node (common node) N12.

  Resistance elements R21T and R21B are connected in series between output terminals OT and OB. Resistance elements R22T and R22B are connected in parallel to resistance elements R21T and R21B. Resistance elements R23T and R23B are connected in parallel to resistance elements R21T and R21B. Switch elements S21T and S21B are connected in series to resistance elements R21T and R21B. Switch elements S22T and S22B are connected in series to resistance elements R22T and R22B. Switch elements S23T and S23B are connected in series to resistance elements R23T and R23B.

In the present embodiment, the resistance values of the resistance elements R11T and R11B are 2R ₁ , the resistance values of the resistance elements R12T and R12B are 4R ₁ , the resistance values of the resistance elements R13T and R13B are 8R ₁ , and the resistance elements The resistance values of R14T and R14B are 8R ₁ , the resistance values of resistance elements R21T and R21B are 2R ₁ , the resistance values of resistance elements R22T and R22B are 4R ₁ , and the resistance values of resistance elements R23T and R23B A case where is 8R ₁ will be described as an example.

  Each switch element S11T-S14T, S11B-S14B, S21T-S23T, S21B-S23B is comprised by FET (Field Effect Transistor), such as MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) and JFET (Junction Field Effect Transistor), for example. Is done. Therefore, it is preferable that the on-resistances of the switch elements S11T to S14T, S11B to S14B, S21T to S23T, and S21B to S23B are adjusted so as to satisfy the following expression (4). Thereby, the influence of element variation, temperature characteristics, etc. is reduced.

RS14 = RS13 = 2 × RS12 = 4 × RS11
= RS23 = 2 × RS22 = 4 × RS21 (4)

  RS11 to RS14 indicate on-resistances of the switch elements S11T to S14T, respectively, and indicate on-resistances of the switch elements S11B to S14B, respectively. RS21 to RS23 indicate the on-resistances of the switch elements S21T to S23T, respectively, and the on-resistances of the switch elements S21B to S23B, respectively.

  As will be described in detail later, the switch elements S14T and S14B are not necessarily provided because they are always on. However, the switch elements S14T and S14B are preferably provided because they are effective in reducing the influence of element variations and temperature characteristics.

  Programmable voltage-current converter PVIC1 controls each conduction state of switch elements S11T-S14T, S11B-S14B and switch elements S21T-S23T, S21B-S23B based on a control signal from a control circuit (not shown). The combined resistance between the input terminal IT and the output terminal OT and the combined resistance between the input terminal IB and the output terminal OB are controlled in a programmable manner. As a result, the inverting amplifier circuit 1 can amplify the input voltage Vin with a desired voltage gain and output it as an amplification result Vout.

<Operation of Inverting Amplifying Circuit 1 According to First Embodiment>
Next, the operation of the inverting amplifier circuit 1 according to the present embodiment will be described in detail.

  FIG. 5 is a diagram illustrating the relationship between the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC1 and the voltage gain of the inverting amplifier circuit 1.

  Hereinafter, the switch elements S11T and S11B are collectively referred to as a switch element S11. The switch elements S12T and S12B are collectively referred to as a switch element S12. The switch elements S13T and S13B are collectively referred to as a switch element S13. The switch elements S14T and S14B are collectively referred to as a switch element S14. The switch elements S21T and S21B are collectively referred to as a switch element S21. The switch elements S22T and S22B are collectively referred to as a switch element S22. The switch elements S23T and S23B are collectively referred to as a switch element S23.

(Operation of Inversion Amplifier Circuit 1 in State A)
First, the first and second terminals of the switch elements S11 to S13 are turned on (denoted as “1-2” in the drawing), the switch element S14 is turned on (short), and the switch elements S21 to S23 are turned off ( open) (hereinafter also referred to as state A), the operation of the inverting amplifier circuit 1 will be described.

In the state A, the voltage-current conversion gain gm1 of the programmable voltage-current converter PVIC1 is 1 / R ₁ which is the same as the voltage-current conversion gain gm10 of the voltage-current converter PVIC10 shown in FIG. The voltage gain G1 of the inverting amplifier circuit 1 at this time is 20 × log10 (| G1 |) dB, which is the same as the voltage gain G10 of the inverting amplifier circuit 10.

  More specifically, in the state A, the resistance elements R11T to R14T are connected in parallel between the input terminal IT and the node N11T (output terminal OT). The resistance elements R11B to R14B are connected in parallel between the input terminal IB and the node N11B (output terminal OB). Therefore, the combined resistance RtotalT when the input terminal IT is viewed from the node N11T and the combined resistance RtotalB when the input terminal IB is viewed from the node N11B are expressed as the following Expression (5).

RtotalT = RtotalB = R ₁ (5)

  In the state A, since the switch elements S21 to S23 are off, the output current Iin1 of the programmable voltage-current converter PVIC1 is a positive current flowing from the programmable voltage-current converter PVIC1 toward the operational amplifier OPA. Assuming current, it is expressed as the following formula (6).

_{Iin1 = I OT -I OB = (} V INT -V INB) / R 1 ··· (6)

  The current Iin1 is converted into a voltage by the feedback resistors RFBT and RFBB, and then output from the output terminals OUTT and OUTB. Therefore, the voltage gain G1 of the inverting amplifier circuit 1 in the state A is expressed as the following equation (7).

G1 = (V _OUTT −V _OUTB ) / (V _INT −V _INB )
= −Iin1 × R ₂ / (V _INT −V _INB )
= −R ₂ / R ₁ (7)

  Here, the output terminals OT and OB of the programmable voltage-current converter PVIC1 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA to which negative feedback is applied by the feedback resistors RFBT and RFBB, respectively. Therefore, the output terminals OT and OB of the programmable voltage-current converter PVIC1 exhibit the same potential (that is, they are virtually short-circuited). Therefore, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB is twice that of RtotalT or RtotalB. That is, the following formula (8) is established.

RtotalI = 2R ₁ (8)

  On the other hand, the input terminals IT and IB of the programmable voltage-current converter PVIC1 are connected to an amplifier circuit (not shown) that is so small that the output impedance can be ignored, for example. Therefore, the input terminals IT and IB of the programmable voltage-current converter PVIC1 have the same potential. Therefore, the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB is twice that of RtotalT or RtotalB. That is, the following formula (9) is established.

RtotalO = 2R ₁ (9)

(Operation of Inversion Amplifier Circuit 1 in State B)
Next, the first and third terminals of the switch element S11 are turned on (denoted as “1-3” in the figure), the first and second terminals of the switch elements S12 and S13 are turned on, the switch elements S14, The operation of the inverting amplifier circuit 1 when S21 is on and the switch elements S22 and S23 are off (hereinafter also referred to as state B) will be described.

In the state B, the voltage-current conversion gain gm1 of the programmable voltage-current converter PVIC1 is 1 / (2R ₁ ). That is, the voltage / current conversion gain gm1 is ½ of the voltage / current conversion gain gm10. Further, the voltage gain G1 of the inverting amplifier circuit 1 at this time is 20 × log10 (| G1 | / 2) dB. That is, the voltage gain G1 of the inverting amplifier circuit 1 at this time is attenuated by about 6 dB from the voltage gain G10 of the inverting amplifier circuit 10.

  More specifically, in the state B, the resistance elements R12T to R14T are connected in parallel between the input terminal IT and the node N11T (output terminal OT). The resistance elements R12B to R14B are connected in parallel between the input terminal IB and the node N11B (output terminal OB). On the other hand, the resistance elements R11T and R11B are connected in series between the input terminals IT and IB. The resistance elements R21T and R21B are connected in series between the output terminals OT and OB.

  Therefore, the combined resistance RtotalT when the input terminal IT is viewed from the node N11T and the combined resistance RtotalB when the input terminal IB is viewed from the node N11B are expressed as the following Expression (10).

RtotalT = RtotalB = 2R ₁ (10)

  Therefore, the voltage gain G1 of the inverting amplifier circuit 1 in the state B is expressed as the following equation (11).

G1 = −R ₂ / (2R ₁ ) (11)

  Here, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB is equal to twice RtotalT or RtotalB and the resistance elements R11T and R11B connected in series. Is expressed as the following equation (12).

RtotalI = 2R ₁ (12)

  On the other hand, the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB is equal to twice RtotalT or RtotalB and the resistance elements R21T and R21B connected in series. It is expressed as the following formula (13).

RtotalO = 2R ₁ (13)

(Operation of the inverting amplifier circuit 1 in the state C)
Next, the first and third terminals of the switch elements S11 and S12 are turned on, the first and second terminals of the switch element S13 are turned on, the switch elements S21, S22, and S14 are turned on, and The operation of the inverting amplifier circuit 1 when the switch element S23 is off (hereinafter also referred to as state C) will be described.

In the state C, the voltage-current conversion gain gm1 of the programmable voltage-current converter PVIC1 is 1 / (4R ₁ ). That is, the voltage-current conversion gain gm1 is 1/4 of the voltage-current conversion gain gm10. At this time, the voltage gain G1 of the inverting amplifier circuit 1 is 20 × log10 (| G1 | / 4) dB. That is, the voltage gain G1 of the inverting amplifier circuit 1 at this time is attenuated by about 12 dB from the voltage gain G10 of the inverting amplifier circuit 10.

  More specifically, in the state C, the resistance elements R13T and R14T are connected in parallel between the input terminal IT and the node N11T (output terminal OT). The resistance elements R13B and R14B are connected in parallel between the input terminal IB and the node N11B (output terminal OB). On the other hand, the resistance elements R11T and R11B are connected in series between the input terminals IT and IB. The resistance elements R12T and R12B are connected in series between the input terminals IT and IB. The resistance elements R21T and 21B are connected in series between the output terminals OT and OB. The resistance elements R22T and R22B are connected in series between the output terminals OT and OB.

  Therefore, the combined resistance RtotalT when the input terminal IT is viewed from the node N11T and the combined resistance RtotalB when the input terminal IB is viewed from the node N11B are expressed as the following Expression (14).

RtotalT = RtotalB = 4R ₁ (14)

  Therefore, the voltage gain G1 of the inverting amplifier circuit 1 in the state C is expressed as the following equation (15).

G1 = −R ₂ / (4R ₁ ) (15)

  Here, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB is two times Rtotal or RtotalB, resistance elements R11T and R11B connected in series, and resistance elements R12T and R12B connected in series. Are connected in parallel, and are expressed as the following Expression (16).

RtotalI = 2R ₁ (16)

  On the other hand, the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB is two times RtotalT or RtotalB, resistance elements R21T and R21B connected in series, and resistance elements R22T and R22B connected in series. Are connected in parallel, it is expressed as the following equation (17).

RtotalO = 2R ₁ (17)

(Operation of the inverting amplifier circuit 1 in the state D)
Next, the inverting amplifier circuit 1 when the first and third terminals of the switch elements S11 to S13 are ON and the switch elements S21 to S23 and SS14 are ON (hereinafter also referred to as state D). Will be described.

In the state D, the voltage-current conversion gain gm1 of the programmable voltage-current converter PVIC1 is 1 / (8R ₁ ). That is, the voltage-current conversion gain gm1 is 1/8 of the voltage-current conversion gain gm10. At this time, the voltage gain G1 of the inverting amplifier circuit 1 is 20 × log10 (| G1 | / 8) dB. That is, the voltage gain G1 of the inverting amplifier circuit 1 at this time is attenuated by about 18 dB from the voltage gain G10 of the inverting amplifier circuit 10.

  More specifically, in the state D, the resistance element R14T is connected in parallel between the input terminal IT and the node N11T (output terminal OT). The resistor element R14B is connected in parallel between the input terminal IB and the node N11B (output terminal OB). On the other hand, the resistance elements R11T and R11B, the resistance elements R12T and R12B, and the resistance elements R13T and R13B are connected in series between the input terminals IT and IB, respectively. The resistance elements R21T and R21B, the resistance elements R22T and R22B, and the resistance elements R23T and R23B are connected in series between the output terminals OT and OB, respectively.

  Therefore, the combined resistance RtotalT when the input terminal IT is viewed from the node N11T and the combined resistance RtotalB when the input terminal IB is viewed from the node N11B are expressed as the following Expression (18).

RtotalT = RtotalB = 8R ₁ (18)

  Therefore, the voltage gain G1 of the inverting amplifier circuit 1 in the state D is expressed by the following equation (19).

G1 = −R ₂ / (8R ₁ ) (19)

  Here, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB is two times Rtotal or RtotalB, resistance elements R11T and R11B connected in series, and resistance elements R12T and R12B connected in series. Since the resistor elements R13T and R13B connected in series are connected in parallel, the following expression (20) is obtained.

RtotalI = 2R ₁ (20)

  On the other hand, the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB is two times RtotalT or RtotalB, resistance elements R21T and R21B connected in series, and resistance elements R22T and R22B connected in series. Since the resistance elements R23T and R23B connected in series are connected in parallel, the following expression (21) is obtained.

RtotalO = 2R ₁ (21)

  As described above, the programmable voltage-current converter PVIC1 according to the present embodiment sets a current path through which a current having a desired voltage-current conversion gain gm1 flows by switching the conduction states of the plurality of switch elements in a programmable manner. At the same time, a detour path (a path of the node N12 and a path of the nodes N21 to N23) that bypasses the unnecessary current based on the voltage-current conversion gain gm1 is set. Thereby, the inverting amplifier circuit 1 according to the present embodiment maintains the combined resistances RtotalI and RtotalO constant even when the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC1 are switched. be able to.

  Thereby, in the inverting amplifier circuit 1 according to the present embodiment, the problem that the frequency characteristic of the amplification result Vout changes unintentionally due to the phase rotation of the feedback signal does not occur. Further, in the inverting amplifier circuit 1 according to the present embodiment, since the resistance value viewed from the preceding amplifier circuit (not shown) does not change, the voltage gain of the preceding amplifier circuit changes unintentionally. There is no problem. That is, the inverting amplifier circuit 1 according to the present embodiment can output a highly accurate amplification result Vout.

  In the present embodiment, the programmable voltage-to-current converter PVIC1 has a detour path (first detour path) of current flowing through the nodes N21 to N23 and a detour path (second path) of current flowing through the node N12. The case of having a detour route) has been described as an example, but is not limited thereto. The programmable voltage-current converter PVIC1 can be appropriately changed to a configuration having at least one of the first and second bypass paths. For example, the configuration having only the first detour path can suppress an unintended change in the frequency characteristic of the amplification result Vout due to the phase rotation of the feedback signal. On the other hand, the configuration having only the second detour path can suppress unintended changes in the voltage gain of the amplifier circuit in the previous stage.

  In this embodiment, the case where the inverting amplifier circuit 1 selectively sets four voltage gains different by 6 dB has been described as an example, but the present invention is not limited to this. The inverting amplifier circuit 1 can be appropriately changed to a configuration in which an arbitrary number and an arbitrary value of voltage gain are selectively set.

<Embodiment 2>
FIG. 6 is a diagram of a configuration example of the inverting amplifier circuit (semiconductor integrated circuit) 2 according to the second embodiment. 6 is different from the inverting amplifier circuit 1 shown in FIG. 3 in the configuration of the programmable voltage-current converter. This will be specifically described below. Note that the inverting amplifier circuit 2 illustrated in FIG. 6 is applied to, for example, the RF subsystem 603 in the wireless communication terminal 500 illustrated in FIG.

  The inverting amplifier circuit 2 shown in FIG. 6 includes an operational amplifier (amplifier circuit) OPA, a feedback resistor (first feedback resistor) RFBT, a feedback resistor (second feedback resistor) RFBB, and a programmable voltage-current converter (variable resistor unit). PVIC2 is provided. The configuration other than the programmable voltage-current converter PVIC2 is the same as that of the inverting amplifier circuit 1 shown in FIG.

  FIG. 7 is a circuit diagram showing a specific configuration example of the programmable voltage-current converter PVIC2. The programmable voltage-current converter PVIC2 includes resistance elements (first resistance elements) R30T to R34T, resistance elements (second resistance elements) R30B to R34B, switch elements (first switch elements) S31T to S34T, and switch elements (second switches). Element) S31B to S34B, switch element (third switch element) S41T to S43T, switch element (fourth switch element) S41B to S43B, resistance attenuator (first resistance attenuator) ATT1T to ATT3T, and resistance attenuator ( (Second resistance attenuator) ATT1B to ATT3B.

  In the resistor element R30T, one end is connected to the input terminal IT, and the other end is connected to the node N31T. Each of resistance elements R31T to R34T has one end connected to nodes N31T to N34T and the other end connected to one end of each of switching elements S31T to S34T. The other ends of the switch elements S31T to S34T are connected to the output terminal OT. In the resistance attenuator ATT1T, the terminal i is connected to the node N31T, the terminal o is connected to the node N32T, and the terminal c is connected to one end of the switch element S41T. In the resistance attenuator ATT2T, the terminal i is connected to the node N32T, the terminal o is connected to the node N33T, and the terminal c is connected to one end of the switch element S42T. In the resistance attenuator ATT3T, the terminal i is connected to the node N33T, the terminal o is connected to the node N34T, and the terminal c is connected to one end of the switch element S43T. The other ends of the switch elements S41T to S43T are connected to a node (common node) N41.

  In resistance element R30B, one end is connected to input terminal IB, and the other end is connected to node N31B. Each of resistance elements R31B to R34B has one end connected to nodes N31B to N34B and the other end connected to one end of each of switching elements S31B to S34B. The other ends of the switch elements S31B to S34B are connected to the output terminal OB. In the resistance attenuator ATT1B, the terminal i is connected to the node N31B, the terminal o is connected to the node N32B, and the terminal c is connected to one end of the switch element S41B. In the resistance attenuator ATT2B, the terminal i is connected to the node N32B, the terminal o is connected to the node N33B, and the terminal c is connected to one end of the switch element S42B. In the resistance attenuator ATT3B, the terminal i is connected to the node N33B, the terminal o is connected to the node N34B, and the terminal c is connected to one end of the switch element S43B. The other ends of the switch elements S41B to S43B are connected to a node (common node) N41.

In the present embodiment, an example will be described in which the resistance values of the resistance elements R30T to R34T and R30B to R34B are R _1/2 .

  Each switch element S31T-S34T, S31B-S34B, S41T-S43T, S41B-S43B is comprised by FET, such as MOSFET and JFET, for example. Note that the switch elements S31T to S34T, S31B to S34B, S41T to S43T, and S41B to S43B may all have the same on-resistance.

<First Specific Configuration Example of Resistance Attenuator>
FIG. 8 is a diagram illustrating a first specific configuration example of the resistance attenuator. The resistance attenuator shown in FIG. 8 is a so-called T-type resistance attenuator and includes resistance elements R51 to R53. One end of the resistor element R51 is connected to the terminal i. One end of the resistor element R52 is connected to the terminal o. One end of the resistor element R53 is connected to a terminal (common terminal) c. The other ends of the resistance elements R51 to R53 are connected to each other.

  In the following, the resistance of the resistance attenuator viewed from the i terminal is RS, the impedance of the resistance attenuator viewed from the o terminal is RL, the resistance values of the resistance elements R51 and R52 are Ratt1, and the resistance value of the resistance element R53 A case where is Ratt2 will be described as an example.

  Here, when the attenuation amount of the resistance attenuator shown in FIG. 8 is X dB, the resistance values Ratt1 and Ratt2 of the resistance elements R51 to R53 are expressed as the following Expression (22) and Expression (23), respectively. The

<Second Specific Configuration Example of Resistance Attenuator>
FIG. 9 is a diagram illustrating a second specific configuration example of the resistance attenuator. The resistance attenuator shown in FIG. 9 is a so-called π-type resistance attenuator, and includes resistance elements R61 to R63. In the resistor element R61, one end is connected to the terminal (common terminal) c, and the other end is connected to the terminal i. In the resistance element R62, one end is connected to the terminal c and the other end is connected to the terminal o. In the resistance element R63, one end is connected to the terminal i and the other end is connected to the terminal o.

  In the following description, the impedance of the resistance attenuator viewed from the i terminal is RS, the impedance of the resistance attenuator viewed from the o terminal is RL, the resistance values of the resistance elements R61 and R62 are Ratt1, and the resistance value of the resistance element R63. A case where is Ratt2 will be described as an example.

  Here, when the attenuation amount of the resistance attenuator shown in FIG. 9 is X dB, the resistance values Ratt1 and Ratt2 of the resistance values R61 to R62 are expressed by the following equations (24) and (25), respectively. The

  In the present embodiment, the case where the resistance attenuators ATT1T to ATT3T and ATT1B to ATT3B are all the T-type resistance attenuators shown in FIG. 8 will be described as an example.

Here, if the attenuation amount of each resistance attenuator is 6 dB, k≈2. Furthermore, when _{RS = RL = R 1/2} , the equation (22) and _(23), the Ratt1 = R 1/6, Ratt2 = 2R 1/3. In the _following, described as an example where a Ratt1 = R 1/6, Ratt2 = 2R 1/3.

  The programmable voltage-to-current converter PVIC2 controls the respective conduction states of the switch elements S31T to S34T, S31B to S34B, S41T to S43T, and S41B to S43B based on a control signal from a control circuit (not shown), thereby providing an input terminal. The combined resistance between IT and the output terminal OT and the combined resistance between the input terminal IB and the output terminal OB are controlled in a programmable manner. As a result, the inverting amplifier circuit 2 can amplify the input voltage Vin with a desired voltage gain and output it as an amplification result (differential amplified signal) Vout.

<Operation of Inversion Amplifier Circuit 2 According to Second Embodiment>
Next, the operation of the inverting amplifier circuit 2 according to the present embodiment will be described in detail. FIG. 10 is a diagram illustrating the relationship between the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC2 and the voltage gain of the inverting amplifier circuit 2.

(Operation of the inverting amplifier circuit 2 in the state A)
First, the operation of the inverting amplifier circuit 2 when the switch elements S31T and S31B are on and the other switch elements are off (hereinafter also referred to as state A) will be described.

In the state A, the voltage-current conversion gain gm2 of the programmable voltage-current converter PVIC2 is 1 / R ₁ which is the same as the voltage-current conversion gain gm10 of the voltage-current converter PVIC10 shown in FIG. Further, the voltage gain G2 of the inverting amplifier circuit 2 at this time is 20 × log10 (| G2 |) dB, which is the same as the voltage gain G10 of the inverting amplifier circuit 10.

  More specifically, in the state A, the resistance elements R30T and R31T are connected in series between the input terminal IT and the output terminal OT. Resistance elements R30B and R31B are connected in series between the input terminal IB and the output terminal OB. Therefore, the combined resistance RtotalT when the input terminal IT is viewed from the output terminal OT and the combined resistance RtotalB when the input terminal IB is viewed from the output terminal OB are expressed as the following Expression (26).

RtotalT = RtotalB = R ₁ (26)

  Therefore, in the state A, the output current Iin2 of the programmable voltage-current converter PVIC2 is expressed as the following equation (27), assuming that the current flowing from the programmable voltage-current converter PVIC2 toward the operational amplifier OPA is a positive current. Is done.

_{Iin2 = I OT -I OB = (} V INT -V INB) / R 1 ··· (27)

  The current Iin2 is converted into a voltage by the feedback resistors RFBT and RFBB, and then output from the output terminals OUTT and OUTB. Therefore, the voltage gain G2 of the inverting amplifier circuit 2 in the state A is expressed as the following equation (28).

G2 = (V _OUTT −V _OUTB ) / (V _INT −V _INB )
= −Iin2 × R ₂ / (V _INT −V _INB )
= -R ₂ / R ₁ (28)

  Here, the output terminals OT and OB of the programmable voltage-current converter PVIC2 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA to which negative feedback is applied by the feedback resistors RFBT and RFBB, respectively. Therefore, the output terminals OT and OB of the programmable voltage-current converter PVIC2 exhibit the same potential (that is, they are virtually short-circuited). Therefore, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB is twice that of RtotalT or RtotalB. That is, the following equation (29) is established.

RtotalI = 2R ₁ (29)

  On the other hand, the input terminals IT and IB of the programmable voltage-current converter PVIC2 are connected to an amplifier circuit (not shown) that is so small that the output impedance can be ignored, for example. Therefore, the input terminals IT and IB of the programmable voltage-current converter PVIC1 have the same potential. Therefore, the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB is twice that of RtotalT or RtotalB. That is, the following formula (30) is established.

RtotalO = 2R ₁ (30)

(Operation of Inversion Amplifier Circuit 2 in State B)
Next, the operation of the inverting amplifier circuit 2 when the switch elements S32T, S32B, S41T, and S41B are on and the other switch elements are off (hereinafter also referred to as state B) will be described. .

  In the state B, the switch elements S31T and S31B are off, so that no current flows through the resistance elements R31T and R31B connected in series to the switch elements S31T and S31B. Further, since the switch elements S33T, S34T, S42T, S43T, S33B, S34B, S42B, and S43B are open, no current flows through the resistance attenuators ATT2T, ATT3T, ATT2B, and ATT3B connected thereto.

  FIG. 11 is a diagram illustrating a configuration of the programmable voltage-current converter PVIC2 in which a switch element and a path through which no current flows are omitted in the state B. As apparent from FIG. 11, in the state B, the configuration of the programmable voltage-current converter PVIC2 in which the output terminals OT and OB are viewed from the input terminals IT and IB, and the input terminals IT and IB from the output terminals OT and OB. It can be seen that the configuration of the programmable voltage-current converter PVIC2 is the same.

  Here, the output terminals OT and OB of the programmable voltage-current converter PVIC2 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA to which negative feedback is applied by the feedback resistors RFBT and RFBB, respectively. Therefore, the output terminals OT and OB of the programmable voltage-current converter PVIC2 exhibit the same potential (that is, they are virtually short-circuited). On the other hand, the input terminals IT and IB of the programmable voltage-current converter PVIC2 are connected to an amplifier circuit (not shown) that is so small that the output impedance can be ignored, for example. Therefore, the input terminals IT and IB of the programmable voltage-current converter PVIC2 show the same potential. Accordingly, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB and the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB are expressed by the following equation (31). It is expressed in

RtotalI = RtotalO = 2R ₁ (31)

  FIG. 12 is an equivalent circuit of FIG. Referring to FIG. 12, in the state B, the output current Iin2 of the programmable voltage-current converter PVIC2 is expressed as the following equation (32), assuming that the current flowing from the programmable voltage-current converter PVIC2 toward the operational amplifier OPA is a positive current. It is expressed as

_{Iin2 = I OT -I OB = (} V INT -V INB) / (2R 1) ··· (32)

  Therefore, the voltage gain G2 of the inverting amplifier circuit 2 in the state B is expressed as the following equation (33).

G2 = (V _OUTT −V _OUTB ) / (V _INT −V _INB )
= −Iin2 × R ₂ / (V _INT −V _INB )
= -R ₂ / (2R ₁ ) (33)

  In other words, the voltage gain G2 of the inverting amplifier circuit 2 in the state B is 20 × log10 (| G2 | / 2) dB. That is, the voltage gain G2 of the inverting amplifier circuit 2 in the state B is attenuated by about 6 dB from the voltage gain G10 of the inverting amplifier circuit 10.

(Operation of the inverting amplifier circuit 2 in the state C)
Next, the inverting amplifier circuit 2 when the switch elements S33T, S33B, S41T, S41B, S42T, and S42B are on and the other switch elements are off (hereinafter also referred to as state C). The operation will be described.

  In the state C, since the switch elements S31T, S31B, S32T, and S32B are off, no current flows through the resistance elements R31T, R31B, R32T, and R32B connected in series to these elements. Further, since the switch elements S34T, S34B, S43T, and S43B are off, no current flows through the resistance attenuators ATT3T and ATT3B connected thereto.

  FIG. 13 is a diagram illustrating a configuration of the programmable voltage-current converter PVIC2 in which the switch element and the path through which no current flows are omitted in the state C. As apparent from FIG. 13, in state C, the configuration of the programmable voltage-current converter PVIC2 when the output terminals OT and OB are viewed from the input terminals IT and IB, and the input terminals IT and IB from the output terminals OT and OB. It can be seen that the configuration of the programmable voltage-current converter PVIC2 is the same.

  Here, the output terminals OT and OB of the programmable voltage-current converter PVIC2 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA to which negative feedback is applied by the feedback resistors RFBT and RFBB, respectively. Therefore, the output terminals OT and OB of the programmable voltage-current converter PVIC2 exhibit the same potential (that is, they are virtually short-circuited). On the other hand, the input terminals IT and IB of the programmable voltage-current converter PVIC2 are connected to an amplifier circuit (not shown) that is so small that the output impedance can be ignored, for example. Therefore, the input terminals IT and IB of the programmable voltage-current converter PVIC2 show the same potential. Accordingly, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB, and the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB are expressed by the following equation (34). It is expressed in

RtotalI = RtotalO = 2R ₁ (34)

  FIG. 14 is an equivalent circuit of FIG. Referring to FIG. 14, in the state C, the output current Iin2 of the programmable voltage-current converter PVIC2 is expressed as the following equation (35), assuming that the current flowing from the programmable voltage-current converter PVIC2 toward the operational amplifier OPA is a positive current. It is expressed as

_{Iin2 = I OT -I OB = (} V INT -V INB) / (4R 1) ··· (35)

  Therefore, the voltage gain G2 of the inverting amplifier circuit 2 in the state C is expressed as the following Expression (36).

G2 = (V _OUTT −V _OUTB ) / (V _INT −V _INB )
= −Iin2 × R ₂ / (V _INT −V _INB )
= −R ₂ / (4R ₁ ) (36)

  In other words, the voltage gain G2 of the inverting amplifier circuit 2 in the state C is 20 × log10 (| G2 | / 4) dB. That is, the voltage gain G2 of the inverting amplifier circuit 2 in the state C is attenuated by about 12 dB from the voltage gain G10 of the inverting amplifier circuit 10.

(Operation of Inversion Amplifier Circuit 2 in State D)
Next, inversion when the switch elements S34T, S34B, S41T, S41B, S42T, S42B, S43T, and S43B are on and the other switch elements are off (hereinafter also referred to as state D). The operation of the amplifier circuit 2 will be described.

  In the state D, since the switch elements S31T, S31B, S32T, S32B, S33T, and S33B are off, current flows through the resistance elements R31T, R31B, R32T, R32B, R33T, and R33B connected in series to these elements. Absent.

  FIG. 15 is a diagram illustrating a configuration of the programmable voltage-current converter PVIC2 in which a switch element and a path through which no current flows are omitted in the state D. As apparent from FIG. 15, in state D, the configuration of the programmable voltage-current converter PVIC2 when the output terminals OT and OB are viewed from the input terminals IT and IB, and the input terminals IT and TB from the output terminals OT and OB. It can be seen that this is the same as the programmable voltage-current converter PVIC2 seen in FIG.

  Here, the output terminals OT and OB of the programmable voltage-current converter PVIC2 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA to which negative feedback is applied by the feedback resistors RFBT and RFBB, respectively. Therefore, the output terminals OT and OB of the programmable voltage-current converter PVIC2 exhibit the same potential (that is, they are virtually short-circuited). On the other hand, the input terminals IT and IB of the programmable voltage-current converter PVIC2 are connected to an amplifier circuit (not shown) that is so small that the output impedance can be ignored, for example. Therefore, the input terminals IT and IB of the programmable voltage-current converter PVIC2 show the same potential. Accordingly, the combined resistance RtotalI when the output terminals OT and OB are viewed from the input terminals IT and IB, and the combined resistance RtotalO when the input terminals IT and IB are viewed from the output terminals OT and OB are expressed by the following equation (37). It is expressed in

RtotalI = RtotalO = 2R ₁ (37)

  FIG. 16 is an equivalent circuit of FIG. Referring to FIG. 16, in the state D, the output current Iin2 of the programmable voltage-current converter PVIC2 is expressed by the following equation (38) when the current flowing from the programmable voltage-current converter PVIC2 to the operational amplifier OPA is a positive current. ).

_{Iin2 = I OT -I OB = (} V INT -V INB) / (8R 1) ··· (38)

  Therefore, the voltage gain G2 of the inverting amplifier circuit 2 in the state D is expressed as the following equation (39).

G2 = (V _OUTT −V _OUTB ) / (V _INT −V _INB )
= −Iin2 × R ₂ / (V _INT −V _INB )
= -R ₂ / (8R ₁ ) (39)

  In other words, the voltage gain G2 of the inverting amplifier circuit 2 in the state D is 20 × log10 (| G2 | / 8) dB. That is, the voltage gain G2 of the inverting amplifier circuit 2 in the state D is attenuated by about 18 dB from the voltage gain G10 of the inverting amplifier circuit 10.

  As described above, the programmable voltage-current converter PVIC2 according to the present embodiment sets a current path through which a current having a desired voltage-current conversion gain gm2 flows by switching the conduction states of the plurality of switch elements in a programmable manner. At the same time, a detour path (path of the node N41) for detouring the unnecessary current is set based on the voltage-current conversion gain gm2. Thus, the inverting amplifier circuit 2 according to the present embodiment maintains the combined resistances RtotalI and RtotalO constant even when the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC2 are switched. be able to.

  Thereby, in the inverting amplifier circuit 2 according to the present embodiment, the problem that the frequency characteristic of the amplification result Vout changes unintentionally due to the phase rotation of the feedback signal does not occur. Further, in the inverting amplifier circuit 2 according to the present embodiment, since the resistance value viewed from the preceding amplifier circuit (not shown) does not change, the voltage gain of the preceding amplifier circuit changes unintentionally. There is no problem. That is, the inverting amplifier circuit 2 according to the present embodiment can output a highly accurate amplification result Vout.

  Furthermore, in the programmable voltage-current converter PVIC2 according to the present embodiment, the voltage applied to the switch element in the off state (open) is smaller than in the case of the programmable voltage-current converter PVIC1. The switch element is configured by an FET such as a MOSFET or JFET. For this reason, as the semiconductor process becomes finer, a leak current is likely to flow through the switch element in the off state. Therefore, the programmable voltage-current converter PVIC2 according to the present embodiment suppresses the leakage current flowing through the off-state switch element by reducing the voltage applied to the off-state switch element. Thereby, the programmable voltage-current converter PVIC2 concerning this Embodiment can perform voltage-current conversion more accurately. Hereinafter, the difference between the programmable voltage-current converter PVIC1 and the programmable voltage-current converter PVIC2 will be briefly described.

<Difference between programmable voltage-current converter PVIC1 and PVIC2>
First, in the programmable voltage-current converter PVIC1 (see FIG. 4), since the output terminals OT and OB are virtual shorts, a predetermined bias voltage level is indicated. For example, when a large input voltage Vin is supplied to the input terminals IT and IB, a large voltage is applied between both terminals of the switch element in the off state. As a result, a leakage current may flow through the switch element in the off state.

  On the other hand, in the programmable voltage-current converter PVIC2 (see FIG. 7), even when a large input voltage Vin is supplied to the input terminals IT and IB, the input voltage Vin is divided by the resistance attenuators ATT1T to ATT3T and ATT1B to ATT3B. Therefore, the voltage applied between both terminals of the switch element in the off state is small. Thereby, the leakage current flowing through the switch element in the off state is suppressed. Hereinafter, a specific example will be described.

  FIG. 17 is a diagram illustrating a configuration of the programmable voltage-current converter PVIC2 in the state B. As shown in FIG. 17, the switch elements in the off state (open) are switch elements S31T, S31B, S33T, S33B, S34T, S34B, S42T, S42B, S43T, and S43B. Here, even when a large input voltage Vin is supplied to the input terminals IT and IB, the input voltage Vin is divided by the resistance elements arranged in a mesh shape, and therefore, between both terminals of the switch element in the off state. The applied voltage is small. Thereby, the leakage current flowing through the switch element in the off state is suppressed. The same can be said for states A, C, and D.

  In the present embodiment, the case where the inverting amplifier circuit 2 selectively sets four voltage gains different by 6 dB is described as an example, but the present invention is not limited to this. The inverting amplifier circuit 2 can be appropriately changed to a configuration in which an arbitrary number and an arbitrary value of voltage gain are selectively set.

  In the present embodiment, the case where each of the resistance attenuators ATT1T to ATT3T and ATT1B to ATT3B is the T-type resistance attenuator shown in FIG. 8 is described as an example, but the present invention is not limited thereto. Even if the resistance attenuators ATT1T to ATT3T and ATT1B to ATT3B are the π-type resistance attenuators shown in FIG. 9, the same effects can be obtained.

<Embodiment 3>
FIG. 18 is a diagram illustrating a configuration example of the inverting amplifier circuit (semiconductor integrated circuit) 3 according to the third embodiment. The inverting amplifier circuit 1 shown in FIG. 3 is a fully differential inverting amplifier circuit. On the other hand, the inverting amplifier circuit 3 shown in FIG. 18 is a single-ended inverting amplifier circuit. This will be specifically described below. Note that the inverting amplifier circuit 3 illustrated in FIG. 18 is applied to, for example, the RF subsystem 603 in the wireless communication terminal 500 illustrated in FIG.

  The inverting amplifier circuit 3 shown in FIG. 18 includes an operational amplifier (amplifier circuit) OPA, a feedback resistor RFBT, and a programmable voltage-current converter (variable resistor unit) PVIC3. Of the components of the inverting amplifier circuit 3 shown in FIG. 18, the same components as those of the inverting amplifier circuit 1 shown in FIG.

  The input terminal IT of the programmable voltage-current converter PVIC3 is connected to the input terminal (external input terminal) INT of the inverting amplifier circuit 3. The output terminal OT of the programmable voltage-current converter PVIC3 is connected to the inverting input terminal of the operational amplifier OPA. The non-inverting input terminal of the operational amplifier OPA is connected to a ground voltage terminal (reference voltage terminal) GND to which a ground voltage (reference voltage) is supplied. The output terminal of the operational amplifier OPA is connected to the output terminal OUTT of the inverting amplifier circuit 3. The feedback resistor RFBT is provided between the output terminal and the inverting input terminal of the operational amplifier OPA.

  FIG. 19 is a circuit diagram showing a specific configuration example of the programmable voltage-current converter PVIC3. The programmable voltage-current converter PVIC3 includes resistance elements (first resistance elements) R11T to R14T, resistance elements (second resistance elements) R21T to R23T, switch elements (first switch elements) S11T to S14T, and switch elements (first 2 switch elements) S21T to S23T. That is, the programmable voltage-current converter PVIC3 has only a plurality of resistance elements and a plurality of switch elements provided on the True side of the programmable voltage-current converter PVIC1.

  Among the components of the programmable voltage-current converter PVIC3 shown in FIG. 19, the same components as those of the programmable voltage-current converter PVIC1 shown in FIG. Nodes N12 and N21 to N23 are connected to the ground voltage terminal GND.

  The programmable voltage-to-current converter PVIC3 controls the respective conduction states of the switch elements S11T to S14T and the switch elements S21T to S23T based on a control signal from a control circuit (not shown), whereby the input terminal IT and the output terminal OT Programmable control of the combined resistance between the two. As a result, the inverting amplifier circuit 3 can amplify the input voltage Vin with a desired voltage gain and output it as an amplification result (amplified signal) Vout.

  The specific operation of the programmable voltage-current converter PVIC3 is the same as the operation on the True side of the programmable voltage-current converter PVIC1, and thus the description thereof is omitted.

  As described above, the programmable voltage-current converter PVIC3 according to the present embodiment sets a current path through which a current having a desired voltage-current conversion gain flows by switching each conduction state of the plurality of switch elements in a programmable manner. Then, a detour path (a path of the node N12 and a path of the nodes N21 to N23) for detouring the unnecessary current based on the voltage-current conversion gain is set. As a result, the inverting amplifier circuit 3 according to the present embodiment maintains the combined resistances RtotalI and RtotalO constant even when the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC3 are switched. be able to.

  Thereby, in the inverting amplifier circuit 3 according to the present embodiment, the problem that the frequency characteristic of the amplification result Vout changes unintentionally due to the phase rotation of the feedback signal does not occur. Further, in the inverting amplifier circuit 3 according to the present embodiment, since the resistance value seen from the preceding amplifier circuit (not shown) does not change, the voltage gain of the preceding amplifier circuit changes unintentionally. There is no problem. That is, the inverting amplifier circuit 3 according to the present embodiment can output a highly accurate amplification result Vout.

  In the present embodiment, the programmable voltage-current converter PVIC3 has a detour path (first detour path) of current flowing through the nodes N21 to N23 and a detour path (second path) of current flowing through the node N12. The case of having a detour route) has been described as an example, but is not limited thereto. The programmable voltage-current converter PVIC3 can be appropriately changed to a configuration having at least one of the first and second bypass paths. For example, the configuration having only the first detour path can suppress an unintended change in the frequency characteristic of the amplification result Vout due to the phase rotation of the feedback signal. On the other hand, the configuration having only the second detour path can suppress unintended changes in the voltage gain of the amplifier circuit in the previous stage.

<Embodiment 4>
FIG. 20 is a diagram illustrating a configuration example of the inverting amplifier circuit (semiconductor integrated circuit) 4 according to the fourth embodiment. 20 is different from the inverting amplifier circuit 3 shown in FIG. 18 in the configuration of the programmable voltage-current converter. This will be specifically described below. Note that the inverting amplifier circuit 4 illustrated in FIG. 20 is applied to, for example, the RF subsystem 603 in the wireless communication terminal 500 illustrated in FIG.

  The inverting amplifier circuit 4 shown in FIG. 20 includes an operational amplifier (amplifier circuit) OPA, a feedback resistor RFBT, and a programmable voltage-current converter (variable resistor unit) PVIC4. Since the configuration other than the programmable voltage-current converter PVIC4 is the same as that of the inverting amplifier circuit 3 shown in FIG. 18, the description thereof is omitted.

  FIG. 21 is a circuit diagram showing a specific configuration example of the programmable voltage-current converter PVIC4. The programmable voltage-current converter PVIC4 includes resistance elements (first resistance elements) R30T to R34T, switching elements (first switching elements) S31T to S34T, switching elements (second switching elements) S41T to S43T, and a resistance attenuator ATT1T. Has ~ ATT3T. In other words, the programmable voltage-current converter PVIC4 has only a plurality of resistance elements and a plurality of switch elements provided on the True side of the programmable voltage-current converter PVIC2 shown in FIG.

  Of the components of the programmable voltage-current converter PVIC4 shown in FIG. 21, the same components as those of the programmable voltage-current converter PVIC2 shown in FIG. Node 41 is connected to ground voltage terminal GND.

  The programmable voltage-current converter PVIC4 controls the conduction state of each of the switch elements S31T to S34T and S41T to S43T based on a control signal from a control circuit (not shown), whereby the input voltage between the input terminal IT and the output terminal OT. Programmable control of the combined resistance. As a result, the inverting amplifier circuit 3 can amplify the input voltage Vin with a desired voltage gain and output it as an amplification result (amplified signal) Vout.

  Since the specific operation of the programmable voltage-current converter PVIC4 is the same as the operation on the True side of the programmable voltage-current converter PVIC2, its description is omitted.

  As described above, the programmable voltage-current converter PVIC4 according to the present embodiment sets a current path through which a current having a desired voltage-current conversion gain flows by switching each conduction state of the plurality of switch elements in a programmable manner. Then, a detour path (path of the node N41) for detouring the unnecessary current is set based on the voltage-current conversion gain. Thereby, the inverting amplifier circuit 4 according to the present embodiment maintains the combined resistances RtotalI and RtotalO constant even when the conduction states of the plurality of switch elements provided in the programmable voltage-current converter PVIC4 are switched. be able to.

  Thereby, in the inverting amplifier circuit 4 according to the present embodiment, there is no problem that the frequency characteristic of the amplification result Vout changes unintentionally due to the phase rotation of the feedback signal. Further, in the inverting amplifier circuit 4 according to the present embodiment, since the resistance value viewed from the preceding amplifier circuit (not shown) does not change, the voltage gain of the preceding amplifier circuit changes unintentionally. There is no problem. That is, the inverting amplifier circuit 4 according to the present embodiment can output a highly accurate amplification result Vout.

  Furthermore, in the programmable voltage / current converter PVIC4 according to the present embodiment, the voltage applied to the switch element in the off state (open) is smaller than in the case of the programmable voltage / current converter PVIC3. The switch element is configured by an FET such as a MOSFET or JFET. For this reason, as the semiconductor process becomes finer, a leak current is likely to flow through the switch element in the off state. Therefore, the programmable voltage-current converter PVIC4 according to the present embodiment suppresses the leakage current flowing through the off-state switch element by reducing the voltage applied to the off-state switch element. Thereby, the programmable voltage-current converter PVIC4 according to the present embodiment can perform voltage-current conversion with higher accuracy.

  As described above, the programmable voltage-to-current converter according to the first to fourth embodiments has a current path through which a current having a desired voltage-current conversion gain flows by switching each conduction state of the plurality of switch elements in a programmable manner. In addition to setting, a detour path for detouring unnecessary current based on the voltage-current conversion gain is set. As a result, the inverting amplifier circuit according to the first to fourth embodiments has an input / output impedance (synthetic resistors RtotalI, RtotalO) even when the conduction states of the plurality of switch elements provided in the programmable voltage-current converter are switched. ) Can be kept constant.

  Thereby, in the inverting amplifier circuit according to the first to fourth embodiments, there is no problem that the frequency characteristic of the amplification result Vout is unintentionally changed due to the phase rotation of the feedback signal. Further, in the inverting amplifier circuits according to the first to fourth embodiments, since the resistance value viewed from the preceding amplifier circuit (not shown) does not change, the voltage gain of the preceding amplifier circuit changes unintentionally. The problem does not arise. That is, the inverting amplifier circuit according to the first to fourth embodiments can output the amplification result Vout with high accuracy.

  In the above embodiment, the case where the input / output impedance (combined resistance RtotalI, RtotalO) of the programmable voltage-current converter is always constant has been described as an example, but the present invention is not limited to this. It is sufficient that the fluctuation of the input / output impedance of the programmable voltage-current converter is suppressed by diverting the unnecessary current based on the voltage-current conversion gain.

<Difference from cited document>
In the configuration disclosed in Non-Patent Document 1, the configuration of the feedback resistor portion is different from that of the inverting amplifier circuit 20 shown in FIG. More specifically, the configuration disclosed in Non-Patent Document 1 can set the resistance value of the feedback resistor in a programmable manner. However, the configuration disclosed in Non-Patent Document 1 causes the same problem as in the case of the inverting amplifier circuit 20 shown in FIG. On the other hand, as described above, the inverting amplifier circuits 1 to 4 according to the above embodiments do not cause such a problem.

  Note that a capacitance element or the like is usually provided in the feedback resistance portion of the inverting amplifier circuit in order to form a channel filter. Therefore, in the configuration disclosed in Non-Patent Document 1, the circuit scale increases.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

500 Wireless communication terminal 501 Case 502 Display device 503 Touch panel 504 Operation button 505, 506 Camera device 601 Application processor 602 Baseband processor 603 RF subsystem 604 Memory 605 Battery 606 Power management IC
607 Display unit 608 Camera unit 609 Operation input unit 610 Audio IC
611 Microphone 612 Speaker 1-4 Inverting amplifier circuit PVIC1-PVIC4 Programmable voltage-current converter R11T-R14T, R11B-R14B Resistive element S11T-S14T, S11B-S14B Switch element R21T-R23T, R21B-R23B Resistive element S21T-S23T, S21B ~ S23B switch element R30T ~ R34T, R30B ~ R34B resistance element S30T ~ S34T, S30B ~ S34B switch element ATT1T ~ ATT3T, ATT1B ~ ATT3B resistance attenuator R51 ~ R53, R61 ~ R63 resistance element OPA operational amplifier RFBT, RFBB feedback resistance

Claims (16)

An antenna,
A quadrature mixer that performs demodulation processing by multiplying a high-frequency signal wirelessly received via the antenna and a local oscillation signal;
An amplification unit that amplifies the output signal of the orthogonal mixer and outputs it as a baseband signal;
An arithmetic processing unit that executes predetermined processing based on the baseband signal,
The amplification unit is
An operational amplifier that amplifies a difference voltage between an input voltage supplied to the inverting input terminal and a reference voltage supplied to the non-inverting input terminal and outputs an amplified signal;
A feedback resistor that negatively feeds back the amplified signal to the inverting input terminal of the operational amplifier;
A current path having a first resistance value corresponding to a control signal is set between an external input terminal and the inverting input terminal of the operational amplifier, and a node on the current path and a reference voltage terminal to which the reference voltage is supplied A variable resistance unit that sets a first bypass path of a second resistance value according to the control signal between,
The variable resistance portion is
A plurality of first resistance elements provided in parallel between the external input terminal and the inverting input terminal of the operational amplifier;
A plurality of first switch elements provided between one end of each of the plurality of first resistance elements and an inverting input terminal of the operational amplifier, the conduction state of which is controlled based on the control signal;
A plurality of resistance attenuators provided between the other ends of the plurality of first resistance elements;
A plurality of second switch elements provided between a common terminal of each of the plurality of resistance attenuators and the reference voltage terminal, the conduction state of which is controlled based on the control signal;
Wireless communication device.   The wireless communication apparatus according to claim 1, wherein the variable resistance unit sets the first bypass path between an inverting input terminal of the operational amplifier and the reference voltage terminal.   3. The variable resistance unit according to claim 2, wherein the current path and the first bypass path are set so that an impedance when the variable resistance unit is viewed from the operational amplifier is constant regardless of a state of the control signal. Wireless communication device.   The wireless communication device according to claim 2, wherein the variable resistance unit further sets a second bypass path having a second resistance value according to the control signal between the external input terminal and the reference voltage terminal.   The variable resistor unit is configured such that an impedance viewed from the operational amplifier is constant regardless of a state of the control signal, and an impedance viewed from the external input terminal is the variable resistor unit. The wireless communication apparatus according to claim 4, wherein the current path, the first bypass path, and the second bypass path are set so as to be constant regardless of a state of a control signal.   The wireless communication apparatus according to claim 1, wherein the variable resistance unit sets the first bypass path between the external input terminal and the reference voltage terminal. The variable resistance portion is
A plurality of first resistance elements provided in parallel between the external input terminal and the inverting input terminal of the operational amplifier;
A plurality of first switch elements provided between each of the plurality of first resistance elements and an inverting input terminal of the operational amplifier, the conduction state of which is controlled based on the control signal;
A plurality of second resistance elements provided in parallel between an inverting input terminal of the operational amplifier and the reference voltage terminal;
The wireless communication device according to claim 1, further comprising: a plurality of second switch elements that are connected in series to each of the plurality of second resistance elements and whose conduction state is controlled based on the control signal.   The plurality of first switch elements connect each of the plurality of first resistance elements to one of an inverting input terminal and the reference voltage terminal of the operational amplifier based on the control signal. The wireless communication device described. An antenna,
A quadrature mixer that performs demodulation processing by multiplying a high-frequency signal wirelessly received via the antenna and a local oscillation signal;
An amplification unit that amplifies the output signal of the orthogonal mixer and outputs it as a baseband signal;
An arithmetic processing unit that executes predetermined processing based on the baseband signal,
The amplification unit is
An operational amplifier;
A first feedback resistor that negatively feeds back one of the differential output signals of the operational amplifier;
A second feedback resistor that negatively feeds back the other differential output signal of the operational amplifier;
A first resistance value corresponding to a control signal is set between the first external input terminal and the inverting input terminal of the operational amplifier, and between the second external input terminal and the non-inverting input terminal of the operational amplifier. And a second resistance path for setting a first bypass path of a second resistance value according to the control signal between the nodes on the first and second current paths, With
The variable resistance portion is
A plurality of first resistance elements provided in parallel between the first external input terminal and the inverting input terminal of the operational amplifier;
A plurality of second resistance elements provided in parallel between the second external input terminal and the non-inverting input terminal of the operational amplifier;
A plurality of first switch elements provided between one end of each of the plurality of first resistance elements and an inverting input terminal of the operational amplifier, the conduction state of which is controlled based on the control signal;
A plurality of second switch elements provided between one end of each of the plurality of second resistance elements and a non-inverting input terminal of the operational amplifier, the conduction state of which is controlled based on the control signal;
A plurality of first resistance attenuators provided between the other ends of the plurality of first resistance elements;
A plurality of second resistance attenuators provided between the other ends of the plurality of second resistance elements;
A plurality of third switch elements provided between a common terminal and a common node of each of the plurality of first resistance attenuators, the conduction state of which is controlled based on the control signal;
A plurality of fourth switch elements provided between the respective common terminals of the plurality of second resistance attenuators and the common node, the conduction state of which is controlled based on the control signal;
Wireless communication device.   The wireless communication device according to claim 9, wherein the variable resistance unit sets the first bypass path between an inverting input terminal and a non-inverting input terminal of the operational amplifier.   The variable resistance unit includes the first current path, the second current path, and the first bypass path so that impedance when the variable resistance unit is viewed from the operational amplifier is constant regardless of the state of the control signal. The wireless communication device according to claim 10, wherein:   The wireless communication device according to claim 10, wherein the variable resistance unit further sets a second detour path having a second resistance value according to the control signal between the first and second external input terminals.   The variable resistor unit is configured such that impedance when the variable resistor unit is viewed from the operational amplifier is constant regardless of the state of the control signal, and from the first and second external input terminals to the variable resistor unit. The first current path, the second current path, the first detour path, and the second detour path are set so that the impedance seen from the above is constant regardless of the state of the control signal. The wireless communication device described.   The wireless communication device according to claim 9, wherein the variable resistance unit sets the first bypass path between the first and second external input terminals. The variable resistance portion is
A plurality of first resistance elements provided in parallel between the first external input terminal and the inverting input terminal of the operational amplifier;
A plurality of second resistance elements provided in parallel between the second external input terminal and the non-inverting input terminal of the operational amplifier;
A plurality of first switch elements provided between each of the plurality of first resistance elements and an inverting input terminal of the operational amplifier, the conduction state of which is controlled based on the control signal;
A plurality of second switch elements provided between each of the plurality of second resistance elements and a non-inverting input terminal of the operational amplifier, the conduction state of which is controlled based on the control signal;
A plurality of third resistance elements provided in parallel between the inverting input terminal and the non-inverting input terminal of the operational amplifier;
The wireless communication device according to claim 9, further comprising: a plurality of third switch elements that are connected in series to each of the plurality of third resistance elements and whose conduction state is controlled based on the control signal. The plurality of first switch elements connect each of the plurality of first resistance elements to one of an inverting input terminal and a common node of the operational amplifier based on the control signal,
The plurality of second switch elements connect each of the plurality of second resistance elements to one of the non-inverting input terminal of the operational amplifier and the common node based on the control signal. The wireless communication device described.

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