JP2016082067A - Solid-state imaging device and method of manufacturing solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device which suppresses occurrence of color mixture, and a method of manufacturing the solid-state imaging device.SOLUTION: A pixel array 23 of the solid-state imaging device includes a semiconductor layer 4 in which photoelectric conversion elements 40 are arranged in a two-dimensional array, a light shielding member 8, and an insulating member 6. The light shielding member 8 is provided in the semiconductor layer 4 so as to surround a side peripheral surface on a light receiving surface 43 side of each of the photoelectric conversion elements 40. The insulating member 6 is provided in the semiconductor layer 4 so as to surround a side peripheral surface opposite to the light receiving surface 43 side of each of the photoelectric conversion elements 40.SELECTED DRAWING: Figure 4

Description

  Embodiments described herein relate generally to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

  2. Description of the Related Art Conventionally, a solid-state imaging device includes a plurality of photoelectric conversion elements that photoelectrically convert incident light into an amount of charge corresponding to the amount of received light, and a plurality of color filters provided corresponding to the photoelectric conversion elements. In recent years, such a solid-state imaging device has been increased in the number of pixels and reduced in size, and the pixel pitch tends to be reduced.

  For this reason, in the solid-state imaging device, color mixture may occur between adjacent pixels due to the fine pixel pitch. Such color mixing includes optical color mixing and electrical color mixing. Optical color mixing occurs when light that has passed through a color filter enters an adjacent photoelectric conversion element instead of a photoelectric conversion element corresponding to the color filter. Electrical color mixing occurs when the charge photoelectrically converted by the photoelectric conversion element moves to the adjacent photoelectric conversion element. These mixed colors adversely affect the image quality of the captured image.

JP 2012-169530 A

  An object of one embodiment of the present invention is to provide a solid-state imaging device and a method for manufacturing the solid-state imaging device that can suppress the occurrence of color mixing.

  According to one embodiment of the present invention, a solid-state imaging device is provided. The solid-state imaging device includes a semiconductor layer, a light shielding member, and an insulating member. The light shielding member is provided in the semiconductor layer so as to surround the side peripheral surface on the light receiving surface side of each photoelectric conversion element. The insulating member is provided in the semiconductor layer so as to surround the side peripheral surface opposite to the light receiving surface side in each photoelectric conversion element.

FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera including the solid-state imaging device according to the embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the embodiment. FIG. 3 is an explanatory diagram illustrating a part of the light receiving surface of the pixel array according to the embodiment. FIG. 4 is an explanatory diagram illustrating a cross section taken along line AA ′ illustrated in FIG. 3 of the pixel array according to the embodiment. FIG. 5 is a schematic cross-sectional view illustrating the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 6 is a schematic cross-sectional view illustrating the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 7 is a schematic cross-sectional view illustrating the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 8 is a schematic cross-sectional view illustrating the manufacturing process of the solid-state imaging device according to the embodiment. FIG. 9 is an explanatory diagram schematically illustrating a cross section of a pixel array according to a modification of the embodiment.

  Exemplary embodiments of a solid-state imaging device and a method for manufacturing the solid-state imaging device will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

  FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera 1 including a solid-state imaging device 14 according to the embodiment. As shown in FIG. 1, the digital camera 1 includes a camera module 11 and a post-processing unit 12.

  The camera module 11 includes an imaging optical system 13 and a solid-state imaging device 14. The imaging optical system 13 takes in light from a subject and forms a subject image. The solid-state imaging device 14 captures a subject image formed by the imaging optical system 13 and outputs an image signal obtained by the imaging to the post-processing unit 12. In addition to the digital camera 1, the camera module 11 is applied to an electronic device such as a mobile terminal with a camera.

  The post-processing unit 12 includes an ISP (Image Signal Processor) 15, a storage unit 16, and a display unit 17. The ISP 15 performs signal processing of the image signal input from the solid-state imaging device 14. The ISP 15 performs high image quality processing such as noise removal processing, defective pixel correction processing, and resolution conversion processing.

  Then, the ISP 15 outputs the image signal after the signal processing to the signal processing circuit 21 (see FIG. 2) described later provided in the storage unit 16, the display unit 17, and the solid-state imaging device 14 in the camera module 11. An image signal fed back from the ISP 15 to the camera module 11 is used for adjustment and control of the solid-state imaging device 14.

  The storage unit 16 stores the image signal input from the ISP 15 as an image. In addition, the storage unit 16 outputs an image signal of the stored image to the display unit 17 according to a user operation or the like. The display unit 17 displays an image according to an image signal input from the ISP 15 or the storage unit 16. The display unit 17 is, for example, a liquid crystal display.

  Next, the solid-state imaging device 14 included in the camera module 1 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device 14 according to the embodiment. As shown in FIG. 2, the solid-state imaging device 14 includes an image sensor 20 and a signal processing circuit 21.

  Here, the image sensor 20 is a so-called backside-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on the surface opposite to the surface on which incident light enters in a photoelectric conversion element that photoelectrically converts incident light. The case where it is is demonstrated. Note that the image sensor 20 according to the embodiment is not limited to the back-illuminated CMOS image sensor, and may be any image sensor such as a front-illuminated CMOS image sensor or a CCD (Charge Coupled Device) image sensor. Good.

  The image sensor 20 includes a peripheral circuit 22 and a pixel array 23. The peripheral circuit 22 includes a vertical shift register 24, a timing control unit 25, a CDS (correlated double sampling) 26, an ADC (analog / digital conversion unit) 27, and a line memory 28, and these are mainly configured by analog circuits. Is done.

The pixel array 23 is provided in the imaging region of the image sensor 20. In the pixel array 23, a plurality of photoelectric conversion elements corresponding to each pixel of the captured image are arranged in a two-dimensional array (matrix) in the horizontal direction (row direction) and the vertical direction (column direction). In the pixel array 23, each photoelectric conversion element corresponding to each pixel generates and accumulates signal charges (for example, electrons) corresponding to the amount of incident light.
Then, the pixel array 23 acquires a voltage signal corresponding to the amount of charge photoelectrically converted by a plurality of photoelectric conversion elements corresponding to each pixel as color information of each pixel.

  The timing control unit 25 is a processing unit that outputs a pulse signal serving as a reference for operation timing to the vertical shift register 24, the CDS 26, the ADC 27, and the line memory 28. The vertical shift register 24 outputs to the pixel array 23 a selection signal for sequentially selecting photoelectric conversion elements for reading out signal charges from a plurality of photoelectric conversion elements two-dimensionally arranged in an array (matrix). It is a processing unit.

  The pixel array 23 outputs the signal charge accumulated in each photoelectric conversion element selected in units of rows by the selection signal input from the vertical shift register 24 from the photoelectric conversion element to the CDS 26 as a pixel signal indicating the luminance of each pixel. To do.

  The CDS 26 is a processing unit that removes noise from the pixel signal input from the pixel array 23 by correlated double sampling and outputs the noise to the ADC 27. The ADC 27 is a processing unit that converts an analog pixel signal input from the CDS 26 into a digital pixel signal and outputs the digital pixel signal to the line memory 28. The line memory 28 is a processing unit that temporarily holds the pixel signal input from the ADC 27 and outputs the pixel signal to the signal processing circuit 21 for each row of photoelectric conversion elements in the pixel array 23.

  The signal processing circuit 21 is a processing unit that performs predetermined signal processing on the pixel signal input from the line memory 28 and outputs the processed signal to the subsequent processing unit 12, and is mainly configured by a digital circuit. The signal processing circuit 21 performs signal processing such as lens shading correction, flaw correction, and noise reduction processing on the pixel signal.

  As described above, in the image sensor 20, a plurality of photoelectric conversion elements arranged in the pixel array 23 photoelectrically convert incident light into signal charges of an amount corresponding to the amount of received light, and the peripheral circuit 22 stores each photoelectric conversion element. Imaging is performed by reading the signal charges accumulated in the pixel signal as pixel signals.

  In such an image sensor 20, by narrowing the space between adjacent photoelectric conversion elements, it is possible to increase the number of installed photoelectric conversion elements in the pixel array 23 and reduce the occupation area of the photoelectric conversion elements. However, when the space between adjacent photoelectric conversion elements becomes narrow, there is a concern about optical color mixing and electrical color mixing between adjacent photoelectric conversion elements.

  As a measure for preventing such color mixture, there is a method of providing STI (Shallow Trench Isolation) or DTI (Deep Trench Isolation) between the photoelectric conversion elements. In STI, a shallow groove is dug around a photoelectric conversion element in a semiconductor layer and an annealing process is performed to recover crystal defects in the groove, and then an insulating film is formed on the inner peripheral surface of the groove, and light shielding of metal or the like is performed there. The member is embedded, and the photoelectric conversion elements are optically and electrically separated at the surface layer portion of the semiconductor layer.

  In the case of a backside illumination (BSI) structure, the STI trench is formed on the backside semiconductor layer opposite to the surface on which the wiring layer is formed after the wiring layer is formed on the surface of the semiconductor layer. Is done. Therefore, in the case of the BSI structure, since the wiring layer is adversely affected by the heat of the annealing process that recovers the crystal defects in the groove, it is not possible to form a deep groove that requires a long time for the annealing process.

  On the other hand, the DTI performs an annealing process for digging a deep groove in the semiconductor layer before forming the wiring layer and recovering crystal defects in the groove, and then burying an insulating member such as silicon oxide in the groove, The photoelectric conversion elements are electrically separated from each other at the surface layer portion and middle lower layer portion of the layer.

  However, DTI cannot block light incident obliquely on the light receiving surface of the semiconductor layer because the insulating member embedded in the groove has translucency. That is, the DTI cannot optically separate the photoelectric conversion elements between the surface layers of the semiconductor layer.

  In addition, in DTI, an insulating film is formed on the inner peripheral surface of a deep groove, and a light shielding member such as metal is embedded therein, so that each photoelectric conversion element is optically and electrically connected between the surface layer portion and the middle lower layer portion of the semiconductor layer. It is conceivable to separate the elements. However, such DTI is not practical for use as a product because the metal embedded by the heat treatment performed in the manufacturing process is thermally diffused and adversely affects the characteristics of the photoelectric conversion element.

  Therefore, in the present embodiment, in the pixel array 23, the photoelectric conversion elements are optically separated at the surface layer portion of the semiconductor layer, and the photoelectric conversion elements are electrically separated at the middle and lower layer portions of the semiconductor layer. An element isolation region that can be used is provided.

  Here, an example of the configuration of the pixel array 23 that enables optical and electrical element separation between adjacent photoelectric conversion elements will be described with reference to FIGS. 3 and 4. FIG. 3 is an explanatory diagram illustrating a part of the light receiving surface of the pixel array 23 according to the embodiment. FIG. 4 is an explanatory diagram illustrating a cross section taken along line AA ′ illustrated in FIG. 3 of the pixel array 23 according to the embodiment.

  3 does not show the microlens 31, the color filter 32, and the planarization layer 33 shown in FIG. 4 in order to show the shape of the element isolation region 5 provided in the pixel array 23 in plan view. In addition, here, for convenience, the side on which the light 9 of the pixel array 23 is incident is referred to as the upper side, and the side opposite to the side on which the light 9 is incident on the pixel array 23 is referred to as the lower side.

  As shown in FIG. 3, the pixel array 23 includes a plurality of photoelectric conversion elements 40 that are two-dimensionally arranged in a matrix. The pixel array 23 includes an element isolation region 5 between adjacent photoelectric conversion elements 40. Specifically, the pixel array 23 includes a planar grid-like element isolation region 5 surrounding the light receiving surface 43 of each photoelectric conversion element 40.

  The cross section of the pixel array 23 is as shown in FIG. Specifically, the pixel array 23 includes a support substrate 37, a multilayer wiring layer 38 provided on the support substrate 37 via an adhesive layer 36, and a semiconductor layer 4 provided on the multilayer wiring layer 38. Further, the pixel array 23 includes a planarization layer 33, a color filter 32, and a microlens 31 that are sequentially stacked on the semiconductor layer 4 via a fixed charge film 70.

  The multilayer wiring layer 38 is a layer in which the read gate 41 and the multilayer wiring 42 are provided inside the interlayer insulating film 35. The adhesive layer 36 and the support substrate 37 will be described in the method for forming the pixel array 23. The semiconductor layer 4 is a layer in which a plurality of second conductivity type (N-type) Si regions 39 are provided in a two-dimensional array inside the first conductivity type (P-type) Si layer 34. In the pixel array 23, a photodiode formed by a PN junction between the P-type Si layer 34 and the N-type Si region 39 becomes the photoelectric conversion element 40.

  The flattening layer 33 is a layer having translucency provided to flatten the laminated surface of the color filter 32 laminated after the flattening layer 33 is formed. The color filter 32 is a filter that selectively transmits one of red, green, blue, and white color light. The microlens 31 is a plano-convex lens that collects incident light 9.

  Further, as shown in FIG. 4, the element isolation region 5 described above is formed from the surface on the light receiving surface side to the surface opposite to the surface in the P-type Si layer 34. The element isolation region 5 includes a light shielding member 8, an insulating member 6, and a fixed charge film 70.

  The light shielding member 8 is provided on the P-type Si layer 34 so as to surround the side peripheral surface of each photoelectric conversion element 40 on the light receiving surface 43 side. That is, the light shielding member 8 is provided in the surface layer portion where the optical color mixture in the P-type Si layer 34 is likely to occur. The upper end surface of the light shielding member 8 protrudes from the end surface on the upper surface side of the P-type Si layer 34 by a predetermined length. Further, the lower end surface of the light shielding member 8 is located below the upper end surface of the photoelectric conversion element 40.

  The light shielding member 8 is, for example, one of W (tungsten), Ti (titanium), Ta (tantalum), Al (aluminum), Cu (copper), and Hf (hafnium), or at least two of these. Made of a combination of two or more materials.

  The light shielding member 8 prevents the light 9 having passed through the color filter 32 from entering the adjacent photoelectric conversion element 40 from the photoelectric conversion element 40 side corresponding to the color filter 32. Thereby, the pixel array 23 suppresses the occurrence of optical color mixing.

  The insulating member 6 is provided on the P-type Si layer 34 so as to surround the side peripheral surface opposite to the light receiving surface 43 side of each photoelectric conversion element 40. That is, the insulating member 6 is provided in the middle and lower layer portions where optical color mixing in the P-type Si layer 34 hardly occurs and electric color mixing easily occurs. The upper end surface of the insulating member 6 is in contact with the lower end surface of the light shielding member 8 through the fixed charge film 70. The lower end surface of the insulating member 6 is in contact with the upper end surface of the interlayer insulating film 35 provided on the surface opposite to the light receiving surface of the P-type Si layer 34.

  The insulating member 6 is made of, for example, one of SiO 2 (silicon oxide), SiN (silicon nitride), and Si (silicon), or a material obtained by combining at least two of these.

  The insulating member 6 prevents the signal charges accumulated in the photoelectric conversion element 40 from leaking to the adjacent photoelectric conversion element 40. Thereby, the pixel array 23 suppresses the occurrence of electrical color mixing.

  The fixed charge film 70 is provided on the outer peripheral surface and the bottom surface of the light shielding member 8 and the upper surface of the P-type Si layer 34. In this embodiment, the fixed charge film 70 provided on the outer peripheral surface and the bottom surface of the light shielding member 8 is a part of the configuration of the element isolation region 5. The fixed charge film 70 is made of, for example, either HfO 2 (hafnium oxide) or TaO (tantalum oxide). The fixed charge film 70 holds a negative charge in the film, and the positive charge in the P-type Si layer 34 is recombined with the negative charge in the film, thereby preventing the occurrence of dark current.

  Further, the pixel array 23 includes a first conductivity type (P type) Si region 7 containing activated P type impurities (boron). Specifically, the P-type Si region 7 is provided in a region surrounding the side peripheral surface of the element isolation region 5 in the P-type Si layer 34. Here, the activated P-type impurity means a P-type impurity in a state diffused by heat in the P-type Si region 7.

  As described above, the pixel array 23 is provided with the light shielding member 8 so as to surround the side peripheral surface on the light receiving surface 43 side of each photoelectric conversion element 40, and the side opposite to the light receiving surface 43 side of each photoelectric conversion element 40. An insulating member 6 is provided so as to surround the peripheral surface.

  As a result, the pixel array 23 optically separates the photoelectric conversion elements 40 between the surface layers of the P-type Si layer 34 by the light shielding member 8. Therefore, the pixel array 23 can prevent the light 9 that has passed through the color filter 32 from entering the adjacent photoelectric conversion element 40 from the photoelectric conversion element 40 side corresponding to the color filter 32, so that optical color mixing can be performed. Occurrence can be suppressed.

  Further, the pixel array 23 electrically isolates the photoelectric conversion elements 40 in the middle and lower layers of the P-type Si layer 34 by the insulating member 6. Therefore, the pixel array 23 can prevent the signal charge accumulated in the photoelectric conversion element 40 from leaking to the adjacent photoelectric conversion element 40, and can suppress the occurrence of electrical color mixture.

  Further, in the pixel array 23, the end surface on the light incident side of the light shielding member 8 protrudes from the end surface on the light receiving surface side of the P-type Si layer 34, so that the light shielding member 8 is close to the microlens 31. Thereby, the pixel array 23 can more reliably prevent the light 9 transmitted through the color filter 32 from entering the adjacent photoelectric conversion element 40 from the photoelectric conversion element 40 side corresponding to the color filter 32.

  In addition, since the pixel array 23 projects the end face of the light shielding member 8, the light shielding member 8 serves as an anchor with respect to the planarization layer 33, so that the adhesion with the P-type Si layer 34 is improved. The color filter 32 and the microlens 31 can be effectively prevented from peeling off.

  Next, a method for manufacturing the solid-state imaging device 14 including the method for forming the pixel array 23 will be described with reference to FIGS. Note that the manufacturing method of the portion other than the pixel array 23 in the solid-state imaging device 14 is the same as that of a general CMOS image sensor. For this reason, below, the manufacturing process of the part shown in FIG. 4 in the pixel array 23 in the solid-state imaging device 14 is selectively shown.

  5 to 8 are schematic vertical cross-sectional views illustrating the manufacturing process of the solid-state imaging device 14 according to the embodiment. As shown in FIG. 5A, when the pixel array 23 is manufactured, a P-type Si layer 34 is formed on a semiconductor substrate 44 such as a Si wafer. At this time, for example, a P-type Si layer 34 is formed by epitaxially growing a Si layer doped with a P-type impurity such as boron on the semiconductor substrate 44. The P-type Si layer 34 may be formed by ion-implanting P-type impurities into the Si wafer and performing an annealing process.

  Subsequently, an N-type impurity such as phosphorus is ion-implanted into the formation position of the photoelectric conversion element 40 in the P-type Si layer 34 to perform an annealing process, so that an N-type impurity is added to the P-type Si layer 34. Si regions 39 are two-dimensionally arranged in a matrix. Thus, a photoelectric conversion element 40 that is a photodiode is formed in the P-type Si layer 34 by a PN junction between the P-type Si layer 34 and the N-type Si region 39. Thus, the semiconductor layer 4 in which the N-type Si region 39 is provided in the P-type Si layer 34 is formed.

  Next, as shown in FIG. 5B, for example, a resist 50 is applied to the upper surface of the semiconductor layer 4, and a portion (see FIGS. 3 and 4) where the element isolation region 5 is formed by photolithography. The resist 50 is removed, and other resists 50 are left.

  Using this resist 50 as a mask, for example, RIE (Reactive Ion Etching) is performed, and as shown in FIG. 5C, a portion of the P-type Si layer 34 not covered with the resist 50 is formed on the semiconductor substrate 44. The through-groove 10 is formed by removing up to the upper surface. Specifically, the through groove 10 is formed in a lattice shape in plan view surrounding the light receiving surface 43 (see FIGS. 3 and 4) of the photoelectric conversion element 40. Thereafter, the resist 50 used as a mask is removed.

  Subsequently, as shown in FIG. 5D, for example, a P-type impurity 71 such as boron (here, B: boron) is directed from the inner peripheral surface of the through groove 10 toward the inside of the P-type Si layer 34. ) Is ion-implanted. For example, ion implantation of a P-type impurity 71 (hereinafter referred to as boron 71) is performed by dividing the irradiation of the ion beam 91 onto the inner peripheral surface of the through groove 10 into the inner peripheral surface and the bottom surface of the through groove 10. Do it once.

  Next, by annealing the semiconductor layer 4, the boron 71 is thermally diffused, and as shown in FIG. 6A, the P-type Si region 7 surrounding the side peripheral surface of the through groove 10 is formed. Form. The P-type Si region 7 is formed in order to restore the outer peripheral surface of the through groove 10 damaged by RIE to a state free from defects. That is, the outer peripheral surface of the through-groove 10 may be damaged by RIE, resulting in crystal defects and dangling bonds. The P-type Si region 7 is formed to capture electrons generated due to dangling bonds on the outer peripheral surface of the through groove 10.

  Further, the P-type Si region 7 has not only a role of recovering crystal defects on the outer peripheral surface of the through groove 10 but also a role of element isolation between the photoelectric conversion elements 40. Specifically, a P-type Si region 7 having a higher P-type impurity concentration than the P-type Si layer 34 is formed on the outer peripheral surface of the through groove 10. As described above, by providing the P-type Si region 7 which is opposite to the N-type Si region 39, the photoelectric conversion elements 40 are electrically separated.

  Further, since the above-described annealing treatment is performed before the multilayer wiring layer 38 is formed on the upper surface of the semiconductor layer 4, it can be performed at a high temperature for a long time. Thereby, the crystal defects on the outer peripheral surface of the through groove 10 formed in the P-type Si layer 34 can be more reliably recovered. That is, even if the groove is relatively deep enough to penetrate the front and back of the P-type Si layer 34, crystal defects on the outer peripheral surface of the groove can be sufficiently recovered.

  Next, as shown in FIG. 6B, silicon oxide is formed into a P-type silicon by using, for example, CVD (Chemical Vapor Deposition) into the through groove 10 whose outer peripheral surface is covered with the P-type Si region 7. A silicon oxide film 60 as an insulating member is formed in the through groove 10 by filling up to the upper end surface of the Si layer 34.

  Subsequently, as shown in FIG. 6C, a multilayer wiring layer 38 is formed on the upper surface of the semiconductor layer 4. In the step of forming the multilayer wiring layer 38, first, a read gate 41 or the like is formed at a predetermined position on the surface of the semiconductor layer 4 by using, for example, polysilicon.

  Thereafter, a series of steps of forming an interlayer insulating film 35, patterning a wiring pattern in the interlayer insulating film 35, and forming a multilayer wiring 42 by embedding a metal such as copper in the formed wiring pattern, for example. repeat. Thereby, the multilayer wiring layer 38 is formed.

  Then, as shown in FIG. 6D, an adhesive layer 36 is formed on the upper surface of the multilayer wiring layer 38, and a support substrate 37 such as a Si wafer is attached to the upper surface of the adhesive layer 36. Note that the support substrate 37 may be directly attached to the upper surface of the multilayer wiring layer 38 without using the adhesive layer 36.

  Thereafter, the top and bottom of the structure shown in FIG. 6D is reversed, and then the back surface (here, the upper surface side) of the semiconductor substrate 44 is ground and polished, so that the semiconductor substrate 44 is thinned to a predetermined thickness. Turn into. Then, as shown in FIG. 7A, the back surface (here, the top surface) of the semiconductor layer 4 serving as the light receiving surface is exposed.

  Subsequently, as shown in FIG. 7B, for example, wet processing with dilute hydrofluoric acid or the like is performed, and the silicon oxide film 60 in the through groove 10 is moved to a predetermined position below the upper end surface of the photoelectric conversion element 40. The groove 51 is formed by removing. Here, the portion where the silicon oxide film 60 in the through groove 10 is removed becomes the groove 51. The depth of the groove 51 is controlled by controlling the wet etching time for the silicon oxide film 60.

  In this process, since the silicon oxide film 60 in the through groove 10 is removed by wet etching, there is no possibility that the outer peripheral surface of the groove 51 is damaged and crystal defects are generated unlike in dry etching. Therefore, the wet process does not need to be annealed to recover crystal defects on the outer peripheral surface of the groove 51, and can be performed on the semiconductor layer 4 on which the multilayer wiring layer 38 is formed.

  Thus, the wet process is performed to form the groove 51, whereby the insulating member 6 embedded in the through groove 10 on the opposite side to the side on which the light 9 is incident is formed. The upper end surface of the insulating member 6 is positioned slightly lower than the upper end surface of the photoelectric conversion element 40, and the lower end surface of the insulating member 6 is in contact with the upper surface of the interlayer insulating film 35.

  Thereafter, as shown in FIG. 7C, the upper surface of the P-type Si layer 34 and the inner peripheral surface of the groove 51 are fixed using, for example, ALD (Atomic Layer Deposition) and made of, for example, hafnium oxide. A charge film 70 is formed.

  Then, as shown in FIG. 7D, a tungsten film 80 as a light shielding member is deposited on the upper surface of the fixed charge film 70 by using, for example, CVD, and the inner peripheral surface is covered with the fixed charge film 70. A tungsten film 80 is embedded in the trench 51.

  Next, as shown in FIG. 8A, for example, a resist 52 is applied to the upper surface of the tungsten film 80, and a portion (see FIGS. 3 and 4) where the element isolation region 5 is formed by photolithography. The resist 52 is left, and the other resists 52 are removed.

  Using this resist 52 as a mask, for example, RIE is performed to remove the portion of the tungsten film 80 that is not covered with the resist 52 as shown in FIG. Thereafter, the resist 52 used as a mask is removed.

  In this way, the light shielding member 8 embedded in the inside of the through groove 10 where the light 9 is incident is formed. The upper end surface of the light shielding member 8 protrudes from the light receiving surface of the P-type Si layer 34 by the thickness of the tungsten film 80 deposited, and the lower end surface of the light shielding member 8 passes through the fixed charge film 70 and the upper end surface of the insulating member 6. Abut.

  In this manner, the end surface on the light incident side of the light shielding member 8 is projected from the end surface on the light receiving surface side of the P-type Si layer 34. Thereby, the formation position of the color filter 32 and the microlens 31 can be easily determined using the light shielding member 8 protruding from the P-type Si layer 34 as a mark.

  Further, by forming the insulating member 6, the fixed charge film 70, and the light shielding member 8 in the through groove 10, the element isolation region 5 having a lattice shape in plan view surrounding the light receiving surface 43 of each photoelectric conversion element 40 is formed. .

  Thereafter, as shown in FIG. 8C, the planarization layer 33 to be a waveguide is formed by, for example, depositing SiN (silicon nitride) on the opening surrounded by the light shielding member 8 by using, for example, CVD. Form. Thereafter, the color filter 32 and the microlens 31 are formed on the upper surface of the planarizing layer 33 formed between the light shielding members 8 with the light shielding member 8 protruding from the end surface on the light receiving surface side of the P-type Si layer 34 as a mark. Are sequentially formed to form the pixel array 23 shown in FIG.

  As described above, the pixel array 23 according to the embodiment surrounds the periphery of the light receiving surface 43 of each photoelectric conversion element 40 and penetrates from the light receiving surface of the P-type Si layer 34 to a surface opposite to the surface. A through groove 10 is provided. In the through groove 10, the light shielding member 8 is provided inside the through groove 10 on the side where the light 9 is incident, and the insulating member 6 is provided inside the through groove 10 opposite to the side where the light 9 is incident. .

  As a result, the pixel array 23 optically separates the photoelectric conversion elements 40 between the surface layers of the P-type Si layer 34 by the light shielding member 8. Therefore, the pixel array 23 can prevent the light 9 transmitted through the color filter 32 from entering the adjacent photoelectric conversion element 40 from the photoelectric conversion element 40 side corresponding to the color filter 32, and optical color mixing. Can be suppressed.

  Further, the pixel array 23 electrically isolates the photoelectric conversion elements 40 in the middle and lower layers of the P-type Si layer 34 by the insulating member 6. For this reason, the pixel array 23 can prevent the signal charge accumulated in the photoelectric conversion element 40 from leaking to the adjacent photoelectric conversion element 40, and can suppress the occurrence of electrical color mixture.

  Note that the configuration of the pixel array according to the embodiment is not limited to the configuration illustrated in FIG. 4. Next, a pixel array according to a modification of the embodiment will be described with reference to FIG. FIG. 9 is an explanatory diagram illustrating a pixel array 23a according to a modification of the embodiment.

  In the following description, among the constituent elements of the pixel array 23a shown in FIG. 9, the same constituent elements as those shown in FIG. 4 are given the same reference numerals as those shown in FIG. Description is omitted.

  As shown in FIG. 9, the pixel array 23 a includes an insulating film 72 instead of the fixed charge film 70. The insulating film 72 is provided on the outer peripheral surface and the bottom surface of the light shielding member 8 inside the through groove 10. The insulating film 72 is made of, for example, silicon oxide.

  As a result, the pixel array 23 a can be optically separated by the insulating member 72 in addition to being optically separated by the light blocking member 8 on the side where the light 9 is incident inside the through groove 10. Therefore, the occurrence of color mixing can be further suppressed.

  Further, as shown in FIG. 4, the element isolation region 5 in the above-described embodiment is formed in a lattice shape and continuously surrounds the light receiving surface 43 of each photoelectric conversion element 40, but is not limited to this shape. The light receiving surface 43 of the photoelectric conversion element 40 may be surrounded discontinuously.

  Specifically, the pixel arrays 23 and 23a may be configured such that the element isolation region 5 is formed between the photoelectric conversion elements 40 facing each other in plan view. Even with this configuration, the photoelectric conversion elements 40 can be optically and electrically separated from each other, and the occurrence of optical color mixing and electrical color mixing can be suppressed.

  In the above-described embodiment, the Si layer 34 and the Si region 7 are P-type and the Si region 39 is N-type, but the Si layer 34 and the Si region 7 are N-type, and the Si region 39 is P-type. , 23a may be configured. In such a case, the fixed charge film 70 in the pixel array 23 is configured to hold a positive charge.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 Digital camera, 10 Through groove, 11 Camera module, 12 Post process part, 13 Imaging optical system, 14 Solid-state imaging device, 15 ISP, 16 Storage part, 17 Display part, 20 Image sensor, 21 Signal processing circuit, 22 Peripheral circuit , 23 pixel array, 24 vertical shift register, 25 timing control unit, 26 CDS, 27 ADC, 28 line memory, 31 microlens, 32 color filter, 33 planarization layer, 34 P-type Si layer, 35 interlayer insulation film, 36 adhesive layer, 37 support substrate, 38 multilayer wiring layer, 39 N-type Si region, 4 semiconductor layer, 40 photoelectric conversion element, 41 readout gate, 42 multilayer wiring, 43 light receiving surface, 44 semiconductor substrate, 5 element isolation region, 50 resists, 51 grooves , 52 resist, 6 insulating member, 60 silicon oxide film, 7 P type Si region, 70 fixed charge film, 71 P type impurity, 72 insulating film, 8 light shielding member, 80 tungsten film, 9 light, 91 ion beam

Claims (5)

A semiconductor layer in which photoelectric conversion elements are arranged in a two-dimensional array;
A light shielding member provided in the semiconductor layer so as to surround a side peripheral surface on a light receiving surface side in each of the photoelectric conversion elements;
A solid-state imaging device comprising: an insulating member provided on the semiconductor layer so as to surround a side peripheral surface opposite to a light receiving surface side in each of the photoelectric conversion elements. The end surface on the light receiving surface side of the light shielding member is
The solid-state imaging device according to claim 1, wherein the solid-state imaging device protrudes from an end surface of the semiconductor layer on the light receiving surface side. The solid-state imaging device according to claim 1, further comprising an insulating film that covers an outer peripheral surface inside the semiconductor layer of the light shielding member. The light shielding member and the insulating member are
The solid-state imaging device according to any one of claims 1 to 3, wherein the solid-state imaging device is provided in a through groove that penetrates the front and back of the semiconductor layer. Forming photoelectric conversion elements in a two-dimensional array on the semiconductor layer;
Forming a through groove penetrating from the light receiving surface of the semiconductor layer to a surface opposite to the surface so as to surround each photoelectric conversion element in a plan view;
Forming an insulating member in the inside of the through groove opposite to the side on which light is incident;
Forming a light shielding member inside the through-groove on the light incident side. A method of manufacturing a solid-state imaging device.

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