JP2016045972A - Nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory that can be used with optimum product specification corresponding to a user.SOLUTION: A nonvolatile memory 10 according to one embodiment comprises a memory unit 16, a sequencer circuit 11 for controlling a rewrite operation to the memory unit 16 in accordance with a rewrite command 21, an operation mode selection circuit 12 for selecting an operation mode at the time of rewrite operation in accordance with operation mode selection information 22, a voltage value storage unit 13 in which a rewrite voltage value is stored, a voltage setting register 14 for setting the rewrite voltage, and a power supply circuit 15 for generating the power supply voltage set by the voltage setting register 14. When carrying out the rewrite operation to the memory unit 16 in accordance with the rewrite command 21, the power supply voltage conforming to the operation mode selection information 22 that corresponds to the rewrite command 21 is applied, and the rewrite operation to the memory unit 16 is carried out.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a nonvolatile memory, for example, a nonvolatile memory capable of selecting an operation mode during a rewrite operation.

  One of rewritable nonvolatile memory systems such as a flash memory is a floating gate system in which information is stored in a floating gate between a semiconductor substrate and a control gate electrode. Since the floating gate is covered with an insulating film such as an oxide film, it is normally in an insulating state. However, when a voltage is applied to the upper control gate electrode, a tunnel current flows through the insulating film, and charges are stored in the floating gate (writing operation). On the other hand, when a voltage is applied to the substrate side, the charges stored in the floating gate are released to the substrate (erase operation). Thus, in the nonvolatile memory, data can be stored depending on whether or not charges are stored in the floating gate.

  Patent Document 1 discloses a technique in which a memory module is divided into a plurality of blocks, an area for storing a rewrite condition is provided in each block, and each block is rewritten according to the condition.

US Pat. No. 7,292,473

  Recently, as a characteristic of a nonvolatile memory, an increase in rewriting speed and an improvement in rewriting durability are required. For example, by suppressing the voltage at the time of rewriting the nonvolatile memory, deterioration of the insulating film of the memory cell can be suppressed, and the rewriting tolerance of the nonvolatile memory can be improved. However, in this case, since the voltage at the time of rewriting is kept low, the rewriting speed becomes slow. On the contrary, the rewriting speed can be increased by increasing the voltage at the time of rewriting, but in this case, since the insulating film of the memory cell is deteriorated, the rewriting durability of the nonvolatile memory is lowered.

  Here, the characteristics of the nonvolatile memory required by the user vary depending on the user who uses the nonvolatile memory. In other words, there are users who place importance on the rewriting speed and other users who place importance on rewriting resistance. However, in the current nonvolatile memory, the user cannot arbitrarily select the operation mode at the time of rewriting operation, and thus there is a problem that the user cannot use the nonvolatile memory with an optimum product specification.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A nonvolatile memory according to an embodiment includes a memory unit that stores data, a sequencer circuit that controls a rewrite operation to the memory unit according to an input rewrite command, and an operation mode during a rewrite operation to the memory unit An operation mode selection circuit that selects the memory unit, and when performing a rewrite operation to the memory unit according to the rewrite command, a rewrite operation to the memory unit with a power supply voltage according to the operation mode selection information corresponding to the rewrite command To implement.

  According to the embodiment, it is possible to provide a non-volatile memory that can be used with an optimum product specification according to a user.

FIG. 3 is a block diagram illustrating a configuration example when the nonvolatile memory according to the first embodiment is used in a microcomputer. 1 is a block diagram showing a nonvolatile memory according to a first embodiment; 3 is a circuit diagram illustrating an example of a memory cell included in the nonvolatile memory according to the first embodiment; FIG. 3 is a table showing characteristics of each operation mode of the nonvolatile memory according to the first embodiment; 4 is a timing chart for explaining timings when a rewrite command and operation mode selection information are supplied to the nonvolatile memory according to the first embodiment; FIG. 6 is a diagram for explaining a state in which operation mode selection information is supplied to the nonvolatile memory according to the first embodiment. 4 is a table showing an example of register values and voltage values of a voltage setting register included in the nonvolatile memory according to the first embodiment; 3 is a flowchart for explaining an operation of the nonvolatile memory according to the first embodiment; FIG. 6 is a block diagram illustrating a nonvolatile memory according to a second embodiment. FIG. 10 is a diagram for explaining an example of an operation mode information storage unit included in the nonvolatile memory according to the second embodiment; FIG. 10 is a diagram for explaining another example of the operation mode information storage unit included in the nonvolatile memory according to the second embodiment. 6 is a flowchart for explaining an operation of the nonvolatile memory according to the second embodiment; FIG. 10 is a diagram for explaining another example of the operation mode information storage unit included in the nonvolatile memory according to the second embodiment.

<Embodiment 1>
The first embodiment will be described below with reference to the drawings.
FIG. 1 is a diagram for explaining a usage example of the nonvolatile memory 10 according to the first embodiment, and is a block diagram illustrating a configuration example when the nonvolatile memory 10 is used in the microcomputer 100. As shown in FIG. 1, the microcomputer 100 includes a CPU (Central Processing Unit) 101, a RAM (Random Access Memory) 102, a port 103, a PLL (Phase Locked Loop) circuit 104, a bus interface 105, and a nonvolatile memory 10. .

  The CPU (101) is an arithmetic circuit, for example, reads a predetermined program stored in the nonvolatile memory 10, and executes the read program to perform a predetermined process. The RAM (102) temporarily stores data generated when the program is executed by the CPU (101). The microcomputer 100 inputs data from the outside via the port 103 and outputs data to the outside via the port 103. The PLL circuit (104) receives a reference clock and generates an internal clock 110 using the input reference clock. The generated internal clock 110 is supplied to the CPU (101), RAM (102), port 103, bus interface 105, and nonvolatile memory 10. The bus interface 105 is an interface for connecting an internal device of the microcomputer 100 and an external device. The nonvolatile memory 10 is a rewritable memory such as a flash memory, and stores predetermined data. The CPU (101), the RAM (102), the port 103, the bus interface 105, and the nonvolatile memory 10 are connected to each other via a bus 111.

  Hereinafter, the nonvolatile memory 10 will be described in detail. FIG. 2 is a block diagram showing the nonvolatile memory according to the present embodiment. As shown in FIG. 2, the nonvolatile memory 10 according to the present embodiment includes a sequencer circuit 11, an operation mode selection circuit 12, a voltage value storage unit 13, a voltage setting register 14, a power supply circuit 15, and a memory unit 16. .

  The sequencer circuit 11 controls the rewrite operation to the memory unit 16 according to the input rewrite command 21. Here, the “rewriting operation” refers to an operation for writing data in the memory unit 16 (write operation) and an operation for erasing data held in the memory unit 16 (erase operation).

  When the rewrite command 21 for instructing the write operation is supplied, the sequencer circuit 11 controls the control gates (hereinafter also referred to as gates) GL1 and GL2 and the sources SL1 and SL2 of the memory cells (see FIG. 3) included in the memory unit 16. The power supply circuit 5 is controlled such that a voltage is applied to the power supply circuit 5. That is, by providing a potential difference between the gates GL1 and GL2 and the sources SL1 and SL2 (the gate side is set to a high potential), charges are injected from the source to the floating gate, and data is written into the memory cell.

  Further, when the rewrite command 21 instructing the erasing operation is supplied, the sequencer circuit 11 has a potential difference (source) between the gates GL1 and GL2 and the sources SL1 and SL2 of the memory cell (see FIG. 3) included in the memory unit 16. The power supply circuit 5 is controlled so as to generate a high potential on the side. As a result, the charge stored in the floating gate is released to the substrate, and the data written in the memory cell is erased.

  As described above, the sequencer circuit 11 controls the power supply circuit 15 according to the input rewrite command 21 to control the voltage applied to the memory cell of the memory unit 16.

  The operation mode selection circuit 12 selects an operation mode at the time of rewriting to the memory unit 16 according to the input operation mode selection information 22. Information about the selected operation mode is supplied to the voltage value storage unit 13. Here, the operation mode includes a speed priority mode (first operation mode) that prioritizes the rewrite speed to the memory unit 16 and a tolerance priority mode (second operation mode) that prioritizes the rewrite resistance of the memory unit 16. is there.

  The floating gate type nonvolatile memory records data using the presence / absence of charge of the floating gate (difference in charge amount). The presence or absence of charge in the floating gate appears as a difference in gate voltage (threshold voltage Vth). That is, when charge is stored in the floating gate, the resistance between the source and the drain is increased, so that a current flows at a high gate voltage (threshold voltage Vth is increased). On the other hand, when no electric charge is stored in the floating gate, the resistance between the source and the drain is lowered, so that a current flows at a low gate voltage (the threshold voltage Vth is lowered).

  As described above, in the nonvolatile memory that determines the presence / absence of data using the threshold voltage Vth of the gate, the threshold voltage Vth when charge is accumulated in the floating gate and the threshold when charge is not accumulated in the floating gate. It is necessary to ensure a width with respect to the voltage Vth. The width of the threshold voltage Vth can be adjusted by using the voltage value at the time of rewriting and the rewriting time (voltage application time). At this time, if the voltage at the time of rewriting is increased, the rewriting time can be shortened, but the deterioration of the insulating film of the memory cell is accelerated. For this reason, when the voltage at the time of rewriting is increased, the reliability of data after the rewriting operation is repeated a certain number of times or more is lowered. On the other hand, by suppressing the voltage at the time of rewriting to a low level, the deterioration of the insulating film of the memory cell can be suppressed, and the rewriting tolerance of the nonvolatile memory can be improved. However, in this case, since the voltage at the time of rewriting is kept low, the rewriting speed becomes slow.

  In the present embodiment, a speed priority mode that prioritizes the rewrite speed to the memory unit 16 and a tolerance priority mode that prioritizes the rewrite resistance of the memory unit 16 are provided as operation modes during the rewrite operation. That is, as shown in FIG. 4, in the speed priority mode, the rewrite speed can be increased, but the number of rewrites is reduced (for example, about 100 times). On the other hand, in the tolerance priority mode, the number of rewrites can be increased (for example, about 100,000 times), but the rewrite speed is slow. In the nonvolatile memory 10 according to the present embodiment, the operation mode at the time of the rewrite operation is set according to the operation mode selection information 22 supplied to the nonvolatile memory 10.

  For example, the operation mode selection information 22 is supplied to the nonvolatile memory 10 together with the rewrite command 21. In other words, when the rewrite command 21 is supplied to the nonvolatile memory 10, operation mode selection information 22 indicating the operation mode when the rewrite command 21 is executed is supplied to the nonvolatile memory 10. For example, as illustrated in FIG. 5, the rewrite command 21 may be configured to be continuously supplied to the nonvolatile memory 10 after the operation mode selection information 22 is supplied to the nonvolatile memory 10. Further, as shown in FIG. 6, a terminal for supplying the operation mode selection information 22 to the nonvolatile memory 10 may be provided.

  The voltage value storage unit 13 illustrated in FIG. 2 stores a rewrite voltage value corresponding to the operation mode selected by the operation mode selection circuit 12. For example, the voltage value storage unit 13 stores a combination of a gate voltage value and a source voltage value corresponding to each operation mode. Each of the speed priority mode and the tolerance priority mode may be further subdivided into a plurality of operation modes (for example, speed priority mode A, speed priority mode B,..., Tolerance priority mode A, tolerance priority). Mode B, etc.). In this case, combinations of gate voltage values and source voltage values corresponding to the subdivided operation modes are stored. Information on the rewrite voltage value corresponding to the operation mode is supplied to the voltage setting register 14.

  The voltage setting register 14 sets a rewrite voltage corresponding to the voltage value supplied from the voltage value storage unit 13. FIG. 7 is a table showing an example of register values and voltage values stored in the voltage setting register 14. As shown in FIG. 7, the voltage setting register 14 stores each voltage value and a register value corresponding to each voltage value.

  For example, when the operation mode selection information 22 supplied to the operation mode selection circuit 12 is the tolerance priority mode, the voltage value storage unit 13 sets the gate voltage value (7V) and the source voltage value (−4V) corresponding to the tolerance priority mode. ) Are output to the voltage setting register 14, respectively. The voltage setting register 14 outputs a register value (0x08) corresponding to the gate voltage value (7V) and a register value (0x05) corresponding to the source voltage value (−4V) to the power supply circuit 15, respectively.

  Further, for example, when the operation mode selection information 22 supplied to the operation mode selection circuit 12 is the speed priority mode, the voltage value storage unit 13 sets the gate voltage value (9 V) and the source voltage value (9 V) corresponding to the speed priority mode ( −5V) to the voltage setting register 14 respectively. The voltage setting register 14 outputs a register value (0x0F) corresponding to the gate voltage value (9V) and a register value (0x0A) corresponding to the source voltage value (−5V) to the power supply circuit 15, respectively.

  As described above, the voltage setting register 14 supplies the power supply circuit 15 with a rewrite voltage register value corresponding to the voltage value supplied from the voltage value storage unit 13.

  The power supply circuit 15 generates the power supply voltage set by the voltage setting register 14. That is, the power supply circuit 15 is activated by an instruction from the sequencer circuit 11, generates a power supply voltage corresponding to the register value supplied from the voltage setting register 14, and supplies the power supply voltage to the memory unit 16.

  The memory unit 16 is a non-volatile memory that stores predetermined data, and includes, for example, a flash memory. Data to be written in the memory unit 16 is supplied via, for example, the bus 111 shown in FIG.

  In this embodiment, when the rewrite operation to the memory unit 16 is performed according to the rewrite command 21, the rewrite operation to the memory unit 16 is performed with the power supply voltage according to the operation mode selection information 22 corresponding to the rewrite command 21. The operation is carried out. For example, the power supply voltage (gate-source voltage) in the speed priority mode is set higher than the power supply voltage (gate-source voltage) in the tolerance priority mode.

  Next, the operation of the nonvolatile memory 10 according to the present embodiment will be described using the flowchart shown in FIG. First, the nonvolatile memory 10 inputs the rewrite command 21 and the operation mode selection information 22 (Step S1). The sequencer circuit 11 selects a rewrite operation according to the input rewrite command 21 (step S2).

  When the rewrite command 21 instructing the write operation is supplied, the sequencer circuit 11 sets the write operation as the rewrite operation of the nonvolatile memory 10 (step S3). On the other hand, when the rewrite command 21 instructing the erase operation is supplied, the sequencer circuit 11 sets the erase operation as the rewrite operation of the nonvolatile memory 10 (step S4).

  Next, the operation mode selection circuit 12 selects an operation mode at the time of the rewrite operation to the memory unit 16 according to the input operation mode selection information 22 (step S5). For example, when the operation mode selection information 22 supplied to the operation mode selection circuit 12 is the speed priority mode, the nonvolatile memory 10 has a higher voltage as the rewrite operation voltage of the memory unit 16 (higher than that in the tolerance priority mode). Voltage) is set (step S6). Specifically, when the operation mode selection information 22 is the speed priority mode, the operation mode selection circuit 12 selects the speed priority mode as the operation mode and supplies information regarding the selected operation mode to the voltage value storage unit 13. To do. The voltage value storage unit 13 outputs the gate voltage value and the source voltage value corresponding to the speed priority mode to the voltage setting register 14, respectively. The voltage setting register 14 outputs a register value corresponding to the gate voltage value and a register value corresponding to the source voltage value to the power supply circuit 15 respectively. The power supply circuit 15 generates a power supply voltage corresponding to each register value output from the voltage setting register 14.

  On the other hand, when the operation mode selection information 22 supplied to the operation mode selection circuit 12 is in the tolerance priority mode, the nonvolatile memory 10 has a low voltage as a rewrite operation voltage of the memory unit 16 (lower than that in the speed priority mode). Voltage) is set (step S7). Specifically, when the operation mode selection information 22 is the tolerance priority mode, the operation mode selection circuit 12 selects the tolerance priority mode as the operation mode, and supplies information regarding the selected operation mode to the voltage value storage unit 13. To do. The voltage value storage unit 13 outputs the gate voltage value and the source voltage value corresponding to the tolerance priority mode to the voltage setting register 14, respectively. The voltage setting register 14 outputs a register value corresponding to the gate voltage value and a register value corresponding to the source voltage value to the power supply circuit 15 respectively. The power supply circuit 15 generates a power supply voltage corresponding to each register value output from the voltage setting register 14.

  Thereafter, the write operation or the erase operation is performed with the power supply voltage (gate voltage / source voltage) set by the above method (step S8).

  As described in the background art, recently, as a characteristic of a nonvolatile memory, an increase in rewrite speed and an improvement in rewrite resistance are required. For example, by suppressing the voltage at the time of rewriting the nonvolatile memory, deterioration of the insulating film of the memory cell can be suppressed, and the rewriting tolerance of the nonvolatile memory can be improved. However, in this case, since the voltage at the time of rewriting is kept low, the rewriting speed becomes slow. On the contrary, the rewriting speed can be increased by increasing the voltage at the time of rewriting, but in this case, since the insulating film of the memory cell is deteriorated, the rewriting durability of the nonvolatile memory is lowered.

  Here, the characteristics of the nonvolatile memory required by the user vary depending on the user who uses the nonvolatile memory. In other words, there are users who place importance on the rewriting speed and other users who place importance on rewriting resistance. However, in the current nonvolatile memory, the user cannot arbitrarily select the operation mode at the time of rewriting operation, and thus there is a problem that the user cannot use the nonvolatile memory with an optimum product specification.

  Therefore, in the nonvolatile memory 10 according to the present embodiment, the power supply voltage (gate-source voltage) at the time of the rewrite operation is set according to the operation mode selection information 22 selected by the user. Specifically, when the speed priority mode that prioritizes the rewrite speed to the memory unit 16 is selected, the power supply voltage (gate-source voltage) when the rewrite operation is in the tolerance priority mode is selected. Voltage). On the contrary, when the tolerance priority mode giving priority to the rewrite tolerance of the memory unit 16 is selected, the power supply voltage (gate-source voltage) at the time of the rewrite operation is the power supply voltage (gate-source voltage) in the speed priority mode. Is set to be lower. Therefore, the nonvolatile memory 10 according to the present embodiment can provide a nonvolatile memory that can be used with an optimum product specification according to the user.

  Further, in the nonvolatile memory 10 according to the present embodiment, the operation mode selection information 22 can be input in the same manner as when the rewrite command 21 is input, so that it is easy for the user who uses the nonvolatile memory 10. The operation mode can be selected.

  In the embodiment described above, the combination of the voltage between the gate and the source (see FIG. 7) is shown. However, the rewrite conditions are set by combining other voltage values and application times related to the rewrite characteristics. Also good. In the above description, two types of operation modes (speed priority mode and tolerance priority mode) have been described as examples. However, in this embodiment, the operation modes may be further increased. With such a configuration, the operation mode and rewrite conditions can be arbitrarily set, and various applications can be handled. Further, in the present embodiment, the voltage value storage unit 13 may be provided in the memory unit 16 or may be provided in an external EEPROM (Electrically Erasable Programmable Read-Only Memory). With such a configuration, a rewrite mode can be set for each product.

<Embodiment 2>
Next, a second embodiment will be described. FIG. 9 is a block diagram of the nonvolatile memory according to the second embodiment. As shown in FIG. 9, the nonvolatile memory 30 according to the present embodiment includes a sequencer circuit 31, an operation mode selection circuit 12, a voltage value storage unit 13, a voltage setting register 14, a power supply circuit 15, and a memory unit 32. . The nonvolatile memory 30 according to the present embodiment differs from the nonvolatile memory 10 described in the first embodiment in the configuration of the sequencer circuit 31 and the memory unit 32. Other than this, since it is the same as the nonvolatile memory 10 described in the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  The sequencer circuit 31 controls the rewrite operation to the memory unit 32 according to the input rewrite command 21. The rewrite command 21 includes address information of the memory unit 32 that performs rewriting, and the sequencer circuit 31 supplies the address information 25 to the operation mode information storage unit 33 of the memory unit 32. Since other operations are the same as those of the sequencer circuit 11 described in the first embodiment, a duplicate description is omitted.

  The memory unit 32 includes an operation mode information storage unit 33, a speed priority area 34, and a tolerance priority area 35. The speed priority area 34 (first memory area) is a memory area giving priority to the rewriting speed among the memory areas provided in the memory unit 32. The tolerance priority area 35 (second memory area) is a memory area giving priority to rewrite tolerance among the memory areas provided in the memory unit 32. Here, the power supply voltage (gate-source voltage) supplied to the speed priority area 34 is set higher than the power supply voltage (gate-source voltage) supplied to the tolerance priority area 35. The ratio of the speed priority area 34 and the tolerance priority area 35 can be arbitrarily determined by the user.

  The operation mode information storage unit 33 stores operation mode information corresponding to the addresses of the memory areas (speed priority area 34 and tolerance priority area 35) of the memory part 32. That is, the operation mode information storage unit 33 stores the address of the memory area and the operation mode of the memory area indicated by the address in association with each other. The operation mode information storage unit 33 outputs the operation mode information of the memory area corresponding to the address 25 supplied from the sequencer circuit 31 to the operation mode selection circuit 12 as the operation mode selection information 26. Note that the operation mode selection circuit 12, the voltage value storage unit 13, the voltage setting register 14, and the power supply circuit 15 are the same as those described in the first embodiment, and thus redundant description is omitted.

  FIG. 10 is a diagram for explaining an example of the operation mode information storage unit included in the memory unit 32. As shown in FIG. 10, the operation mode information storage unit 42 may be provided in an area different from the memory area 41 in which data is stored. In this case, the operation mode information storage unit 42 stores the start address of the memory area 41, the end address of the memory area, and the operation mode information (speed priority mode, tolerance priority mode) of the memory area in association with each other. Specifically, when the memory area indicated by the start address and the end address is the speed priority area 34, the speed priority mode is stored as the operation mode information. Similarly, when the memory area indicated by the start address and the end address is the tolerance priority area 35, the tolerance priority mode is stored as the operation mode information.

  FIG. 11 is a diagram for explaining another example of the operation mode information storage unit included in the memory unit 32. As shown in FIG. 11, in the memory unit 32, the memory area 45 is divided into a plurality of erase unit blocks 46. In this case, the operation mode information storage unit 47 is provided for each erase unit block 46. The operation mode information storage unit 47 stores operation mode information for each erase unit block. Specifically, when the erase unit block 46 is included in the speed priority area 34, the speed priority mode is stored as the operation mode information in the operation mode information storage unit 47 provided in the erase unit block 46. . Similarly, when the erase unit block 46 is included in the tolerance priority area 35, the tolerance priority mode is stored as the operation mode information in the operation mode information storage unit 47 provided in the erase unit block 46.

  Next, the operation of the nonvolatile memory 30 according to the present embodiment will be described using the flowchart shown in FIG. First, the nonvolatile memory 30 inputs a rewrite command 21 (including address information) (step S11). The sequencer circuit 11 selects a rewrite operation according to the input rewrite command 21 (step S12).

  When the rewrite command 21 instructing the write operation is supplied, the sequencer circuit 31 sets the write operation as the rewrite operation of the nonvolatile memory 30 (step S13). On the other hand, when the rewrite command 21 instructing the erase operation is supplied, the sequencer circuit 31 sets the erase operation as the rewrite operation of the nonvolatile memory 30 (step S14).

  In addition, the sequencer circuit 31 supplies the address information 25 included in the rewrite command 21 to the operation mode information storage unit 33 of the memory unit 32. The operation mode information storage unit 33 outputs the operation mode information of the memory area corresponding to the address 25 supplied from the sequencer circuit 31 to the operation mode selection circuit 12 as the operation mode selection information 26. The operation mode selection circuit 12 selects an operation mode at the time of rewriting operation to the memory unit 32 according to the input operation mode selection information (operation mode information) (step S15).

  For example, when the operation mode selection information 26 supplied to the operation mode selection circuit 12 is the speed priority mode, the nonvolatile memory 30 has a higher voltage as the rewrite operation voltage of the memory unit 32 (higher than that in the tolerance priority mode). Voltage) is set (step S16). Specifically, when the operation mode selection information 26 is the speed priority mode, the operation mode selection circuit 12 selects the speed priority mode as the operation mode, and supplies information regarding the selected operation mode to the voltage value storage unit 13. To do. The voltage value storage unit 13 outputs the gate voltage value and the source voltage value corresponding to the speed priority mode to the voltage setting register 14, respectively. The voltage setting register 14 outputs a register value corresponding to the gate voltage value and a register value corresponding to the source voltage value to the power supply circuit 15 respectively. The power supply circuit 15 generates a power supply voltage corresponding to each register value output from the voltage setting register 14.

  On the other hand, when the operation mode selection information 26 supplied to the operation mode selection circuit 12 is in the tolerance priority mode, the nonvolatile memory 30 has a low voltage as a rewrite operation voltage of the memory unit 32 (lower than that in the speed priority mode). Voltage) is set (step S17). Specifically, when the operation mode selection information 26 is the tolerance priority mode, the operation mode selection circuit 12 selects the tolerance priority mode as the operation mode, and supplies information regarding the selected operation mode to the voltage value storage unit 13. To do. The voltage value storage unit 13 outputs the gate voltage value and the source voltage value corresponding to the tolerance priority mode to the voltage setting register 14, respectively. The voltage setting register 14 outputs a register value corresponding to the gate voltage value and a register value corresponding to the source voltage value to the power supply circuit 15 respectively. The power supply circuit 15 generates a power supply voltage corresponding to each register value output from the voltage setting register 14.

  Thereafter, the write operation or the erase operation is performed with the power supply voltage (gate voltage / source voltage) set by the above method (step S18).

  Thus, in the nonvolatile memory 30 according to the present embodiment, a plurality of memory areas (speed priority area 34 and tolerance priority area 35) are set in one nonvolatile memory. It can be used for various purposes. In addition, since the user can arbitrarily set the ratio of the speed priority area 34 and the tolerance priority area 35, a nonvolatile memory that is highly convenient for the user can be provided. When changing the ratio of the speed priority area 34 and the tolerance priority area 35, for example, the operation mode information (operation mode information associated with the address of the memory area) stored in the operation mode information storage unit 33 is rewritten.

  In the nonvolatile memory 30 according to the present embodiment, the user can arbitrarily select the operation mode at the time of the rewrite operation. In this case, the nonvolatile memory 30 has the following protection. It is preferable to provide a function.

  For example, once the memory area is used in the speed priority mode, the insulating film of the memory cell in the memory area deteriorates. For this reason, if the memory area is subsequently used in the tolerance priority mode, the reliability of data cannot be ensured. Therefore, when the erasure unit block is set to the speed priority area (speed priority mode), the erasure unit block is changed from the speed priority area (speed priority mode) to the resistance priority area (resistance priority mode). May be configured to be prohibited.

  Even when the memory area is used once in the speed priority mode, the deterioration of the insulating film of the memory cell in the memory area does not progress so much when the number of rewrites is small. Therefore, even when the erasure unit block is set to the speed priority area (speed priority mode), if the number of rewrites is equal to or less than the predetermined number, the erasure unit block is moved from the speed priority area (speed priority mode). The setting may be changed to the tolerance priority area (resistance tolerance mode).

  On the other hand, when the memory area is used in the durability priority mode, deterioration of the insulating film of the memory cell in the memory area can be suppressed. Reliability can be ensured. Therefore, if the erasure unit block is set in the tolerance priority area (resistance tolerance mode), even if this erasure unit block is changed from the tolerance priority area (resistance tolerance mode) to the speed priority area (speed priority mode) Good.

  Also, as shown in FIG. 13, in the nonvolatile memory 30 according to the present embodiment, the operation mode information storage unit 51 can store the operation mode information for each erase unit block 52 in the memory area 50 over time. It may be configured. At this time, the operation mode information is stored in an OTP (One Time Program) unit of the operation mode information storage unit 51. For example, as shown in FIG. 13, the operation mode information storage unit for the erase unit block A records that the tolerance priority mode is set first and then the speed priority mode is set. Thus, by recording the operation mode information with time, even if the nonvolatile memory 30 fails, the history of the operation mode of the failed erase unit block can be checked.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 10 Nonvolatile memory 11 Sequencer circuit 12 Operation mode selection circuit 13 Voltage value storage part 14 Voltage setting register 15 Power supply circuit 16 Memory part 21 Rewrite command 22 Operation mode selection information 31 Sequencer circuit 32 Memory part 33 Operation mode information storage part 34 Speed priority Area 35 Resistant priority area 41 Memory area 42 Operation mode information storage section 45 Memory area 46 Erase unit block 47 Operation mode information storage section 50 Memory area 51 Operation mode information storage section 52 Erase unit block 100 Microcomputer 101 CPU
102 RAM
103 port 104 PLL circuit 105 bus interface

Claims (12)

A memory unit for storing data;
A sequencer circuit for controlling a rewrite operation to the memory unit in accordance with an input rewrite command;
An operation mode selection circuit for selecting an operation mode at the time of a rewrite operation to the memory unit according to the input operation mode selection information;
A voltage value storage unit storing a rewrite voltage value corresponding to the selected operation mode;
A voltage setting register for setting a rewrite voltage according to the voltage value stored in the voltage value storage unit;
A power supply circuit for generating a power supply voltage set by the voltage setting register,
When performing a rewrite operation to the memory unit according to the rewrite command, a rewrite operation to the memory unit is performed with a power supply voltage according to operation mode selection information corresponding to the rewrite command.
Non-volatile memory. The operation mode includes a first operation mode that prioritizes rewriting speed to the memory unit, and a second operation mode that prioritizes rewrite endurance of the memory unit,
The power supply voltage in the first operation mode is set higher than the power supply voltage in the second operation mode.
The non-volatile memory according to claim 1. The memory unit includes an operation mode information storage unit that stores operation mode information corresponding to an address of a memory area of the memory unit,
The operation mode information storage unit outputs operation mode information of a memory area corresponding to an input address to the operation mode selection circuit as the operation mode selection information.
The non-volatile memory according to claim 1.   The non-volatile memory according to claim 3, wherein the memory unit includes a first memory area that prioritizes rewrite speed and a second memory area that prioritizes rewrite endurance.   The nonvolatile memory according to claim 4, wherein the power supply voltage supplied to the first memory area is set higher than the power supply voltage supplied to the second memory area. The operation mode information storage unit is provided in an area different from a memory area in which the data is stored,
The operation mode information storage unit stores a start address of the memory area, an end address of the memory area, and operation mode information of the memory area in association with each other.
The non-volatile memory according to claim 3. The operation mode information storage unit is provided for each erase unit block of the memory area,
The operation mode information storage unit stores operation mode information for each erase unit block,
The non-volatile memory according to claim 3.   The operation mode information storage unit is configured to be able to store the operation mode information over time for each erase unit block, and the operation mode information is stored in an OTP (One Time Program) unit. Nonvolatile memory as described in 1. The operation mode includes a first operation mode that prioritizes rewriting speed to the memory unit, and a second operation mode that prioritizes rewrite endurance of the memory unit,
When a predetermined erase unit block is set in the first operation mode, the predetermined erase unit block is configured not to change the setting from the first operation mode to the second operation mode.
The non-volatile memory according to claim 3. The operation mode includes a first operation mode that prioritizes rewriting speed to the memory unit, and a second operation mode that prioritizes rewrite endurance of the memory unit,
When a predetermined erase unit block is set to the second operation mode, the predetermined erase unit block is configured to be changeable from the second operation mode to the first operation mode.
The non-volatile memory according to claim 3. The operation mode includes a first operation mode that prioritizes rewriting speed to the memory unit, and a second operation mode that prioritizes rewrite endurance of the memory unit,
When the number of rewrites of the predetermined erase unit block in the first operation mode is equal to or less than the predetermined number, the predetermined erase unit block can be changed from the first operation mode to the second operation mode. It is configured,
The non-volatile memory according to claim 3.   The nonvolatile memory according to claim 1, wherein the memory unit is configured using a flash memory.

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