JP2015130391A - Printed wiring board, semiconductor device and laminated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce coupling capacitance between two signal lines adjacent to each other while adjusting a propagation time of a signal propagating through the signal line by a coating member composed of a dielectric substance to reduce crosstalk jitter to improve signal quality.SOLUTION: Among a plurality of wiring patterns 251-258 in which two wiring patterns 251, 252, for example, are partially coated with coating members 271, 272 in a wiring direction, each of which is composed of a dielectric substance having higher relative permittivity than that of a dielectric substance of a dielectric layer. A length of one coating member 272 of the coating members 271, 272 in the wiring direction is set at a length not greater than a length of the other coating member 271 in the wiring direction. At least one end part of both end parts 272A, 272B of the coating member 272 in the wiring direction is arranged away from an interval R1 adjacent to the coating member 271 to the outside.

Description

  The present invention relates to a printed wiring board in which a plurality of signal lines are arranged in parallel, a semiconductor device including the printed wiring board, and a stacked semiconductor device including the semiconductor device.

  With the increase in functionality and miniaturization of portable electronic devices, semiconductor devices used in electronic devices are required to have multiple pins and a narrow pitch. A semiconductor package called a BGA (Ball Grid Array) is known as a structure for increasing the number of pins and narrowing the pitch of a semiconductor device. In order to further reduce the size, for example, a stacked semiconductor called PoP (Package on Package) in which a semiconductor package having a semiconductor element for memory is stacked on a semiconductor package having a semiconductor element for logic. The device is known.

  When communication is performed between a system LSI, which is an upper and lower semiconductor element in a stacked semiconductor device, and a DDR memory, eight signal lines (bus wirings) that transmit data signals and two differentials that transmit strobe signals Wiring is required. The data signal between the semiconductor elements needs to be synchronized in timing with the system clock so as not to malfunction. In order to synchronize the timing of the signal, the propagation time of the signal in the semiconductor element and on the interposer substrate is controlled. In recent years, the speed of the system has been increased, and the frequency of the signal flowing through the signal line has risen, making it difficult to control the time to ensure synchronization so as not to malfunction.

  There is a large difference between the pad pitch of a semiconductor element connected to an interposer of a generally used organic substrate and the pitch of a BGA pad connecting semiconductor devices to each other due to a difference in manufacturing technology. For example, the pad pitch of the semiconductor element is several tens [μm], whereas the pitch of the BGA pads is several hundred [μm], which is about 10 times as large. For this reason, when connecting a pad to which a semiconductor element is bonded and a BGA pad for connecting semiconductor devices to each other, a region in the lateral direction (direction perpendicular to the wiring direction) for developing the signal line is required. . This causes variations in the wiring length.

  In the stacked semiconductor device, a plurality of BGA pads for connecting the semiconductor devices are provided on the periphery of the interposer in order to secure a region for mounting the semiconductor element. Among the plurality of rows of BGA pads, the pads arranged on the innermost circumference side and the pads arranged on the outermost circumference side are different in distance from the semiconductor element in the vertical direction (wiring direction). This also causes variations in the wiring length.

  Since the propagation time of a signal propagating through each signal line varies due to such wiring length variation, as one of the methods for adjusting the propagation time on the interposer, in order to adjust the physical length of the signal line It has been proposed that the signal line has a meander wiring structure. The meander wiring structure is a method of aligning signal propagation times by aligning wiring lengths (physical lengths) among a plurality of signal lines while folding the signal lines into rectangles. However, in this method, the area occupied by the signal line increases as the signal line has a meander wiring structure, and the printed wiring board becomes larger.

  In view of this, another method has been proposed in which the signal length is adjusted by covering the signal line with a dielectric material having a high relative dielectric constant so as to align the signal propagation time (see Patent Document 1). In Patent Document 1, a signal line having a short wiring length with respect to a reference signal line is covered with a dielectric material having a high relative dielectric constant, and the length of the dielectric material is set to a length corresponding to the wiring length. By doing so, the propagation speed of the signal propagating through the signal line is changed to align the signal propagation time.

JP 2001-217509 A

  However, in the technique disclosed in Patent Document 1, since a dielectric material having a high relative dielectric constant is coated on two adjacent signal lines, the coupling capacitance (capacitance) due to capacitive coupling between the signal lines is increased. The crosstalk jitter was increased in the signal.

  More specifically, there is capacitive coupling between a signal line and a ground conductor pattern which is a reference potential arranged in a different layer (lower layer) from the signal line. In the stacked semiconductor device, the signal line width on the interposer is narrowed and the signal line interval is shortened, thereby increasing the signal line density and realizing miniaturization. Therefore, the distance between the signal lines is smaller than the distance between the signal lines and the ground conductor pattern. By covering the adjacent two signal lines with a dielectric having a high relative dielectric constant, the distance between the signal lines can be reduced. The coupling capacitance is relatively larger than the coupling capacitance with respect to the ground conductor pattern. As described above, when the coupling capacitance between the signal lines is increased, the crosstalk between the signal lines is increased, which is a factor of increasing the crosstalk jitter in the signal.

  Therefore, the present invention is a covering member made of a dielectric, and while adjusting the propagation time of a signal propagating through a signal line, the coupling capacitance between two adjacent signal lines is reduced, and crosstalk jitter is reduced to reduce the signal. The purpose is to improve quality.

  The present invention includes a dielectric layer and a conductor layer adjacent to the dielectric layer and in which a plurality of signal lines are arranged in parallel at intervals, and at least of the plurality of signal lines are adjacent to each other. Each of the two signal lines is a covering member made of a dielectric having a dielectric constant higher than that of the dielectric of the dielectric layer, and is partially covered in the wiring direction, and one of the two signal lines adjacent to each other. The length of the signal line is longer than the length of the other signal line, and the length of the covering member formed on the one signal line in the direction along the one wiring is formed on the other signal line. The length of the covering member is not more than the length in the direction along the other wiring, and the covering member formed on the one signal line and the covering member formed on the other signal line are not adjacent to each other It has a section.

  According to the present invention, the propagation time is adjusted by the covering member, the coupling capacity between adjacent signal lines is reduced, and the crosstalk jitter is reduced, thereby improving the signal quality of propagation through the signal lines.

It is explanatory drawing which shows schematic structure of the laminated semiconductor device which concerns on 1st Embodiment. It is explanatory drawing which shows the wiring structure of the interposer in the semiconductor package of the lower stage of the laminated semiconductor device which concerns on 1st Embodiment. 3 is an explanatory diagram illustrating a wiring structure of an interposer according to Embodiment 1. FIG. It is sectional drawing of the interposer which follows the IV-IV 'line | wire shown to Fig.2 (a). It is explanatory drawing which shows the wiring structure of the interposer in the lower stage semiconductor package of the laminated semiconductor device which concerns on 2nd Embodiment. 10 is an explanatory view showing a wiring structure of an interposer of Comparative Example 2. FIG.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
1A and 1B are explanatory views showing a schematic configuration of the stacked semiconductor device according to the first embodiment of the present invention. FIG. 1A is a sectional view of the stacked semiconductor device, and FIG. 1B is a printed wiring board. FIG. As shown in FIG. 1A, the stacked semiconductor device 100 is a stacked semiconductor package having a package-on-package (PoP) structure. The stacked semiconductor device 100 is configured by stacking a lower semiconductor package 200 that is a first semiconductor device and an upper semiconductor package 300 that is a second semiconductor device.

  The semiconductor package 200 includes a lower semiconductor element 201 as a first semiconductor element and a lower interposer 202 as a first printed wiring board (first interposer). The semiconductor package 300 includes an upper semiconductor element 301 as a second semiconductor element and an upper interposer 302 as a second printed wiring board (second interposer).

  The interposers 202 and 302 are multi-layer substrates having a square shape in plan view. In the first embodiment, the interposer 202 is a multilayer substrate in which a core layer 211 and build-up layers 212 and 213 formed on upper and lower surfaces thereof constitute four conductor layers.

  More specifically, as shown in FIG. 1B, the core layer 211 includes a dielectric layer (insulator layer) 224 and a conductor layer provided adjacent to both surfaces (both sides) of the dielectric layer 224. 223, 225. The build-up layer 212 includes a dielectric layer (insulator layer) 222 and a conductor layer 221 provided adjacent to one surface of the dielectric layer 222. The build-up layer 213 includes a dielectric layer (insulator layer) 226 and a conductor layer 227 provided adjacent to one surface of the dielectric layer 226. That is, the interposer 202 is configured by laminating four conductor layers 221, 223, 225, 227 and dielectric layers 222, 224, 226 disposed between the conductor layers 221, 223, 225, 227. Has been. The conductor layers 221 and 227 are surface layers, the conductor layers 223 and 225 are inner layers, and the surfaces of the conductor layers 221 and 227 are covered and protected by solder resists 228 and 229, respectively. The dielectric layer 222 is formed of a dielectric 280 such as resin. A ground conductor pattern (solid pattern) 290 to which a ground potential is applied is formed on the conductor layer 223 adjacent to the conductor layer 221 with the dielectric layer 222 interposed therebetween.

  The semiconductor element 201 illustrated in FIG. 1A is, for example, a system LSI, and the semiconductor element 301 is, for example, a DDR memory. Communication between the semiconductor elements 201 and 301 is performed via the lower and upper interposers 202 and 302 and solder balls 400 as solder joints that connect them. A plurality of upper and lower bonding pads (pad groups) 230 and 330 are provided in a peripheral shape on the opposing surfaces of the lower and upper interposers 202 and 302, and the pads 230 and 330 are bonded together by solder balls 400. Has been. Communication between the semiconductor element 201 and the semiconductor element 301 is performed using eight signal lines (bus wirings) that transmit data signals and two differential wirings that transmit strobe signals.

  FIG. 2 is an explanatory diagram showing a wiring structure of the interposer 202 in the lower semiconductor package 200 of the stacked semiconductor device 100 according to the first embodiment. FIG. 2A is a plan view of the interposer 202 viewed from the conductor layer 221 side, and illustration of the solder resist 228 is omitted. FIG. 2B is a plan view for explaining the arrangement relationship between the two covering members.

  In the first embodiment, which is DDR interface communication, as shown in FIG. 2A, eight pads 241 to 248 to which eight signal terminals (output terminals) 261 to 268 of the semiconductor element 201 are joined are conductors. The layer 221 is formed. Further, eight pads 231 to 238 (230) for joining the solder balls 400 are formed on the conductor layer 221. The pads 231 to 238 and the pads 241 to 248 are connected by eight strip-shaped wiring patterns (conductor patterns) 251 to 258 serving as signal lines (bus wiring). That is, pads 241 to 248 are formed at one end of the wiring patterns 251 to 258, and pads 231 to 238 are formed at the other end of the wiring patterns 251 to 258.

  The plurality of wiring patterns 251 to 258 are juxtaposed at intervals in the conductor layer 221. The wiring patterns 251 to 258 are formed with different wiring lengths. In the first embodiment, the wiring patterns 251, 253, 255, 257, 252, 254, 256, and 258 are used from the shorter wiring length. . That is, among the plurality of wiring patterns 251 to 258, the wiring pattern 258 is a signal line having the longest wiring length.

  Among the plurality of wiring patterns 251 to 258, at least two wiring patterns adjacent to each other, in the first embodiment, the wiring patterns 251 to 257 are partially covered with the respective covering members 271 to 277 in the wiring direction. . The covering members 271 to 277 are formed of a dielectric having a higher relative dielectric constant than the dielectric 280 of the dielectric layer 222 and the solder resist 228. In the first embodiment, each of the covering members 271 to 277 is formed of a dielectric having the same relative dielectric constant. That is, since each covering member 271 to 277 may be formed of the same material, manufacturing is easy.

  In the first embodiment, the wiring patterns 251 to 257 other than the signal line having the longest wiring length, that is, the wiring patterns 251 to 257 other than the wiring pattern 258 are covered with the respective covering members 271 to 277. That is, the wiring pattern 258 having the longest wiring length is used as a reference, and the wiring pattern 258 is not covered with the covering member. Thereby, the propagation time of the signal propagating through the wiring patterns 251 to 257 is aligned with the propagation time of the signal propagating through the wiring pattern 258, and signal synchronization is ensured.

  In the first embodiment, the covering members 271 to 277 are formed so as to cover the wiring patterns 251 to 257 along the wiring direction at intervals. The covering members 271 to 277 are arranged so as to be shifted in the wiring direction.

  Hereinafter, the covering members 271 and 272 that respectively cover the two wiring patterns 251 and 252 adjacent to each other will be described in detail with reference to FIG. As shown in FIG. 2B, the length of one of the two wiring patterns 251 and 252 is longer than the length of the other wiring pattern 251. As shown in FIG. 2B, the length of one of the covering members 271 and 272 along the wiring pattern 252 of one covering member 272 is the same as the length of the other covering member 271 along the wiring pattern 251. It is set below the length. In the first embodiment, the covering member 272 is set shorter than the covering member 271.

  Of the both ends 272A, 272B in the wiring direction of the covering member 272, at least one end, in the first embodiment, both ends 272A, 272B are outward from the section (range) R1 adjacent to the other covering member 271. They are shifted in the wiring direction. In other words, both the covering members 271 and 272 have non-adjacent sections (non-opposing portions) that do not oppose each other in a direction orthogonal to the wiring direction, that is, are not adjacent to each other. It is preferable that the non-adjacent sections in the respective covering members 271 and 272 face each other in a direction orthogonal to the wiring direction, that is, the length in the wiring direction is longer than that of the adjacent adjacent section (opposed portion). In the first embodiment, the entire covering members 271 and 272 are non-adjacent sections (non-opposing portions), and there are no adjacent sections (opposing portions).

  As described above, the propagation time of the signal propagating through the wiring patterns 251 through 257 by the covering members 271 through 277 is adjusted so as to be aligned with the propagation time of the signal propagating through the wiring pattern 258. Further, since the covering members 271 to 277 are arranged so as to be shifted from each other, the coupling capacitance due to the capacitive coupling between the adjacent wiring patterns is reduced, the crosstalk between the wiring patterns is reduced, and the crosstalk jitter in the signal is reduced. The Therefore, the signal quality that propagates through the wiring patterns 251 to 258 is improved. Further, since the wiring patterns 251 to 258 do not need to have a meander wiring structure, the interposer 202 can be downsized, and the semiconductor package 200 and the stacked semiconductor device 100 can be downsized.

  Here, in the first embodiment, the plurality of wiring patterns are composed of three or more wiring patterns, and the wiring patterns 251, 252, and 253 will be described as examples of the three wiring patterns adjacent to each other.

  In the covering members 271, 272, and 273, in order to increase the non-adjacent section, among the three adjacent wiring patterns 251, 252, and 253, the central wiring pattern 252 is longer than the wiring patterns 251 and 253 on both sides. Is preferably set long. Thereby, the length of the covering member 272 on the central wiring pattern 252 in the wiring direction can be made shorter than the length of the covering members 271 and 273 in the wiring direction. Accordingly, the non-adjacent sections can be increased in the covering members 271, 272, and 273, and further, the covering members 271, 272, and 273 are prevented from facing each other in the direction orthogonal to the wiring direction (the entire covering members 271 to 273 are arranged). Non-adjacent section). Therefore, crosstalk between the wiring patterns 251, 252, and 253 can be effectively reduced, and jitter due to crosstalk is reduced in signals propagating through the wiring patterns 251 to 253, so that signal quality is effectively improved. .

  In addition, as the three adjacent wiring patterns, wiring patterns 252, 253, and 254 will be described as an example. In the covering members 272, 273, 274, in order to increase the non-adjacent section, among the three adjacent wiring patterns 252, 253, 254, the central wiring pattern 253 is longer than the wiring patterns 252, 254 on both sides. Is preferably set short. Accordingly, the length in the wiring direction of the covering members 272 and 274 on the wiring patterns 252 and 254 on both sides can be made shorter than the length in the wiring direction of the covering member 273 on the central wiring pattern 253. Accordingly, the non-adjacent sections can be increased in the covering members 272, 273, and 274, and further, the covering members 272, 273, and 274 are prevented from facing each other in the direction orthogonal to the wiring direction (the entire covering members 272 to 274 are arranged). Non-adjacent section). Therefore, crosstalk between the wiring patterns 252, 253, and 254 can be effectively reduced, and jitter due to crosstalk is reduced in signals propagating through the wiring patterns 252 to 254, so that signal quality is effectively improved. .

  Furthermore, in the first embodiment, the plurality of wiring patterns include five or more wiring patterns, that is, eight wiring patterns 251 to 258. Of these eight wiring patterns 251 to 258, five adjacent wiring patterns 251 to 255 including the upper three wiring patterns 251, 253, and 255 will be described in the order of decreasing wiring length.

  Among these five wiring patterns 251 to 255 (wiring pattern group, signal line group), a wiring pattern 253 is arranged at the center of the wiring pattern group, and wiring patterns 251 and 255 are arranged on both sides of the wiring pattern group. Has been. Between the three wiring patterns 251, 253, and 255 having a short wiring length, wiring patterns 252 and 254 having a longer wiring length are arranged. That is, the wiring pattern 252 is disposed between the wiring pattern 251 and the wiring pattern 253, and the wiring pattern 254 is disposed between the wiring pattern 253 and the wiring pattern 255. In other words, the wiring patterns 251, 253, and 255 are arranged separated by the wiring patterns 252 and 254 having a wiring length longer than these wiring patterns.

  Further, the covering members 271 to 275 made of a dielectric having a higher relative dielectric constant than the surrounding dielectrics 228 and 280 are not covered on the five wiring patterns 251 to 255 between adjacent wiring patterns (not opposed to each other). Thus, the coating is shifted in the wiring direction (longitudinal direction). Thereby, the crosstalk between the wiring patterns 251 to 255 can be effectively reduced, and the crosstalk jitter in the signal is reduced, so that the signal quality can be effectively improved.

  Of the eight wiring patterns 251 to 258, five adjacent wiring patterns 252 to 256 including the three lower wiring patterns 252, 254, and 256 (in order of increasing wiring length) are arranged in the shortest wiring length. Will be described. Of the five wiring patterns 252 to 256 (wiring pattern group, signal line group), the wiring pattern 254 is arranged at the center of the wiring pattern group, and the wiring patterns 252 and 256 are arranged on both sides of the wiring pattern group. ing. Between the three wiring patterns 252, 254, and 256 having a long wiring length, wiring patterns 253 and 255 having a wiring length shorter than these are arranged. That is, the wiring pattern 253 is disposed between the wiring pattern 252 and the wiring pattern 254, and the wiring pattern 255 is disposed between the wiring pattern 254 and the wiring pattern 256. In other words, the wiring patterns 252, 254, 256 are arranged separated by the wiring patterns 253, 255 having a shorter wiring length than these wiring patterns.

  Further, the covering members 272 to 276 made of a dielectric having a relative dielectric constant higher than that of the surrounding dielectrics 228 and 280 are not covered (not opposed) between the adjacent wiring patterns on the five wiring patterns 252 to 256. Thus, the coating is shifted in the wiring direction (longitudinal direction). Thereby, the crosstalk between the wiring patterns 252 to 256 can be effectively reduced, and the crosstalk jitter in the signal is reduced, so that the signal quality can be effectively improved.

  In the first embodiment, the wiring pattern 255 and the wiring pattern 257 having a longer wiring length than the wiring pattern 252 are separated by the wiring pattern 256 having a longer wiring length than the wiring patterns 255 and 257. The covering members 276 and 277 are also covered on the two wiring patterns 256 and 257 while being shifted in the wiring direction (longitudinal direction) so as not to be covered (not opposed) between the adjacent wiring patterns 256 and 257. Yes. It is assumed that the covering members 271 to 277 have a longer distance (the length of the non-adjacent section) between the adjacent wiring patterns than the length in which the covering members run in parallel (the length of the adjacent section). Preferably, each covering member is independently covered so as not to be covered (not opposed) between adjacent wiring patterns.

  Here, the parallel bus wiring is a bus wiring having 8 bits as one signal group. In the first embodiment, eight wiring patterns 251 to 258 are formed in the interposer 202 as this type of bus wiring. Yes. In the eight wiring patterns 251 to 258, it is necessary to synchronize the timing of signals. Among these eight wiring patterns 251 to 258, at least the upper three wiring patterns 251, 253, and 255 are separated by the wiring patterns 252 and 254 having longer wiring lengths than the wiring patterns 251, 253, and 255 in the order of decreasing wiring length. It is arranged. Therefore, in the first embodiment, the short wiring patterns 251, 253, 255 are not adjacent to each other. Therefore, it becomes possible to dispose the covering members 271 to 275 made of a dielectric material having a high relative dielectric constant in the wiring direction so as not to face each other, and the coupling capacitance due to capacitive coupling between the wiring patterns is minimized. However, the signal propagation time can be adjusted.

  The operation will be specifically described below. In the first embodiment, when controlling the propagation time in a signal group that ensures timing synchronization, the propagation times of other wirings are basically aligned with the propagation time of the wiring pattern 258 having a long wiring length. For this reason, covering members 271 to 277 made of a dielectric material having a high relative dielectric constant are arranged over the area in the longitudinal direction (wiring direction) on the wiring patterns 251 to 257 having a short wiring length.

  At that time, if the wiring patterns having a short wiring length are adjacent to each other, a region where a covering member made of a dielectric material having a high relative dielectric constant exists between the adjacent wiring patterns becomes long (the facing portion becomes long). As a result, the coupling capacitance between the wiring patterns cannot be sufficiently reduced.

  Therefore, by changing the arrangement order of the wiring patterns according to the wiring length of the wiring pattern, the signal propagation time is adjusted while reducing the coupling capacitance due to capacitive coupling between the wiring patterns. Ideally, the larger the wiring length difference between adjacent wiring patterns, the longer the dielectric with a high relative dielectric constant for a wiring pattern with a shorter wiring length and the higher the dielectric constant between adjacent wiring patterns. It is possible to cover the bodies without running them side by side.

  That is, it is possible to maintain a state in which the coupling capacitance between the wiring pattern and the ground conductor pattern 290 is larger than the coupling capacitance between adjacent wiring patterns. Therefore, the propagation time can be adjusted while reducing the coupling capacitance between the wiring patterns.

  In the eight wiring patterns 251 to 258 that synchronize the timing of signals, a case is considered in which two rows of connection pads 230 (231 to 238) used for bonding the upper and lower semiconductor packages 200 and 300 are provided on the periphery of the interposer 202. . That is, in the first embodiment, the plurality of pads 230 are arranged in two rows.

  In the first embodiment, the wiring patterns 252, 254, and 256 that are groups having a long wiring length are arranged between the wiring patterns 251, 253, 255, and 257 that are a group having a short wiring length. A wiring pattern 258 having the longest wiring length is disposed outside the wiring pattern 257.

  In FIG. 2A, the four pads 231, 233, 235, and 237 to which the upper four wiring patterns 251, 253, 255, and 257 are connected in the order of decreasing wiring length are arranged inside, and the remaining four pads 232, An N-shaped arrangement in which 234, 236, and 238 are arranged outside is assumed. Thereby, the dispersion | variation in the wiring length difference of each adjacent wiring pattern becomes small. Therefore, it is possible to suppress variations in the propagation time difference.

  The N-shaped arrangement is arranged in the order of pads 231, 233, 235, 237 on the inner side (side closer to the semiconductor element 201) and in the order of pads 232, 234, 236, 238 on the outer side (side farther from the semiconductor element 201). It is realized by doing. The arrangement order of the wiring patterns is wiring patterns 251, 252, 253, 254, 255, 256, 257, and 258. The arrangement order of the wiring lengths is 1, 5, 2, 6, 3, 7, 4 and 8, where 1 is the shortest pattern and 8 is the longest pattern. As described above, it is preferable to arrange three or more wiring length orders between adjacent wiring patterns, but two or more wiring patterns may be used.

  Of the eight wiring patterns 251 to 258, the covering members 271 to 277 made of a dielectric material having a high relative dielectric constant are applied to the seven wiring patterns 251 to 257 other than the wiring pattern 258 having the longest reference wiring length. Ideally it should be coated. Effectively, it is sufficient to cover the five wiring patterns 251 to 255 including the upper three wiring patterns 251, 253, and 255 and the wiring patterns 252 and 254 between the wiring patterns in order of decreasing wiring length. Further, by coating the remaining two wiring patterns 256 and 257 with covering members 276 and 277 made of a dielectric material having a high relative dielectric constant, it is possible to reduce the variation in propagation time. Further, by shifting the covering member so as not to be covered between the adjacent wirings, it is possible to reduce the interval between the adjacent wiring patterns, to reduce the wiring area, and to reduce the area of the interposer 202 and thus the semiconductor package 200. The size of the type semiconductor device 100 can be reduced.

Example 1
In the first embodiment, electromagnetic field analysis was performed as Example 1 in order to verify the effect of adjusting the propagation time and reducing the coupling capacitance by capacitive coupling. The tool used was Mentor's XFX, a commercially available 2D analysis. The size of the assumed semiconductor package was 13 [mm □], the size of the Chip was 7 [mm □], and the BGA pad pitch was 0.4 [mm]. The covering members 271 to 277 made of a dielectric material having a high relative dielectric constant were formed of two or more dielectric materials having different relative dielectric constants. Specifically, the covering members 271, 272, 273, 274, and 276 have the same relative dielectric constant, and the ratio between the covering members 271, 272, 273, 274, 276, the covering member 275, and the covering member 277 is a ratio. Different dielectric constants were used.

  FIG. 3 is an explanatory diagram illustrating a wiring structure of the printed wiring board (interposer) 202 according to the first embodiment. FIG. 3A is a plan view of the printed wiring board (interposer) 202 as viewed from the conductor layer 221 side, and the solder resist 228 is not shown.

  3B is a cross-sectional view of the interposer 202 taken along line IIIb-IIIb ′ in FIG. 3A, and FIG. 3C is a cross-sectional view of the interposer 202 taken along line IIIc-IIIc ′ in FIG. It is a figure and the surface layer 221 and the lower layer 223 are shown in figure. As shown in FIG. 3B, covering members 271, 273, 275, and 277 made of a dielectric material having a high relative dielectric constant are provided on the wiring patterns 251, 253, 255, and 257, and other insulating materials are provided. Further, a solder resist 228 made of a dielectric is provided. A ground conductor pattern 290 to which a ground potential is applied is provided directly below the wiring patterns 251 to 258 with the dielectric 280 interposed therebetween. As shown in FIG. 3 (c), covering members 272, 274, and 276 made of a dielectric material having a high relative dielectric constant are provided on the wiring patterns 252, 254, and 256, and other solder materials made of a dielectric material are used for insulation. A resist 228 is provided.

  The analysis conditions are shown below. The width of the wiring patterns 251 to 258 is 20 [μm], the thickness is 10 [μm], the material is copper, and the interval between the wiring patterns 251 to 258 is 20 [μm]. The ground conductor pattern 290 to which the ground potential is applied has a thickness of 10 [μm] and is made of copper.

The height and width of the covering members 271 to 277 are both 30 [μm], the relative permittivity of the covering members 271,272,273,274,276 is 50, the relative permittivity of the covering member 275 is 35,
The relative dielectric constant of the covering member 277 was 15. For example, the material is RAYBRID manufactured by Toray Industries, Inc. or CS-3396 manufactured by Risho Kogyo Co., Ltd.

  For example, the covering member 271 of the wiring pattern 251 having the shorter wiring length is a dielectric having a higher relative dielectric constant than the covering member 275 of the wiring pattern 255 or the covering member 277 of the wiring pattern 257 having the longer wiring length. Is formed. That is, the higher the relative dielectric constant of the covering member, the slower the signal propagation speed of the wiring pattern and the longer the signal propagation time. Therefore, the relative dielectric constant of the covering member that covers the shorter wiring length of the wiring pattern than the longer wiring length of the wiring pattern is the relative dielectric constant of the covering member that covers the longer wiring length of the wiring pattern. Higher than that.

  The relative dielectric constant of the solder resist 228 made of a dielectric was set to 3.0. For example, the material is PSR-4000 series PSR-4000, AUS5, etc. manufactured by Taiyo Ink Manufacturing Co., Ltd.

  The dielectric 280 had a thickness of 40 [μm] and a relative dielectric constant of 4.8. For example, the material is MCL-E-679 series, MCL-E-679GT manufactured by Hitachi Chemical Co., Ltd., MEGRON series manufactured by Panasonic, R-1515, or the like.

  The wiring length of the wiring pattern 251 is 4.0 [mm], the wiring length of the wiring pattern 252 is 4.55 [mm], the wiring length of the wiring pattern 253 is 4.13 [mm], and the wiring length of the wiring pattern 254 is 4. .79 [mm], and the wiring length of the wiring pattern 255 was 4.40 [mm]. The wiring length of the wiring pattern 256 was 5.03 [mm], the wiring length of the wiring pattern 257 was 4.64 [mm], and the wiring length of the wiring pattern 258 was 5.31 [mm]. The difference in the order of the wiring lengths of the adjacent wirings is set to two or more between the adjacent wirings. As in the first embodiment, the order of wiring lengths between adjacent wirings may be switched.

  The length of the covering member 271 is 3.1 [mm], the length of the covering member 272 is 1.4 [mm], the length of the covering member 273 is 3.1 [mm], and the length of the covering member 274 is 1. .6 [mm], and the length of the covering member 275 was 3.1 [mm]. The length of the covering member 276 was 0.9 [mm], and the length of the covering member 277 was 3.1 [mm].

  The signal propagation time in each of the wiring patterns 251 to 258 is 31.87 [ps], 31.98 [ps], 32.70 [ps], 33.92 [ps], 33.82 [ps], 34 in order. .05 [ps], 33.77 [ps], and 34.04 [ps]. The propagation time of the wiring pattern 258 having the longest wiring length was 34.04 [ps], the propagation time of the shortest wiring pattern 251 was 32.69 [ps], and the difference in propagation time was 1.35 [ps].

  As Comparative Example 1, the result in the case where a coating member having a high relative dielectric constant is not coated will be described. The propagation times of the wiring patterns 251 to 258 are, in order, 25.64 [ps], 26.47 [ps], 28.20 [ps], 29.17 [ps], 29.74 [ps], and 30.70. [Ps], 32.24 [ps], and 34.04 [ps]. The difference in propagation time between the wiring pattern 258 having the longest reference wiring length and the wiring pattern 251 having the shortest wiring length was 1.35 [ps] in Example 1 and 8.40 [ps] in Comparative Example 1.

  Example 1 was able to improve the propagation time difference by 83.9% compared to Comparative Example 1. In addition, the variation range was 2.18 [ps] and 8.40 [ps], and it was confirmed that the first embodiment can reduce the variation in propagation time in the system and improve the signal quality. .

  FIG. 6 is an explanatory diagram showing a wiring structure of a printed wiring board (interposer) of Comparative Example 2. FIG. 6A is a plan view of the printed wiring board (interposer) viewed from the conductor layer 221 side, and the solder resist 228 is not shown. FIG. 6B is a cross-sectional view of the printed wiring board along the line VIb-VIb ′ in FIG. 6A, and illustrates a surface layer 221 and a lower layer 223 thereof.

  In Comparative Example 2, the wiring patterns 251 to 257 are covered with the covering members 1271 to 1277 made of the same material as the covering members 271 to 277 of the first embodiment. Is different from the first embodiment. That is, in the comparative example 2, as shown to Fig.6 (a), the position of the one edge part of all the coating | coated members 1271-1277 is arrange | equalized.

  The coupling capacity by capacitive coupling between the wiring pattern 251 having the shortest wiring length and the wiring pattern 252 adjacent thereto was compared between the case of Example 1 and the case of Comparative Example 2.

  In Comparative Example 2, the wiring pattern dimensions, dielectric dimensions, and relative dielectric constant were the same as in Example 1. The length of the dielectric covering member having a high relative dielectric constant was the same as that of Example 1, the length of the covering member 1271 was 3.1 [mm], and the length of the covering member 1272 was 1.4 [mm].

  The total coupling capacitance in the section in which the wiring patterns 251 and 252 in the case of Example 1 are running in parallel is 0.22 [pF], and in the case of Comparative Example 2, it is 0.28 [pF]. As in Example 1, the covering member made of a dielectric material having a high relative dielectric constant was shifted and covered in the wiring direction, so that the coupling capacity was 23.9% smaller than that in Comparative Example 2.

  Further, as Comparative Example 3, in the structure of Comparative Example 2 shown in FIG. 6, the total coupling capacitance in the parallel running section when the wiring pattern interval is widened to 30 [μm] is the case of Example 1. And the case of Comparative Example 3 were compared. In the case of the comparative example 3, it was 0.24 [pF], and the coupling capacitance was smaller than that in the case where the wiring interval of the example 1 was 20 [μm]. Therefore, in the case of the comparative example 3, it has been found that the wiring interval needs to be 10 [μm] wider than that in the case of the first example. This indicates that the wiring area of 10 [μm] per bit increases. For example, in the case of 8 bits, 80 [μm] per signal group for ensuring timing, and in the case of 64 bits as an electronic device system, the wiring area increases by 640 [μm]. That is, with the structure of the first embodiment, the wiring area can be reduced, and the interposer 202, and thus the semiconductor package 200 and the stacked semiconductor device 100 can be downsized.

  In addition, although the interval of each wiring pattern in this embodiment is 20 [μm], it is preferably 10 [μm] or more and 30 [μm] or less. When the interval between the wiring patterns is narrower than 10 [μm], it is difficult to cover the wiring patterns with the covering member. Further, when Example 1 and Comparative Example 2 in the case where the width is larger than 30 [μm] are compared, it is assumed that the difference in the coupling capacitance is 5% or less, and the substantial effect is reduced.

(Example 2)
About 1st Embodiment, it verified about the effect of adjustment of propagation time and reduction of coupling capacity similarly to Example 1. FIG. Only one type of dielectric material is used for the covering members 271 to 277 made of a dielectric material having a high relative dielectric constant. That is, the relative dielectric constants of the covering members 271 to 277 are the same.

  FIG. 4 is a cross-sectional view of the interposer 202 taken along the line IV-IV ′ shown in FIG. 2A, and shows the buildup layer 212. In FIG. 4, covering members 271, 273, 275, and 277 made of a dielectric material having a high relative dielectric constant are provided on the wiring patterns 251, 253, 255, and 257, but on the remaining wiring patterns 252, 254, and 256. A covering member is also provided. In addition, a solder resist 228 made of a dielectric is provided for insulation. A ground conductor pattern 290 to which a ground potential is applied is provided directly below the wiring patterns 251 to 258 with the dielectric 280 interposed therebetween.

  The analysis conditions are shown below. The widths of the wiring patterns 251 to 258 were 20 [μm], the thickness was 10 [μm], the material was copper, and the interval between the wiring patterns was 20 [μm]. The height and width of the covering members 271 to 277 were both 30 [μm], and the relative dielectric constant was 50. The relative permittivity of the solder resist 228 was set to 3.0. The ground conductor pattern 290 has a thickness of 10 [μm] and is made of copper. The dielectric 280 had a thickness of 40 [μm] and a relative dielectric constant of 4.8.

  The wiring length of the wiring pattern 251 is 4.0 [mm], the wiring length of the wiring pattern 252 is 4.55 [mm], the wiring length of the wiring pattern 253 is 4.13 [mm], and the wiring length of the wiring pattern 254 is 4. 79 mm. Further, the wiring length of the wiring pattern 255 is 4.40 [mm], the wiring length of the wiring pattern 256 is 5.03 [mm], the wiring length of the wiring pattern 257 is 4.64 [mm], and the wiring length of the wiring pattern 258 Was set to 5.31 [mm].

  The length of the covering member 271 in the wiring direction is 3.1 [mm], the length of the covering member 272 in the wiring direction is 1.4 [mm], and the length of the covering member 273 in the wiring direction is 3.1 [mm]. The length of the covering member 274 in the wiring direction was 1.6 [mm]. The length of the covering member 275 in the wiring direction is 3.1 [mm], the length of the covering member 276 in the wiring direction is 0.9 [mm], and the length of the covering member 277 in the wiring direction is 3.1 [mm]. mm].

  The propagation times of the wiring patterns 251 to 258 are 31.87 [ps], 31.98 [ps], 32.70 [ps], 33.92 [ps], 34.44 [ps], and 34.05 in this order. [Ps], 35.97 [ps], and 34.04 [ps].

  Similar to the first embodiment, the propagation time of the wiring pattern 258 having the longest wiring length is 34.04 [ps], the propagation time of the wiring pattern 251 having the shortest wiring length is 31.87 [ps], and the propagation time difference is 2 .17 [ps]. Compared to 8.4 [ps], which is the difference in propagation time when no countermeasure is taken, Example 2 shows an improvement of 74.2%.

  Also, the propagation time variation ranges are 4.10 [ps] and 8.40 [ps], and the propagation time variation in the system can be reduced in the second embodiment, and the signal quality is improved. Further, since the dielectric having a high relative dielectric constant is controlled by one type, adjustment in terms of length is easy, and the number of times of applying the dielectric is less than that of the first embodiment. It can be manufactured and the cost can be reduced.

[Second Embodiment]
Next, a stacked semiconductor device according to a second embodiment of the present invention will be described. FIG. 5 is an explanatory view showing a wiring structure of an interposer in the lower semiconductor package of the stacked semiconductor device according to the second embodiment. In addition, about the structure similar to the said 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted. FIG. 5A is a plan view of the interposer as seen from the conductor layer 221 side, and illustration of the solder resist 228 is omitted. 5B is an enlarged view of the covering member in FIG. 5A, FIG. 5C is a cross-sectional view taken along the line Vc-Vc ′ in FIG. 5B, and FIG. 5D is FIG. ) Is a cross-sectional view taken along the line Vd-Vd ′, and FIG. 5E is a cross-sectional view taken along the line Ve-Ve ′ in FIG. Of the cross-sectional structure of the interposer, FIG. 5C to FIG. 5E show the surface wiring and the lower layer.

  Also in the second embodiment, as in the first embodiment, the pads 241 to 248 to which the signal terminals 261 to 268 of the semiconductor element 201 are joined and the pads 231 to 238 are connected by the wiring patterns 251 to 258. The three wiring patterns 251, 253, and 255 having a short wiring length from the pads 241 to 248 to the pads 231 to 238 are arranged separated by the wiring patterns 252 and 254 having a wiring length longer than the wiring pattern. Furthermore, covering members 271X, 272X, and 273 to 277, which are dielectrics having a relative dielectric constant higher than that of the surrounding dielectrics, are arranged on the wiring patterns 251 to 257 while being shifted in the wiring direction.

  In the second embodiment, the covering members 271X and 272X that respectively cover the two wiring patterns 251 and 252 that are adjacent to each other have opposing portions 271Xa and 272Xa that face each other in a direction orthogonal to the wiring direction. The opposing portions 271Xa and 272Xa are cut out so as to expose the side end portions 251c and 252c facing each other in the two covering 251 and 252. That is, two planes (virtual planes) P1 and P2 perpendicular to the stacking direction L passing through the side end portions 251c and 252c facing each other in the two wiring patterns 251 and 252 covered with the covering members 271X and 272X are defined. To do. The facing portions 271Xa and 272Xa are formed by cutting out a portion of the space sandwiched between the two planes P1 and P2.

  In particular, in the wiring pattern 252 adjacent to the shortest wiring pattern 251, the opposed portions 271 </ b> Xa and 272 </ b> Xa may occur. As shown in FIGS. 5C to 5E, when a cross section of the covering members 271X and 272X is viewed, there is no dielectric having a high relative dielectric constant in the region between the wiring patterns 251 and 252. Further, the opposing portions 271Xa and 272Xa are formed by notching. 5C to 5E, the facing portions 271Xa and 272Xa are notched obliquely in the wiring direction.

  According to the second embodiment, as in the first embodiment, the coupling members 271X, 272X, 273 to 277 that adjust the propagation time are shifted in the wiring direction to reduce the coupling capacitance between the wiring patterns. Since the crosstalk jitter is reduced, the signal quality is improved.

  At this time, there may be a case where the opposing portions 271Xa and 272Xa need to be formed in order to earn a dielectric covering region necessary for minimizing the propagation time difference between the wiring pattern having a short wiring length and the adjacent wiring pattern. . In this case, by forming a notch in the facing portions 271Xa and 272Xa, an increase in coupling capacitance between the wiring patterns 251 and 252 can be suppressed, and a decrease in signal quality can be suppressed. In addition, the propagation time difference can be reduced, the interval between adjacent wirings can be narrowed, the wiring area can be reduced, and the semiconductor device can be miniaturized. Furthermore, in the wiring pattern, rapid fluctuations in impedance are reduced between the wiring part covered with the covering member made of a dielectric material having a high relative dielectric constant and the wiring part not covered, and the reflection of the signal waveform is reduced. The signal quality is further improved.

(Example 3)
In the stacked semiconductor device of the second embodiment, in order to verify the effect of adjusting the propagation time and reducing the coupling capacitance, in the wiring structure of FIG. 5 described in the second embodiment, the electromagnetic field is similar to the above example. Analysis was performed.

  This will be described below using the wiring structure of FIG. Cover members 271X and 272X made of a dielectric material having a high relative dielectric constant are provided on the wiring patterns 251 and 252, and a solder resist 228 is provided for other insulation. A ground conductor pattern 290 is provided directly below the wiring patterns 251 to 258 with the dielectric 280 interposed therebetween.

  The analysis conditions are shown below. The widths of the wiring patterns 251 to 258 were 20 [μm], the thickness was 10 [μm], the material was copper, and the interval between the wiring patterns was 20 [μm].

  The height and width of the covering members 271X, 272X, 273 to 277 were both 30 [μm], and the relative dielectric constant was 50. The relative permittivity of the solder resist 228 was set to 3.0. The ground conductor pattern 290 has a thickness of 10 [μm] and is made of copper. The dielectric 280 had a thickness of 40 [μm] and a relative dielectric constant of 4.8.

  The wiring length of the wiring pattern 251 is 3.5 [mm], the wiring length of the wiring pattern 252 is 4.05 [mm], the wiring length of the wiring pattern 253 is 3.63 [mm], and the wiring length of the wiring pattern 254 is 4. .29 [mm], and the wiring length of the wiring pattern 255 was 3.9 [mm]. The wiring length of the wiring pattern 256 was 8.53 [mm], the wiring length of the wiring pattern 257 was 4.14 [mm], and the wiring length of the wiring pattern 258 was 4.81 [mm].

  The length of the covering member 271X in the wiring direction is 2.8 [mm], the length of the covering member 272X in the wiring direction is 1.25 [mm], and the length of the covering member 273 in the wiring direction is 2.8 [mm]. The length of the covering member 274 in the wiring direction was 1.49 [mm]. The length of the covering member 275 in the wiring direction is 2.8 [mm], the length of the covering member 276 in the wiring direction is 1.73 [mm], and the length of the covering member 277 in the wiring direction is 2.8 [mm]. mm]. Further, the facing portions 271Xa and 272Xa of the covering members 271X and 272X on the wiring patterns 251 and 252 have a length in the wiring direction of 0.7 [mm] and are obliquely covered in the longitudinal direction.

  The difference in propagation time between the longest wiring pattern 258 and the shortest wiring pattern 251 was 5.27 [ps]. As a comparative example, each wiring pattern length was the same as described above, and the case where the ends of the covering members 271X and 272X were not cut obliquely was also analyzed.

  The length of the covering member coated on the wiring pattern 251 in the wiring direction is 2.9 [mm], the length of the covering member coated on the wiring pattern 252 in the wiring direction is 1.15 [mm], and on the wiring pattern 253 The length in the wiring direction of the covering member coated on was 2.9 [mm]. The length in the wiring direction of the covering member coated on the wiring pattern 254 was 1.39 [mm], and the length in the wiring direction of the covering member coated on the wiring pattern 255 was 2.9 [mm]. The length in the wiring direction of the covering member coated on the wiring pattern 256 was 1.63 [mm], and the length in the wiring direction of the covering member coated on the wiring pattern 257 was 8.9 [mm].

  In the case of this comparative example, the signal propagation time difference between the longest wiring pattern 258 and the shortest wiring pattern 251 is 5.77 [ps]. It was confirmed that the difference in propagation time can be reduced by 8.7% by covering the covering members 271X and 272X obliquely in the wiring direction at the facing portions as in Example 3.

  Further, the standard deviation indicating the length variation of the eight wiring patterns is changed from 1.10 to 1.03, and the variation in the system can be suppressed. Also in the coupling capacity, the capacity per unit length was improved by 28.5% to 0.05 [pF / mm] with respect to 0.07 [pF / mm].

  Furthermore, by covering the wiring direction obliquely, impedance fluctuations are reduced between the wiring part covered with a covering member made of a dielectric material having a high relative dielectric constant and the wiring part not covered, and the signal waveform is reflected. Is reduced and the signal quality is improved.

  The present invention is not limited to the embodiment described above, and many modifications are possible within the technical idea of the present invention.

  In the above embodiment, the case where the wiring pattern as the signal line is formed on the surface layer of the printed wiring board has been described, but even if the wiring pattern as the signal line is formed on the inner layer of the printed wiring board, The invention is applicable.

  In the above-described embodiment, the BGA connection pads 230 (231 to 238) arranged on the periphery of the interposer have been described as having a two-row structure. The invention is applicable.

  In the above embodiment, the covering member formed of a dielectric material having a high relative dielectric constant has been described as being continuously covered in the wiring direction. However, the present invention can be applied even if the dielectric material is intermittently covered. Is possible.

  In the above embodiment, the stacked semiconductor device has been described. However, the present invention is not limited to this. The present invention can also be applied to a printed wiring board which is an interposer of a semiconductor device alone or a stackable semiconductor device instead of a stacked type, and the present invention is also applied to a printed wiring board which is a motherboard on which a semiconductor device or the like is mounted. Applicable.

  In the above embodiment, the signal line with the longest wiring length is not covered with the covering member, but the present invention does not exclude the case where the signal line with the longest wiring length is covered with the covering member. The case where the covering member is covered on the signal line having the longest wiring length is also included.

DESCRIPTION OF SYMBOLS 100 ... Stack type semiconductor device, 200 ... Semiconductor package (semiconductor device), 201 ... Semiconductor element, 202 ... Interposer (printed wiring board), 221 ... Conductor layer, 222 ... Dielectric layer, 251-258 ... Wiring pattern (signal line) , 271 to 277 ... covering member, 272A, 272B ... end, R1 ... section

Claims (12)

A dielectric layer; and a conductor layer adjacent to the dielectric layer and in which a plurality of signal lines are arranged side by side at intervals,
Of the plurality of signal lines, at least two signal lines adjacent to each other are partially covered in the wiring direction with a covering member made of a dielectric having a relative dielectric constant higher than that of the dielectric of the dielectric layer. ,
Of two signal lines adjacent to each other, the length of one signal line is longer than the length of the other signal line, and the length in the direction along the one wiring of the covering member formed on the one signal line Is less than or equal to the length in the direction along the other wiring of the covering member formed on the other signal line,
The printed wiring board, wherein the covering member formed on the one signal line and the covering member formed on the other signal line have non-adjacent sections that are not adjacent to each other.   The plurality of signal lines are composed of three or more signal lines, and the adjacent three signal lines are two signal lines in which the wiring length of one signal line located at the center of the three signal lines is located on both sides. The printed wiring board according to claim 1, wherein the wiring length is longer than each of the wiring lines, or the wiring length is shorter than each of the two signal lines located on both sides.   The plurality of signal lines are composed of five or more signal lines, and five adjacent signal lines are located at the length of one signal line located at the center of the five signal lines and at both ends of the five signal lines. 2. The printed wiring board according to claim 1, wherein the two signal lines are the upper three signal lines or the lower three signal lines in order of decreasing wiring length among the five signal lines. .   4. The print according to claim 1, wherein among the plurality of signal lines, signal lines other than the signal line having the longest wiring length are covered with the respective covering members. 5. Wiring board.   5. The print according to claim 1, wherein the conductor layer is a surface layer, and the plurality of signal lines are protected by a solder resist having a relative dielectric constant lower than that of the covering member. Wiring board.   The printed wiring board according to claim 1, wherein the covering member is formed of a dielectric having the same relative dielectric constant.   6. The printed wiring board according to claim 1, wherein the covering member is formed of a dielectric material having a higher relative dielectric constant when the signal line has a shorter wiring length than when the signal line has a shorter wiring length. . The covering members covering the two signal lines adjacent to each other have adjacent sections adjacent to each other,
8. The print according to claim 1, wherein each of the adjacent sections is cut out so as to expose the side end portions facing each other in the two signal lines that are covered. Wiring board.   The printed wiring board according to any one of claims 1 to 8, wherein the entire covering member formed on two adjacent signal lines among the plurality of signal lines is the non-adjacent section. .   The printed wiring board according to any one of claims 1 to 9, wherein an interval between two adjacent signal lines is 10 [μm] or more and 30 [μm] or less. A printed wiring board according to any one of claims 1 to 10,
A semiconductor device comprising a plurality of signal terminals, wherein each of the signal terminals is bonded to a pad formed at one end of each signal line of the printed wiring board. A semiconductor device according to claim 11;
A semiconductor device different from the semiconductor device, which is stacked on the semiconductor device,
The another semiconductor device has a printed wiring board different from the printed wiring board, and a semiconductor element different from the semiconductor element,
A stacked semiconductor device, wherein a pad formed on the other end of each signal line of the printed wiring board is bonded to the other printed wiring board.

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