JP2015103226A - Data calculation method, data calculation apparatus, and defect inspection apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform logical operations of plural run data groups in a short time.SOLUTION: A data calculation method comprises: a run expansion step which expands and stores a plurality of run data sets in the address space of run expansion memory by executing a run expansion operation for each run data set, the run expansion operation adding a predetermined value to the value stored at the address of the run data expansion memory corresponding to the starting coordinates of the run data set, and at the same time subtracting a predetermined value from the value stored at the address of the run data expansion memory corresponding to the ending coordinates of the run data set; an overlapping information acquisition step which acquires overlapping information indicating the overlapping state of a plurality of run data sets by executing a scan operation for each address of the address space, the scan operation writing the total sum of stored values to the 0-th address or the m-th address of the address space at the completion of the run expansion step to the m-th address of the address space; and a logical operation step which performs logical operations for a plurality of run data groups on the basis of the overlapping information.

Description

  The present invention relates to a data operation technique for performing a logical operation on a plurality of run data groups and a defect inspection apparatus to which the data operation technique is applied.

  In the field of manufacturing technology such as semiconductor substrates and printed circuit boards, in order to detect defects contained in products and to analyze and evaluate them, images of evaluation objects are picked up with a microscope or the like, and images including defect portions are obtained from the obtained images. Extracting. Then, the defect image is accurately obtained by executing a mask process using the mask image on the extracted image. In order to perform this masking process, for example, a logical operation described in Patent Document 1 is executed on the run data of the image.

JP-A-7-203178

  In the invention described in Patent Document 1, the logical product, logical sum, and exclusive logical sum of two images are obtained without converting the run data groups of the two images to be processed into bitmap data. More specifically, two run data groups to be processed are determined to be connected in order from one end of the run, and logical product, logical sum, and exclusive logical sum are determined according to overlapping portions. . Therefore, connection determination becomes more complex as the number of run data constituting the run data group increases, and there is a problem that the time required for logical operation increases. In addition, when performing a logical operation on three or more run data groups, the complexity of connection determination further increases dramatically, and the time required for the logical operation also increases dramatically.

  The present invention has been made in view of the above problems, and provides a data operation technique capable of performing a logical operation of a plurality of run data groups in a short time and a technique for efficiently performing defect inspection using the data operation technique. The purpose is to do.

  According to a first aspect of the present invention, there is provided a data operation method in which at least one or more run data obtained by run-lengthing binary image data is used as a run data group, and a logical operation is performed on a plurality of different run data groups. The default value is added to the value stored in the address of the run development memory corresponding to the start coordinate of the run data, while the default value is added to the value stored in the address of the run development memory corresponding to the end coordinate of the run data. A data expansion operation for subtracting a value is executed for each run data, so that a plurality of run data are expanded and stored in the address space of the run expansion memory, and the m th address in the address space is run. When the expansion process is completed, a scan operation is performed to write the sum of the values stored in the 0th to mth addresses of the address space. An overlap information acquisition step for executing execution for each address in the dress space and acquiring overlap information indicating an overlap state of a plurality of run data, and logical product, logical sum and exclusive OR of a plurality of run data groups based on the overlap information And a logical operation step for obtaining at least one of them.

  According to a second aspect of the present invention, there is provided a data operation device that performs at least one run data obtained by converting the binary image data into run lengths as a run data group and performs a logical operation on a plurality of different run data groups. While the run expansion memory that stores values related to the start and end coordinates of the run data and the value stored at the address of the run expansion memory corresponding to the start end coordinates of the run data, the default value is added. A data expansion operation for subtracting a predetermined value from the value stored in the address of the run expansion memory corresponding to the end coordinate of the run data is performed for each run data, and a plurality of run data is expanded in the address space of the run expansion memory. A run expansion processing unit for executing and an address empty for the mth address of the address space in the run expansion memory in which a plurality of run data are expanded An overlap information acquisition unit that writes the sum of the values stored in each of the 0th to mth addresses, and executes a scan operation for each address in the address space to acquire overlap information indicating an overlap state of a plurality of run data; And a logical operation unit for obtaining at least one of a logical product, a logical sum, and an exclusive logical sum of a plurality of run data groups based on the overlap information.

  In the invention (data operation method and data operation device) configured as described above, the logical operation of the run data group is executed without converting the run data group into bitmap data. In addition, after obtaining overlap information indicating the overlap state of a plurality of run data by the data expansion operation for each run data and the scan operation for each address, the logical product, logical sum and exclusive of the run data groups are obtained based on the overlap information. Seeking at least one of the logical ORs. For this reason, not only when the number of run data or the number of run data groups is small, but even when the number of run data increases, logical operations can be executed by simple data processing.

  Further, a third aspect of the present invention is a defect inspection apparatus, an image acquisition unit that acquires an inspection target image, an image extraction unit that inspects the inspection target image and extracts an extracted image including a defective part, An extracted run data group having at least one or more run data obtained by run-lengthing an extracted image for each row, and a mask run having at least one or more run data obtained by running a mask image for each row. A defect inspection apparatus including a data operation unit that obtains defect image data by masking a portion other than the defect portion of the extracted image with a mask image by performing a logical operation with the data group, wherein the data operation unit , Stored in the run expansion memory for storing values related to the start and end coordinates of the run data and the address of the run expansion memory corresponding to the start end coordinates of the run data. A data expansion operation is performed for each run data to add the default value to the existing value and subtract the default value from the value stored in the address of the run expansion memory corresponding to the end coordinate of the run data. A run development processing unit that develops data in the address space of the run development memory, and the mth address in the address space in the run development memory in which a plurality of run data is developed, is changed to the 0th to mth addresses in the address space. An overlap information acquisition unit that writes a sum of stored values, executes a scan operation for each address in the address space, and acquires overlap information indicating an overlap state of a plurality of run data, and extracted run data based on the overlap information A logical operation processing unit that calculates the logical product of the group and mask run data group and removes parts other than the defective part It is characterized in that.

  In the invention configured as described above (defect inspection apparatus), a logical product of the extracted run data group and the mask run data group is calculated by the above-described data calculation technique, and parts other than the defective part are removed from the extracted image. Defect image data is obtained.

  According to this invention, regardless of the number of run data or the number of run data groups, overlap information indicating the overlap state of all run data is obtained by executing the run development process and the overlap information acquisition process, and the overlap information is obtained. It is possible to obtain at least one of a logical product, a logical sum, and an exclusive logical sum of all the run data groups based on the above. Therefore, the logical operation of the run data group can be performed in a short time.

  Further, by using the above-described data calculation technique, parts other than the defective part are removed from the extracted image, and good defect image data can be obtained in a short time. Therefore, the time required for defect inspection can be shortened.

It is a figure which shows schematic structure of the defect inspection apparatus equipped with one Embodiment of the data arithmetic unit concerning this invention. It is a block diagram which shows schematic structure of an image process part. It is a block diagram which shows schematic structure of the data processing part corresponded to one Embodiment of the data arithmetic unit concerning this invention. It is explanatory drawing which shows typically an example of the data calculation operation | movement by a data processing part. It is a figure which shows the content of the data expansion | deployment operation performed with each processor core. It is a figure which shows the content of the overlap information acquisition process. It is a figure which shows the operation | movement outline | summary of a prefix scan. It is a figure which shows the content of the logical product determination process. It is explanatory drawing which shows typically the other example of the data calculation operation | movement by a data processing part. It is a figure which shows the content of the OR determination process. It is explanatory drawing which shows typically another example of the data calculation operation | movement by a data processing part. It is a figure which shows the content of exclusive OR determination processing.

  FIG. 1 is a diagram showing a schematic configuration of a defect inspection apparatus equipped with an embodiment of a data operation apparatus according to the present invention. The defect inspection apparatus 1 inspects for defects such as pinholes and foreign matters appearing on the appearance of a semiconductor substrate (hereinafter referred to as “substrate”) S to be inspected. The defect inspection apparatus 1 includes an imaging device 2 that images an inspection target region on the substrate S and a control device 3 that performs defect inspection based on image data from the imaging device 2.

  In the inspection system equipped with the defect inspection apparatus 1, when a defect is found on the substrate S in the substrate detection apparatus M provided on the production line of the substrate S separately from the defect inspection apparatus 1, the position coordinates of the defect are The defect inspection apparatus 1 is given. The substrate detection apparatus M incorporated in the production line inspects the entire substrate S by a predetermined processing algorithm, and acquires and outputs the position coordinates if there is a region on the substrate surface that satisfies the requirement as a defect. Therefore, the imaging unit included in the substrate detection apparatus M has a relatively low resolution, and the processing algorithm is fixed.

  On the other hand, the defect inspection apparatus 1 is connected to the substrate detection apparatus M through an interface (not shown), and an image pickup apparatus 2 having higher resolution captures an area in which position coordinates are reported as a defect from the substrate detection apparatus M. At the same time, the control device 3 examines the image to determine in detail the presence or absence of the defect and the type thereof, and displays the image of the defective portion on the display unit.

  The imaging device 2 moves the stage 22 relative to the imaging unit 21 that acquires image data by imaging the inspection target region on the substrate S, the stage 22 that holds the substrate S, and the imaging unit 21. A stage driving unit 23 is provided. In addition, the imaging unit 21 includes an illumination unit 211 that emits illumination light, an optical system 212 that guides illumination light to the substrate S and receives light from the substrate S, and an image of the substrate S formed by the optical system 212. An imaging device 213 for converting the signal into an electrical signal. The stage drive unit 23 includes a ball screw, a guide rail, and a motor. The device control unit 4 provided in the control device 3 controls the stage drive unit 23 and the imaging unit 21, so that the inspection target region on the substrate S is changed. Imaged.

  The control device 3 has a device control unit 4, and when the device control unit 4 executes a control program read in advance, each unit of the control device shown in FIG. 1 is operated as follows. The control device 3 includes an image acquisition unit 5 and an image processing unit 6 in addition to the device control unit 4 described above. The image acquisition unit 5 converts the electrical signal output from the imaging unit 21 into data, and acquires image data corresponding to the captured image. The image processing unit 6 performs appropriate image processing on the image data acquired by the image acquisition unit 5 to detect a defect included in the image and create an image of a defective portion (hereinafter referred to as “defect image”). The image processing unit 6 includes a data processing unit that is an embodiment of the data arithmetic device according to the present invention, and masks images extracted from images (inspection target images) captured by the imaging device 2. By processing, it is possible to derive information on the defective portion. The configuration and operation of the image processing unit 6, especially the data processing unit will be described in detail later.

  Further, the control device 3 displays a storage unit 7 for storing various data, an input receiving unit 8 such as a keyboard and a mouse for receiving an operation input from the user, and a visual information for the user such as an operation procedure and a processing result. Part 9 and the like. Although not shown in the figure, the apparatus has a reader for reading information from a computer-readable recording medium such as an optical disk, a magnetic disk, a magneto-optical disk, etc. A communication unit that transmits and receives signals is appropriately connected through an interface (I / F).

  FIG. 2 is a block diagram illustrating a schematic configuration of the image processing unit. The image processing unit 6 includes a filtering unit 61, a difference extraction unit 62, a binarization processing unit 63 and a data processing unit 64. A captured image is sent from the image acquisition unit 5 to the filtering unit 61, and a reference image is sent from the storage unit 7. Of these two images, the picked-up image is an image of the substrate S picked up by the image pickup device 2 and corresponds to an inspection target image to be subjected to defect detection inspection. Further, the reference image is an image corresponding to an ideal substrate having no defect, and in this embodiment, as will be described below, defect detection is performed from the inspection target image by comparing the inspection target image with the reference image. . These defect images and reference images are stored in the storage unit 7 and referred to as necessary. However, image data stored in an external storage medium may be read as necessary.

  The filtering unit 61 performs a filtering process for removing minor image differences unrelated to image noise and defects for each of the inspection target image and the reference image, and sends each image to the difference extraction unit 62. The difference extraction unit 62 extracts areas having different image contents by obtaining a difference between the inspection target image and the reference image after the filtering process, and sends the difference image to the binarization processing unit 63. Then, the binarization processing unit 63 binarizes the difference image with an appropriate threshold value, generates extracted image data, and sends it to the data processing unit 64. The data processing unit 64 converts the extracted image data into run lengths to generate a run data group including a plurality of run data, and converts the mask image data provided from the storage unit 7 into run lengths to generate run data including a plurality of run data. Create a group. In this specification, run data generated by run length extraction image data is referred to as “extraction run data”, and run data generated by run length mask image data is referred to as “mask run data”. As will be described later, the run data obtained by the logical product of the extracted run data group and the mask run data group is referred to as “defective run data”.

  FIG. 3 is a block diagram showing a schematic configuration of a data processing unit corresponding to one embodiment of the data arithmetic device according to the present invention. The data processing unit 64 is configured by a GPU (Graphics Processing Unit) and has a plurality of processor cores 641. Each processor core 641 functions as a run development processing unit 642, an overlap information acquisition processing unit 643, and a logic determination processing unit 644, and performs a run development operation on the run development memory for each run data and a scan operation for each address of the run development memory. Each of the determination operations is executed as one thread. In the present embodiment, the run development operation for each run data corresponds to an example of the “development thread” of the present invention, and the determination operation for each address corresponds to an example of the “determination thread” of the present invention. The run development operation, scan operation, and determination operation will be described in detail later.

  The data processing unit 64 includes a storage unit 645 that temporarily stores the extracted run data, the mask run data, and the defect run data. The storage unit 645 has an address space for storing values developed by the run development operation, and the memory space defined by the address space functions as the “run development memory” of the present invention. The storage unit 645 is also provided with a start position memory and an end position memory that store values obtained by performing a scan operation for each address of the run development memory. These run development memory, start position memory and end position memory will also be described in detail later.

  The data processing unit 64 further includes a run generation unit 647, a parallel processing control unit 648, and a data initial setting unit 649. The run generation unit 647 performs run length processing on the extracted image data to generate an extracted run data group, and performs run length processing on the mask image data to generate a mask run data group, and stores them in the storage unit 645. Let In addition, the parallel processing control unit 648 causes the threads executed in each processor core 641 to be executed in parallel while performing exclusive control. Further, the data initial setting unit 649 appropriately clears the memory contents of the run development memory, the start position memory, and the end position memory to zero. In this embodiment, the mask run data group is generated from the mask image data. However, the mask run data group is stored in the storage unit 7 in advance, and the mask run data group from the storage unit 7 is used for masking. You may comprise so that a process may be performed.

  Next, a data calculation operation by the data processing unit 64 configured as described above will be described with reference to FIGS. FIG. 4 is an explanatory diagram schematically showing an example of a data calculation operation by the data processing unit. Here, in order to help understanding of the data calculation operation, 1 × 6 pixel binary image data indicated by reference character De in FIG. 4 is input to the data processing unit 64 as the extracted image data created by the binarization processing unit 63. An example will be described in which binary image data of 1 × 6 pixels indicated by reference numeral Dm in FIG. 4 is given to the data processing unit 64 as mask image data.

  A run length process is performed on the extracted image data input to the data processing unit 64 by the run generation unit 647 to generate extracted run data, which is stored in the storage unit 645. Many known techniques have been proposed for the run-length processing, and the general run-length processing is used as it is in this embodiment as well, and the run-length processing is performed by applying the run-length processing to the extracted image data De. Two pieces of extracted run data re [0] are obtained. In the figure, reference numeral “X0” indicates a column index (starting end coordinate) indicating the start pixel position of the run in the image data, and reference numeral “X1” indicates a column index (end index position indicating the end pixel position of the run in the image data). “Y” indicates the row index of the run in the image data.

  In addition to the extracted image data, the data processing unit 64 performs a run length process on the mask image data to generate mask run data, which is stored in the storage unit 645. Two mask run data rm [0] and rm [1] are obtained by the run length process for the mask image data Dm.

  Thus, an extracted run data group composed of the extracted run data re [0] and a mask run data group composed of the mask run data rm [0], rm [1] are generated. Then, “run development processing”, “overlap information acquisition processing”, and “logical product determination processing” are executed, and the logical product of the extracted run data group and the mask run data group is calculated.

  In the run development process, after the value stored in the address of the run development memory is cleared to zero, the data development operation is performed for each run data, and all the run data included in both run data groups are stored in the run development memory s1. This is developed and stored in the address space, and corresponds to an example of the “run development process” of the present invention. Here, it is possible to perform the data development operation serially, but in this case, a great amount of time is spent on the run development processing.

  Therefore, in this embodiment, the data expansion operation for each run data is defined as one “expanded thread”, and the expanded threads are executed in parallel by the processor cores 641. That is, as shown in FIGS. 3 and 5, the 0th processor core 641 executes the data expansion operation using the run data re [0] as the processing target run data, and the first processor core 641 concurrently executes the run data. The data expansion operation is executed with rm [0] as the processing target run and the second processor core 641 with the run data rm [1] as the processing target run. However, since each data expansion operation involves rewriting the run expansion memory s1 as described below, the parallel processing control unit 648 performs exclusive control between the processor cores 641 in this embodiment.

FIG. 5 is a diagram showing the contents of the data expansion operation executed in each processor core. The data expansion operation adds a predetermined value (“1” in the present embodiment) to the value stored in the address of the run expansion memory s1 corresponding to the start end coordinate of the run data, while corresponding to the end coordinate of the run data. The predetermined value is subtracted from the value stored in the address of the run development memory s1. For example, the 0th thread adds 1 to the value s1 [2] stored in the address (the address [2] in FIG. 4) of the run development memory s1 corresponding to the start end coordinate X0 of the run data re [0]. In other words, while waiting for the rewriting by another thread to the address [2] of the run development memory s1, the addition processing of the following equation is performed on the condition that the prohibition of rewriting is released: s1 [2] = s1 [ 2] +1
Execute. Subsequently, 1 is subtracted from the value s1 [6] stored in the address (address [6] in FIG. 4) of the run development memory s1 corresponding to the end coordinate X1 of the run data re [0]. In other words, while waiting for the rewriting by another thread to the address [6] of the run development memory s1, the subtraction processing s1 [6] = s1 [ 6] -1
Execute.

  By performing such a data expansion operation for each run data, all the run data of the extracted run data group and the run data of the mask run data group are expanded and stored in the address spaces [0] to [6] of the run expansion memory s1. Is done. Then, by performing a prefix scan (also referred to as “prefix scan”) on the data thus expanded, overlap information indicating an overlap state of all run data is acquired (overlap information acquisition processing).

  FIG. 6 is a diagram showing the contents of the overlap information acquisition process, and FIG. 7 is a diagram showing an outline of the prefix scan operation. Here, the “prefix scan” means a process of adding the sum from the 0th to the mth of the original array to the mth of the one-dimensional array. In this embodiment, the prefix scan operation for each address is performed in parallel rather than serially. That is, in addition to the run development memory s1, two other run development memories s2 and s3 are provided in the storage unit 645, and as shown in FIGS. 6 and 7, the prefix scan operation for each address is performed as one “scan thread”. And a scan thread is executed in parallel by each processor core 641.

  In the specific example shown in FIG. 4, the one-dimensional array {1, -1, 1, 1, 0, -1, -1} of the address space [0] to [6] of the run development memory s1 An array {1, 0, 1, 2, 2, 1, 0} is obtained by a fix scan operation, and a logical operation can be performed based on a value stored in each address, that is, overlap information indicating an overlap state for each pixel. It becomes. In the present embodiment, it is necessary to perform logical product of two run data groups in order to perform mask processing, and the logical determination processing unit 644 performs logical product determination processing as logical operation determination by paying attention to the value “2”. . However, the value “2” merely indicates that the run data groups overlap at the pixel corresponding to the address [m], and the address [m−1] is used to confirm that the start data is the start coordinate. It is necessary to confirm that the value s1 [m−1] stored in is smaller than “2” (1 or less). In order to confirm that the coordinates are the end coordinates, it is necessary to confirm that the value s1 [m + 1] stored in the address [m + 1] is smaller than “2” (1 or less). Note that even if the number of run data groups is 3 or more, it is basically the same. Focusing on the number N of run data groups (a natural number of 2 or more), the logical product determination process described below is performed. Can do.

  FIG. 8 is a diagram showing the contents of the logical product determination process. This logical product determination process is performed by using the start coordinates of the run data obtained by performing the logical product process on pixels corresponding to each address based on the values stored in the respective addresses of the run development memory s1 after the overlap information acquisition process is executed. It is determined whether or not it is a terminal coordinate. In the present embodiment, prior to the logical product determination process, the values stored in the addresses of the start position memory ss and the end position memory se are cleared to zero. In the logical product determination process, the determination operation is performed with one pixel and one thread as in the overlap information acquisition process. That is, the determination operation for determining whether or not the mth address in the address space corresponds to the start end coordinate or end end coordinate of the run after the logical operation is defined as one “determination thread” as shown in FIG. In 641, the determination thread is executed in parallel.

Each determination thread is roughly divided into determination of the start end coordinate and determination of the end coordinate. The determination of the start end coordinate is made based on the value (= s1 [m]) stored at the mth address in the address space and the value (= s1 [m-1]) stored at the (m−1) th address. Based on whether or not the mth address corresponds to the starting end coordinate of the run after the AND operation. More specifically, the following two conditions (AND1) and (AND2)
(AND1) value s1 [m] matches the number N of run data groups,
(AND2) ... value s1 [m-1] is (N-1) or less,
When both are satisfied, the value stored in the address [m] of the start position memory ss is set to “1”. Therefore, in the specific example shown in FIG. 4, since the number of run data N = 2 and the above conditions (AND1) and (AND2) are satisfied only when m = 3, only the value ss [3] is “1”. The other values ss [0] to ss [2], ss [4], and ss [5] are maintained at “0”.

The determination of the end coordinates is based on the value (= s1 [m]) stored at the mth address in the address space and the value (= s1 [m + 1]) stored at the (m + 1) th address. This is performed depending on whether or not the mth address corresponds to the end coordinates of the run after the logical product processing. More specifically, together with the above condition (AND1), the condition (AND3), that is,
(AND3) ... value s1 [m + 1] is (N-1) or less,
Is satisfied, the value stored in the address [m] of the end position memory se is set to “1”. Therefore, in the specific example shown in FIG. 4, since the number of run data N = 2 and the above conditions (AND1) and (AND3) are satisfied only when m = 4, only the value se [4] is “1”. The other values se [0] to se [3] and se [5] are maintained as “0”.

  Thus, the start end coordinates and end coordinates of the run after the logical product of the extracted run data group and the mask run data group are obtained. Subsequently, defect run data rd [m] is acquired based on the storage information in the start position memory ss and the end position memory se. For example, in the specific example shown in FIG. 4, the value ss [3] is “1”, the value se [4] is “1”, and the other values are “0”. m] is run data rd [0] (start coordinate X0 = 3, end coordinate X1 = 5, row index Y = 0). Then, defect image data is created and output based on the defect run data rd [m] (defect image data creation processing: logical sum image data creation processing).

  As described above, according to this embodiment, the logical product of two run data groups is obtained without converting the extracted run data group and the mask run data group into bitmap data, and the logical operation can be performed in a short time. It can be carried out. Although it is the same as the invention described in Patent Document 1 in that conversion to bitmap data is not required, it is greatly different in the following points. That is, in this embodiment, overlap information indicating the overlap state of all run data is acquired by a data expansion operation for each run data and a scan operation for each address, and the extracted run data group and the mask run data are further based on the overlap information. Find the logical product of groups. Therefore, compared to the logical operation method in the invention described in Patent Document 1, that is, the connection determination is performed in order from one end of the run, and the logical operation is performed according to the overlapping portion, high-speed arithmetic processing can be performed, and the calculation time is reduced. Can be shortened. In particular, when the number of run data increases, the advantage of this embodiment further increases.

  In the above embodiment, when executing the run development process, the run development operation for each run data is set as the development thread, and the run development operation is executed in parallel by one run data one development thread. The time required is shortened. In this embodiment, the number of development threads and the number of run data are made to coincide with each other, but the division mode of a plurality of run data is not limited to this. In other words, the division mode of the plurality of run data may be appropriately changed according to the number of the processor cores 641. The plurality of run data is divided into a plurality of sets according to the number of the processor cores 641, and each processor core is divided. Alternatively, the run expansion operation may be executed as an expansion thread for one or a plurality of run data. The same applies to the overlap information acquisition process and the logical product determination process.

  In the above embodiment, parallel processing by a plurality of processor cores 641 is performed not only in the run development process but also in the overlap information acquisition process and the logical product determination process, which greatly contributes to shortening of the processing time. That is, in the prefix scan performed in the overlap information acquisition process, the prefix scan operation for each address is set as one “scan thread”, and the scan threads are performed in parallel by the processor cores 641. In the logical product determination process, the determination operation is performed by one pixel and one determination thread. In other words, the determination operation for determining whether the mth address in the address space corresponds to the start end coordinate or the end coordinate of the run after the logical operation is defined as one “determination thread”, and the determination threads are parallelized by each processor core 641. Is going. Therefore, the time required for the overlap information acquisition process and the logical product determination process can be shortened.

  Furthermore, in the above embodiment, the parallel processing control unit 648 located above the 0th to nth processor cores 641 performs access management of the run development memory s1, and different processor cores 641 have the same address of the run development memory s1. Data rewriting is prevented. That is, when the value s1 [m] stored in the address [m] of the run expansion memory s1 is rewritten by one expansion thread, the other expansion threads are temporarily prohibited from rewriting the value s1 [m]. doing. On the other hand, the run expansion memory s1 other than the address [m] is liberated to permit data rewriting. Therefore, the run development process can be performed at high speed while avoiding the competition of the run development process.

  By the way, in the above embodiment, in order to perform mask processing, logical product determination is performed as logical determination processing based on overlap information. However, other processing, for example, logical sum determination processing is performed to integrate inspection results. Can do. In addition, exclusive logical sum determination processing can be performed as the logical determination processing, and the same operation and effect as in the logical product determination processing can be obtained. Hereinafter, the logical sum determination process and the exclusive logical sum determination process will be described with reference to the drawings.

  FIG. 9 is an explanatory diagram schematically showing another example of the data calculation operation by the data processing unit. Here, in order to help the understanding of the data operation, the first image data of 1 × 6 pixels indicated by the symbol D1 in FIG. 9 is used as the first image data created by the binarization processing unit 63. A case where 1 × 6 pixel second image data indicated by reference numeral D2 in FIG. 9 is given to the data processing unit 64 as the second image data will be described as an example. In order to avoid redundant description, the first image data D1 is the same as the extracted image data De in FIG. 4, and the second image data D2 is the same as the mask image data Dm in FIG. Yes. Therefore, the process until the overlap information is obtained is the same as that in the above embodiment (FIG. 4). These points are the same in the explanation of the exclusive OR determination process described later.

  FIG. 10 shows the contents of the logical sum determination process. In this logical sum determination process, the start coordinate of the run data obtained by performing the logical sum process on the pixel corresponding to each address based on the value stored in each address of the run development memory s1 after the overlap information acquisition process is executed. It is determined whether or not it is a terminal coordinate. In this embodiment, also in the logical sum determination process, the determination operation is performed with one pixel and one thread as in the overlap information acquisition process. That is, the determination operation for determining whether or not the mth address in the address space corresponds to the start end coordinate or end end coordinate of the run after the OR operation is defined as one “determination thread” as shown in FIG. The determination thread is executed in parallel by the core 641.

Each determination thread is roughly divided into determination of the start end coordinate and determination of the end coordinate. The determination of the start end coordinate is made based on the value (= s1 [m]) stored at the mth address in the address space and the value (= s1 [m-1]) stored at the (m−1) th address. Based on this, it is determined whether or not the mth address corresponds to the start end coordinate of the run after the logical operation. More specifically, the following two conditions (OR1) and (OR2)
(OR1) ... value s1 [m] is 1 or more,
(OR2) value s1 [m−1] is “0”,
When both are satisfied, the value ss [m] stored in the address [m] of the start position memory ss is set to “1”. Therefore, in the specific example shown in FIG. 9, since the above conditions (OR1) and (OR2) are satisfied at m = 0 and 2, the values ss [0] and ss [2] are “1”, and otherwise The values ss [1] and ss [3] to ss [5] are maintained at “0”.

The determination of the end coordinates is based on the value (= s1 [m]) stored at the mth address in the address space and the value (= s1 [m + 1]) stored at the (m + 1) th address. It is determined whether or not the mth address corresponds to the end coordinates of the run after the logical sum process. More specifically, together with the above condition (OR1), the condition (OR3), that is,
(OR3) value s1 [m + 1] is “0”,
Is satisfied, the value se [m] stored in the address [m] of the end position memory se is set to “1”. Therefore, in the specific example shown in FIG. 9, since the above conditions (OR1) and (OR3) are satisfied only when m = 0, 5, the values se [0] and se [5] are “1”. The values se [1] to se [4] other than are maintained as “0”.

  In this way, the start end coordinates and end coordinates of the run after the logical sum processing of the first run data group and the second run data group are obtained. Subsequently, run data rd [m] of the logical sum process is acquired based on the stored information in the start position memory ss and the end position memory se. For example, in the specific example shown in FIG. 9, the values ss [0] and ss [2] are “1”, the values se [0] and se [5] are “1”, and other values are “0”. Therefore, the run data rd [m] after the logical sum process has run data rd [0] (start coordinate X0 = 3, end coordinate X1 = 1, row index Y = 0) and run data rd [1]. ] (Start end coordinate X0 = 2, end coordinate X1 = 6, row index Y = 0). Then, logical image data is created based on the run data rd [m] and output (logical image data creation process).

  FIG. 11 is an explanatory diagram schematically showing another example of the data calculation operation by the data processing unit. FIG. 12 is a diagram showing the contents of exclusive OR determination processing. In this exclusive OR determination process, run data in which pixels corresponding to each address are obtained by the exclusive OR process based on values stored in each address of the run development memory s1 after the overlap information acquisition process is executed. It is determined whether it is the start end coordinate or the end coordinate. In the present embodiment, also in the exclusive OR determination process, the determination operation is performed with one pixel and one thread as in the overlap information acquisition process. That is, the determination operation for determining whether or not the mth address in the address space corresponds to the start end coordinate or end end coordinate of the run after exclusive OR processing is set as one “determination thread” as shown in FIG. Each processor core 641 executes determination threads in parallel.

Each determination thread is roughly divided into determination of the start end coordinate and determination of the end coordinate. The determination of the start end coordinate is made based on the value (= s1 [m]) stored at the mth address in the address space and the value (= s1 [m-1]) stored at the (m−1) th address. Based on this, it is determined whether or not the mth address corresponds to the start end coordinate of the run after the logical operation. More specifically, the following two conditions (XOR1) and (XOR2)
(XOR1) value s1 [m] is an odd number,
(XOR2) ... value s1 [m-1] is an even number,
When both are satisfied, the value ss [m] stored in the address [m] of the start position memory ss is set to “1”. Therefore, in the specific example shown in FIG. 11, since the above conditions (XOR1) and (XOR2) are satisfied at m = 0, 2, and 5, the values ss [0], ss [2], and ss [5] “1”, and the other values ss [1], ss [3], and ss [4] are maintained at “0”.

The determination of the end coordinates is based on the value (= s1 [m]) stored at the mth address in the address space and the value (= s1 [m + 1]) stored at the (m + 1) th address. It is determined whether or not the mth address corresponds to the end coordinates of the run after the exclusive OR process. More specifically, together with the condition (XOR1) described above, the condition (XOR3), that is,
(XOR3) ... value s1 [m + 1] is an even number,
Is satisfied, the value se [m] stored in the address [m] of the end position memory se is set to “1”. Therefore, in the specific example shown in FIG. 11, since the above conditions (XOR1) and (XOR3) are satisfied at m = 0, 2, and 5, the values se [0], se [2], and se [5] “1”, and the other values se [1], se [3], and se [4] are maintained at “0”.

  In this way, the start end coordinates and end coordinates of the run after the exclusive OR process of the first run data group and the second run data group are obtained. Subsequently, the run data rd [m] after the exclusive OR process is acquired based on the storage information of the start position memory ss and the end position memory se. For example, in the specific example shown in FIG. 11, the values ss [0], ss [2], and ss [5] are “1”, and the values se [0], se [2], and se [5] are “1”. Since the other values are “0”, the run data rd [m] after the exclusive OR process is run data rd [0] (start coordinate X0 = 0, end coordinate X1 = 1, row Index Y = 0), run data rd [1] (start end coordinate X0 = 2, end coordinate X1 = 3, row index Y = 0), run data rd [2] (start end coordinate X0 = 5, end coordinate X1) = 6, row index Y = 0). Then, exclusive OR image data is created and output based on the run data rd [m] (exclusive OR image data creation processing).

  The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, a GPU having a plurality of processor cores 641 is used to execute the run development process, overlap information acquisition process, and logical determination process (logical product determination, logical sum determination, exclusive logical OR determination). However, a plurality of CPUs may be provided in place of the GPU, and each CPU may be configured to execute one thread.

  In the above embodiment, the mask image data Dm (FIG. 4) and the second image data D2 (FIGS. 9 and 11) are run-lengthed by the data processing unit 65 to obtain a run data group. The run data group corresponding to the data Dm and D2 may be stored in the storage unit 7 in advance, and the run data group may be provided from the storage unit 7 to the data processing unit 65.

  In the above embodiment, the logical operation is performed on the two run data groups. However, the data operation method according to the present invention can be applied to three or more run data groups. Thus, when performing a logical operation on three or more run data groups, the advantage of the present invention is further increased. That is, in the invention described in Patent Document 1, when there are three or more run data groups, the complexity of connection determination increases dramatically, and an increase in processing time due to the increase in run data groups is inevitable. On the other hand, in the present invention, the number of run data to be expanded increases due to an increase in the run data group, and the time required for the run expansion process may be longer than in the case of two run data groups. However, the time required for overlap information acquisition processing and logical determination processing (logical product determination, logical sum determination, exclusive logical sum determination) is not affected by the number of run data groups. Therefore, the data calculation process can be performed in a short time despite the increase in the number of run data.

  Furthermore, in the above-described embodiment, the data calculation technique for logically calculating a plurality of run data groups is applied to the defect inspection apparatus, but the application target is not limited to this for the data calculation method and apparatus according to the present invention. However, the present invention can be applied to all devices using the above data calculation technique.

  The present invention can be suitably applied to a data operation technique for performing a logical operation on a plurality of run data groups.

DESCRIPTION OF SYMBOLS 1 ... Inspection system 5 ... Image acquisition part 6 ... Image processing part 21 ... Imaging part 62 ... Difference extraction part (image extraction part)
63 ... Binarization processing unit 64 ... Data processing unit (data arithmetic unit)
641 ... Processor core 642 ... Run development processing unit 643 ... Overlapping information acquisition processing unit 644 ... Logic determination processing unit 645 ... Storage unit 647 ... Run generation unit 648 ... Parallel processing control unit 649 ... Data initial setting unit

Claims (13)

A data operation method for performing a logical operation on a plurality of different run data groups, using at least one or more run data obtained by converting the binary image data into run lengths,
The predetermined value is added to the value stored in the address of the run development memory corresponding to the start coordinate of the run data, while the value stored in the address of the run development memory corresponding to the end coordinate of the run data is A run development step of developing and storing the plurality of run data in the address space of the run development memory by executing a data development operation for subtracting a predetermined value for each run data;
When the run expansion process is completed for the mth address in the address space, the total of the values stored in the 0th to mth addresses of the address space is written, and a scan operation is performed in the address space. An overlap information acquisition step that executes overlap information indicating the overlap state of the plurality of run data executed for each address;
And a logical operation step of obtaining at least one of a logical product, a logical sum, and an exclusive logical sum of the plurality of run data groups based on the overlap information. The data calculation method according to claim 1,
Dividing the plurality of run data into a plurality of sets and performing a data expansion operation to be performed on each set as an expansion thread,
While adding and subtracting the default value by one expansion thread of the plurality of expansion threads under exclusive control and prohibiting access by other expansion threads to the address subject to addition and subtraction by the one expansion thread A data operation method for executing the plurality of development threads in parallel. A data calculation method according to claim 2,
A data operation method in which the number of expansion threads matches the number of run data. The data calculation method according to claim 2 or 3, wherein
In the run development step, a data operation method for permitting access by an other development thread to an address other than an address subject to addition / subtraction by the one development thread. A data calculation method according to any one of claims 1 to 4, wherein
Whether or not the mth address corresponds to the start coordinate of the run after the logical operation based on the value stored at the mth address of the address space and the value stored at the (m-1) th address Whether the mth address corresponds to the end coordinates of the run after the logical operation based on the value stored at the mth address and the value stored at the (m + 1) th address The operation for determining
The data operation method, wherein the logical operation step is a step of executing the determination operation for each address in the address space. A data calculation method according to claim 5,
A data operation method that divides a plurality of addresses constituting the address space into a plurality of sets, uses a determination operation for each set as a determination thread, and executes the plurality of determination threads in parallel. A data calculation method according to claim 6,
In the logical operation step, the number of the determination threads matches the number of the addresses in the address space, and the determination thread is executed for each address. A data calculation method according to any one of claims 5 to 7, comprising:
A data calculation method in which the predetermined value is 1. The data calculation method according to claim 8, wherein
When the number of the run data groups is N,
In the logical operation step,
When the value stored in the mth address of the address space is N and the value stored in the (m−1) th address is equal to or less than (N−1), the mth address is after the logical operation. The value stored in the mth address of the address space is N, and the value stored in the (m + 1) th address is less than (N-1). An operation for determining that the m-th address corresponds to the end coordinates of the run after the logical operation is the determination operation.
A data operation method for obtaining a logical product of the plurality of run data by executing the determination operation for each address in the address space. The data calculation method according to claim 8 or 9, wherein
In the logical operation step,
When the value stored in the mth address of the address space is 1 or more and the value stored in the (m−1) th address is 0, the mth address is the start of a run after a logical operation. When the value stored in the mth address of the address space is 1 or more and the value stored in the (m + 1) th address is 0, the mth address is logically calculated. The operation to determine that it corresponds to the end coordinates of the later run is the determination operation,
A data operation method for obtaining a logical sum of the plurality of run data by executing the determination operation for each address in the address space. A data calculation method according to any one of claims 8 to 10, wherein
In the logical operation step,
When the value stored in the mth address in the address space is an odd number and the value stored in the (m−1) th address is an even number, the mth address is the starting coordinate of the run after the logical operation. When the value stored in the mth address in the address space is an odd number and the value stored in the (m + 1) th address is an even number, the mth address The operation that is determined to correspond to the end coordinates of the run is the determination operation,
A data operation method for obtaining an exclusive OR of the plurality of run data by executing the determination operation for each address in the address space. A data operation device that performs at least one or more run data obtained by converting the binary image data into a run data group and performs a logical operation on a plurality of different run data groups,
A run expansion memory for storing values related to the start and end coordinates of the run data;
The predetermined value is added to the value stored in the address of the run development memory corresponding to the start coordinate of the run data, while the value stored in the address of the run development memory corresponding to the end coordinate of the run data is A run development processing unit that executes a data development operation for subtracting a predetermined value for each run data to develop the plurality of run data into an address space of the run development memory;
A scan operation for writing a sum of values stored in the 0th to m-th addresses of the address space to the m-th address of the address space in the run expansion memory in which the plurality of run data are expanded For each address in the address space to obtain overlap information indicating an overlap state of the plurality of run data; and
And a logical operation unit that obtains at least one of a logical product, a logical sum, and an exclusive logical sum of the plurality of run data groups based on the overlap information. An image acquisition unit for acquiring an image to be inspected;
An image extraction unit that inspects the inspection target image and extracts an extracted image including a defective portion;
An extracted run data group having at least one or more run data obtained by run-lengthing the extracted image for each row, and a mask having at least one or more run data obtained by running the mask image for each row. By performing a logical operation with the run data group, a data operation unit that obtains defect image data by masking a portion other than the defective portion of the extracted image with the mask image,
The data calculation unit is
A run expansion memory for storing values related to the start and end coordinates of the run data;
The predetermined value is added to the value stored in the address of the run development memory corresponding to the start coordinate of the run data, while the value stored in the address of the run development memory corresponding to the end coordinate of the run data is A run development processing unit that executes a data development operation for subtracting a predetermined value for each run data to develop the plurality of run data into an address space of the run development memory;
A scan operation for writing a sum of values stored in the 0th to m-th addresses of the address space to the m-th address of the address space in the run expansion memory in which the plurality of run data are expanded For each address in the address space to obtain overlap information indicating an overlap state of the plurality of run data; and
A defect inspection apparatus comprising: a logical operation processing unit that calculates a logical product of the extracted run data group and the mask run data group based on the overlap information and removes parts other than the defective part.

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