JP2015172663A - display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform both writing and deletion of data simultaneously while increasing the circuit scale, in a display device of an active matrix system.SOLUTION: A first writing transistor T1 has an input terminal connected to a l-th data line, and a control terminal connected to a k-th scan line. A second writing transistor T2 has an input terminal connected to an output terminal of the first writing transistor T1, a control terminal connected to a (k-i)-th (i≥2) scan line, and an output terminal connected to a control terminal of a drive transistor T4. The deletion transistor T3 has an input terminal connected to a fixed potential for deletion, a control terminal connected to a (k-j)-th (j≥i+1) scan line, and an output terminal connected to the control terminal of the drive transistor T4.

Description

  The present invention relates to an active matrix display device.

  Organic EL displays are being developed and put into practical use as next-generation displays for liquid crystal displays. The driving methods for thin displays can be broadly divided into a passive matrix method and an active matrix method. In this specification, attention is focused on an active matrix system capable of displaying a higher image quality.

  The driving method of the active matrix type organic EL display is roughly classified into an analog driving method and a digital driving method. In the analog driving method, gradation is expressed by supplying an analog voltage to a driving transistor that drives an organic EL. On the other hand, in the digital driving method, there are only two types of voltage to be supplied, “low” and “high”, and the gradation is expressed by a time width for supplying the voltage. Since an analog voltage is used in the analog driving method, a variation in threshold voltage of the driving transistor becomes a factor causing nonuniform gradation. In the digital driving method, only the on state and the off state of the driving transistor are used, and therefore, the digital driving method is not easily affected by variations in threshold voltage. However, since the gray scale is expressed by the time width in the digital driving method, it is necessary to operate the driving circuit and the pixel circuit at a higher speed than in the analog driving method.

  When the refresh rate is 60 Hz, data can be rewritten once every 1/60 seconds in the analog drive method. However, for example, in order to display an image of 256 gradations, it is necessary to have a configuration capable of supplying 256 analog voltages to the drive transistor. On the other hand, in the digital driving method, gradation is expressed with 256 time widths. That is, in principle, it is necessary to rewrite data (that is, writing and erasing) at 256 times faster than analog driving. On the other hand, as a method for reducing the operation speed in the digital driving method, a method of superimposing and executing data writing and erasing has been proposed (see, for example, Patent Document 1 and Patent Document 2).

JP 2002-82651 A JP-A-2005-91435

  In the conventional method of executing data writing and erasing in a superimposed manner, in addition to the scanning line driver circuit, a circuit for generating a signal for selecting an operation state is required, or the output pulse width of the scanning line driver circuit is set as data. It was necessary to change between the writing operation and the erasing operation. These cause an increase in cost and a decrease in yield due to an increase in circuit scale, an increase in the number of wirings, an increase in the number of parts, and the like.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a technique for executing data writing and erasing in a superimposed manner while suppressing an increase in circuit scale in an active matrix display device. There is.

  In order to solve the above problems, a display device according to one embodiment of the present invention includes a pixel region formed by arranging n (n ≧ 4) scanning lines and m (m ≧ 1) data lines. The pixel circuit formed corresponding to the kth (1 ≦ k ≦ n) scanning line and the lth (1 ≦ l ≦ m) data line in the pixel region emits light. A first switching element having an input terminal connected to the l-th data line and a control terminal connected to the k-th scanning line; an element; a driving switching element that controls current supply to the light-emitting element; The input terminal is connected to the output terminal of the first writing switching element, the control terminal is connected to the (ki) th (i ≧ 2) scanning line, and the output terminal is connected to the driving switching element. The second write switching element connected to the control terminal and the input terminal erased An erasing switching element having a control terminal connected to the (k−j) th (j ≧ i + 1) scanning line and an output terminal connected to the control terminal of the driving switching element. Have.

  Another embodiment of the present invention is also a display device. This device is a display device including a pixel region formed by arranging n (n ≧ 4) scanning lines and m (m ≧ 1) data lines, and k in the pixel region. A pixel circuit formed corresponding to the th (1 ≦ k ≦ n) th scanning line and the lth (1 ≦ l ≦ m) data line is a light emitting element and a drive for controlling current supply to the light emitting element. Switching element, a first writing switching element having an input terminal connected to the l-th data line, a control terminal connected to the (ki) th (i ≧ 2), and an input terminal being the first A second writing switching element connected to the output terminal of the writing switching element, a control terminal connected to the kth scanning line, and an output terminal connected to the control terminal of the driving switching element; Are connected to a fixed potential for erasing and the control terminal is (k−j) th (j i + 1) is connected to the scanning lines, and an output terminal; and a erasure switching element connected to a control terminal of the driving switching element.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention among methods, circuits, devices, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, in an active matrix display device, data writing and erasing can be performed in a superimposed manner while suppressing an increase in circuit scale.

1 is a diagram illustrating a circuit configuration of an active matrix organic EL display device according to an embodiment of the present invention. 7 is a diagram illustrating a configuration of a pixel circuit according to Comparative Example 1. FIG. 3 is a timing chart illustrating an operation of the pixel circuit in FIG. 2. 6 is a diagram illustrating a configuration of a pixel circuit according to a comparative example 2. FIG. 5 is a timing chart showing the operation of the pixel circuit of FIG. It is a figure which shows the structure of the pixel circuit which concerns on an Example. 7 is a timing chart illustrating an operation of the pixel circuit in FIG. 6. It is a figure which shows the structure of the pixel circuit which concerns on a modification. It is a figure which shows the structural example of a scanning line drive circuit. FIG. 10 is a timing chart of the shift register in FIG. 9. It is a figure which shows the structure of the register | resistor which concerns on a comparative example. FIG. 3 is a diagram illustrating a configuration of a register according to an embodiment.

  FIG. 1 is a diagram showing a circuit configuration of an active matrix organic EL display device 100 according to an embodiment of the present invention. An active matrix organic EL display device (hereinafter simply referred to as a display device) 100 includes a pixel region 103, a data line driving circuit 101, and a scanning line driving circuit 102. The pixel region 103 includes a plurality of scanning lines (also referred to as gate signal lines) G (1) to G (n) (n ≧ 4) and at least one data line (also referred to as a source signal line) D (1). To D (m) (m ≧ 1) are formed in a matrix, and a plurality of pixels are arranged in a matrix.

  The plurality of scanning lines G (1) to G (n) are formed in parallel to each other, and the plurality of data lines D (1) to D (m) are connected to the plurality of scanning lines G (1) to G (n). It is formed to intersect. A plurality of pixel circuits 104 are formed corresponding to a plurality of points where the plurality of scanning lines G (1) to G (n) and the plurality of data lines D (1) to D (m) intersect. One pixel circuit 104 constitutes one pixel.

  The data line driving circuit 101 receives image data from an image data supply unit (not shown) and supplies the data to the data lines D (1) to D (m) in synchronization with the clock signal. In this embodiment, since a digital driving method is assumed, digital data expressed by gradation in time division is supplied.

  The scanning line driving circuit 102 supplies scanning signals to the plurality of scanning lines G (1) to G (n) in synchronization with the clock signal, and supplies the scanning signals to the data lines D (1) to D (m). The processed data is guided to a predetermined pixel circuit. The organic EL element in the pixel circuit emits light according to the supplied data.

  Hereinafter, a configuration example of the pixel circuit 104 (k, l) formed corresponding to the kth (1 ≦ k ≦ n) scan line and the lth (1 ≦ l ≦ m) data line will be described.

  FIG. 2 is a diagram illustrating a configuration of the pixel circuit 104 (k, l) according to the first comparative example. The pixel circuit 104 (k, l) includes an organic EL element OE, a first writing transistor T1, a second writing transistor T2, an erasing transistor T3, a driving transistor T4, and a capacitor C1. The anode terminal of the organic EL element OE is connected to the power supply line VD via the driving transistor T4, and the cathode terminal of the organic EL element OE is connected to the ground. The organic EL element OE conducts when the driving transistor T4 is turned on, and emits light according to the flowing current. When the driving transistor T4 is turned off, the organic EL element OE is cut off and is turned off. Instead of the organic EL element OE, another diode type light emitting element may be used.

  The first writing transistor T1, the second writing transistor T2, the erasing transistor T3, and the driving transistor T4 are each formed of a thin film transistor (TFT) and function as a switching element. The n-channel type is adopted for the first write transistor T1, the second write transistor T2, and the erase transistor T3, and the p-channel type is adopted for the drive transistor T4. In the following description, the source terminal of these transistors functions as an input terminal, the drain terminal functions as an output terminal, and the gate terminal functions as a control terminal.

  The driving transistor T4 is a driving switching element that controls current supply to the organic EL element OE. The source terminal of the drive transistor T4 is connected to the power supply line VD, the drain terminal is connected to the anode terminal of the organic EL element OE, and data is input to the gate terminal.

  The first write transistor T1 has a source terminal connected to the l-th data line, a gate terminal connected to the k-th scan line, and a drain terminal connected to the source terminal of the second write transistor T2. The first writing transistor T1 is turned on when the kth scanning line is active (high level in this specification), and turned off when it is inactive (low level in this specification). Data is input to the first write transistor T1 from the lth data line, and when the kth scan line is active, the input data is output to the second write transistor T2.

  The second write transistor T2 has a source terminal connected to the drain terminal of the first write transistor T1, a gate terminal connected to the block control line BC, and a drain terminal connected to the gate terminal of the drive transistor T4. The block control line BC is a signal line for supplying a block signal for distinguishing between a write operation and an erase operation. An active period (a high level period in this specification) designates a writing operation period, and a non-active period (a low level period in this specification) designates an erasing period.

  The second write transistor T2 is turned on when the block control line BC is active, and turned off when the block control line BC is inactive. Data is input from the first write transistor T1 to the second write transistor T2, and when the block control line BC is active, the input data is output to the gate terminal of the drive transistor T4.

  The capacitor C1 is a charge holding capacitor that is connected between the gate terminal and the source terminal of the driving transistor T4 and holds data supplied from the l-th data line as charges.

  The erase transistor T3 has a source terminal connected to the power supply line VD, a gate terminal connected to the (k−1) th scanning line, and a drain terminal connected to the gate terminal of the drive transistor T4. The erase transistor T3 is turned on when the (k-1) th scanning line is active, and turned off when the (k-1) th scanning line is inactive. The erase transistor T3 resets the capacitor C1 by setting both ends of the capacitor C1 to the same potential when the (k−1) th scanning line is active.

  The gate terminal of the drive transistor T4 is connected to the drain terminal of the second write transistor T2 and the drain terminal of the erase transistor T3. The gate voltage of the driving transistor T4 is controlled by the output signal of the second writing transistor T2 and the output signal of the erasing transistor T3, and the driving transistor T4 is turned on / off.

  FIG. 3 is a timing chart showing the operation of the pixel circuit 104 (k, l) in FIG. FIG. 3A shows a timing chart during a write operation, and FIG. 3B shows a timing chart during an erase operation. In the pixel circuit 104 (k, l) in FIG. 2, when both the first writing transistor T1 and the second writing transistor T2 are in the on state, the data on the data line D (l) is held in the capacitor C1, and writing is performed. It becomes operation. Therefore, writing is possible when the block control line BC is at a high level as shown in FIG. 3A, and writing is prohibited when it is at a low level as shown in FIG. 3B. In FIG. 3A, the capacitor C1 is initialized when the (k-1) th scanning line is at a high level, and the writing operation is performed when the next kth scanning line is at a high level. In FIG. 3B, a scanning signal similar to that in FIG. 3A is supplied, but writing cannot be performed because the block control line BC is at a low level, and only an erasing operation is performed.

  In a driving method in which data writing and erasing are performed in a superimposed manner to reduce the operation speed, it is necessary to separately supply a data writing signal and an erasing signal to each pixel circuit. In Comparative Example 1, both signals are separated by supplying a block signal for distinguishing between a write operation and an erase operation.

  FIG. 4 is a diagram illustrating a configuration of the pixel circuit 104 (k, l) according to the second comparative example. Hereinafter, differences from Comparative Example 1 will be described, and overlapping descriptions will be omitted as appropriate. In Comparative Example 2, the second write transistor T2 has a source terminal connected to the drain terminal of the first write transistor T1, a gate terminal connected to the (k−1) th scanning line, and a drain terminal connected to the drive transistor T4. Is connected to the gate terminal. The second writing transistor T2 is turned on when the (k−1) th scanning line is active, and turned off when it is inactive. Data is input to the second writing transistor T2 from the first writing transistor T1, and when the (k-1) th scanning line is active, the input data is output to the gate terminal of the driving transistor T4.

  The erase transistor T3 has a source terminal connected to the power supply line VD, a gate terminal connected to the (k−2) th scanning line, and a drain terminal connected to the gate terminal of the drive transistor T4. The erase transistor T3 is turned on when the (k-2) th scanning line is active, and turned off when the (k-2) th scanning line is inactive. The erasing transistor T3 resets the capacitor C1 by setting both ends of the capacitor C1 to the same potential when the (k-2) th scanning line is active. Other connection relationships are the same as those in Comparative Example 1.

  FIG. 5 is a timing chart showing the operation of the pixel circuit 104 (k, l) in FIG. FIG. 5A shows a timing chart during a write operation, and FIG. 5B shows a timing chart during an erase operation. In Comparative Example 2, the pulse width (Tw) at the time of writing and the pulse width (Td) at the time of erasing are changed. A write operation is performed when pulses in adjacent columns overlap, and an erase operation is performed when there is no overlap.

  In the pixel circuit 104 (k, l) in FIG. 4, when both the first writing transistor T1 and the second writing transistor T2 are in the on state, the data on the data line D (l) is held in the capacitor C1, and writing is performed. It becomes operation. As shown in FIG. 5A, when both the (k−1) th scanning line and the kth scanning line are at a high level, the pixel circuit 104 (k, l) performs a writing operation. The capacitor C1 is initialized by the high level of the (k-2) th scanning line before the half pulse. In FIG. 5B, since there is no overlap between pulses in adjacent columns, only the erase operation is performed.

  In the configuration of Comparative Example 1 described above, a circuit for generating a block signal for selecting an operation state is required in addition to the scanning line driving circuit 102. In the configuration of Comparative Example 2, it is necessary to change the output pulse width of the scanning line driving circuit 102 between the data writing operation and the erasing operation. These cause an increase in cost and a decrease in yield due to an increase in circuit scale, an increase in the number of wirings, an increase in the number of parts, and the like. In particular, when the scanning line driving circuit 102 is formed of a thin film transistor (TFT) integrally with the display panel, a larger problem occurs.

  In the pixel circuit according to the embodiment described below, a circuit that does not require an additional circuit and does not complicate the configuration of the scanning line driving circuit 102 can be realized.

  FIG. 6 is a diagram illustrating a configuration of the pixel circuit 104 (k, l) according to the embodiment. Hereinafter, differences from Comparative Examples 1 and 2 will be described, and overlapping description will be omitted as appropriate. The first write transistor T1 has a source terminal connected to the l-th data line, a gate terminal connected to the k-th scan line, and a drain terminal connected to the source terminal of the second write transistor T2. The first writing transistor T1 is turned on when the kth scanning line is active, and turned off when the kth scanning line is inactive. Data is input to the first write transistor T1 from the lth data line, and when the kth scan line is active, the input data is output to the second write transistor T2.

  The second write transistor T2 has a source terminal connected to the drain terminal of the first write transistor T1, a gate terminal connected to the (k-2) th scanning line, and a drain terminal connected to the gate terminal of the drive transistor T4. Connected. The second writing transistor T2 is turned on when the (k-2) th scanning line is active, and is turned off when the (k-2) th scanning line is inactive. Data is input to the second writing transistor T2 from the first writing transistor T1, and when the (k-2) th scanning line is active, the input data is output to the gate terminal of the driving transistor T4.

  The erase transistor T3 has a source terminal connected to the erase signal line EL, a gate terminal connected to the (k-3) th scanning line, and a drain terminal connected to the gate terminal of the drive transistor T4. The erase signal line EL supplies a predetermined fixed potential. For example, a power supply potential or a ground potential is supplied. When a p-channel type semiconductor element is used for the driving transistor T4, a power supply potential is supplied. When an n-channel semiconductor element is used for the driving transistor T4, a ground potential is supplied. In any case, when the erase transistor T3 is turned on, the drive transistor T4 can be turned off. When the erasing signal line EL supplies the power supply potential, the erasing signal line EL may be substituted with the power supply line VD as in the first and second comparative examples. When the erase signal line EL supplies a ground potential, the erase signal line EL may be substituted with the ground terminal of the organic EL element OE. Note that in the configuration in which the erase signal line EL is provided, a fixed potential other than the power supply potential and the ground potential can be used as the reset potential.

  The erase transistor T3 is turned on when the (k-3) th scanning line is active, and is turned off when the (k-3) th scanning line is inactive. The erasing transistor T3 resets the capacitor C1 when the (k-3) th scanning line is active.

  The gate terminal of the drive transistor T4 is connected to the drain terminal of the second write transistor T2 and the drain terminal of the erase transistor T3. The gate voltage of the driving transistor T4 is controlled by the output signal of the second writing transistor T2 and the output signal of the erasing transistor T3, and the driving transistor T4 is turned on / off.

  When both the kth scanning line and the (k-2) th scanning line are in the active state, the signal of the lth data line is supplied to the gate terminal of the driving transistor T4 and becomes the gate voltage. The gate voltage is stored in the capacitor C1 and controls on / off of the driving transistor T4.

  When the (k-3) th scanning line is in the active state, the potential of the erase signal line EL is supplied as the gate voltage to the gate terminal of the driving transistor T4. As a result, the driving transistor T4 is turned off, and the capacitor C1 is initialized.

  FIG. 7 is a timing chart showing the operation of the pixel circuit 104 (k, l) in FIG. FIG. 7A shows a timing chart during a write operation, and FIG. 7B shows a timing chart during an erase operation. The writing operation is controlled by overlapping signals of scanning lines that are not one adjacent to each other by using signals having the same pulse width during the writing operation and the erasing operation. In this way, by driving the pixel circuit with a plurality of scanning lines straddling one or more scanning lines, the pulse width Tw during the writing operation and the pulse width Td during the erasing operation can be made the same.

  In FIG. 7A, the scanning line driving circuit 102 generates two pulses with an interval corresponding to one pulse, and supplies the two pulses in order from the first scanning line to the nth scanning line. Although FIG. 7A and FIG. 7B are drawn separately, only the scanning signal of FIG. 7A is actually supplied to the plurality of scanning lines G (1) to G (n). When the erase operation is executed alone, the scanning signal shown in FIG. 7B is used.

  In the period t1 of FIGS. 7A and 7B, the second pulse of the two pulses supplied to the (k-3) th scanning line and the (k-1) th scanning line are supplied. By the first pulse of the two pulses, the pixel circuit 104 ((k−1), l) is in a writing operation. At the same time, the pixel circuit 104 (k, l) performs an erasing operation by the second pulse of the two pulses supplied to the (k-3) th scanning line. In the period t2, the pixel circuit 104 (the second pulse of the two pulses supplied to the (k−2) th scanning line and the first pulse of the two pulses supplied to the kth scanning line are used. k, l) is the write operation. At the same time, the pixel circuit 104 ((k + 1), l) performs an erasing operation by the second pulse of the two pulses supplied to the (k-2) th scanning line. That is, data can be written to the target pixel circuit while refreshing the pixel circuit one stage below to be written at the next clock.

  6 and 7, the kth scanning line is connected to the first writing transistor T1, the (k-2) th scanning line is connected to the second writing transistor T2, and the erasing transistor T3 is connected to (k-3). In the above description, the first scanning line is connected to drive one pixel circuit. This connection method is an example, and is not limited to this connection method.

  The (k−i) th (i ≧ 2) scanning line may be connected to the second writing transistor T2. In this case, the scanning line driving circuit 102 generates two pulses with an interval of (i−1) pulses, and supplies the two pulses in order from the first scanning line to the nth scanning line.

  The (k−j) th (j ≧ i + 1) scanning line may be connected to the erasing transistor T3. The refresh timing can be adjusted by the position of the scanning line connected to the erasing transistor T3.

  As described above, according to this embodiment, it is not necessary to add an additional signal generation circuit or a function of changing the output pulse width to the scanning line driving circuit 102. A single scanning line driver circuit 102 having a single-width pulse output function without a pulse width changing function can be used to supply a writing signal and an erasing signal to the pixel circuit by a digital driving method. Accordingly, the circuit scale can be minimized, the number of parts can be reduced, and the cost can be reduced and the yield can be improved. This embodiment is suitable for driving an active matrix type organic EL display device, and can also be applied to driving other active matrix type devices.

  FIG. 8 is a diagram illustrating a configuration of a pixel circuit 104 (k, l) according to a modification. The pixel circuit 104 (k, l) according to the modified example reverses the connection relationship between the first writing transistor T1 and the second writing transistor T2 in the pixel circuit 104 (k, l) according to the embodiment of FIG. Circuit. That is, the first write transistor T1 has a source terminal connected to the l-th data line, a gate terminal connected to the (ki) th (i ≧ 2) scan line, and a drain terminal connected to the second write line. Connected to the source terminal of transistor T2. The second write transistor T2 has a source terminal connected to the drain terminal of the first write transistor T1, a gate terminal connected to the kth scanning line, and a drain terminal connected to the gate terminal of the drive transistor T4. Even in this connection relationship, the same operation as in the embodiment is possible.

  FIG. 9 is a diagram illustrating a configuration example of the scanning line driving circuit. A plurality of registers 21 to 232 are connected in cascade to form a shift register. FIG. 9 illustrates an example of a 32-stage shift register. Each of the registers 21 to 232 receives a clock signal CLK, an inverted clock signal CLKB, a previous stage output signal OUT (n−1), and a next stage output signal OUT (n + 1). Although not shown, the registers 21 to 232 are also supplied with a high-side reference potential VGH (for example, a power supply potential) and a low-side reference potential (for example, a ground potential).

  FIG. 10 shows a timing chart of the shift register of FIG. FIG. 10A shows a timing chart of a general scanning signal, and FIG. 10B shows a timing chart of the scanning signal of FIG. As described above, the shift register in FIG. 9 can be applied to a scan line driver circuit (gate driver) other than the scan line driver circuit 102 in FIG.

  FIG. 11 shows a configuration of the register 22 according to the comparative example. In FIG. 11, the configuration of the second-stage register 22 is illustrated, but the other-stage registers have the same configuration. The first stage register 21 receives a start signal START instead of the output signal OUT (n−1) of the previous stage. The start signal START is a signal that is the basis of each scanning signal.

  The register 22 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, and a capacitor C2. It is assumed that TFTs made of an n-channel oxide semiconductor are used for the first transistor Q1 to the sixth transistor Q6.

  The output signal OUT (n−1) of the previous stage is input to the input terminal of the first transistor Q1, and the clock signal CLK is input to the control terminal of the first transistor Q1. The output terminal of the first transistor Q1 is connected to one end of the capacitor C2 and the control terminal of the fifth transistor Q5.

  The input terminal and the control terminal of the second transistor Q2 are connected to the high side reference potential VGH. The output terminal of the second transistor Q2 is connected to the output terminal of the fourth transistor Q4, the control terminal of the third transistor Q3, and the control terminal of the sixth transistor Q6.

  The input terminal of the third transistor Q3 is connected to the low side reference potential VGL. The control terminal of the third transistor Q3 is connected to the output terminal of the second transistor Q2. The output terminal of the third transistor Q3 is connected to one end of the capacitor C2.

  The input terminal of the fourth transistor Q4 is connected to the low side reference potential VGL. The control terminal of the fourth transistor Q4 is connected to one end of the capacitor C2. The output terminal of the fourth transistor Q4 is connected to the output terminal of the second transistor Q2.

  The inverted clock signal CLKB is input to the input terminal of the fifth transistor Q5. The control terminal of the fifth transistor Q5 is connected to one end of the capacitor C2 and the output terminal of the first transistor Q1. The output terminal of the fifth transistor Q5 is connected to the other end of the capacitor C2 and the output terminal of the register 22.

  The input terminal of the sixth transistor Q6 is connected to the low-side reference potential VGL. The control terminal of the sixth transistor Q6 is connected to the output terminal of the second transistor Q2. The output terminal of the sixth transistor Q6 is connected to the other end of the capacitor C2 and the output terminal of the register 22.

  In this circuit configuration, the first transistor Q1 is turned on when the clock signal CLK is at a high level and the output signal OUT (n-1) at the previous stage is at a high level. As a result, charges are accumulated in the capacitor C2, and the fifth transistor Q5 is turned on. Further, the fourth transistor Q4 is turned on, and the third transistor Q3 and the sixth transistor Q6 are turned off. When the clock signal CLK transits to a low level from this state, the first transistor Q1 is turned off. Even if the first transistor Q1 is turned off, the fifth transistor Q5 is kept on for a certain period of time by the charge accumulated in the capacitor C2. By setting the accumulated voltage of the capacitor C2 higher than the high-side reference potential VGH, the pulse waveform of the output signal OUT (n) can be sharpened.

  When the clock signal CLK becomes high level again and the voltage of the capacitor C2 falls below the threshold voltage of the fourth transistor Q4, the fourth transistor Q4 is turned off, and the third transistor Q3 and the sixth transistor Q6 are turned on. As a result, both ends of the capacitor C2 are connected to the low-side reference potential VGL.

  The threshold voltage of the transistor should be set slightly on the plus side from zero, but there are variations due to processes and the like. For example, when the threshold voltage of the first transistor Q1 or the second transistor Q2 is shifted to the negative side, it may cause a malfunction. Further, when the threshold voltage of the sixth transistor Q6 is shifted to the plus side, the turn-on timing of the sixth transistor Q6 is delayed, and the fall time of the output signal OUT (n) becomes long.

  FIG. 12 shows a configuration of the register 22 according to the embodiment. Hereinafter, differences from the comparative example of FIG. 11 will be described, and overlapping description will be omitted as appropriate. The first transistor Q1 and the second transistor Q2 are configured with an STT (Series-connected Two-transistor) structure. That is, the first transistor Q1 includes a 1.1th transistor Q1a and a 1.2th transistor Q1b connected in series. The third transistor Q3 is composed of a 3.1 transistor Q3a and a 3.2 transistor Q3b connected in series. The 1.1th transistor Q1a, the 1.2th transistor Q1b, the 3.1st transistor Q3a, and the 3.2th transistor Q3b are all n-channel type transistors.

  The register 22 according to the embodiment further includes a seventh transistor Q7 and an eighth transistor Q8. The input terminal of the seventh transistor Q7 is connected to the high side reference potential VGH. A self-stage output signal OUT (n) is fed back to the control terminal of the seventh transistor Q7. The output terminal of the seventh transistor Q7 is connected to a connection point between the 1.1st transistor Q1a and the 1.2th transistor Q1b, and a connection point between the 3.1st transistor Q3a and the 3.2th transistor Q3b. . The seventh transistor Q7 is turned on while the output signal OUT (n) of its own stage is at a high level, and fixes the potential at these connection points to the high side reference potential VGH.

  The input terminal of the eighth transistor Q8 is connected to the low-side reference potential VGL. The output signal OUT (n + 1) at the next stage is fed back to the control terminal of the eighth transistor Q8. The output terminal of the eighth transistor Q8 is connected to the other end of the capacitor C2 and the output terminal of the register 22.

  In the register 22 according to the embodiment, the first transistor Q1 and the third transistor Q3 have an SST structure, so that the negative shift tolerance of the threshold voltages of the first transistor Q1 and the third transistor Q3 can be improved. Even if the threshold voltage of the first transistor Q1 or the third transistor Q3 is shifted to minus, the output signal OUT (n) can be raised without malfunction.

  Further, the fall time can be increased by feeding back the output signal OUT (n + 1) of the next stage to the eighth transistor Q8. Even if the threshold voltage of the sixth transistor Q6 is shifted more positively, the output signal OUT (n) can be lowered without delay.

  Further, the number of transistors added to the register 22 according to the comparative example is small, and the yield does not decrease. Further, since the output signal OUT (n) is generated from the inverted clock signal CLKB, the quality of the output voltage level can be improved as compared with the case where the output signal OUT (n−1) is generated.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  For example, the digital driving method is assumed in the display device according to the above-described embodiment, but the present invention can also be applied to an analog driving method.

  T1 first write transistor, C1 capacitor, Q1 first transistor, Q1a first transistor, Q1b 1.2 transistor, T2 second write transistor, Q2 second transistor, C2 capacitor, T3 erase transistor, OE organic EL element, Q3 third transistor, Q3a 3.1 transistor, Q3b 3.2 transistor, T4 drive transistor, Q4 fourth transistor, Q5 fifth transistor, Q6 sixth transistor, Q7 seventh transistor, Q8 eighth transistor , 21 to 232 registers, 100 display device, 101 data line driving circuit, 102 scanning line driving circuit, 103 pixel region, 104 pixel circuit.

Claims (8)

A display device including a pixel region formed by arranging n (n ≧ 4) scanning lines and m (m ≧ 1) data lines,
A pixel circuit formed corresponding to the kth (1 ≦ k ≦ n) scan line and the lth (1 ≦ l ≦ m) data line in the pixel region is:
A light emitting element;
A driving switching element for controlling current supply to the light emitting element;
A first write switching element having an input terminal connected to the l-th data line and a control terminal connected to the k-th scan line;
The input terminal is connected to the output terminal of the first writing switching element, the control terminal is connected to the (ki) th (i ≧ 2) scanning line, and the output terminal is the control terminal of the driving switching element. A second write switching element connected to
An erasing circuit having an input terminal connected to a fixed potential for erasing, a control terminal connected to a (k−j) th (j ≧ i + 1) scanning line, and an output terminal connected to a control terminal of the driving switching element A switching element;
A display device comprising: When both the kth scanning line and the (ki) th scanning line are in the active state, the signal of the lth data line is supplied to the control terminal of the driving switching element,
2. The display device according to claim 1, wherein when the (k−j) th scanning line is in an active state, the fixed potential is applied to a control terminal of the driving switching element. A scanning line driving circuit for supplying a scanning signal to the n scanning lines;
2. The scanning line driving circuit according to claim 1, wherein the scanning line driving circuit generates two pulses with an interval of (i-1) pulses, and supplies the two pulses in order from the first scanning line to the nth scanning line. 2. The display device according to 2. The k-th scan line and the l-th pulse are obtained by the second pulse of the two pulses supplied to the (ki) th scan line and the first pulse of the two pulses supplied to the k-th scan line. The pixel circuit formed corresponding to the data line is in the write operation,
The pixel circuit formed corresponding to the (k + j−i) -th scanning line and the l-th data line is erased by the second pulse of the two pulses supplied to the (ki) -th scanning line. The display device according to claim 3, wherein: i = 2, j = 3,
The display device according to claim 3, wherein the scanning line driving circuit generates two pulses with a gap of one pulse. The driving switching element is an n-type semiconductor transistor,
The display device according to claim 1, wherein the fixed potential is a ground potential. The driving switching element is a p-type semiconductor transistor,
The display device according to claim 1, wherein the fixed potential is a power supply potential. A display device including a pixel region formed by arranging n (n ≧ 4) scanning lines and m (m ≧ 1) data lines,
A pixel circuit formed corresponding to the kth (1 ≦ k ≦ n) scan line and the lth (1 ≦ l ≦ m) data line in the pixel region is:
A light emitting element;
A driving switching element for controlling current supply to the light emitting element;
A first write switching element having an input terminal connected to the l-th data line and a control terminal connected to the (ki) th (i ≧ 2);
A second writing input terminal connected to the output terminal of the first writing switching element, a control terminal connected to the kth scanning line, and an output terminal connected to the control terminal of the driving switching element A switching element;
An erasing circuit having an input terminal connected to a fixed potential for erasing, a control terminal connected to a (k−j) th (j ≧ i + 1) scanning line, and an output terminal connected to a control terminal of the driving switching element A switching element;
A display device comprising:

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