JP2015167245A - Light-emitting diode, light-emitting diode lamp and luminaire - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting diode, light-emitting diode lamp and luminaire which have both rapid response and high output, and emit infrared light.SOLUTION: A light-emitting diode comprises an active layer 11 of quantum well structure where a well layer comprising a compound semiconductor having a composition formula (InGa)As (0≤X1≤1) and a barrier layer comprising a compound semiconductor having a composition formula (AlGa)As (0≤X2≤1) are laminated alternately, a light-emitting part 7 having a first clad layer 9 and a second clad layer 13 sandwiching the active layer 11 therebetween, a current diffusion layer 8 formed on the light-emitting part 7, and a functional substrate 3 joined to the current diffusion layer 8. The first and the second clad layers 9, 13 comprise a compound semiconductor having a composition formula (AlGa)InP (0≤X3≤1, 0<Y1≤1), and the number of pairs of the well layer and the barrier layer is 5 or less.

Description

  The present invention relates to a light-emitting diode, a light-emitting diode lamp, and a lighting device, and more particularly, to a light-emitting diode that emits infrared light, a light-emitting diode lamp, and a lighting device having high-speed response and high output.

Light emitting diodes that emit red light or infrared light have widespread applications such as communication, various sensors, night lighting, and light sources for plant factories.
Correspondingly, the demand for light emitting diodes that emit infrared light has changed from one that emphasizes high output characteristics or one that emphasizes high-speed response to one that emphasizes both. ing. In particular, in a light emitting diode for communication, high-speed response and high output are indispensable for performing large-capacity optical space transmission.

  As a light emitting diode that emits red light and infrared light, a light emitting diode in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate by a liquid phase epitaxial method is known (for example, Patent Documents 1 to 4).

  Patent Document 4 discloses a so-called substrate removal type light emitting diode in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate using a liquid phase epitaxial method, and then the GaAs substrate used as the growth substrate is removed. ing. In the light emitting diode disclosed in Patent Document 4, the output is 4 mW or less when the response speed (rise time) is about 40 to 55 nsec. In addition, when the response speed is about 20 nsec, the output is slightly higher than 5 mW, and it is considered that the light-emitting diode manufactured by using the liquid phase epitaxial method has the highest response speed and high output.

  Moreover, what uses an InGaAs active layer is known as an infrared light emitting diode which can have a high emission peak wavelength of 900 nm or more (Patent Documents 5 to 7).

JP-A-6-21507 JP 2001-274454 A Japanese Patent Laid-Open No. 7-38148 JP 2006-190792 A JP 2002-26377 A JP 2002-111048 A JP 2002-344013 A

However, the output of the conventional technology described above is not sufficient as a light emitting diode for communication.
Unlike a semiconductor laser, a light-emitting diode uses spontaneous emission light, so that high-speed response and high output are in a trade-off relationship. Therefore, for example, even if the layer thickness of the light emitting layer is simply reduced to increase the carrier confinement effect to increase the light emission recombination probability of electrons and holes, the light output is reduced even if high-speed response is achieved. There's a problem.

Further, as an infrared light emitting diode that can have a high emission peak wavelength of 900 nm or more, a light emitting diode using an active layer including a well layer made of InGaAs has been put into practical use.
Also in the light emitting diode provided with such an InGaAs well layer, development of a higher light emitting efficiency is desired from the viewpoint of further performance improvement, energy saving, cost and the like.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a light-emitting diode, a light-emitting diode lamp, and an illumination device that emit infrared light having both high-speed response and high output.

  As a result of intensive research in order to solve the above problems, the present inventor alternately laminated ternary mixed crystal well layers made of InGaAs and ternary mixed crystal barrier layers made of AlGaAs in 5 pairs or less alternately. An active layer is used as the quantum well structure, a clad layer sandwiching the active layer is made of quaternary mixed crystal AlGaInP, and a compound semiconductor layer including the active layer and the clad layer is epitaxially grown on the growth substrate. And a compound semiconductor layer was affixed (bonded) to the transparent substrate again, thereby completing a light emitting diode that emits infrared light at high output while maintaining high-speed response.

  In addition, the present inventor used a quantum well structure in which ternary mixed crystal well layers made of InGaAs and quaternary mixed crystal barrier layers made of AlGaInP were alternately stacked in 5 pairs or less as an active layer. The cladding layer sandwiching the active layer is made of quaternary mixed crystal AlGaInP, and after the compound semiconductor layer including the active layer and the cladding layer is epitaxially grown on the growth substrate, the growth substrate is removed, and the compound semiconductor layer is formed as a transparent substrate. Thus, a light-emitting diode that emits infrared light at high output while maintaining high-speed response was completed.

  At this time, the present inventor first adopts a quantum well structure having a high carrier confinement effect and suitable for a high-speed response as an active layer, and also in order to secure a high injected carrier density, the well layer and the barrier layer. The number of pairs was 5 or less. With this configuration, a response speed equal to or higher than the above-mentioned fastest response speed of a light-emitting diode manufactured using a liquid phase epitaxial method was realized.

  In addition, a cladding layer sandwiching a quantum well structure of a ternary mixed crystal or a quantum well structure composed of a ternary mixed crystal well layer and a quaternary mixed crystal barrier layer has a large band gap and has a large wavelength with respect to the emission wavelength. Since it is transparent and does not contain As which is easy to make defects, quaternary mixed crystal AlGaInP having good crystallinity was adopted.

  Conventional infrared light emitting diodes using an InGaAs-based active layer do not have a type in which a compound semiconductor layer including the active layer is attached (bonded) to a transparent substrate, and a GaAs substrate on which a compound semiconductor layer is grown is used. I used it as it was. However, the GaAs substrate is highly doped to enhance conductivity, and absorption of light by carriers is inevitable. Therefore, after the growth of the compound semiconductor layer, the growth substrate GaAs substrate is removed, and light absorption by carriers can be avoided, and a type of bonding (bonding) to a transparent substrate that can be expected to have high output and high efficiency is adopted.

  As described above, the present inventor employs a structure in which a quantum well structure of 5 pairs or less is used as an active layer to ensure high-speed response, and in this structure, a ternary mixed crystal or a ternary-4 element Adopting an epoch-making combination of using a quaternary mixed crystal for the cladding layer sandwiching the quantum well structure, the growth substrate used for the growth of the compound semiconductor layer is removed, and the compound semiconductor layer is changed to a substrate having no light absorption. By adopting a configuration with affixed, we succeeded in achieving higher output.

The present invention provides the following means.
(1) A well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X2 Ga _1-X2 ) As (0 ≦ X2 ≦ 1) A light emitting portion having an active layer having a quantum well structure in which barrier layers made of a compound semiconductor are alternately stacked, a first cladding layer and a second cladding layer sandwiching the active layer, and a light emitting portion formed on the light emitting portion And a functional substrate bonded to the current diffusion layer, wherein the first and second cladding layers have a composition formula (Al _X3 Ga _1-X3 ) _Y1 In _1-Y1 P (0 ≦ A light-emitting diode comprising a compound semiconductor of X3 ≦ 1, 0 <Y1 ≦ 1), wherein the number of pairs of the well layer and the barrier layer is 5 or less.
(2) A well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X4 Ga _1-X4 ) _Y2 In _1-Y2 P (0 ≦ Light emission having an active layer having a quantum well structure in which barrier layers made of compound semiconductors of X4 ≦ 1, 0 <Y2 ≦ 1) are alternately stacked, and a first cladding layer and a second cladding layer sandwiching the active layer Part, a current diffusion layer formed on the light emitting part, and a functional substrate bonded to the current diffusion layer, wherein the first and second cladding layers have a composition formula (Al _X5 Ga _{1- X5} ) _{Y3In1 -Y3P} (0≤X5≤1, 0 <Y3≤1), wherein the number of pairs of the well layer and the barrier layer is 5 or less.
(3) The light-emitting diode according to any one of (1) and (2) above, wherein a bonding area between the active layer and the cladding layer is 20000 to 90000 μm ² .
Note that the “joining area between the active layer and the clad layer” means that when the active layer and the clad layer are joined via a layer such as a guide layer, these layers and the active layer or the clad layer Including the junction area between.
(4) Any one of (1) to (3) above, wherein an In composition X1 of the well layer is 0 ≦ X1 ≦ 0.3, and a thickness of the well layer is 3 to 10 nm. A light emitting diode according to 1.
(5) The light-emitting diode according to any one of (1) to (3), wherein an In composition X1 of the well layer is 0.1 ≦ X1 ≦ 0.3.
(6) The light-emitting diode according to any one of (1) to (5), wherein the functional substrate is transparent to an emission wavelength.
(7) The light-emitting diode according to any one of (1) to (6), wherein the functional substrate is made of GaP, sapphire, or SiC.

(8) A well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X2 Ga _1-X2 ) As (0 ≦ X2 ≦ 1) A light emitting portion having an active layer having a quantum well structure in which barrier layers made of a compound semiconductor are alternately stacked, a first cladding layer and a second cladding layer sandwiching the active layer, and a light emitting portion formed on the light emitting portion A current diffusion layer and a functional substrate disposed opposite to the light emitting portion and including a reflection layer having a reflectance of 90% or more with respect to an emission wavelength, and a functional substrate bonded to the current diffusion layer, The first and second cladding layers are made of a compound semiconductor having a composition formula ( _{AlX3Ga1 -X3} ) _{Y1In1 -Y1P} (0≤X3≤1, 0 <Y1≤1), and the well layer and the barrier layer Light emitting die characterized in that the number of pairs is 5 or less Over de.
(9) A well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X4 Ga _1-X4 ) _Y2 In _1-Y2 P (0 ≦ Light emission having an active layer having a quantum well structure in which barrier layers made of compound semiconductors of X4 ≦ 1, 0 <Y2 ≦ 1) are alternately stacked, and a first cladding layer and a second cladding layer sandwiching the active layer And a current diffusion layer formed on the light emitting portion, and a reflective layer disposed opposite to the light emitting portion and having a reflectance of 90% or more with respect to the light emission wavelength, and bonded to the current diffusion layer And the first and second cladding layers have a composition formula (Al _X5 Ga _1-X5 ) _Y3 In _1-Y3 P (0 ≦ X5 ≦ 1, 0 <Y3 ≦ 1). Composed of a compound semiconductor, the number of pairs of the well layer and the barrier layer is 5 or less Light emitting diodes, characterized in that.
(10) The light-emitting diode according to any one of (8) and (9) above, wherein a junction area between the active layer and the clad layer is 20000 to 90000 μm ² .
(11) Any one of (8) to (10) above, wherein the In composition X1 of the well layer is 0 ≦ X1 ≦ 0.3, and the thickness of the well layer is 3 to 10 nm. To light emitting diode.
(12) The light-emitting diode according to any one of (8) to (10), wherein an In composition X1 of the well layer is 0.1 ≦ X1 ≦ 0.3.
(13) The light-emitting diode according to any one of (8) to (12), wherein the functional substrate includes a layer made of silicon or germanium.
(14) The light-emitting diode according to any one of (8) to (12), wherein the functional substrate includes a metal substrate.
(15) The light-emitting diode according to (14), wherein the metal substrate includes a plurality of metal layers.
(16) The light-emitting diode according to any one of (1) to (15), wherein the number of pairs of the well layer and the barrier layer is 3 or less.
(17) The light-emitting diode according to any one of (1) to (16), wherein the current diffusion layer is made of GaP.
(18) The light-emitting diode according to any one of (1) to (17), wherein a thickness of the current diffusion layer is in a range of 0.5 to 20 μm.
(19) The side surface of the functional substrate has a vertical surface that is substantially perpendicular to the main light extraction surface on the side close to the light emitting unit, and the main light extraction surface on the side far from the light emitting unit. The light-emitting diode according to any one of (1) to (18), wherein the light-emitting diode has an inclined surface inclined inward.
(20) The light-emitting diode according to (19), wherein the inclined surface includes a rough surface.
(21) The light-emitting diode according to any one of (19) and (20) above, wherein the first electrode and the second electrode are provided on the main light extraction surface side of the light-emitting diode.
(22) The light-emitting diode according to (21), wherein the first electrode and the second electrode are ohmic electrodes.

(23) A light-emitting diode lamp comprising the light-emitting diode according to any one of (1) to (22).
(24) A lighting device including a plurality of the light emitting diodes according to any one of (1) to (22) and / or the light emitting diode lamp according to (23).

  In the present invention, the term “functional substrate” means that after growing a compound semiconductor layer on a growth substrate, the growth substrate is removed and bonded to the compound semiconductor layer via a current diffusion layer to support the compound semiconductor layer. When a predetermined layer is formed on the current diffusion layer and then a predetermined substrate is bonded onto the predetermined layer, the substrate including the predetermined layer is referred to as a “functional substrate”.

According to the light emitting diode of the present invention, an active layer having a quantum well structure in which a well layer made of a ternary mixed crystal of InGaAs and a barrier layer made of a ternary mixed crystal of AlGaAs are alternately stacked is adopted, and the confinement effect of injected carriers is adopted. By using a structure with a large quantum well structure, sufficient injected carriers are confined in the well layer, so that the carrier density in the well layer increases, and as a result, the probability of luminescence recombination increases and the response Increases speed.
Also, the carriers injected into the quantum well structure spread to the whole well layer in the quantum well structure due to the tunneling effect due to its wave nature, but the number of pairs of well layers and barrier layers in the quantum well structure is 5 Since the following configuration is adopted, a decrease in the confinement effect of injected carriers due to the spread is avoided as much as possible, and high-speed response is ensured.
Furthermore, since the structure emits light from the active layer having the quantum well structure, the monochromaticity is high.

  Furthermore, according to the light emitting diode of the present invention, an active layer having a ternary / quaternary quantum well structure in which a well layer composed of a ternary mixed crystal of InGaAs and a barrier layer composed of a quaternary mixed crystal of AlGaInP are alternately stacked is employed. In addition, a structure using a quantum well structure with a large confinement effect of injected carriers can be obtained.

In addition, the first clad layer and the second clad layer sandwiching the active layer employ a configuration made of AlGaInP that is transparent to the emission wavelength and has high crystallinity because it does not contain As that easily creates defects. As a result, the probability of non-radiative recombination of electrons and holes via defects is reduced, and the light emission output is improved.
Further, since the first clad layer and the second clad layer sandwiching the active layer are composed of quaternary mixed crystal AlGaInP, the barrier layer and the clad layer are made of ternary mixed crystal as compared with the light emitting diode. Al concentration is low and moisture resistance is improved.

  In addition, since the growth substrate of the compound semiconductor layer is removed and the functional substrate is bonded to the current diffusion layer, light absorption by the growth substrate is avoided and the light emission output is improved. That is, since the band gap of the GaAs substrate normally used as the growth substrate for the compound semiconductor layer is narrower than the band gap of the active layer, the light from the active layer is absorbed by the GaAs substrate, and the light extraction efficiency decreases. By removing the GaAs substrate, the light emission output is improved.

According to the light emitting diode of the present invention, by adopting a configuration in which the junction area between the active layer and the clad layer is 20000-90000 μm ² , the current density is increased by making the junction area 90000 μm ² or less. While ensuring the output, the light emission recombination probability is increased and the response speed is improved. On the other hand, by setting the junction area to 20000 μm ² or more, by suppressing the saturation of the light emission output with respect to the energization current, there is no significant decrease in the light emission output and a high output is secured.

  According to the light emitting diode of the present invention, by adopting a configuration in which the In composition X1 of the well layer is 0 ≦ X1 ≦ 0.3 and the thickness of the well layer is 3 to 10 nm, Compared with this, the response speed is high and a high output is realized.

  According to the light emitting diode of the present invention, by adopting a configuration in which the functional substrate is transparent with respect to the emission wavelength, a higher output is realized as compared with the light emitting diode using an absorbing substrate.

  According to the light emitting diode of the present invention, by adopting a configuration in which the functional substrate is made of GaP, sapphire or SiC, silicon, or germanium, the thermal expansion coefficient is close to that of the light emitting portion, so that the stress can be reduced. Moreover, since it is a material which does not corrode easily, moisture resistance improves.

  According to the light emitting diode of the present invention, by adopting a configuration in which both the functional substrate and the current diffusion layer are made of GaP, the bonding strength between them can be increased.

It is a top view of the light emitting diode lamp using the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram along the A-A 'line | wire shown in FIG. 1 of the light emitting diode lamp using the light emitting diode which is one Embodiment of this invention. It is a top view of the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram along the B-B 'line | wire shown in FIG. 3 of the light emitting diode which is one Embodiment of this invention. It is a figure for demonstrating the active layer which comprises the light emitting diode which is one Embodiment of this invention. It is a graph which shows the correlation with the number of pairs of the well layer of the light emitting diode which is the 1st Embodiment of this invention, and a barrier layer, and light emission output and response speed (the junction area of an active layer and a clad layer is 123000 micrometers ² ) If). 4 is a graph showing the correlation between the number of well layers and barrier layers of the light emitting diode according to the first embodiment of the present invention, the light emission output, and the response speed (the junction area between the active layer and the cladding layer is 53000 μm ² ). If). It is a cross-sectional schematic diagram of the epiwafer used for the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram of the bonded wafer used for the light emitting diode which is one Embodiment of this invention. It is a graph which shows the correlation with the number of pairs of the well layer of the light emitting diode and barrier layer, and light emission output at the time of using AlGaInP for the barrier layer of the light emitting diode which is one Embodiment of this invention. It is a graph which shows the correlation with In composition (Y1) of the barrier layer of a light emitting diode at the time of using AlGaInP for a barrier layer, and the light emission output of the light emitting diode which is one Embodiment of this invention. It is a graph which shows the dependence of the number of pairs of a well layer and a barrier layer with respect to the correlation of the forward current of a light emitting diode and light emission output at the time of using AlGaInP for a barrier layer of the light emitting diode which is one Embodiment of this invention. . It is a top view of the light emitting diode which is other embodiment of this invention, (a) Top view, (b) It is a cross-sectional schematic diagram along the C-C 'line | wire shown in (a). It is a cross-sectional schematic diagram of the light emitting diode which is other embodiment of this invention. It is a graph which shows the relationship between the number of pairs when a junction area is 123000 micrometers ² and 53000 micrometers ² , and a response speed at the time of using AlGaAs for the barrier layer of the light emitting diode which is one Embodiment of this invention. It is a graph which shows the relationship between the number of pairs in the case where AlGaAs is used for the barrier layer of the light emitting diode which is one Embodiment of this invention, when the junction area is 123000 micrometers ² and 53000 micrometers ² , and a light emission output.

  Hereinafter, a light emitting diode according to an embodiment to which the present invention is applied and a light emitting diode lamp using the same will be described in detail with reference to the drawings. In the drawings used in the following description, the same members are denoted by the same reference numerals or the reference numerals are omitted. Also, the drawings used in the following description are schematic, and length, width, thickness ratio, and the like may be different from actual ones.

<Light emitting diode lamp>
1 and 2 are views for explaining a light-emitting diode lamp using a light-emitting diode according to an embodiment to which the present invention is applied. FIG. 1 is a plan view, and FIG. It is sectional drawing along the A 'line.

As shown in FIGS. 1 and 2, in the light-emitting diode lamp 41 using the light-emitting diode 1 of the present embodiment, one or more light-emitting diodes 1 are mounted on the surface of a mount substrate 42.
More specifically, an n electrode terminal 43 and a p electrode terminal 44 are provided on the surface of the mount substrate 42. In addition, the n-type ohmic electrode 4 that is the first electrode of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding). On the other hand, the p-type ohmic electrode 5, which is the second electrode of the light emitting diode 1, and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46. The surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general sealing resin 47 such as silicon resin or epoxy resin.

<Light Emitting Diode (First Embodiment)>
3 and 4 are diagrams for explaining the light emitting diode according to the first embodiment to which the present invention is applied. FIG. 3 is a plan view, and FIG. 4 is taken along the line BB ′ shown in FIG. FIG. FIG. 5 is a cross-sectional view of a laminated structure of a well layer and a barrier layer.
The light emitting diode according to the first embodiment includes a well layer 17 made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X2 Ga _1-X2 ). An active layer 11 having a quantum well structure in which barrier layers 18 made of a compound semiconductor of As (0 ≦ X2 ≦ 1) are alternately stacked, a first cladding layer 9 and a second cladding layer 13 sandwiching the active layer 11, And a functional substrate 3 bonded to the current diffusion layer 8, and the first and second cladding layers 9 and 13 are composed of the composition. It is made of a compound semiconductor of the formula (Al _X3 Ga _1-X3 ) _Y1 In _1-Y1 P (0 ≦ X3 ≦ 1, 0 <Y1 ≦ 1), and the number of pairs of the well layer 17 and the barrier layer 18 is 5 or less. It is characterized by.
In addition, the main light extraction surface in this embodiment is a surface of the compound semiconductor layer 2 opposite to the surface to which the functional substrate 3 is attached.

  As shown in FIG. 4, the compound semiconductor layer (also referred to as an epitaxial growth layer) 2 has a structure in which a pn junction type light emitting portion 7 and a current diffusion layer 8 are sequentially stacked. A known functional layer can be added to the structure of the compound semiconductor layer 2 as appropriate. For example, a contact layer for reducing the contact resistance of an ohmic electrode, a current diffusion layer for planarly diffusing the element driving current over the entire light emitting portion, and conversely, limiting a region through which the element driving current flows. Therefore, a known layer structure such as a current blocking layer or a current confinement layer can be provided. The compound semiconductor layer 2 is preferably formed by epitaxial growth on a GaAs substrate.

  As shown in FIG. 4, the light emitting unit 7 includes at least a p-type lower cladding layer (first cladding layer) 9, a lower guide layer 10, an active layer 11, an upper guide layer 12, n on a current diffusion layer 8. A mold upper clad layer (second clad layer) 13 is sequentially laminated. That is, the light emitting unit 7 includes a lower clad layer 9 disposed to face the lower side and the upper side of the active layer 11 in order to “confine” the carrier (carrier) and light emission that cause radiative recombination in the active layer 11. A so-called double hetero (English abbreviation: DH) structure including the lower guide layer 10, the upper guide layer 12, and the upper cladding layer 13 is preferable in order to obtain high-intensity light emission.

  As shown in FIG. 5, the active layer 11 forms a quantum well structure in order to control the emission wavelength of the light emitting diode (LED). That is, the active layer 11 has a multilayer structure (laminated structure) of a well layer 17 and a barrier layer (also referred to as a barrier layer) 18 having a barrier layer (also referred to as a barrier layer) 18 at both ends. Therefore, for example, a five-pair pair quantum well structure includes five well layers 17 and six barrier layers 18.

The layer thickness of the active layer 11 is preferably in the range of 0.02 to 2 μm. Further, the conductivity type of the active layer 11 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ . When the crystallinity is improved to reduce defects, light absorption is suppressed and light emission output can be improved.

The well layer 17 is made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1).
The In composition X1 is preferably 0 ≦ X1 ≦ 0.3. By making In composition X1 into this range, it can have a desired light emission wavelength in the range of 830-1000 nm.

  Table 1 below shows the correlation between the In composition (X1) and the emission peak wavelength, in which the thickness of the well layer 17 is fixed to 5 nm. As shown in Table 1 below, it can be seen that the emission peak wavelength is longer as the In composition (X1) of the well layer 17 is lower. Further, from the tendency of the change, the In composition (X1) corresponding to the emission peak wavelength not described in Table 1 below can be estimated.

The thickness of the well layer 17 is preferably in the range of 3 to 30 nm, more preferably in the range of 3 to 10 nm.
Table 2 below shows the correlation between the layer thickness of the well layer 17 and the emission peak wavelength when the In composition (X1) of the well layer 17 is 0.20. Table 3 below shows the relationship between the layer thickness of the well layer 17 and the emission peak wavelength when the In composition (X1) of the well layer 17 is 0.05.

  As shown in Tables 2 and 3, when the thickness of the well layer 17 is reduced, the emission peak wavelength is shortened due to the quantum effect, whereas when the layer thickness is thick, the emission peak wavelength is determined by the composition. Further, from the tendency of the change, the layer thickness corresponding to the emission peak wavelength not described in Tables 2 and 3 can be estimated.

Based on the relationship between the emission peak wavelength, the In composition (X1) of the well layer 17 and the layer thickness as described above, the well layer 17 has a desired emission wavelength within a range of 830 nm to 1000 nm. The In composition (X1) and the layer thickness can be determined.
For example, it is possible to manufacture a light emitting diode in which the In composition X1 of the well layer is 0 ≦ X1 ≦ 0.3, the thickness of the well layer is in the range of 3 to 10 nm, and the emission wavelength is set to 830 to 1000 nm.

Barrier layer 18 is made of a compound semiconductor composition formula _{(Al X2 Ga 1-X2)} As (0 ≦ X2 ≦ 1). X preferably has a composition with a larger band gap than the well layer 17 in order to prevent absorption in the barrier layer 18 and increase luminous efficiency. The barrier layer 18 preferably has a low Al concentration from the viewpoint of crystallinity. Therefore, the Al composition X2 of the barrier layer 18 is more preferably in the range of 0.1 to 0.3.
The optimum X2 composition is determined by the relationship with the composition of the well layer. When the crystallinity is improved to reduce defects, light absorption is suppressed, and as a result, light emission output can be improved.

  The layer thickness of the barrier layer 18 is preferably equal to or greater than the layer thickness of the well layer 17. By sufficiently increasing the thickness of the barrier layer 18 in the layer thickness range in which the tunnel effect occurs, the confinement effect of carriers is increased by combining the coupling of the well layer by the tunnel effect and the limitation of the spread, and the electron And the hole emission recombination probability increases, and the emission output can be improved.

  In the light emitting diode of the present invention, in the multilayer structure of the well layer 17 and the barrier layer 18, the number of pairs in which the well layers 17 and the barrier layers 18 are alternately stacked is 5 pairs or less. I do not care. That is, the active layer 11 preferably includes 1 to 5 well layers 17. With such a configuration, the effect of confining carriers is increased, the probability of luminescence recombination of electrons and holes is increased, and a high response speed (rise time) of 25 nsec or less can be ensured. As shown in the examples described later, the response speed increased as the number of pairs of the well layer 17 and the barrier layer 18 was decreased from 5 to 1. Under the conditions shown in the example, the maximum speed of 15 nsec was realized when the number of pairs was one. In the case of an active layer having a multiple quantum well structure, the smaller the number of quantum well layers, the narrower the region where electrons and holes are confined, so that the probability of light emission recombination increases, and as a result, the response speed increases.

6 and 7 respectively show a case where the junction area between the active layer 11 and the lower clad layer 9 or the upper clad layer 13 is 123000 μm ² (350 μm × 350 μm: FIG. 6), and narrower than that, 53000 μm ² (230 μm × 230 μm: FIG. 7) is a graph showing the correlation between the number of pairs of well layers and barrier layers of the light emitting diode, and the light emission output and response speed.
Based on the graphs shown in FIGS. 6 and 7, a single well layer 17 is sufficient as a suitable range of the luminous efficiency of the active layer 11. On the other hand, since there is a lattice irregularity between the well layer 17 and the barrier layer 18, if the number of pairs is too large, the light emission efficiency is reduced due to the generation of crystal defects.
For this reason, in the present invention, the number of pairs of the well layer 17 and the barrier layer 18 is 5 pairs or less.

  For example, in the data shown in the graph of FIG. 6, when the number of pairs of the well layer 17 and the barrier layer 18 is one pair, the light emission output is 6.8 mW and the response speed Tr is 15 nsec. When the emission output is 7 mW and the response speed Tr is 18 nsec and 5 pairs, the emission output is 6.9 mW and the response speed Tr is 23 nsec. On the other hand, when the number of pairs of the well layer and the barrier layer is 10, the light emission output is 6.5 mW and the response speed Tr is 32 nsec. Is inferior. In addition, when the number of pairs of the well layer and the barrier layer is 20, the light emission output is reduced to 5.0 mW and the response speed Tr is 43 nsec, indicating that both the light emission efficiency and the high speed are inferior.

  In the data shown in the graph of FIG. 7, when the number of pairs of the well layer 17 and the barrier layer 18 is one pair, the light emission output is 7.0 mW and the response speed Tr is 12 nsec. When the light emission output is 7.1 mW and the response speed Tr is 15 nsec and 5 pairs, the light emission output is 7.0 mW and the response speed Tr is 18 nsec. Both have high light emission efficiency and high speed response. On the other hand, when the number of pairs of the well layer and the barrier layer is 10 pairs, the light emission output is 6.2 mW and the response speed Tr is 23 nsec. Is inferior. In addition, when the number of pairs of the well layer and the barrier layer is 20, the light emission output is reduced to 5.2 mW and the response speed Tr is 36 nsec, indicating that both the light emission efficiency and the high speed are inferior.

6 and 7, when the number of pairs of the well layer 17 and the barrier layer 18 is 3 out of 1 to 5 pairs, the response speed Tr is 18 nsec and 15 nsec, respectively. 3 pairs are most preferable when the light output is the most important, since the maximum output is 7.0 mV and 7.1 mV, respectively.
From the viewpoint of speeding up, one pair is most desirable. However, since the confinement of electrons and holes is limited within a very narrow range, output saturation is likely to occur with an increase in injection current. On the other hand, since a strain exists in the well layer of the present invention, in a region of three pairs or more, as the number of pairs increases, crystal defects due to the strain expand and output decreases. From this, the response speed is inferior to the structure of 2 pairs or less, but 3 pairs are more desirable in view of the balance with the output.

If the number of well layers 17 and barrier layers 18 is reduced, the junction capacitance (capacitance) of the PN junction increases. This is because the well layer 17 and the barrier layer 18 are undoped or have a low carrier concentration, so that the well layer 17 and the barrier layer 18 function as a depletion layer in the PN junction, and the capacitance becomes larger as the depletion layer is thinner.
In general, in order to increase the response speed, it is desirable that the capacitance is small. However, in the structure of the present invention, by reducing the number of the well layers 17 and the barrier layers 18, the response speed is increased even though the capacitance is increased. A faster effect was found. This is presumed to be because the effect of increasing the recombination rate of injected carriers by reducing the number of well layers 17 and barrier layers 18 is greater.

The junction area between the active layer 11 and the lower cladding layer 9 or the upper cladding layer 13 is preferably 20000 to 90000 μm ² .

By setting the junction area between the active layer 11 and the lower cladding layer 9 or the upper cladding layer 13 to 90000 μm ² or less, the current density is increased, the light emission recombination probability is increased, and the response speed is improved. As shown in Examples described later, when the present inventors diligently experimented, for example, when the bonding area between the active layer 11 and the lower cladding layer 9 or the upper cladding layer 13 is 123000 μm ² (350 μm × 350 μm), In the case of a narrower 53000 μm ² (230 μm × 230 μm), in the latter case, the response speed is improved by 20% or more when the number of pairs of the well layer 17 and the barrier layer 18 is 5 pairs, It was revealed that the response speed was improved by 20% even when the number was one pair.

On the other hand, by setting the bonding area between the active layer 11 and the lower clad layer 9 or the upper clad layer 13 to 20000 μm ² or more, the light output is not greatly reduced, and high output is secured. As shown in Examples described later, the inventors have conducted intensive experiments. For example, when the junction area between the active layer 11 and the lower cladding layer 9 or the upper cladding layer 13 is 53000 μm ² , the well layer 17 and the barrier layer It became clear that when the number of pairs of layers 18 is 5, the light emission output is 7.0 mW (response speed 18 nsec), and even when one pair is used, the light emission output is 7.0 mW (response speed 12 nsec). .

  In the present embodiment, as illustrated in FIG. 4, the lower guide layer 10 and the upper guide layer 12 are provided on the lower surface and the upper surface of the active layer 11, respectively. Specifically, the lower guide layer 10 is provided on the lower surface of the active layer 11, and the upper guide layer 12 is provided on the upper surface of the active layer 11.

The lower guide layer 10 and the upper guide layer 12 have a composition of (Al _X6 Ga _{1 -X6} ) As (0 <X6 ≦ 1). The Al composition X6 is preferably a composition having a band gap equal to or larger than that of the barrier layer 15, and more preferably in the range of 0.2 to 0.5.
The optimum X6 composition from the viewpoint of crystallinity is determined by the relationship with the composition of the well layer 17. When the crystallinity is improved to reduce defects, light absorption is suppressed, and as a result, light emission output can be improved.

  In Table 4 below, when the layer thickness of the well layer 17 is set to 5 nm, the Al composition (X2, X6) of the barrier layer 18, the lower guide layer 10, and the upper guide layer 12 that maximizes the light emission output at each light emission peak wavelength. ). Here, the barrier layer 18, the lower guide layer 10, and the upper guide layer 12 are preferably configured to have a band gap larger than that of the well layer 17, but in order to increase the crystallinity and improve the light emission output, The optimum composition is determined in relation to the composition of the well layer 17. Thus, if the crystallinity of the barrier layer 18, the lower guide layer 10, and the upper guide layer 12 is improved to reduce defects, light absorption is suppressed, and as a result, light emission output can be improved.

The lower guide layer 10 and the upper guide layer 12 are provided to reduce the propagation of defects between the lower cladding layer 9 and the upper cladding layer 13 and the active layer 11, respectively.
That is, the V group constituent element of the lower guide layer 10, the upper guide layer 12, and the active layer 11 is arsenic (As), whereas in the present invention, the V group constituent element of the lower cladding layer 9 and the upper cladding layer 13 is phosphorus. Since it is (P), defects are likely to occur at the interface. Propagation of such defects to the active layer 11 causes a reduction in the performance of the light emitting diode. For this reason, the thickness of the lower guide layer 10 and the upper guide layer 12 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.

The conductivity type of the lower guide layer 10 and the upper guide layer 12 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ .

  The lower cladding layer 9 and the upper cladding layer 13 are provided on the lower surface of the lower guide layer 10 and the upper surface of the upper guide layer 12, respectively, as shown in FIG.

The lower cladding layer 9 and the upper cladding layer 13 are made of a compound semiconductor of (Al _X3 Ga _1-X3 ) _Y1 In _1-Y1 P (0 ≦ X3 ≦ 1, 0 <Y1 ≦ 1), and have a band higher than that of the barrier layer 18. A material having a large gap is preferable, and a material having a larger band gap than the lower guide layer 10 and the upper guide layer 12 is more preferable. As the _{material, (Al X3 Ga 1-X3} ) Y1 In 1-Y1 P (0 ≦ X3 ≦ 1,0 <Y1 ≦ 1) Al composition X3 has the composition is 0.2 to 0.4 It is preferable. Y1 is preferably 0.4 to 0.6. X3 functions as a cladding layer and is selected in a range that is transparent to the emission wavelength, and Y1 is selected as a range in which good quality crystal growth is possible from the viewpoint of lattice matching with the substrate because the cladding layer is a thick film. .

  The lower clad layer 9 and the upper clad layer 13 are configured to have different polarities. The carrier concentration and thickness of the lower clad layer 9 and the upper clad layer 13 can be in a known suitable range, and it is preferable to optimize the conditions so that the luminous efficiency of the active layer 11 is increased. Further, the warpage of the compound semiconductor layer 2 can be reduced by controlling the composition of the lower cladding layer 9 and the upper cladding layer 13.

Specifically, as the lower cladding layer 9, for example, a p-type doped with _{Mg (Al X3a Ga 1-X3a} ) Y1a In 1-Y1a P (0.3 ≦ X3a ≦ 0.7,0.4 ≦ Y1a It is desirable to use a semiconductor material composed of ≦ 0.6). The carrier concentration is preferably in the range of 2 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.1 to 1 μm.

On the other hand, as the upper cladding layer 13, for example, Si-doped n-type ( _{AlX3bGa1 -X3b} ) _{Y1bIn1 -Y1bP} ( _{0.3≤X3b≤0.7, 0.4≤Y1b≤0} ) .6) is preferably used. The carrier concentration is preferably in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.1 to 1 μm.
The polarities of the lower cladding layer 9 and the upper cladding layer 13 can be selected in consideration of the element structure of the compound semiconductor layer 2.

  Further, above the constituent layers of the light emitting unit 7, a contact layer for lowering the contact resistance of the ohmic electrode, a current diffusion layer for planarly diffusing the element driving current throughout the light emitting unit, and conversely A known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.

As shown in FIG. 4, the current spreading layer 8 is provided below the light emitting unit 7. The current spreading layer 8 relieves strain caused by the active layer 12 when the compound semiconductor layer 2 is epitaxially grown on the GaAs substrate.
The current spreading layer 8 may be made of a material that is transparent to the emission wavelength from the light emitting unit 7 (active layer 11), for example, GaP. When GaP is applied to the current diffusion layer 8, bonding can be facilitated and high bonding strength can be obtained by using the functional substrate 3 as a GaP substrate.

  The thickness of the current spreading layer 8 is preferably in the range of 0.5 to 20 μm. If the thickness is 0.5 μm or less, current diffusion is insufficient, and if it is 20 μm or more, the cost for crystal growth to the thickness increases.

  The functional substrate 3 is bonded to the surface of the compound semiconductor layer 2 opposite to the main light extraction surface. That is, the functional substrate 3 is bonded to the current diffusion layer 8 side constituting the compound semiconductor layer 2 as shown in FIG. The functional substrate 3 has sufficient strength to mechanically support the light emitting unit 7, and can transmit light emitted from the light emitting unit 7, and is optical with respect to the emission wavelength from the active layer 11. Made of transparent material. Further, a chemically stable material excellent in moisture resistance is desirable. For example, it is desirable to employ a material that does not contain Al or the like which is easily corroded.

  The functional substrate 3 is a substrate having a thermal expansion coefficient close to that of the light emitting portion and excellent in moisture resistance, and is preferably made of GaP, SiC having good thermal conductivity, or sapphire having high mechanical strength. The functional substrate 3 preferably has a thickness of, for example, about 50 μm or more in order to support the light emitting unit 7 with sufficient mechanical strength. In order to facilitate the mechanical processing of the functional substrate 3 after bonding to the compound semiconductor layer 2, it is preferable that the thickness does not exceed about 300 μm. That is, the functional substrate 3 is most preferably composed of an n-type GaP substrate in terms of transparency and cost having a thickness of about 50 μm or more and about 300 μm or less.

  Further, as shown in FIG. 4, the side surface of the functional substrate 3 is a vertical surface 3 a that is substantially perpendicular to the main light extraction surface on the side close to the compound semiconductor layer 2, and is far from the compound semiconductor layer 2. On the side, the inclined surface 3b is inclined inward with respect to the main light extraction surface. Thereby, the light emitted from the active layer 11 to the functional substrate 3 side can be efficiently extracted to the outside. Further, part of the light emitted from the active layer 11 to the functional substrate 3 side is reflected by the vertical surface 3a and can be extracted by the inclined surface 3b. On the other hand, the light reflected by the inclined surface 3b can be extracted by the vertical surface 3a. Thus, the light extraction efficiency can be increased by the synergistic effect of the vertical surface 3a and the inclined surface 3b.

Moreover, in this embodiment, as shown in FIG. 4, it is preferable to make angle (alpha) which the inclined surface 3b and the surface parallel to a light emission surface make into the range of 55 degree | times-80 degree | times. By setting it as such a range, the light reflected by the bottom part of the functional board | substrate 3 can be efficiently taken out outside.
Moreover, it is preferable to make the width | variety (thickness direction) of the vertical surface 3a into the range of 30 micrometers-100 micrometers. By setting the width of the vertical surface 3a within the above range, the light reflected at the bottom of the functional substrate 3 can be efficiently returned to the light emitting surface at the vertical surface 3a, and further emitted from the main light extraction surface. It becomes possible. Thereby, the luminous efficiency of the light emitting diode 1 can be improved.

In addition, the inclined surface 3b of the functional substrate 3 is preferably roughened. Since the inclined surface 3b is roughened, an effect of increasing the light extraction efficiency at the inclined surface 3b can be obtained.
That is, by roughening the inclined surface 3b, total reflection on the inclined surface 3b can be suppressed and light extraction efficiency can be increased.

The bonding interface between the compound semiconductor layer 2 and the functional substrate 3 may be a high resistance layer.
That is, a high resistance layer (not shown) may be formed between the compound semiconductor layer 2 and the functional substrate 3. This high resistance layer exhibits a higher resistance value than that of the functional substrate 3, and when the high resistance layer is formed, the compound semiconductor layer 2 has a reverse direction from the current diffusion layer 8 side to the functional substrate 3 side. It has a function of reducing current. Moreover, although the junction structure which exhibits a withstand voltage with respect to the voltage of the reverse direction applied carelessly from the functional board | substrate 3 side is comprised, the breakdown voltage is a pn junction. It is preferable that the voltage is lower than the reverse voltage of the light emitting unit 7 of the mold.

The n-type ohmic electrode (first electrode) 4 and the p-type ohmic electrode (second electrode) 5 are low-resistance ohmic contact electrodes provided on the main light extraction surface of the light-emitting diode 1.
Here, the n-type ohmic electrode 4 is provided above the upper cladding layer 11, and for example, an alloy made of AuGe, Ni alloy / Au can be used. On the other hand, as shown in FIG. 4, the p-type ohmic electrode 5 can use AuBe / Au or an alloy made of AuZn / Au on the exposed surface of the current diffusion layer 8.

  Here, in the light emitting diode 1 of the present embodiment, it is preferable that the p-type ohmic electrode 5 is formed on the current diffusion layer 8 as the second electrode. By setting it as such a structure, the effect of reducing an operating voltage is acquired. In addition, by forming the p-type ohmic electrode 5 on the current diffusion layer 8 made of p-type GaP, a good ohmic contact can be obtained, so that the operating voltage can be lowered.

  In the present embodiment, it is preferable that the polarity of the first electrode is n-type and the polarity of the second electrode is p-type. By adopting such a configuration, it is possible to achieve high brightness of the light emitting diode 1. On the other hand, if the first electrode is p-type, current diffusion is deteriorated, resulting in a decrease in luminance. On the other hand, by making the first electrode n-type, current diffusion is improved, and high luminance of the light emitting diode 1 can be achieved.

  In the light emitting diode 1 of this embodiment, as shown in FIG. 3, it is preferable to arrange so that the n-type ohmic electrode 4 and the p-type ohmic electrode 5 are diagonally positioned. The p-type ohmic electrode 5 is most preferably surrounded by the compound semiconductor layer 2. By setting it as such a structure, the effect of reducing an operating voltage is acquired. Further, by enclosing the four sides of the p-type ohmic electrode 5 with the n-type ohmic electrode 4, the current easily flows in the four directions, and as a result, the operating voltage decreases.

Moreover, in the light emitting diode 1 of this embodiment, as shown in FIG. 3, it is preferable that the n-type ohmic electrode 4 has a mesh such as a honeycomb or a lattice shape. With such a configuration, an effect of improving reliability can be obtained. Further, by using the lattice shape, a current can be uniformly injected into the active layer 11, and as a result, an effect of improving reliability can be obtained.
In the light emitting diode 1 of this embodiment, the n-type ohmic electrode 4 is preferably composed of a pad-shaped electrode (pad electrode) and a linear electrode (linear electrode) having a width of 10 μm or less. With such a configuration, high luminance can be achieved. Furthermore, by reducing the width of the linear electrode, the opening area of the light extraction surface can be increased, and high luminance can be achieved.

In the present embodiment, although not shown, a configuration in which a third electrode is formed on the back side of the functional substrate 3 can be employed. By adopting a configuration including such a third electrode, the transparent substrate (functional substrate) can be configured to reflect light toward the substrate, thereby further increasing the output. As the reflective metal material, materials such as Au, Ag, and Al can be used.
Further, by using eutectic metal such as AuSn or solder material on the electrode surface side, it is not necessary to use paste in the die bonding process, and the process can be simplified. Further, by connecting the functional substrate 3 and the n-electrode terminal 43 with a third electrode made of metal, the heat conduction is improved and the heat dissipation characteristics of the light emitting diode are improved.

<Method for manufacturing light-emitting diode>
Next, the manufacturing method of the light emitting diode 1 of this embodiment is demonstrated. FIG. 8 is a cross-sectional view of an epi-wafer used for the light-emitting diode 1 of the present embodiment. FIG. 9 is a cross-sectional view of a bonded wafer used for the light emitting diode 1 of the present embodiment.

(Formation process of compound semiconductor layer)
First, as shown in FIG. 8, the compound semiconductor layer 2 is produced. The compound semiconductor layer 2 includes a buffer layer 15 made of GaAs on a GaAs substrate 14, an etching stop layer (not shown) provided for selective etching, and a contact layer 16 made of n-type AlGaAs doped with Si. The n-type upper clad layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, the p-type lower clad layer 9, and the current diffusion layer 8 made of Mg-doped p-type GaP are sequentially laminated. .

  As the GaAs substrate 14, a commercially available single crystal substrate manufactured by a known manufacturing method can be used. The surface of the GaAs substrate 14 on which the epitaxial growth is performed is desirably smooth. The surface orientation of the surface of the GaAs substrate 14 is easy to epitaxially grow, and a substrate that is turned off within ± 20 ° from the (100) plane and (100) that are mass-produced is desirable from the standpoint of quality stability. Furthermore, the range of the plane orientation of the GaAs substrate 14 is more preferably 15 ° off ± 5 ° from the (100) direction to the (0-1-1) direction. In this specification, in the notation of Miller index, “-” means a bar attached to the index immediately after that.

The dislocation density of the GaAs substrate 14 is desirably low in order to improve the crystallinity of the compound semiconductor layer 2. Specifically, for example, 10,000 pieces cm ⁻² or less, preferably 1,000 pieces cm ⁻² or less are suitable.

The GaAs substrate 14 may be n-type or p-type. The carrier concentration of the GaAs substrate 14 can be appropriately selected from desired electrical conductivity and element structure. For example, when the GaAs substrate 14 is a silicon-doped n-type, the carrier concentration is preferably in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . On the other hand, when the GaAs substrate 14 is a p-type doped with zinc, the carrier concentration is preferably in the range of 2 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ .

  The thickness of the GaAs substrate 14 has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate 14 is thinner than an appropriate range, the compound semiconductor layer 2 may be broken during the manufacturing process. On the other hand, when the thickness of the GaAs substrate 14 is thicker than an appropriate range, the material cost increases. For this reason, when the substrate size of the GaAs substrate 14 is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 μm is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 μm is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 μm is desirable.

  Thus, by increasing the thickness of the substrate in accordance with the substrate size of the GaAs substrate 14, the warpage of the compound semiconductor layer 2 due to the active layer 7 can be reduced. As a result, the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 11 can be reduced. The shape of the GaAs substrate 14 is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.

  The buffer layer 15 is provided to reduce the propagation of defects between the GaAs substrate 14 and the constituent layers of the light emitting unit 7. For this reason, the buffer layer 15 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected. The buffer layer 15 is preferably made of the same material as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 15 as with the GaAs substrate 14. The buffer layer 15 can also be a multilayer film made of a material different from that of the GaAs substrate 14 in order to reduce the propagation of defects. The thickness of the buffer layer 15 is preferably 0.1 μm or more, and more preferably 0.2 μm or more.

The contact layer 16 is provided to reduce the contact resistance with the electrode. The material of the contact layer 16 is preferably a material having a band gap larger than that of the active layer 11, and Al _X7 Ga _1-X7 As, (Al _X7 Ga _1-X7 ) _Y4 In _1-Y4 P (0 ≦ X7 ≦ 1). , 0 <Y4 ≦ 1) can be preferably used. The lower limit value of the carrier concentration of the contact layer 16 is preferably 5 × 10 ¹⁷ cm ⁻³ or more, and more preferably 1 × 10 ¹⁸ cm ⁻³ or more in order to reduce the contact resistance with the electrode. The upper limit value of the carrier concentration is desirably 2 × 10 ¹⁹ cm ⁻³ or less at which the crystallinity is likely to decrease. The thickness of the contact layer 16 is preferably 0.5 μm or more, and optimally 1 μm or more. The upper limit value of the thickness of the contact layer 16 is not particularly limited, but is desirably 5 μm or less in order to bring the cost for epitaxial growth to an appropriate range.

  In the present embodiment, a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied. Among these, it is most desirable to apply the MOCVD method which is excellent in mass productivity. Specifically, the GaAs substrate 14 used for the epitaxial growth of the compound semiconductor layer 2 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film. Each layer constituting the compound semiconductor layer 2 can be laminated by setting a GaAs substrate 14 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing the layer. As the MOCVD apparatus, a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.

When each layer of the compound semiconductor layer 2 is epitaxially grown, examples of the group III constituent material include trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ((CH ₃ ) ₃ In) can be used. Further, as a Mg doping raw material, for example, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) or the like can be used. Further, as a Si doping material, for example, disilane (Si ₂ H ₆ ) or the like can be used.
In addition, phosphine (PH ₃ ), arsine (AsH ₃ ), or the like can be used as a raw material for the group V constituent element.
As the growth temperature of each layer, 720 to 770 ° C. can be applied when p-type GaP is used as the current diffusion layer 8, and 600 to 700 ° C. can be applied to the other layers.
Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.

  The compound semiconductor layer 2 manufactured in this way has a good surface state with few crystal defects despite having the light emitting portion 7. The compound semiconductor layer 2 may be subjected to surface processing such as polishing corresponding to the element structure.

(Functional substrate bonding process)
Next, the compound semiconductor layer 2 and the functional substrate 3 are bonded.
In joining the compound semiconductor layer 2 and the functional substrate 3, first, the surface of the current diffusion layer 8 constituting the compound semiconductor layer 2 is polished and mirror-finished. Next, the functional substrate 3 to be attached to the mirror-polished surface of the current spreading layer 8 is prepared. The surface of the functional substrate 3 is polished to a mirror surface before being bonded to the current diffusion layer 8. Next, the compound semiconductor layer 2 and the functional substrate 3 are carried into a general semiconductor material pasting apparatus, and electrons are collided with both surfaces which are mirror-polished in a vacuum to make the neutral (neutral) Ar beam. Irradiate. Then, it can join at room temperature by superimposing both surfaces in the sticking apparatus which maintained the vacuum, and applying a load (refer FIG. 7). With respect to bonding, materials having the same bonding surface are more desirable from the viewpoint of stability of bonding conditions.
Bonding (pasting) is optimally performed at room temperature bonding under such a vacuum, but bonding can also be performed using a eutectic metal or an adhesive.

(First and second electrode forming steps)
Next, an n-type ohmic electrode 4 that is a first electrode and a p-type ohmic electrode 5 that is a second electrode are formed.
When forming the n-type ohmic electrode 4 and the p-type ohmic electrode 5, first, the GaAs substrate 14 and the buffer layer 15 are selectively removed from the compound semiconductor layer 2 bonded to the functional substrate 3 with an ammonia-based etchant. Next, the n-type ohmic electrode 4 is formed on the exposed surface of the contact layer 16. Specifically, for example, AuGe, Ni alloy / Pt / Au are laminated by a vacuum deposition method so as to have an arbitrary thickness, and then patterned by using a general photolithography means to form the n-type ohmic electrode 4. Form the shape.

  Next, the current diffusion layer 8 is exposed by selectively removing a predetermined range of the contact layer 16, the upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, and the p-type lower cladding layer 9. Then, the p-type ohmic electrode 5 is formed on the exposed surface of the current diffusion layer 8. Specifically, for example, AuBe / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then patterned using a general photolithography means to form the shape of the p-type ohmic electrode 5. . Then, the low resistance n-type ohmic electrode 4 and the p-type ohmic electrode 5 can be formed by heat-processing, for example on the conditions of 400-500 degreeC and 5 to 20 minutes, and alloying.

(Third electrode forming step)
In the case of adopting the configuration provided with the third electrode (not shown) as described above, the third electrode is formed on the back surface of the functional substrate 3. Depending on the structure of the element, the third electrode can be added with a combination of functions such as an ohmic electrode, a Schottky electrode, a reflection function, and a eutectic die bond structure. On the transparent substrate (functional substrate), a material such as Au, Ag, or Al is formed so that light can be reflected. At this time, for example, a transparent film such as silicon oxide or ITO can be inserted between the functional substrate and the material. In addition, as a forming method at this time, a known technique such as a sputtering method or a vapor deposition method can be used.

Further, by using eutectic metal such as AuSn or lead-free solder material on the electrode surface side, it is not necessary to use a paste in the die bonding process, and the process can be simplified.
In addition, as a forming method at this time, a known technique such as sputtering, vapor deposition, plating, printing, or the like can be used. Thus, by connecting the functional substrate 3 and the n-electrode terminal 43 with the third electrode made of metal, the thermal conductivity is improved and the heat dissipation characteristics of the light emitting diode are improved. When combining two or more of the functions described above, it is also preferable to insert a barrier metal and an oxide between the layers so that the metal does not diffuse. As such a barrier metal and oxide, an optimum one may be selected according to the element structure and the substrate material.

(Functional substrate processing process)
Next, the shape of the functional substrate 3 is processed.
In processing the functional substrate 3, first, V-shaped grooving is performed on the surface where the third electrode (not shown) is not formed. At this time, the inner surface of the V-shaped groove on the third electrode side becomes the inclined surface 3b having an angle α formed with the surface parallel to the light emitting surface. Next, dicing is performed from the compound semiconductor layer 2 side at predetermined intervals to form chips. In addition, the vertical surface 3a of the functional substrate 3 is formed by dicing at the time of chip formation.

  The formation method of the inclined surface 3b is not particularly limited, and conventional methods such as wet etching, dry etching, scribing, and laser processing can be used in combination, but the shape controllability and productivity can be improved. Most preferably, a high dicing method is applied. By applying the dicing method, the manufacturing yield can be improved.

  The method for forming the vertical surface 3a is not particularly limited, but it is preferably formed by laser processing, a scribe / break method or a dicing method. By employing the laser processing and the scribe / break method, the manufacturing cost can be reduced. That is, it is not necessary to provide a margin for chip separation, and a large number of light emitting diodes can be manufactured, so that the manufacturing cost can be reduced. On the other hand, the dicing method is excellent in cutting stability.

  Finally, the crushed layer and dirt are removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide as necessary. In this way, the light emitting diode 1 is manufactured.

<Method for manufacturing light-emitting diode lamp>
Next, a manufacturing method of the light emitting diode lamp 41 using the light emitting diode 1, that is, a mounting method of the light emitting diode 1 will be described.
As shown in FIGS. 1 and 2, a predetermined number of light emitting diodes 1 are mounted on the surface of the mount substrate 42. In mounting the light emitting diode 1, first, the mounting substrate 42 and the light emitting diode 1 are aligned, and the light emitting diode 1 is disposed at a predetermined position on the surface of the mounting substrate 42. Next, die bonding is performed with Ag paste, and the light emitting diode 1 is fixed to the surface of the mount substrate 42. Next, the n-type ohmic electrode 4 of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding). Next, the p-type ohmic electrode 5 of the light emitting diode 1 and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46. Finally, the surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general sealing resin 47 such as silicon resin or epoxy resin. In this way, the light emitting diode lamp 41 using the light emitting diode 1 is manufactured.

  The emission spectrum of the light-emitting diode lamp 41 has a peak emission wavelength in the range of 830 to 1000 nm because the composition of the active layer 11 is adjusted. Further, since the current diffusion layer 8 suppresses variations in the well layer 17 and the barrier layer 18 in the active layer 11, the half width of the emission spectrum is in the range of 10 to 40 nm.

As described above, according to the light-emitting diode 1 of the present embodiment, the well layer 17 composed of the ternary mixed crystal of the composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1), and the composition formula The light emitting unit 7 includes an active layer 11 having a quantum well structure in which barrier layers 18 made of a ternary mixed crystal of (Al _X2 Ga _1-X2 ) As (0 ≦ X2 ≦ 1) are alternately stacked. As described above, by using a quantum well structure that has a large confinement effect of injected carriers, sufficient injected carriers are confined in the well layer 17, thereby increasing the carrier density in the well layer 17. The probability of luminescence recombination increases, and the response speed is improved.
In addition, since the number of pairs of the well layer 17 and the barrier layer 18 in the quantum well structure is set to 5 or less, carriers injected into the quantum well structure are spread over the entire well layer due to the tunnel effect due to the wave nature thereof. A reduction in the confinement effect can be avoided as much as possible, and high-speed response can be ensured.

  In addition, since the upper cladding layer 13 and the lower cladding layer 9 sandwiching the active layer 11 are made of AlGaInP having high crystallinity because it is transparent to the emission wavelength and does not contain As which easily creates a defect. The probability of non-light-emitting recombination of electrons and holes is reduced, and the light emission output is improved. Furthermore, by adopting quaternary mixed crystal AlGaInP as the upper cladding layer 13 and the lower cladding layer 9, the Al concentration is lower than that of the light emitting diode in which both the barrier layer and the cladding layer are ternary mixed crystal, and moisture resistance is improved. Improves.

  Further, in the light emitting diode 1 of the present embodiment, the current diffusion layer 8 is provided on the light emitting unit 7. Since the current spreading layer 8 is transparent with respect to the emission wavelength, the light-emitting diode 1 having high output and high efficiency can be obtained without absorbing the light emitted from the light emitting unit 7. The functional substrate is stable in material and has excellent moisture resistance without worrying about corrosion.

  Therefore, according to the light emitting diode 1 of the present embodiment, by adjusting the conditions of the active layer, it has an emission wavelength of 830 to 1000 nm, is excellent in monochromaticity, has high output and high efficiency, and is moisture resistant. The light emitting diode 1 with high can be provided. Further, according to the light emitting diode 1 of the present embodiment, it is at least about 1.5 times as compared with a transparent substrate type AlGaAs light emitting diode manufactured by a conventional liquid phase epitaxial method and having a GaAs substrate removed. A high-power light emitting diode 1 having the above light output can be provided.

  In addition, according to the light-emitting diode lamp 41 of the present embodiment, the light-emitting diode 1 having excellent monochromaticity, high output, high efficiency, and moisture resistance is provided. For this reason, the light emitting diode lamp 41 suitable for infrared illumination and a sensor can be provided.

<Light Emitting Diode (Second Embodiment)>
In the light emitting diode according to the second embodiment to which the present invention is applied, the AlGaAs barrier layer 18 in the light emitting diode according to the first embodiment is composed of the composition formula (Al _X4 Ga _1-X4 ) _Y2 In _1-Y2 P (0 The difference is that it is replaced with a barrier layer made of a compound semiconductor of ≦ X4 ≦ 1, 0 <Y2 ≦ 1).

As described above, the barrier layer 18 used in the present embodiment is a quaternary mixed crystal having the composition formula (Al _X4 Ga _1-X4 ) _Y2 In _1-Y2 P (0 ≦ X4 ≦ 1, 0 <Y2 ≦ 1). It consists of a compound semiconductor.
The Al composition X4 is preferably a composition having a band gap larger than that of the well layer 17, and specifically, a range of 0 to 0.2 is preferable.
Y2 is preferably in the range of 0.4 to 0.6, and more preferably in the range of 0.45 to 0.55, in order to prevent generation of distortion due to lattice mismatch with the substrate.
The layer thickness of the barrier layer 18 is preferably equal to the layer thickness of the well layer 17 or thicker than the layer thickness of the well layer 17. As described above, by sufficiently increasing the thickness of the barrier layer 18 within the range of the layer thickness in which the tunnel effect occurs, both the coupling of the well layer by the tunnel effect and the limitation of the spread can be achieved, thereby achieving the carrier confinement effect. As a result, the probability of recombination of electrons and holes is increased, and the light output can be improved.

<Light Emitting Diode (Third Embodiment)>
FIGS. 13A and 13B are views for explaining a light emitting diode according to a third embodiment to which the present invention is applied. FIG. 13A is a plan view, and FIG. 13 is a cross-sectional view taken along line CC ′ shown in FIG. 13A (guide layers 10 and 12 are not shown).
The light emitting diode 20 according to the third embodiment includes a well layer 17 made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X2 Ga _1-X2). ) An active layer 11 having a quantum well structure in which barrier layers 18 made of a compound semiconductor of As (0 ≦ X2 ≦ 1) are alternately stacked, and a lower cladding layer (first cladding layer) 9 and an upper portion sandwiching the active layer 11 The light emitting part 7 having the clad layer (second clad layer) 13, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7 are arranged so as to be opposed to the light emitting wavelength, and 90% or more with respect to the emission wavelength. And a functional substrate 31 bonded to the current diffusion layer 8, and the lower cladding layer 9 and the upper cladding layer 13 have a composition formula (Al _X3 Ga _1-X3 ) _Y1 In _{1 -Y1} P (0 ≦ X3 ≦ 1, 0 <Y1 ≦ 1), and the number of pairs of the well layer 17 and the barrier layer 18 is 5 or less.

The light emitting diode 20 according to the third embodiment has a functional substrate 31 that has a reflectance of 90% or more with respect to the light emission wavelength and includes the reflective layer 23 disposed to face the light emitting portion. Light can be efficiently extracted from the light extraction surface.
In the example shown in FIGS. 13A and 13B, the functional substrate 31 includes the second electrode 21 on the lower surface 8 b of the current diffusion layer 8, and further covers the second electrode 8. As described above, a reflective structure in which the transparent conductive film 22 and the reflective layer 23 are laminated and a layer (substrate) 30 made of silicon or germanium are provided.

  In the light emitting diode according to the third embodiment, the functional substrate 31 preferably includes a layer made of silicon or germanium. This is because silicon or germanium is a material that does not corrode easily, and thus moisture resistance is improved.

  The reflective layer 23 is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.

The functional substrate 31 may be a combination of eutectic metal such as AuIn, AuGe, AuSn, and the like and bonded to an inexpensive substrate (layer) such as silicon or germanium for the reflective layer 23 described above. In particular, AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting portion, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
The functional substrate 31 is further inserted with a layer made of a refractory metal such as titanium (Ti), tungsten (W), or platinum (Pt) so that the current diffusion layer, the reflective layer metal, and the eutectic metal do not interdiffuse. It is also desirable from the standpoint of quality stability to have a configured configuration.

<Light Emitting Diode (Fourth Embodiment)>
FIG. 14 is a view for explaining a light emitting diode according to a fourth embodiment to which the present invention is applied.
The light-emitting diode according to the fourth embodiment to which the present invention is applied includes a well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X2 Ga _1-X2 ) Active layer 11 having a quantum well structure in which barrier layers made of a compound semiconductor of As (0 ≦ X2 ≦ 1) are alternately stacked (see well layer 17, barrier layer 18 and active layer 11 shown in FIG. 5) A light emitting part having a lower clad layer (first clad layer) 9 and an upper clad layer (second clad layer) 13 sandwiching the active layer 11, and a current diffusion layer 8 formed on the light emitting part And a functional substrate 51 that is disposed so as to face the light emitting portion and includes a reflective layer 53 having a reflectivity of 90% or more with respect to the light emission wavelength and the metal substrate 50 and bonded to the current diffusion layer 8. , Lower cladding layer 9 and upper cladding layer 3 is a compound semiconductor of a composition formula _{(Al X5 Ga 1-X5)} Y3 In 1-Y3 P (0 ≦ X5 ≦ 1,0 <Y3 ≦ 1), the number of pairs of well layers and the barrier layer is 5 or less It is characterized by that.

In the light emitting diode 60 according to the fourth embodiment, the point that the functional substrate 51 includes the metal substrate 50 is a characteristic configuration with respect to the light emitting diode according to the second embodiment.
The metal substrate 50 has high heat dissipation, contributes to light emission of the light emitting diode with high luminance, and can extend the life of the light emitting diode.
From the viewpoint of heat dissipation, the metal substrate 50 is particularly preferably made of a metal having a thermal conductivity of 130 W / m · K or more. Examples of the metal having a thermal conductivity of 130 W / m · K or more include molybdenum (138 W / m · K) and tungsten (174 W / m · K).

As shown in FIG. 14, the compound semiconductor layer 2 includes an active layer 11, a first clad layer (lower clad) 9 and a second clad layer sandwiching the active layer 11 via a guide layer (not shown). (Upper clad) 13, the current diffusion layer 8 below the first clad layer (lower clad) 9, and the first electrode 55 above the second clad layer (upper clad) 13 in plan view. A contact layer 56 having substantially the same size.
The functional substrate 51 includes a second electrode 57 on the lower surface 8 b of the current diffusion layer 8, and a transparent conductive film 52 and a reflective layer 53 are laminated so as to cover the second electrode 57. The joining surface 50a of the metal substrate 50 is joined to the surface 53b on the opposite side of the compound semiconductor layer 2 of the reflecting layer 53 constituting the reflecting structure.

  The reflective layer 53 is made of, for example, a metal such as copper, silver, gold, or aluminum, or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective structure can be 90% or more. By forming the reflective layer 53, the light from the active layer 11 is reflected by the reflective layer 53 in the front direction f, and the light extraction efficiency in the front direction f can be improved. Thereby, the brightness of the light emitting diode can be further increased.

The reflective layer 53 preferably has a laminated structure made of Ag, a Ni / Ti barrier layer, and an Au-based eutectic metal (connecting metal) from the transparent conductive film 52 side.
The connecting metal is a metal that has a low electrical resistance and melts at a low temperature. By using the connecting metal, the metal substrate 50 can be connected without applying thermal stress to the compound semiconductor layer 2.
As the connection metal, an Au-based eutectic metal that is chemically stable and has a low melting point is used. Examples of the Au-based eutectic metal include eutectic compositions (Au-based eutectic metals) of alloys such as AuSn, AuGe, and AuSi.
Further, it is preferable to add a metal such as titanium, chromium, or tungsten to the connection metal. Thereby, a metal such as titanium, chromium, or tungsten can function as a barrier metal, and impurities contained in the metal substrate 50 can be prevented from diffusing and reacting on the reflective layer 53 side.

The transparent conductive film 52 is composed of an ITO film, an IZO film, or the like. Note that the reflective structure may be composed of only the reflective layer 53.
Further, instead of the transparent conductive film 52 or together with the transparent conductive film 52, a so-called cold mirror using a difference in refractive index of a transparent material, for example, a multilayer film of titanium oxide film, silicon oxide film, white alumina, AlN May be combined with the reflective layer 53.

The metal substrate 50 can be made of a plurality of metal layers.
As the configuration of the plurality of metal layers, as shown in the example shown in FIG. 14, two types of metal layers, that is, a structure in which the first metal layer 50A and the second metal layer 50B are alternately stacked are preferable. . In particular, the number of first metal layers 50A and the number of second metal layers 50B is more preferably an odd number in total.

In this case, from the viewpoint of warping and cracking of the metal substrate, when a material having a smaller thermal expansion coefficient than the compound semiconductor layer 2 is used as the second metal layer 50B, the first metal layer 50A is more than the compound semiconductor layer 3. It is preferable to use a material made of a material having a large thermal expansion coefficient. This is because the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer, so that warpage and cracking of the metal substrate when bonding the compound semiconductor layer and the metal substrate can be suppressed. This is because the production yield of the light emitting diode can be improved.
Similarly, when a material having a larger thermal expansion coefficient than that of the compound semiconductor layer 2 is used as the second metal layer 50B, a material having a smaller thermal expansion coefficient than that of the compound semiconductor layer 2 is used as the first metal layer 50A. It is preferable. Similarly to the above, since the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer, warpage and cracking of the metal substrate when the compound semiconductor layer and the metal substrate are joined can be suppressed. This is because the production yield of the light emitting diode can be improved.
From the above viewpoint, any of the two types of metal layers may be the first metal layer or the second metal layer.

Examples of the two metal layers include silver (thermal expansion coefficient = 18.9 ppm / K), copper (thermal expansion coefficient = 16.5 ppm / K), gold (thermal expansion coefficient = 14.2 ppm / K), and aluminum. (Thermal expansion coefficient = 23.1 ppm / K), nickel (thermal expansion coefficient = 13.4 ppm / K) and a metal layer made of any of these alloys, molybdenum (thermal expansion coefficient = 5.1 ppm / K), Combinations of tungsten (thermal expansion coefficient = 4.3 ppm / K), chromium (thermal expansion coefficient = 4.9 ppm / K), and a metal layer made of any of these alloys can be used.
As a suitable example of the metal substrate 50, what consists of three layers of Cu / Mo / Cu is mentioned. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo. However, a metal substrate composed of three layers of Cu / Mo / Cu can process Mo with high mechanical strength. Since the structure is easily sandwiched between Cu, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.

  The thermal expansion coefficient of the metal substrate as a whole is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm). ) / Mo (25 μm) for a metal substrate consisting of three layers, it is 5.7 ppm / K.

From the viewpoint of heat dissipation, the metal layer constituting the metal substrate is preferably made of a material having high thermal conductivity. This is because by increasing the heat dissipation of the metal substrate, the light emitting diode can emit light with high brightness, and the life of the light emitting diode can be extended.
For example, as a metal substrate, silver (thermal conductivity = 420 W / m · K), copper (thermal conductivity = 398 W / m · K), gold (thermal conductivity = 320 W / m · K), aluminum (thermal conductivity) Rate = 236 W / m · K), molybdenum (thermal conductivity = 138 W / m · K), tungsten (thermal conductivity = 174 W / m · K), and alloys thereof are preferably used. Further, the metal substrate is more preferably made of a material in which the thermal expansion coefficient of each metal layer is substantially equal to the thermal expansion coefficient of the compound semiconductor layer. In particular, the material of the metal layer is preferably a material having a thermal expansion coefficient that is within ± 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer. As a result, it is possible to reduce stress due to heat applied to the light emitting portion when the metal substrate and the compound semiconductor layer are joined, and to suppress cracking of the metal substrate due to heat when the metal substrate is connected to the compound semiconductor layer. Therefore, the manufacturing yield of the light emitting diode can be improved. The thermal conductivity of the entire metal substrate is, for example, 250 W / m · K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu ( In the case of a metal substrate composed of three layers of 70 μm) / Mo (25 μm), it is 220 W / m · K.

<Light Emitting Diode (Fifth Embodiment)>
The light emitting diode according to the fifth embodiment to which the present invention is applied includes a well layer 17 made of a compound semiconductor having a composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X4 Ga). _1-X4 ) _{Y2In1 -Y2P} (0 ≦ X4 ≦ 1, 0 <Y2 ≦ 1) active layers 11 having a quantum well structure in which barrier layers 18 made of a compound semiconductor are alternately stacked; A light emitting part 7 having a lower clad layer (first clad layer) 9 and an upper clad layer (second clad layer) 13 sandwiched therebetween, a current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7 The lower clad layer 9 and the upper clad layer 13 are provided with a functional substrate 31 that is disposed so as to be opposed to each other and includes a reflective layer 23 having a reflectance of 90% or more with respect to the emission wavelength and joined to the current diffusion layer 8. Is represented by the composition formula (Al _X3 Ga _1-X3 It is made of a compound semiconductor of _Y1 In _1-Y1 P (0 ≦ X3 ≦ 1, 0 <Y1 ≦ 1), and the number of pairs of the well layer 17 and the barrier layer 18 is 5 or less.
In the light emitting diode according to the fifth embodiment, the AlGaAs barrier layer 18 in the light emitting diode according to the third embodiment has a composition formula (Al _X4 Ga _1-X4 ) _Y2 In _1-Y2 P (0 ≦ X4 ≦ 1, The barrier layer is made of a compound semiconductor of 0 <Y2 ≦ 1).

As described above, the barrier layer 18 of the present embodiment is made of a compound semiconductor having a composition formula (Al _X4 Ga _{1 -X4} ) _Y2 In _{1 -Y2} P (0 ≦ X4 ≦ 1, 0 <Y2 ≦ 1).
The Al composition (X4) in the above composition formula is preferably a composition having a band gap larger than that of the well layer 17, and specifically, a range of 0 to 0.2 is preferable.
Y2 is preferably in the range of 0.4 to 0.6 and more preferably in the range of 0.45 to 0.55 in order to prevent generation of distortion due to lattice mismatch with the substrate.
The layer thickness of the barrier layer 18 is preferably equal to the layer thickness of the well layer 17 or thicker than the layer thickness of the well layer 17. By sufficiently increasing the thickness of the barrier layer 18 within the range of the layer thickness in which the tunnel effect occurs, by combining the coupling of the well layer by the tunnel effect and the limitation of the spread, the carrier confinement effect is increased. The probability of light emission recombination between electrons and holes is increased, and the light emission output can be improved.

Similarly to the third embodiment, the light emitting diode according to the present embodiment has a reflectance of 90% or more with respect to the emission wavelength, and a functional substrate including a reflective layer disposed to face the light emitting portion. With this configuration, light can be efficiently extracted from the main light extraction surface.
Also in this embodiment, the functional substrate exemplified in the third embodiment can be used.

<Light Emitting Diode (Sixth Embodiment)>
The light emitting diode according to the sixth embodiment to which the present invention is applied includes a well layer 17 made of a compound semiconductor having a composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X4 Ga). _1-X4 ) _{Y2In1 -Y2P} (0 ≦ X4 ≦ 1, 0 <Y2 ≦ 1) active layers 11 having a quantum well structure in which barrier layers 18 made of compound semiconductor layers are alternately stacked; A light emitting part 7 having a lower clad layer (first clad layer) 9 and an upper clad layer (second clad layer) 13 sandwiching the electrode, a current diffusion layer 8 formed on the light emitting part 7, and a light emitting part 7 And a functional substrate 51 including a reflective layer 53 having a reflectivity of 90% or more with respect to the emission wavelength and a metal substrate 50 and bonded to the current diffusion layer 8, and a lower cladding layer 9 and the upper cladding layer 13 have the composition formula (Al _{X5Ga1 -X5} ) _{Y3In1 -Y3P} (0 ≦ X5 ≦ 1, 0 <Y3 ≦ 1), and the number of pairs of the well layer 17 and the barrier layer 18 is 5 or less. To do.
In the light emitting diode according to the sixth embodiment, the AlGaAs barrier layer 18 in the light emitting diode according to the fourth embodiment is represented by the composition formula (Al _X4 Ga _1-X4 ) _Y2 In _1-Y2 P (0 ≦ X4 ≦ 1, The barrier layer is made of a compound semiconductor of 0 <Y2 ≦ 1).

Similarly to the fourth embodiment, the light emitting diode according to the present embodiment also has a functional substrate including a reflective layer that has a reflectance of 90% or more with respect to the emission wavelength and is disposed to face the light emitting portion. Since it is a structure, light can be efficiently extracted from the main light extraction surface.
Also in this embodiment, the functional substrate exemplified in the fourth embodiment can be used.

  Hereinafter, the effect of the present invention will be specifically described with reference to examples. The present invention is not limited to these examples.

  In this example, an example in which a light-emitting diode according to the present invention is manufactured will be specifically described. The light-emitting diode manufactured in this example is an infrared light-emitting diode having an active layer having a quantum well structure of a well layer made of InGaAs and a barrier layer made of AlGaAs. In this example, a compound semiconductor layer grown on a GaAs substrate and a functional substrate were combined to produce a light emitting diode. Then, a light-emitting diode lamp having a light-emitting diode chip mounted on a substrate was prepared for characteristic evaluation.

Example 1
The light-emitting diode of Example 1 is an example of the first embodiment as shown in FIGS. 3 and 4, and the junction area between the well layer and the barrier layer was 123000 μm ² (350 μm × 350 μm).
In the light-emitting diode of Example 1, first, an epitaxial wafer having an emission wavelength of 920 nm was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of an n-type GaAs single crystal doped with Si. In the GaAs substrate, a plane inclined by 15 ° in the (0-1-1) direction from the (100) plane was used as a growth plane, and the carrier concentration was set to 2 × 10 ¹⁸ cm ⁻³ . The layer thickness of the GaAs substrate was about 0.5 μm. As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type contact layer made of Si-doped (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, Si N-type upper cladding layer made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, upper guide layer made of Al _0.3 Ga _0.7 As, In _0.2 Ga Well layer / barrier layer composed of _0.8 As / Al _0.1 Ga _0.9 As pairs, lower guide layer composed of Al _0.3 Ga _0.7 As, Mg-doped (Al _0.7 Ga _{0 .3)} p-type lower cladding layer composed of _0.5 in _{0.5 P,} the intermediate layer, p-type and Mg-doped thin film made of _{(Al 0.5 Ga 0.5) 0.5 in} 0.5 P A current diffusion layer made of GaP was used.

In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 76 mm and a thickness of 350 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga) and trimethylindium ((CH ₃ ) ₃ In) are used as the raw material for the group III constituent element did. Further, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) was used as a Mg doping material. Further, disilane (Si ₂ H ₆ ) was used as a Si doping material. Further, phosphine (PH ₃ ) and arsine (AsH ₃ ) were used as raw materials for the group V constituent elements. As the growth temperature of each layer, the current diffusion layer made of p-type GaP was grown at 750 ° C. The other layers were grown at 700 ° C.

The buffer layer made of GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 3.5 μm. The upper cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The upper guide layer was undoped and had a thickness of about 50 nm. The well layer was undoped In _0.2 Ga _0.8 As with a thickness of about 5 nm, and the barrier layer was undoped Al0.1Ga0.9As with a thickness of about 19 nm. The number of pairs of the well layer and the barrier layer is one. The lower guide layer was undoped and had a thickness of about 50 nm. The lower cladding layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.05 μm. The current diffusion layer made of GaP has a carrier concentration of about 3 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 9 μm.

Next, the current diffusion layer was polished to a region extending from the surface to a depth of about 1 μm and mirror-finished.
By this mirror finishing, the surface roughness (root mean square: rms) of the current diffusion layer was set to 0.18 nm.
On the other hand, a functional substrate made of n-type GaP to be attached to the mirror-polished surface of the current diffusion layer was prepared. A single crystal having a plane orientation of (111) was used for the functional substrate for pasting, to which Si was added so that the carrier concentration was about 2 × 10 ¹⁷ cm ⁻³ . The functional substrate had a diameter of 76 mm and a thickness of 250 μm. The surface of the functional substrate was polished to a mirror surface before being bonded to the current spreading layer, and the surface roughness was finished to 0.12 nm with a root mean square (rms).

Next, the functional substrate and the epitaxial wafer were carried into a general semiconductor material pasting apparatus, and the inside of the apparatus was evacuated to 3 × 10 ⁻⁵ Pa.

Next, the surface of both the functional substrate and the current spreading layer was irradiated with an Ar beam neutralized by colliding electrons for 3 minutes. Thereafter, the surfaces of the functional substrate and the current diffusion layer were superposed in a sticking apparatus maintained in vacuum, a load was applied so that the pressure on each surface was 50 g / cm ^2, and both were bonded at room temperature. In this way, a bonded wafer was formed.

  Next, the GaAs substrate and the GaAs buffer layer were selectively removed from the bonded wafer with an ammonia-based etchant. Next, a first electrode was formed on the surface of the contact layer by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 μm, Pt was 0.2 μm, and Au was 1 μm. Then, patterning was performed using a general photolithography means, and an n-type ohmic electrode was formed as the first electrode. Next, the surface of the light extraction surface, which is the surface from which the GaAs substrate was removed, was roughened.

  Next, the epi layer in the region where the p-type ohmic electrode was formed as the second electrode was selectively removed to expose the current diffusion layer. A p-type ohmic electrode was formed on the exposed surface of the current diffusion layer by vacuum deposition so that AuBe was 0.2 μm and Au was 1 μm. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed. Further, a third electrode was formed by forming Au in a thickness of 0.2 μm on the back side of the functional substrate and forming a pattern in a 230 μm square.

  Next, using a dicing saw, the region where the third electrode is not formed from the back surface of the functional substrate is V so that the angle α of the inclined surface is 70 ° and the thickness of the vertical surface is 130 μm. A letter-shaped grooving was performed. Next, a dicing saw was used to cut from the compound semiconductor layer side at 350 μm intervals to form chips. Then, the crushed layer and dirt due to dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce a light emitting diode of Example 1.

  100 light emitting diode lamps each having the light emitting diode chip of Example 1 manufactured as described above mounted on a mount substrate were assembled. In this light-emitting diode lamp, the mount is supported (mounted) by a die bonder, the n-type ohmic electrode of the light-emitting diode and the n-electrode terminal provided on the surface of the mount substrate are wire-bonded with a gold wire, and the p-type ohmic electrode and the p-type electrode are connected. The electrode terminal was wire bonded with a gold wire and then sealed with a general epoxy resin.

The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are shown in Table 5, FIG. 15 and FIG. FIG. 15 shows a case where the barrier layer is made of a compound semiconductor having the composition formula (Al _X2 Ga _1-X2 ) As (0 ≦ X2 ≦ 1), and the junction area between the active layer and the cladding layer is 123000 μm ² and 53000 μm ² . 16 is a graph showing the relationship between the number of pairs and the response speed, and FIG. 16 is a graph showing the relationship between the number of pairs and the light emission output in the same case as FIG.

In Example 1, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak emission wavelength of 920 nm was emitted. Further, as shown in Table 5, in Example 1, the forward voltage (V _F ) when a current of 20 milliamperes (mA) was passed in the forward direction was equal to the current diffusion layer constituting the compound semiconductor layer and the function. Reflecting the low resistance at the bonding interface with the conductive substrate and the good ohmic characteristics of each ohmic electrode, the voltage was 1.2 volts. Moreover, the response speed (rise time) tr and the light emission output (P ₀ ) when the forward current was 20 mA were 15 nsec and 6.8 mW, respectively.

(Example 2)
The light-emitting diode of Example 2 is an example of the first embodiment, and was manufactured under the same conditions as in Example 1 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. .
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 18 nsec, 7.0 mW, and 1.2 V, respectively.

(Example 3)
The light-emitting diode of Example 3 is an example of the first embodiment, and was manufactured under the same conditions as in Example 1 except that the number of pairs of well layers and barrier layers was five, and the same evaluation was performed. .
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 23 nsec, 6.9 mW, and 1.22 V, respectively.

The light emitting diodes of Examples 4 to 6 shown below are also examples of the first embodiment, but only the point that the junction area between the active layer and the cladding layer is 53000 μm ² (230 μm × 230 μm) is described in Example 1. It is an embodiment different from the above.

Example 4
The light emitting diode of Example 4 was fabricated under the same conditions as in Example 1 except for the junction area between the active layer and the cladding layer, and the same evaluation was performed.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 12 nsec, 7.0 mW, and 1.25 V, respectively.

(Example 5)
The light-emitting diode of Example 5 was fabricated under the same conditions as in Example 4 except that the number of pairs of well layers and barrier layers was 3, and the same evaluation was performed.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 15 nsec, 7.1 mW, and 1.26 V, respectively.

(Example 6)
The light emitting diode of Example 6 was fabricated under the same conditions as in Example 4 except that the number of pairs of well layers and barrier layers was 5, and the same evaluation was performed.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 18 nsec, 7.0 mW, and 1.30 V, respectively.

(Example 7)
The light emitting diode of Example 7 is also an example of the first embodiment, but is an example in which the junction area between the active layer and the cladding layer is 20000 μm ² (200 μm × 100 μm).

The light emitting diode of Example 7 was fabricated under the same conditions as in Example 1 except for the junction area between the active layer and the cladding layer, and the same evaluation was performed.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 14 nsec, 7.0 mW, and 1.36 V, respectively.

(Example 8)
The light-emitting diode of Example 8 is also an example of the first embodiment. However, the light-emitting diode was manufactured under the same conditions as in Example 7 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 12 nsec, 7.0 mW, and 1.35 V, respectively.

Example 9
The light emitting diode of Example 9 is also an example of the first embodiment, but is an example in which the junction area between the active layer and the cladding layer is 90000 μm ² (300 μm × 300 μm).

The light emitting diode of Example 9 was fabricated under the same conditions as in Example 1 except for the junction area between the active layer and the cladding layer, and the same evaluation was performed.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 21 nsec, 6.9 mW, and 1.23 V, respectively.

(Example 10)
The light-emitting diode of Example 10 is also an example of the first embodiment, but is manufactured under the same conditions as in Example 9 except that the number of pairs of well layers and barrier layers is three, and the same evaluation is performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 16 nsec, 7.0 mW, and 1.22 V, respectively.

  The light emitting diodes of Examples 11 to 13 shown below are examples of the second embodiment.

(Example 11)
The light emitting diode of Example 11 is an example in which the junction area between the active layer and the clad layer is 123000 μm ² (350 μm × 350 μm) and the emission wavelength is 960 nm.

The layer structure of the light-emitting diode of Example 11 is as follows.
In Example 11, on a GaAs substrate made of an n-type GaAs single crystal doped with Si, a plane inclined by 15 ° from the (100) plane in the (0-1-1) direction is used as the growth plane, and the carrier concentration is 2 × 10 ¹⁸ cm ^-3 . As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type contact layer made of Si-doped (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, Si N-type upper cladding layer made of (Al _0.3 Ga _0.7 ) _0.5 In _0.5 P doped with, (Al _0.1 Ga _0.9 ) _0.5 In _0.5 P Upper guide layer, well layer / barrier layer composed of a pair of In _0.25 Ga _0.75 As / (Al _0.1 Ga _0.9 ) _0.5 In _0.5 P, (Al _0.1 Ga _{0. 9) 0.5} in _0.5 lower guide layer made of P, doped with Mg _{(Al 0.3} Ga _0.7) p-type lower cladding layer composed of _{0.5 in} 0.5 P, (Al _{0 .5} Ga _0.5) an intermediate layer of a thin film made of _0.5 in _0.5 P, Using current diffusion layer made of g-doped p-type GaP.

The buffer layer made of GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 3.5 μm. The upper cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The upper guide layer was undoped and had a thickness of about 50 nm. The well layer is undoped and has a thickness of In _0.25 Ga _0.75 As, and the barrier layer is undoped and has a thickness of about 19 nm (Al _0.1 Ga _0.9 ) _0.5 In _{0. 5} P. The number of pairs of well layers and barrier layers was five. The lower guide layer was undoped and had a thickness of about 50 nm. The lower cladding layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.05 μm. The current diffusion layer made of GaP has a carrier concentration of about 3 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 9 μm.
The light emitting diode of Example 11 had a response speed (tr), a light emission output (P ₀ ), and a forward voltage (V _F ) of 24 nsec, 6.7 mW, and 1.26 V, respectively.

(Example 12)
The light-emitting diode of Example 12 is also an example of the second embodiment. However, the light-emitting diode was manufactured under the same conditions as in Example 11 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 18 nsec, 6.8 mW, and 1.24 V, respectively.

(Example 13)
The light-emitting diode of Example 13 has the same conditions as Example 11 except that the junction area between the active layer and the cladding layer was 53000 μm ² (230 μm × 230 μm) and the number of pairs of well layers and barrier layers was three. A similar evaluation was made.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 14 nsec, 6.8 mW, and 1.29 V, respectively.

  In Examples 14 to 19 shown below, a compound semiconductor layer was prepared in the same manner as in Examples 1 to 13, and then a functional substrate including a reflective layer was bonded to a current diffusion layer, and the functional substrate was silicon. It is an Example including the layer which consists of. Here, the light emitting diodes of Examples 14 to 16 are examples of the third embodiment, and the light emitting diodes of Examples 17 to 19 are examples of the fifth embodiment.

(Example 14)
The light-emitting diode of Example 14 is an example in which the junction area between the active layer and the clad layer was 123000 μm ² (350 μm × 350 μm). After the compound semiconductor layer was fabricated in the same procedure as in Example 1 and the like, This is a configuration in which a functional substrate having a reflective layer is bonded to a diffusion layer. At this time, the number of well layers and barrier layers was five.
Hereinafter, a method for manufacturing the light-emitting diode of Example 14 will be described with reference to FIGS.

First, on the surface of the current diffusion layer 8, an electrode (second electrode) 21 made of AuBe / Au alloy with a thickness of 0.2 μm and a dot of 20 μmφ is arranged at equal intervals so as to be 50 μm from the end of the light extraction surface. Eight were arranged.
Next, an ITO film 22 which is a transparent conductive film was formed by a sputtering method with a thickness of 0.4 μm. Further, a layer 23 made of silver alloy / Ti / Au was formed to a thickness of 0.2 μm / 0.1 μm / 1 μm to form a reflective layer 23.

On the other hand, a layer 32 made of Ti / Au / In was formed on the surface of a silicon substrate (functional substrate) 31 with a thickness of 0.1 μm / 0.5 μm / 0.3 μm. A layer 33 made of Ti / Au was formed on the back surface of the silicon substrate 31 with a thickness of 0.1 μm / 0.5 μm. Then, the Au on the light emitting diode wafer side and the In surface on the silicon substrate side were superposed and heated at 320 ° C. and pressurized with 500 g / cm ² to bond the functional substrate to the light emitting diode wafer.

  Next, the GaAs substrate is removed, and an ohmic electrode (first electrode) 25 having a diameter of 100 μm and a thickness of 3 μm made of AuGe / Au is formed on the surface of the contact layer 16, and heat-treated at 420 ° C. for 5 minutes. The n-ohmic electrode was alloyed.

Next, using the first electrode 25 as a mask, portions other than the portion immediately below the electrode 25 of the contact layer 16 were removed, and then the surface was roughened.
Next, the semiconductor layer, the reflective layer, and the eutectic metal that were to be cut to be separated into chips were removed, and the silicon substrate 31 was cut into squares at a pitch of 350 μm with a dicing saw.

When a current was passed between the upper and lower electrodes of the light emitting diode (light emitting diode lamp) thus obtained, infrared light having a peak wavelength of 920 nm was emitted. Further, the forward voltage (V _F ) when a current of 20 milliamperes (mA) flows in the forward direction is low in resistance at the junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate. Reflecting good ohmic characteristics of each ohmic electrode, the response speed (tr), the light emission output (P0), and the forward voltage (V _F ) were 24 nsec, 6.5 mW, and 1.24 V, respectively.

(Example 15)
The light-emitting diode of Example 15 is also an example of the third embodiment. However, the light-emitting diode was manufactured under the same conditions as in Example 14 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 20 nsec, 6.7 mW, and 1.24 V, respectively.

(Example 16)
The light-emitting diode of Example 16 has the same conditions as Example 11 except that the junction area between the active layer and the clad layer was 53000 μm ² (230 μm × 230 μm) and the number of pairs of well layers and barrier layers was three. A similar evaluation was made.

As a result of evaluating the characteristics of the light emitting diode (light emitting diode lamp), the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 15 nsec, 6.5 mW, and 1.28 V, respectively. It was.

(Example 17)
In the light-emitting diode of Example 17, the junction area between the active layer and the cladding layer is 123000 μm ² (350 μm × 350 μm), and the number of pairs of well layers and barrier layers is five. The light-emitting diode of Example 17 has a configuration in which a compound semiconductor layer is manufactured in the same procedure as in Example 11, and then a functional substrate having a reflection layer in the current diffusion layer is bonded in the same procedure as in Example 14. is there.
As a result of evaluating the characteristics of this light-emitting diode (light-emitting diode lamp), the response speed (tr), light-emitting output (P ₀ ), and forward voltage (V _F ) were 24 nsec, 6.4 mW, and 1.26 V, respectively. It was.

(Example 18)
The light-emitting diode of Example 18 is also an example of the fifth embodiment. However, the light-emitting diode was manufactured under the same conditions as in Example 17 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 20 nsec, 6.5 mW, and 1.25 V, respectively.

(Example 19)
The light emitting diode of Example 19 is the same as Example 13 except that the junction area between the active layer and the clad layer is 53000 μm ² (230 μm × 230 μm), and the number of pairs of well layers and barrier layers is 3. A similar evaluation was made.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 15 nsec, 6.5 mW, and 1.29 V, respectively.

  Examples 20 and 21 shown below are examples of the fourth embodiment, Examples 22 and 23 are examples of the sixth embodiment, and a compound semiconductor layer is produced in the same manner as in Examples 1 to 13. Thereafter, a functional substrate including a reflective layer and a metal substrate is bonded to the current diffusion layer.

(Example 20)
In the light emitting diode of Example 20, the junction area between the active layer and the cladding layer is 123000 μm ² (350 μm × 350 μm), and the number of pairs of well layers and barrier layers is five. A method for manufacturing the light-emitting diode of Example 20 will be described with reference to FIG.

First, on the surface 8b of the current diffusion layer 8, eight second electrodes 57 made of AuBe / Au alloy with dots having a thickness of 0.2 μm and 20 μmφ are arranged at equal intervals so as to be 50 μm from the end of the light extraction surface. Arranged.
Next, an ITO film 52, which is a transparent conductive film, was formed by sputtering with a thickness of 0.4 μm. Further, a layer 53 made of silver alloy / Ti / Au was formed to a thickness of 0.2 μm / 0.1 μm / 1 μm to form a reflective layer 53.

  Next, the first metal plates 50A and 50A made of a material having a thermal expansion coefficient larger than that of the material of the compound semiconductor layer 2, and the second metal plate made of a material having a thermal expansion coefficient smaller than that of the material of the compound semiconductor layer 2. The metal substrate 50 was formed by hot pressing using 50B. Specifically, Cu having a thickness of 10 μm is used as the first metal plate 50A, and Mo having a thickness of 75 μm is used as the second metal plate 50B. As shown in FIG. 14, two first metal plates are used. The second metal plate 50B is inserted between 50A and 50A, these are stacked, and a load is applied at a high temperature by a predetermined pressurizing device, whereby Cu (10 μm) / Mo (75 μm) / Cu (10 μm) A three-layer metal substrate 50 was formed.

Next, the surface of the reflective layer 53 of the light emitting diode and the metal substrate 50 are superposed and bonded by heating at 400 ° C. and pressurizing at 500 g / cm ² to bond the functional substrate 51. Was made.

Next, the GaAs substrate is removed, and an ohmic electrode 55 made of AuGe / Au and having a diameter of 100 μm and a thickness of 3 μm is formed on the surface of the contact layer 56, and heat-treated at 420 ° C. for 5 minutes to form p and n ohmic electrodes. Alloyed.
Next, using the first electrode 25 as a mask, portions other than the portion immediately below the electrode 25 of the contact layer 16 were removed, and then the surface was roughened.
Then, the semiconductor layer, the reflective layer, and the eutectic metal to be cut to be separated into chips were removed, and the silicon substrate was cut into squares at a pitch of 350 μm with a dicing saw.

As a result of evaluating the characteristics of the light emitting diode (light emitting diode lamp), the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 25 nsec, 6.6 mW, and 1.27 V, respectively. .

(Example 21)
The light-emitting diode of Example 21 is also an example of the fourth embodiment. However, the light-emitting diode was fabricated under the same conditions as in Example 20 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 20 nsec, 6.7 mW, and 1.27 V, respectively.

(Example 22)
In the light-emitting diode of Example 22, the AlGaAs barrier layer in the light-emitting diode of Example 20 is expressed by the composition formula ( _{AlX4Ga1 -X4} ) _{Y2In1 -Y2P} (0≤X4≤1, 0 <Y2≤1). The difference is that the barrier layer is made of a compound semiconductor.
As a result of evaluating the characteristics of the light emitting diode (light emitting diode lamp), the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 25 nsec, 6.4 mW, and 1.31 V, respectively. It was.

(Example 23)
The light-emitting diode of Example 23 is also an example of the sixth embodiment. However, the light-emitting diode was manufactured under the same conditions as in Example 22 except that the number of pairs of well layers and barrier layers was three, and the same evaluation was performed. went.
As a result, the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 21 nsec, 6.5 mW, and 1.30 V, respectively.

  Reference Examples 1 to 4 shown below are examples in which the number of pairs of the well layer and the barrier layer is 10 pairs and 20 pairs, and the ternary mixed crystal quantum well structure or the ternary mixed crystal well of the present invention is used. This is to show that a structure in which a quantum well structure composed of a layer and a quaternary mixed crystal barrier layer is sandwiched between quaternary cladding layers is suitable for high light output.

(Reference Example 1)
The light emitting diode of Reference Example 1 was produced under the same conditions as the light emitting diode of Example 1 except that the number of pairs of well layers and barrier layers was 10, and the same evaluation was performed.
As a result of evaluating the characteristics of the light emitting diode (light emitting diode lamp), the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 32 nsec, 6.5 mW, and 1.32 V, respectively. It was.

(Reference Example 2)
The light-emitting diode of Reference Example 2 was produced under the same conditions as the light-emitting diode of Example 1 except that the number of pairs of well layers and barrier layers was 20, and the same evaluation was performed.
As a result of evaluating the characteristics of the light emitting diode (light emitting diode lamp), the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 43 nsec, 5 mW, and 1.38 V, respectively.

(Reference Example 3)
The light-emitting diode of Reference Example 3 was produced under the same conditions as the light-emitting diode of Example 4 except that the number of pairs of well layers and barrier layers was 10, and the same evaluation was performed.
As a result of evaluating the characteristics of the light emitting diode (light emitting diode lamp), the response speed (tr), the light emission output (P ₀ ), and the forward voltage (V _F ) were 23 nsec, 6.2 mW, and 1.40 V, respectively. It was.

(Reference Example 4)
The light-emitting diode of Reference Example 4 was produced under the same conditions as the light-emitting diode of Example 1 except that the number of pairs of well layers and barrier layers was 20, and the same evaluation was performed.
As a result of evaluating the characteristics of this light-emitting diode (light-emitting diode lamp), the response speed (tr), light-emitting output (P ₀ ), and forward voltage (V _F ) were 36 nsec, 5.2 mW, and 1.51 V, respectively. It was.

As is clear from the results of Reference Examples 1 to 4, even when the number of pairs of well layers and barrier layers is increased, a higher light output (P ₀ ) can be obtained compared to the above examples. It turns out that it cannot be done.

(Comparative Example 1)
The light emitting diode of Comparative Example 1 is a comparative example in which a compound semiconductor layer is formed using a liquid phase epitaxial method which is a conventional technique. Specifically, a light emitting diode having a double hetero structure having Al _0.01 Ga _0.99 As as a light emitting layer was epitaxially grown on a GaAs substrate to produce and evaluate a light emitting diode.

In the manufacture of the light emitting diode of Comparative Example 1, crystal growth was performed on a GaAs substrate using a slide boat type growth apparatus.
Specifically, first, a substrate made of n-type GaAs single crystal is set in the substrate housing groove of the slide boat type growth apparatus, and Ga metal, GaAs polycrystal, metal Al, and Al are prepared in a crucible prepared for growth of each layer. A dopant was added. The growing layer has a four-layer structure of a transparent thick film layer (first p-type layer), a lower cladding layer (p-type cladding layer), an active layer, and an upper cladding layer (n-type cladding layer). did.

  Next, a slide boat type growth apparatus in which these raw materials are set is set in a quartz reaction tube, heated to 950 ° C. in a hydrogen stream, dissolved in raw materials, and then the ambient temperature is lowered to 910 ° C. After pressing to the right and bringing it into contact with the raw material solution (melt), the temperature is lowered at a rate of 0.5 ° C./min. After repeatedly contacting with the melt finally, the ambient temperature was lowered to 703 ° C. to grow the n-clad layer, and then the slider was pushed to separate the raw material solution from the wafer to complete the epitaxial growth.

The above conditions, the n-type (100) plane of the GaAs single crystal _substrate, comprising the n-type upper cladding layer made of Al _{0.01 Ga 0.99} As _50μm, from Al _{0.01 Ga 0.99} As Si The doped light-emitting layer is 20 μm, the p-type lower cladding layer made of Al _0.7 Ga _0.3 As is 20 μm, and the p-type thick film layer made of Al 0.25 Ga _0.75 As transparent to the emission wavelength is 60 μm. Thus, each layer was grown by a liquid phase epitaxial method.

After the epitaxial growth was completed, the epitaxial substrate was taken out, and the p-type GaAs substrate was selectively removed with an ammonia-hydrogen peroxide etchant while protecting the n-type GaAlAs cladding layer surface.
Next, a gold electrode is formed on both sides of the epitaxial wafer, and a surface electrode in which a wire bonding pad having a diameter of 100 μm is arranged at the center is formed on the surface of the n-type AlGaAs upper cladding layer using an electrode mask having a long side of 350 μm. Formed. In addition, ohmic electrodes having a diameter of 20 μm were formed at 80 μm intervals as back electrodes on the back surface of the p-type AlGaAs thick film layer.
Then, after cutting the wafer with a dicing saw at intervals of 350 μm, the crushed layer was removed by etching, whereby the light emitting diode chip of Comparative Example 1 was manufactured so that the n-type AlGaAs layer was on the surface side.

The results of evaluating the characteristics of the light-emitting diode lamp mounted with the light-emitting diode of Comparative Example 1 are shown in Table 5 above.
As shown in Table 5, when a current was passed between the n-type and p-type ohmic electrodes of the light-emitting diode of Comparative Example 1, infrared light having a peak wavelength of 940 nm was emitted. The forward voltage (V _F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.2 volts (V). The light emission output when the forward current was 20 mA was 2 mW. Further, the response speed (tr) was 1700 nsec, and any sample of Comparative Example 1 was inferior to the high-speed response as compared with the example of the present invention.

  The light-emitting diode of the present invention can be used as a light-emitting diode, a light-emitting diode lamp, and an illumination device that emit infrared light having both high-speed response and high output.

1 ... light emitting diode,
2 ... Compound semiconductor layer,
3 ... Functional substrate,
3a ... vertical plane,
3b ... inclined surface,
4 ... n-type ohmic electrode (first electrode),
5 ... p-type ohmic electrode (second electrode),
7: Light emitting part,
8 ... current spreading layer,
9: Lower cladding layer (first cladding layer),
10 ... Lower guide layer,
11 ... active layer,
12 ... Upper guide layer,
13 ... upper clad layer (second clad layer),
14 ... GaAs substrate,
15 ... buffer layer,
16 ... contact layer,
17 ... well layer,
18 ... barrier layer,
20 ... Light emitting diode,
21 ... Electrode,
22 ... Transparent conductive film,
23 ... reflective layer,
25: Bonding electrode,
31 ... Functional substrate,
41. Light emitting diode lamp,
42 ... Mount substrate,
43 ... n electrode terminal,
44... P electrode terminal,
45, 46 ... gold wire,
47 ... epoxy resin,
α ・ ・ ・ An angle formed between the inclined surface and a surface parallel to the light emitting surface,
50 ... Metal substrate,
51. Functional substrate,
52 ... Transparent conductive film,
53 ... reflective layer,
55 ... first electrode,
56 ... contact layer,
57: Second electrode.

Claims (24)

From a well layer made of a compound semiconductor of composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a compound semiconductor of composition formula (Al _X2 Ga _1-X2 ) As (0 ≦ X2 ≦ 1) An active layer having a quantum well structure in which barrier layers are alternately stacked, a first guide layer and a second guide layer sandwiching the active layer, and outside the first guide layer and the second guide layer A light emitting section having a first cladding layer and a second cladding layer provided respectively;
A current spreading layer formed on the light emitting part;
A functional substrate bonded to the current spreading layer,
The first and second cladding layers are composed of a compound semiconductor having a composition formula ( _{AlX3Ga1 -X3} ) _{Y1In1 -Y1P} (0≤X3≤1, 0 <Y1≤1);
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned. A well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X4 Ga _1-X4 ) _Y2 In _{1 -Y2} P (0 ≦ X4 ≦ 1) , 0 <Y2 ≦ 1), an active layer having a quantum well structure in which barrier layers made of a compound semiconductor are alternately stacked, a first guide layer and a second guide layer sandwiching the active layer, and the first guide A light emitting section having a first clad layer and a second clad layer respectively provided on the outer side of the layer and the second guide layer;
A current spreading layer formed on the light emitting part;
A functional substrate bonded to the current spreading layer,
The first and second cladding layers are made of a compound semiconductor having a composition formula ( _{AlX5Ga1 -X5} ) _{Y3In1 -Y3P} (0≤X5≤1, 0 <Y3≤1);
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned. The light emitting diode according to claim 1, wherein a junction area between the active layer and the clad layer is 20000 to 90000 μm ² .   4. The light-emitting diode according to claim 1, wherein an In composition X1 of the well layer is 0 ≦ X1 ≦ 0.3, and a thickness of the well layer is 3 to 10 nm.   The light-emitting diode according to claim 1, wherein an In composition X1 of the well layer is 0.1 ≦ X1 ≦ 0.3.   The light-emitting diode according to claim 1, wherein the functional substrate is transparent with respect to an emission wavelength.   The light emitting diode according to claim 1, wherein the functional substrate is made of GaP, sapphire, or SiC. From a well layer made of a compound semiconductor of composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a compound semiconductor of composition formula (Al _X2 Ga _1-X2 ) As (0 ≦ X2 ≦ 1) An active layer having a quantum well structure in which barrier layers are alternately stacked, a first guide layer and a second guide layer sandwiching the active layer, and outside the first guide layer and the second guide layer A light emitting section having a first cladding layer and a second cladding layer provided respectively;
A current spreading layer formed on the light emitting part;
A functional substrate disposed opposite to the light emitting portion and including a reflective layer having a reflectance of 90% or more with respect to an emission wavelength, and a functional substrate bonded to the current diffusion layer,
The first and second cladding layers are composed of a compound semiconductor having a composition formula ( _{AlX3Ga1 -X3} ) _{Y1In1 -Y1P} (0≤X3≤1, 0 <Y1≤1);
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned. A well layer made of a compound semiconductor having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X4 Ga _1-X4 ) _Y2 In _{1 -Y2} P (0 ≦ X4 ≦ 1) , 0 <Y2 ≦ 1), an active layer having a quantum well structure in which barrier layers made of a compound semiconductor are alternately stacked, a first guide layer and a second guide layer sandwiching the active layer, and the first guide A light emitting section having a first clad layer and a second clad layer respectively provided on the outer side of the layer and the second guide layer;
A current spreading layer formed on the light emitting part;
A functional substrate disposed opposite to the light emitting portion and including a reflective layer having a reflectance of 90% or more with respect to an emission wavelength, and a functional substrate bonded to the current diffusion layer,
The first and second cladding layers are made of a compound semiconductor having a composition formula ( _{AlX5Ga1 -X5} ) _{Y3In1 -Y3P} (0≤X5≤1, 0 <Y3≤1);
The number of pairs of said well layer and barrier layer is 5 or less, The light emitting diode characterized by the above-mentioned. 10. The light emitting diode according to claim 8, wherein a junction area between the active layer and the clad layer is 20000 to 90000 μm ² .   11. The light-emitting diode according to claim 8, wherein an In composition X1 of the well layer is 0 ≦ X1 ≦ 0.3, and a thickness of the well layer is 3 to 10 nm.   11. The light-emitting diode according to claim 8, wherein an In composition X1 of the well layer is 0.1 ≦ X1 ≦ 0.3.   The light emitting diode according to any one of claims 8 to 12, wherein the functional substrate includes a layer made of silicon or germanium.   The light emitting diode according to any one of claims 8 to 12, wherein the functional substrate includes a metal substrate.   The light emitting diode according to claim 14, wherein the metal substrate comprises a plurality of metal layers.   The light emitting diode according to any one of claims 1 to 15, wherein the number of pairs of the well layer and the barrier layer is 3 or less.   The light emitting diode according to any one of claims 1 to 16, wherein the current diffusion layer is made of GaP.   18. The light emitting diode according to claim 1, wherein a thickness of the current diffusion layer is in a range of 0.5 to 20 μm.   The side surface of the functional substrate has a vertical surface that is substantially perpendicular to the main light extraction surface on the side close to the light emitting unit, and is inside the main light extraction surface on the side far from the light emitting unit. The light emitting diode according to claim 1, wherein the light emitting diode has an inclined surface.   The light emitting diode of claim 19, wherein the inclined surface includes a rough surface.   21. The light emitting diode according to claim 19, wherein the first electrode and the second electrode are provided on the main light extraction surface side of the light emitting diode.   The light emitting diode according to claim 21, wherein the first electrode and the second electrode are ohmic electrodes.   A light-emitting diode lamp comprising the light-emitting diode according to any one of claims 1 to 22.   An illuminating device including a plurality of the light emitting diodes according to any one of claims 1 to 22 and / or the light emitting diode lamps according to claim 23.

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