JP2015159435A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an operation of impedance adjustment by a calibration circuit more successfully.SOLUTION: A semiconductor device comprises: a resistive element r2 connected to between a node N2 and a calibration terminal ZQ; a pull-up replica unit RU3 which is connected to the node N2 and in which impedance is controlled depending on an impedance code RPCODE; and a pull-down replica unit RU4 which is connected to the node N2 and fixed to an inactivated state. The impedance code RPCODE is created by a control circuit 111 depending on potential of the calibration terminal ZQ. According to the present embodiment, since the replica unit 101 having a circuit configuration the same with that of an output unit is used, an operation of impedance adjustment by a calibration circuit can be performed more successfully.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a calibration circuit that controls the impedance of an output unit.

  A semiconductor device such as a DRAM (Dynamic Random Access Memory) includes an output unit for outputting data to the outside. The output unit is designed so as to obtain a desired impedance when activated, but the impedance as designed is not always obtained due to the influence of process variations and temperature changes. For this reason, in a semiconductor device that needs to control the impedance of the output unit with high accuracy, an impedance adjustment circuit called a calibration circuit is built in (see Patent Document 1).

  The calibration circuit described in Patent Document 1 has a configuration in which a replica unit having the same circuit configuration as a pull-up unit included in an output unit is connected to a calibration terminal. Then, calibration is performed by controlling the impedance of the replica unit so that the potential of the calibration terminal matches the desired level and reflecting this in the pull-up unit of the output unit.

JP 2008-228276 A

  However, in the calibration circuit described in Patent Document 1, since the replica unit connected to the calibration terminal is only the replica circuit of the pull-up unit, the output unit composed of the pull-up unit and the pull-down unit is actually The circuit configuration is different. For this reason, there is a problem that an adjustment error due to a difference in circuit configuration occurs.

  Such a problem is particularly noticeable when the resistance element included in the output unit is shared by the pull-up unit and the pull-down unit. This is because when a resistive element is shared by a pull-up unit and a pull-down unit, it is preferable to adopt a layout in which these are arranged in a row, and a replica unit having a configuration in which the pull-down unit is deleted from the layout. This is because the layout is significantly different from the actual output unit.

  The semiconductor device according to the present invention includes first and second external terminals, a first node, a first resistance element connected between the first node and the first external terminal, and the first node. A first unit including a first conductivity type transistor connected and having an impedance controlled according to a first cord; and a second unit including a second conductivity type transistor connected to the first node. An output unit; a second node; a second resistance element connected between the second node and the second external terminal; and the first conductivity type transistor connected to the second node; A third unit whose impedance is controlled in accordance with the first cord; a fourth unit including the second conductivity type transistor connected to the second node and brought into a non-conducting state; and the second external terminal. of Position, characterized in that it comprises a calibration circuit having a first control circuit for generating the first code depending on.

  According to the present invention, since the replica unit having the same circuit configuration as the output unit is used, the impedance adjustment operation by the calibration circuit can be performed more accurately.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing a part of a data input / output circuit 50 used in the first embodiment. It is a circuit diagram of output unit OB by a 1st embodiment. It is a circuit diagram of the calibration circuit 100 used in 1st Embodiment. It is a graph which shows the current voltage characteristic of output unit OB. It is a circuit diagram which shows a part of data input / output circuit 50 used in 2nd Embodiment. It is a circuit diagram of output unit OB by a 2nd embodiment. It is a circuit diagram of the calibration circuit 100 used in 2nd Embodiment. It is a circuit diagram of output unit OB by a 3rd embodiment. It is a circuit diagram of the calibration circuit 100 used in 3rd Embodiment. FIG. 9 is a circuit diagram of a calibration circuit 100 according to a fourth embodiment. It is a circuit diagram which shows an example of an output unit. FIG. 13 is a circuit diagram of a calibration circuit for calibrating the output unit shown in FIG. 12. It is a circuit diagram of an improved output unit. It is a figure for demonstrating the layout of the improved output unit.

  Before describing the preferred embodiment of the present invention, the contents of the study until the inventors have completed the invention will be described.

  FIG. 12 is a circuit diagram of the output unit. FIG. 13 is a circuit diagram of a calibration circuit for calibrating the output unit shown in FIG. 12 as an example.

  The output unit shown in FIG. 12 has a configuration in which resistance elements r01 and r02 are connected between the data input / output terminal DQ and the pull-up unit PU and pull-down unit PD, respectively. When calibrating an output unit having such a configuration, a calibration circuit shown in FIG. 13 can be considered.

  The calibration circuit shown in FIG. 13 includes a pull-up replica unit RU01 connected to the calibration terminal ZQ, and a pull-up replica unit RU02 and a pull-down replica unit RU03 connected to the node N01. The pull-up replica units RU01 and RU02 have a configuration in which a plurality of P-channel MOS transistors are connected in parallel, and the pull-down replica unit RU03 has a configuration in which a plurality of N-channel MOS transistors are connected in parallel. . Further, resistance elements r03 to r05 are connected in series to the replica units RU01 to RU03, respectively.

  The operation of the calibration circuit shown in FIG. 13 is as follows.

  First, in a state where the pull-up replica unit RU01 is activated, the control circuit CNT1 compares the potential appearing at the calibration terminal ZQ with the reference potential ZQVREF. Thereby, the impedance of the pull-up replica unit RU01 is compared with the impedance of the reference resistor RZQ, and the impedance code RPCODE is updated based on the result. The impedance code RPCODE is supplied to the pull-up replica unit RU01, and thereby, the impedance of the pull-up replica unit RU01 is controlled to substantially match the impedance of the reference resistor RZQ. The impedance of the pull-up replica unit RU01 is also reflected in the pull-up replica unit RU02.

  Next, in a state where the pull-up replica unit RU02 and the pull-down replica unit RU03 are activated, the control circuit CNT2 compares the potential appearing at the node N01 with the reference potential ZQVREF. Thereby, the impedance of the pull-up replica unit RU02 and the impedance of the pull-down replica unit RU03 are compared, and the impedance code RNCODE is updated based on the result. The impedance code RNCODE is supplied to the pull-down replica unit RU03, so that the impedance of the pull-down replica unit RU03 is controlled so as to substantially match the impedance of the reference resistor RZQ.

  However, in the output unit shown in FIG. 12, two resistance elements r01 and r02 are connected to the data input / output terminal DQ, and the data input depends on the capacity of the resistance element (formed by wiring or diffusion layer) itself. There was a problem that the terminal capacitance at the output terminal DQ was large. In recent years, it has been required to reduce the terminal capacitance of the data input / output terminal DQ (particularly the DQS terminal), and in order to realize this, the adoption of the output unit shown in FIG. 14 is being studied.

  The output unit shown in FIG. 14 has a configuration in which the resistance element r06 is shared by the pull-up unit PU and the pull-down unit PD. That is, the resistor element r06 is connected between the node N02, which is a connection point between the pull-up unit PU and the pull-down unit PD, and the data input / output terminal DQ. According to this configuration, the terminal capacitance at the data input / output terminal can be reduced in accordance with the reduction of the resistance elements.

  When the output unit having such a configuration is employed, the calibration circuit shown in FIG. 13 has a problem that the circuit configuration and layout are different between the output unit and the calibration circuit.

  That is, when the output unit shown in FIG. 14 is laid out on the semiconductor substrate, the pull-up unit PU, the pull-down unit PD, and the resistance element r06 are laid out in a line with respect to the data input / output terminal DQ as shown in FIG. However, since the pull-down replica unit is not connected to the calibration terminal ZQ, the calibration circuit shown in FIG. 13 cannot take the same circuit configuration as the output unit. For this reason, a calibration error occurs due to a difference in circuit configuration and a difference in layout.

  The first to fourth embodiments to be described below solve the above-described problems, and even when the resistance element is shared by the pull-up unit PU and the pull-down unit PD, the calibration operation is performed with high accuracy. A semiconductor device capable of performing the above is provided.

  The general output unit also has a third problem that occurs when the output unit has an ODT (On Die Termination) function. This is related to the second and third embodiments. To explain.

  FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to an embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DDR4 (Double Data Rate 4) type DRAM integrated on a single semiconductor chip, and is mounted on the external substrate 2. The external substrate 2 is a memory module substrate or a motherboard, and is provided with a reference resistor RZQ. The reference resistor RZQ is connected to the calibration terminal ZQ of the semiconductor device 10, and its impedance is used as a reference impedance of the calibration circuit 100. In the present embodiment, the ground potential VSS is supplied to the reference resistor RZQ.

  As shown in FIG. 1, the semiconductor device 10 has a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, / BL, and has a configuration in which memory cells MC are arranged at intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13.

  The paired bit lines BL and / BL are connected to a sense amplifier SAMP provided in the memory cell array 11. The sense amplifier SAMP amplifies the potential difference generated between the bit lines BL and / BL and supplies the read data obtained thereby to the complementary local IO lines LIOT / LIOB. Read data supplied to the local IO lines LIOT / LIOB is transferred to the complementary main IO lines MIOT / MIOB via the switch circuit TG. The read data on the main IO line MIOT / MIOB is converted into a single-ended signal by the main amplifier MAMP and is supplied to the data input / output circuit 50 via the read / write bus RWBS.

  Further, the semiconductor device 10 is provided with an address terminal 21, a command terminal 22, a clock terminal 23, power supply terminals 24 and 25, a data input / output terminal DQ, and a calibration terminal ZQ as external terminals.

  The address terminal 21 is a terminal to which an address signal ADD is input from the outside. The address signal ADD input to the address terminal 21 is supplied to the address control circuit 32 via the address input circuit 31. Of the address signal ADD supplied to the address control circuit 32, the row address XADD is supplied to the row decoder 12, the column address YADD is supplied to the column decoder 13, and the mode signal MADD is supplied to the mode register 14. .

  The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set. Mode signals output from the mode register 14 include impedance selection signals RonA, RonB, and ODTA to ODTC, which are supplied to the data input / output circuit 50. Here, the impedance selection signals RonA and RonB are signals for selecting the output impedance during the read operation, and the impedance selection signals ODTA to ODTC are signals for selecting the termination impedance during the ODT operation.

  The command terminal 22 is a terminal to which a command signal COM is input from the outside. The command signal COM input to the command terminal 22 is supplied to the command decoding circuit 34 via the command input circuit 33. Of the command signal COM, the clock enable signal CKE is also supplied to the internal clock generation circuit 36. The command decode circuit 34 is a circuit that generates various internal commands by decoding the command signal COM. The internal commands include an active signal ACT, a read signal READ, a write signal WRITE, a mode register set signal MRS, a calibration signal ZQC, and the like.

  The active signal ACT is a signal that is activated when the command signal COM indicates a row access (active command). When the active signal ACT is activated, the row address XADD latched in the address control circuit 32 is supplied to the row decoder 12. As a result, the word line WL specified by the row address XADD is selected.

  The read signal READ and the write signal WRITE are signals that are activated when the command signal COM indicates a read command and a write command, respectively. When the read signal READ or the write signal WRITE is activated, the column address YADD latched in the address control circuit 32 is supplied to the column decoder 13. As a result, the bit line BL designated by the column address YADD is selected.

  Therefore, when an active command and a read command are input and a row address XADD and a column address YADD are input in synchronization with these, read data is read from the memory cell MC specified by the row address XADD and the column address YADD. . The read data is output to the outside from the data input / output terminal DQ via the main amplifier MAMP and the data input / output circuit 50.

  On the other hand, when an active command and a write command are input, a row address XADD and a column address YADD are input in synchronization with them, and then write data is input to the data input / output terminal DQ, the write data is stored in the data input / output circuit. 50 and the main amplifier MAMP are supplied to the memory cell array 11 and are written in the memory cells MC specified by the row address XADD and the column address YADD.

  The mode register set signal MRS is a signal that is activated when the command signal COM indicates a mode register set command. Therefore, if the mode register set command is input and the mode signal MADD is input from the address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.

  The calibration signal ZQC is a signal that is activated when the command signal COM indicates a calibration command. When the calibration signal ZQC is activated, the calibration circuit 100 performs a calibration operation, thereby generating an impedance code ZQCODE.

  Here, returning to the description of the external terminals provided in the semiconductor device 10, the external clock signals CK and / CK are input to the clock terminal 23. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 35. Clock input circuit 35 receives external clock signals CK and / CK and generates internal clock signal PCLK. The internal clock signal PCLK is supplied to the internal clock generation circuit 36 activated by the clock enable signal CKE, thereby generating the phase-controlled internal clock signal LCLK. Although not particularly limited, a DLL circuit can be used as the internal clock generation circuit 36. The internal clock signal LCLK is supplied to the data input / output circuit 50 and used as a timing signal for determining the output timing of read data.

  The internal clock signal PCLK is also supplied to the timing generator 37, thereby generating various internal clock signals ICLK. Various internal clock signals ICLK generated by the timing generator 37 are supplied to circuit blocks such as the address control circuit 32 and the command decode circuit 34, and define the operation timing of these circuit blocks.

  The power supply terminal 24 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 24 are supplied to the internal power supply generation circuit 38. The internal power supply generation circuit 38 generates various internal potentials VPP, VOD, VARY, VPERI and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is a potential mainly used in the row decoder 12, the internal potentials VOD and VARY are potentials used in the sense amplifier SAMP in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. The potential used. On the other hand, the reference potential ZQVREF is a reference potential used in the calibration circuit 100.

  The power supply terminal 25 is a terminal to which power supply potentials VDDQ and VSSQ are supplied. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal 25 are supplied to the data input / output circuit 50. The power supply potentials VDDQ and VSSQ are the same as the power supply potentials VDD and VSS supplied to the power supply terminal 24 respectively, but the data input / output circuit prevents the power supply noise generated by the data input / output circuit 50 from propagating to other circuit blocks. For 50, dedicated power supply potentials VDDQ and VSSQ are used.

  The calibration terminal ZQ is connected to the calibration circuit 100. When the calibration circuit 100 is activated by the calibration signal ZQC, the calibration circuit 100 performs a calibration operation with reference to the impedance of the reference resistor RZQ and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the data input / output circuit 50, whereby the impedance of the output unit included in the data input / output circuit 50 is designated.

  FIG. 2 is a circuit diagram showing a part of the data input / output circuit 50.

  As shown in FIG. 2, the data input / output circuit 50 includes a FIFO circuit 51 and a data output circuit 52. The FIFO circuit 51 includes latch circuits LT1 to LT3 that perform parallel-serial conversion on the read data DATAO and DATAE transferred via the read / write bus RWBS in synchronization with the internal clock signal LCLK. As a result, the read data DATAO and DATAE read in parallel via the read / write bus RWBS are serially supplied to the data output circuit 52.

  The data output circuit 52 includes seven output units OB1 to OB7 connected in parallel between the FIFO circuit 51 and the data input / output terminal DQ. These output units OB1 to OB7 have the same circuit configuration, and the impedance of the read data output from the data input / output terminal DQ is switched by selecting the number of output units OB1 to OB7 to be activated. Hereinafter, when there is no need to distinguish between them, the output units OB1 to OB7 may be simply referred to as “output unit OB”. In the present embodiment, seven output units OB1 to OB7 are used, but it goes without saying that the number of output units OB is not limited to this in the present invention.

  In the present embodiment, the seven output units OB1 to OB7 are classified into three groups. The first group is a group composed of four output units OB1 to OB4, and is connected to the FIFO circuit 51 via a common logic circuit 53 and selection circuit 56. The second group is a group composed of two output units OB5 and OB6, and is connected to the FIFO circuit 51 via a logic circuit 54 and a selection circuit 57 common to these units. Further, the third group is a group composed of one output unit OB7, and is connected to the FIFO circuit 51 via the logic circuit 55 and the selection circuit 58.

  The selection circuits 56 to 58 generate enable signals based on the impedance selection signals RonA, RonB, ODTA to ODTC, and thereby select whether to activate the output units OB1 to OB7 included in the group. Here, the impedance selection signals RonA and RonB are signals for selecting an output impedance in the read operation, and the impedance selection signals ODTA to ODTC are signals for selecting a termination impedance in the ODT operation.

  In this embodiment, impedance selection signals RonA and RonB are supplied to selection circuits 57 and 58, respectively, and impedance selection signals ODTA to ODTC are supplied to selection circuits 56 to 58, respectively. The selection circuit 56 does not receive an impedance selection signal corresponding to the read operation. Therefore, the output units OB1 to OB4 are always activated during the read operation.

  The impedance of each output unit OB is designed to be 240Ω, for example. Therefore, if all the output units OB1 to OB7 are activated by setting the impedance selection signals RonA and RonB to the active level, the impedance of the read data becomes 34.3Ω (= 240Ω / 7). Further, if only the impedance selection signal RonA is activated to activate the six output units OB1 to OB6, the impedance of the read data becomes 40Ω (= 240Ω / 6). Furthermore, if only the impedance selection signal RonB is activated and the five output units OB1 to OB4 and OB7 are activated, the impedance of the read data becomes 48Ω (= 240Ω / 5). If the four output units OB1 to OB4 are activated by setting both the impedance selection signals RonA and RonB to the inactive level, the impedance of the read data becomes 60Ω (= 240Ω / 4).

  Such impedance selection can be similarly performed using the impedance selection signals ODTA to ODTC even during the ODT operation.

  However, the impedance of the output unit OB is not necessarily 240Ω as designed due to the influence of process variations and temperature changes. In order to correct such an impedance shift, the output unit OB uses a pull-up unit PU capable of adjusting impedance and a pull-down unit PD capable of adjusting impedance. The impedance adjustment is performed by the corresponding logic circuits 53 to 55.

  The logic circuits 53 to 55 are supplied with the enable signal EN from the corresponding selection circuits 56 to 58, respectively, and the impedance code ZQCODE generated by the calibration circuit 100 is commonly supplied. Then, the logic circuits 53 to 55 generate enable signals Pen and Nen by performing a logical operation using the enable signal EN and the impedance code ZQCODE as input signals, and supply these to the output unit OB. Thereby, the impedance of the output unit OB is adjusted to a desired value (240Ω).

  The impedance code ZQCODE includes an impedance code RPCODE for adjusting the impedance of the pull-down unit PD and an impedance code RNCODE for adjusting the impedance of the pull-down unit PD. In the present embodiment, the impedance codes RPCODE and RNCODE are both n + 1 bit signals.

  FIG. 3 is a circuit diagram of the output unit OB according to the first embodiment.

  As shown in FIG. 3, the output unit OB according to the first embodiment includes a pull-up unit PU connected between a wiring supplied with the power supply potential VDDQ and the node N1, and a wiring supplied with the power supply potential VSSQ. And a node N1 and a resistance element r1 connected between the node N1 and the data input / output terminal DQ. The resistance element r1 is not a parasitic resistance that inevitably exists between the node N1 and the data input / output terminal DQ, but a resistor using a high resistance material such as tungsten or a diffusion layer. Therefore, the area occupied by the resistance element r1 on the chip increases in proportion to the resistance value. In the present embodiment, the resistance value of the resistance element r1 is 120Ω.

  The pull-up unit PU is composed of a plurality of P-channel MOS transistors RPT0 to RPTn connected in parallel. The gate electrodes of the transistors RPT0 to RPTn correspond to the enable signals Pen supplied from the corresponding logic circuits 53 to 55, respectively. The bit to be input is input. As a result, during the pull-up operation, any of the transistors RPT0 to RPTn can be turned on based on the impedance code RPCODE, thereby setting the output impedance when outputting high level read data to a predetermined value, for example, 120Ω. Can be adjusted. The output impedance when outputting high level read data is defined by the combined impedance of the pull-up unit PU and the resistance element r1.

  The pull-down unit PD is composed of a plurality of N-channel type MOS transistors RNT0 to RNTn connected in parallel. The gate electrodes of the transistors RNT0 to RNTn correspond to the enable signals Nen supplied from the corresponding logic circuits 53 to 55, respectively. A bit is input. As a result, in the pull-down operation, any transistor RNT0 to RNTn can be turned on based on the impedance code RNCODE, thereby adjusting the output impedance when outputting low level read data to a predetermined value, for example, 120Ω. can do. The output impedance when outputting low level read data is defined by the combined impedance of the pull-down unit PD and the resistance element r1.

  Thus, in the output unit OB according to the first embodiment, the resistance element r1 is shared by the pull-up unit PU and the pull-down unit PD. In the pull-up operation, the data input / output terminal DQ is driven by 240Ω, which is the combined impedance of the pull-up unit PU and the resistance element r1, and in the pull-down operation, the combined impedance of the pull-down unit PD and the resistance element r1. The data input / output terminal DQ is driven with a certain 240Ω.

  With this configuration, since the resistor connected to the data input / output terminal DQ is only the resistance element r1 having an impedance of 120Ω, the terminal capacitance added to the data input / output terminal DQ is compared with the configuration of FIG. Can be small.

  However, if the resistance element r1 is shared by the pull-up unit PU and the pull-down unit PD, as described above, a problem in accuracy occurs when a general calibration circuit is used. The calibration circuit 100 described next solves such a problem, and can perform a calibration operation with high accuracy.

  FIG. 4 is a circuit diagram of the calibration circuit 100 used in the first embodiment.

  In addition to the pull-up replica units RU3 and RU7 controlled by the impedance code RPCODE and the pull-down replica unit RU6 controlled by the impedance code RNCODE, the calibration circuit 100 shown in FIG. It is characterized in that it has RU4, RU8 and a pull-up replica unit RU5 fixed in an inactive state.

  More specifically, the calibration circuit 100 includes a pull-up replica unit RU3 connected between a wiring supplied with the power supply potential VDDQ and the node N2, a wiring supplied with the power supply potential VSSQ, and a node N2. And a resistance element r2 connected between the node N2 and the calibration terminal ZQ. The resistance element r2 has the same impedance as the resistance element r1 included in the output unit OB.

  Here, the pull-up replica unit RU3 has the same circuit configuration as the pull-up unit PU included in the output unit OB, and the impedance is controlled by the impedance code RPCODE. On the other hand, the pull-down replica unit RU4 has the same circuit configuration as the pull-down unit PD included in the output unit OB, but is fixed in an inactive state. Specifically, the gate electrodes of a plurality of N-channel MOS transistors constituting pull-down replica unit RU4 are fixed to ground potential VSSQ.

  With this configuration, the replica block 101 including the pull-up replica unit RU3, the pull-down replica unit RU4, and the resistance element r2 accurately reproduces the circuit configuration of the output unit OB during the pull-up operation.

  The calibration circuit 100 is connected between the node supplied with the power supply potential VDDQ and the node N5 and the pull-up replica unit RU7 connected between the node N5 and the wire supplied with the power supply potential VSSQ. A pull-down replica unit RU8, and a resistance element r4 connected between the node N5 and the node N4. On the other hand, no resistive element is provided between the pull-up replica unit RU7 and the node N5 and between the pull-down replica unit RU8 and the node N5. The resistance element r4 also has the same impedance as that of the resistance element r1 included in the output unit OB.

  Here, the pull-up replica unit RU7 has the same circuit configuration as the pull-up unit PU included in the output unit OB, and the impedance is controlled by the impedance code RPCODE. On the other hand, the pull-down replica unit RU8 has the same circuit configuration as the pull-down unit PD included in the output unit OB, but is fixed in an inactive state. Specifically, the gate electrodes of a plurality of N-channel type MOS transistors constituting the pull-down replica unit RU8 are fixed to the ground potential VSSQ.

  With this configuration, the circuit configuration of the output unit OB during the pull-up operation is accurately reproduced for the replica block 102 including the pull-up replica unit RU7, the pull-down replica unit RU8, and the resistance element r4.

  Further, the calibration circuit 100 is connected between the wiring supplied with the power supply potential VDDQ and the node N3, and between the wiring supplied with the power supply potential VSSQ and the node N3. A pull-down replica unit RU6, and a resistance element r3 connected between the node N3 and the node N4. Similarly, no resistive element is provided between each of pull-up replica unit RU5 and node N3, and pull-down replica unit RU6 and node N3. The resistance element r3 also has the same impedance as the resistance element r1 included in the output unit OB.

  Here, the pull-down replica unit RU6 has the same circuit configuration as the pull-down unit PD included in the output unit OB, and the impedance is controlled by the impedance code RNCODE. On the other hand, the pull-up replica unit RU5 has the same circuit configuration as the pull-up unit PU included in the output unit OB, but is fixed in an inactive state. Specifically, the gate electrodes of a plurality of P-channel MOS transistors constituting the pull-up replica unit RU5 are fixed to the power supply potential VDDQ.

  With this configuration, the replica block 103 including the pull-up replica unit RU5, the pull-down replica unit RU6, and the resistance element r3 accurately reproduces the circuit configuration of the output unit OB during the pull-down operation.

  Here, the potential of the calibration terminal ZQ is compared with the reference potential ZQVREF by the control circuit 111 in a state where the pull-up replica unit RU3 is activated. In the present embodiment, the level of the reference potential ZQVREF is VDDQ / 2.

  When the potential at the calibration terminal ZQ is higher than the reference potential ZQVREF, the control circuit 111 increases the impedance of the pull-up replica unit RU3 (RU7) by updating the impedance code RPCODE. Conversely, when the potential of the calibration terminal ZQ is lower than the reference potential ZQVREF, the control circuit 111 reduces the impedance of the pull-up replica unit RU3 (RU7) by updating the impedance code RPCODE. Therefore, if such an operation is repeated, the potential of the calibration terminal ZQ substantially coincides with the reference potential ZQVREF. This state is obtained when the combined impedance of the pull-up replica unit RU3 (RU7) and the resistance element r2 substantially matches the impedance of the reference resistor RZQ.

  Further, the potential of the node N4 is compared with the reference potential ZQVREF by the control circuit 112 in a state where the pull-up replica unit RU7 and the pull-down replica unit RU6 are activated.

  When the potential of the node N4 is higher than the reference potential ZQVREF, the control circuit 112 reduces the impedance of the pull-down replica unit RU6 by updating the impedance code RNCODE. Conversely, when the potential of the node N4 is lower than the reference potential ZQVREF, the control circuit 112 increases the impedance of the pull-down replica unit RU6 by updating the impedance code RNCODE. Therefore, if such an operation is repeated, the potential of the node N4 substantially matches the reference potential ZQVREF. This state is obtained when the combined impedance of the pull-down replica unit RU6 and the resistance element r3 substantially matches the combined impedance of the pull-up replica unit RU7 and the resistance element r4, that is, the impedance of the reference resistance RZQ.

  Therefore, first, the pull-up replica unit RU3 is calibrated using the control circuit 111, and the impedance code RPCODE obtained thereby is reflected in the pull-up replica unit RU7. When the RU6 is calibrated, the impedance code RNCODE can be obtained. Since the impedance codes RPCODE and RNCODE obtained in this way are supplied to the logic circuits 53 to 55 included in the data input / output circuit 50, the impedance of each output unit OB1 to OB7 is adjusted to a desired value, that is, 240Ω. can do.

  As described above, in the first embodiment, the replica units RU4, RU8, and RU5 that are inactive are provided in the replica blocks 101 to 103, respectively, and the circuit configuration of the output unit OB is accurately reproduced. . Here, the inactive state refers to a state in which each transistor provided in the replica unit is turned off. For example, VDDQ is supplied to the gate electrode of the P-channel transistor, and VSSQ is supplied to the gate electrode of the N-channel transistor. As a result, an accurate calibration operation can be performed.

  In addition, since the impedance code RNCODE is generated by using both the replica block 102 that performs the pull-up operation and the replica block 103 that performs the pull-down operation, the resistance element r1 is shared in the output unit OB. Nevertheless, the calibration operation can be performed in a state where this is correctly reproduced.

  Note that the output unit OB according to the first embodiment shown in FIG. 3 can perform not only a read operation but also an ODT operation. For example, when the termination level is VDDQ / 2 level, both the pull-up unit PU and the pull-down unit PD may be activated during the ODT operation. Further, when the termination level is the VDDQ level, the pull-up unit PU may be activated during the ODT operation.

  However, since the characteristics required for the output unit OB are different between the read operation and the ODT operation, the same pull-up unit PU or pull-down is used in the read operation and the ODT operation as in the output unit OB shown in FIG. It may not be appropriate to use the unit PD. In such a case, it is preferable to use the output unit OB according to the second or third embodiment described below.

  Before describing the second and third embodiments, characteristics required for the output unit OB during the read operation and the ODT operation will be described.

  FIG. 5 is a graph showing the current-voltage characteristics of the output unit OB.

  Symbols A to C shown in FIG. 5 indicate current-voltage characteristics when the impedance of the pull-up unit PU and the pull-down unit PD is lower than the impedance of the resistance element r1, substantially the same, and higher, respectively. Reference symbol R represents current-voltage characteristics when the pull-up unit PU and the pull-down unit PD are regarded as ideal resistance elements.

  Since the pull-up unit PU and the pull-down unit PD are made of MOS transistors, they have current-voltage characteristics different from ideal resistance elements. For this reason, as shown in FIG. 5, the current-voltage characteristic finally obtained differs depending on the magnitude relationship between the impedance of the pull-up unit PU and pull-down unit PD and the impedance of the resistance element r1.

  Here, since a sufficient driving capability is required during the read operation, it is preferable to have the characteristics indicated by the symbol A. On the other hand, at the time of ODT operation, it is preferable to have a characteristic indicated by a symbol B or C so that a signal to be terminated (eg, write data) is not attenuated more than necessary. Therefore, if the same pull-up unit PU or pull-down unit PD is used in the read operation and the ODT operation, it is difficult to satisfy both the current-voltage characteristics required in the read operation and the current-voltage characteristics required in the ODT operation. Become.

  Such a problem can be solved by using different pull-up unit PU or pull-down unit PD for the read operation and the ODT operation. Focusing on this point, the output unit OB according to the second and third embodiments uses the pull-up unit PU dedicated to ODT.

  First, the second embodiment will be described.

  FIG. 6 is a circuit diagram showing a part of the data input / output circuit 50 used in the second embodiment.

  As shown in FIG. 6, in the data input / output circuit 50 used in the second embodiment, the impedance code OPCODE generated by the calibration circuit 100 is further supplied to the logic circuits 53 to 55. The impedance code OPCODE is a code for adjusting the impedance of the termination unit ODTPU included in the output unit OB, and has an n + 1 bit configuration in this embodiment. The logic circuits 53 to 55 supply the enable signal Oen to the corresponding output unit OB during the ODT operation. Since the other circuit configuration is the same as that of the data input / output circuit 50 shown in FIG. 2, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 7 is a circuit diagram of the output unit OB according to the second embodiment.

  As shown in FIG. 7, the output unit OB according to the second embodiment includes a termination unit ODTPU connected between a wiring to which a power supply potential VDDQ is supplied and a node N9, a node N9, and a data input / output terminal DQ. The resistor element r5 connected between the two is added. The pull-up unit PU, the pull-down unit PD, and the termination unit ODTPU are activated exclusively with each other. Since other circuit configurations are the same as those of the output unit OB shown in FIG. 3, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The resistance element r5 is not a parasitic resistance that inevitably exists between the node N9 and the data input / output terminal DQ, but is a resistor added using a high resistance material such as tungsten or a diffusion layer. In the present embodiment, the resistance value of the resistance element r1 is 160Ω, and the resistance value of the resistance element r5 is 120Ω.

  The termination unit ODTPU is composed of a plurality of P-channel MOS transistors OPT0 to OPTn connected in parallel. The gate electrodes of the transistors OPT0 to OPTn correspond to the enable signals Oen supplied from the corresponding logic circuits 53 to 55, respectively. A bit is input. Thus, during the ODT operation, any of the transistors OPT0 to OPTn can be turned on based on the impedance code OPCODE, and thereby the termination impedance during the ODT operation can be adjusted to a predetermined value, for example, 120Ω. The termination impedance during the ODT operation is defined by the combined impedance of the termination unit ODTPU and the resistance element r5. The combined impedance in this embodiment is 240Ω, 120Ω is assigned to the termination unit ODTPU, and 120Ω is assigned to the resistance element r5.

  The circuit configurations of the pull-up unit PU and the pull-down unit PD are the same as those shown in FIG. 3, but the impedances when activated are different. Specifically, the pull-up unit PU and the pull-down unit PD are both designed to have an impedance of 80Ω when activated.

  Therefore, in the pull-up operation, 80Ω is assigned to the pull-up unit PU and 160Ω is assigned to the resistance element r1, and as a result, the combined impedance when outputting high level read data is 240Ω. Similarly, in the pull-down operation, 80Ω is assigned to the pull-down unit PD and 160Ω is assigned to the resistance element r1, so that the combined impedance when outputting low level read data is also 240Ω.

  As described above, in the second embodiment, although the combined impedance is 240Ω in both the read operation and the ODT operation, the distribution is different from each other. That is, since the pull-up unit PU or the pull-down unit PD having a low impedance is activated during the read operation, the current-voltage characteristic indicated by the symbol A shown in FIG. 5 can be obtained. On the other hand, since the termination unit ODTPU having a high impedance is activated during the ODT operation, the current-voltage characteristic indicated by the symbol B shown in FIG. 5 can be obtained. As a result, it is possible to ensure favorable current-voltage characteristics during both the read operation and the ODT operation.

  FIG. 8 is a circuit diagram of the calibration circuit 100 used in the second embodiment.

  In the calibration circuit 100 shown in FIG. 8, replica blocks 104 and 105 are added, a termination replica unit RU12 and a resistance element r8 are added to the replica block 101, and a termination replica unit RU13 and a resistance element r9 are added to the replica block 102. Is added to the replica block 103, and a terminal replica unit RU14 and a resistance element r10 are added. Since the other circuit configuration is the same as that of the calibration circuit 100 shown in FIG. 4, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The terminal replica unit RU12 and the resistance element r8 in the replica block 101 are connected in series between the wiring to which the power supply potential VDDQ is supplied and the calibration terminal ZQ. The termination replica unit RU12 has the same circuit configuration as the termination unit ODTPU, but is fixed in an inactive state. Specifically, the gate electrodes of a plurality of P-channel MOS transistors constituting the terminal replica unit RU12 are fixed to the power supply potential VDDQ. The resistance element r8 has the same impedance as that of the resistance element r5 included in the output unit OB.

  With this configuration, the replica block 101 accurately reproduces the circuit configuration of the output unit OB during the pull-up operation.

  The terminal replica unit RU13 and the resistance element r9 in the replica block 102 are connected in series between the wiring to which the power supply potential VDDQ is supplied and the node N4. The termination replica unit RU13 has the same circuit configuration as the termination unit ODTPU, but is fixed in an inactive state. Specifically, the gate electrodes of a plurality of P-channel MOS transistors constituting the terminal replica unit RU13 are fixed to the power supply potential VDDQ. The resistance element r9 has the same impedance as that of the resistance element r5 included in the output unit OB.

  With this configuration, the replica block 102 also accurately reproduces the circuit configuration of the output unit OB during the pull-up operation.

  The terminal replica unit RU14 and the resistance element r10 in the replica block 103 are connected in series between the wiring to which the power supply potential VDDQ is supplied and the node N4. The termination replica unit RU14 has the same circuit configuration as the termination unit ODTPU, but is fixed in an inactive state. Specifically, the gate electrodes of a plurality of P-channel MOS transistors constituting the terminal replica unit RU14 are fixed to the power supply potential VDDQ. Further, the resistance element r10 has the same impedance as the resistance element r5 included in the output unit OB.

  With this configuration, the replica block 103 accurately reproduces the circuit configuration of the output unit OB during the pull-down operation.

  The replica block 104 has the same circuit configuration as the replica block 103. That is, the replica block 104 is connected between the line supplied with the power supply potential VDDQ and the node N8, and between the line supplied with the power supply potential VSSQ and the node N8. Pull-down replica unit RU11, resistance element r7 connected between node N8 and node N6, termination replica unit RU16 and resistance element connected in series between a line supplied with power supply potential VDDQ and node N6 r11. The resistance element r7 has the same impedance as the resistance element r1 included in the output unit OB, and the resistance element r11 has the same impedance as the resistance element r5 included in the output unit OB.

  With this configuration, the replica block 104 accurately reproduces the circuit configuration of the output unit OB during the pull-down operation.

  The replica block 105 includes a pull-up replica unit RU17 connected between the wiring supplied with the power supply potential VDDQ and the node N7, and a pull-down replica connected between the wiring supplied with the power supply potential VSSQ and the node N7. A unit RU18, a resistance element r6 connected between the node N7 and the node N6, a terminal replica unit RU10 and a resistance element r12 connected in series between the wiring supplied with the power supply potential VDDQ and the node N6. I have. The resistance element r6 has the same impedance as the resistance element r1 included in the output unit OB, and the resistance element r12 has the same impedance as the resistance element r5 included in the output unit OB.

  In the replica block 105, the pull-up replica unit RU17 and the pull-down replica unit RU18 are both fixed in an inactive state, while the impedance of the terminal replica unit RU10 is controlled by the impedance code OPCODE.

  With this configuration, the replica block 105 accurately reproduces the circuit configuration of the output unit OB during the ODT operation.

  Here, the potential of the node N6 is compared with the reference potential ZQVREF by the control circuit 113 in a state where the terminal replica unit RU10 and the pull-down replica unit RU11 are activated. When the potential of the node N6 is higher than the reference potential ZQVREF, the control circuit 113 increases the impedance of the termination replica unit RU10 by updating the impedance code OPCODE. Conversely, when the potential of the node N6 is lower than the reference potential ZQVREF, the control circuit 113 reduces the impedance of the terminal replica unit RU10 by updating the impedance code OPCODE. Therefore, if such an operation is repeated, the potential of the node N6 substantially matches the reference potential ZQVREF. This state is obtained when the combined impedance of the termination replica unit RU10 and the resistance element r12 substantially matches the combined impedance of the pull-down replica unit RU11 and the resistance element r7, that is, the impedance of the reference resistance RZQ.

  Therefore, first, the pull-up replica unit RU3 is calibrated using the control circuit 111, and the impedance code RPCODE obtained thereby is reflected in the pull-up replica unit RU7. Next, the pull-down replica unit RU6 is calibrated using the control circuit 112 to obtain the impedance code RNCODE. Further, in a state where the impedance code RNCODE is reflected in the pull-down replica unit RU11, the terminal replica unit RU10 is calibrated using the control circuit 113 to obtain the impedance code OPCODE. The impedance codes RPCODE, RNCODE, and OPCODE thus obtained are supplied to the logic circuits 53 to 55 included in the data input / output circuit 50. Thereby, the impedance at the time of read operation and ODT operation of each output unit OB1 to OB7 can be adjusted to a desired value, that is, 240Ω.

  Thus, in the second embodiment, since each output unit OB1 to OB7 includes the termination unit ODTPU, in addition to the effect of the first embodiment, both in the read operation and the ODT operation, Desired current-voltage characteristics can be obtained.

  In addition, since the impedance codes RPCODE, RNCODE, and OPCODE are generated using the replica blocks 101 to 105 that reproduce the output unit OB, an accurate calibration operation can be performed.

  Next, a third embodiment of the present invention will be described.

  FIG. 9 is a circuit diagram of an output unit OB according to the third embodiment.

  As shown in FIG. 9, the output unit OB according to the third embodiment is different from the output unit OB shown in FIG. 7 in that the resistance element r5 is connected in series to the resistance element r1. . That is, in the present embodiment, the termination unit ODTPU is connected to the connection point between the resistance element r1 and the resistance element r5. Since the other circuit configuration is the same as that of the output unit OB shown in FIG.

  In the present embodiment, the resistance value of the resistance element r1 is 40Ω, and the resistance value of the resistance element r5 is 120Ω. That is, since the resistance element r1 having a lower resistance value is used, not only can the occupied area on the chip be reduced, but also the terminal capacitance added to the data input / output terminal DQ can be reduced. It becomes.

  The circuit configurations of the pull-up unit PU and the pull-down unit PD are the same as the circuit configuration shown in FIG. Thereby, when the pull-up unit PU or the pull-down unit PD is activated, the combined impedance becomes 240Ω (= 80Ω + 40Ω + 120Ω). The circuit configuration of the termination unit ODTPU is the same as the circuit configuration shown in FIG. 7, and is designed so that the impedance at the time of activation is 120Ω. Thereby, when the termination unit ODTPU is activated, the combined impedance becomes 240Ω (= 120Ω + 120Ω).

  FIG. 10 is a circuit diagram of the calibration circuit 100 used in the third embodiment. The calibration circuit 100 shown in FIG. 10 is the same as the calibration circuit 100 shown in FIG. 8 except that the connection positions of the resistance elements r8 to r12 are changed according to the output unit OB. Therefore, the overlapping description is omitted.

  As described above, in the third embodiment, the resistance elements r1 and r5 are connected in series as viewed from the pull-up unit PU and the pull-down unit PD. Can be used. Thereby, in addition to the effects of the first and second embodiments, the occupied area on the chip can be reduced, and the terminal capacitance of the data input / output terminal DQ can be reduced.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 11 is a circuit diagram of the calibration circuit 100 according to the fourth embodiment.

  The calibration circuit 100 according to the present embodiment is used when the center level of read data is 4/5 × VDDQ, and four replica blocks 101, 102, and 105 shown in FIG. 11 are connected in parallel. In addition, the second embodiment is different from the second and third embodiments in that the reference potential ZQVREF is at 4/5 × VDDQ level. A calibration operation using such a calibration circuit 100 is performed as follows.

  First, the control circuit 111 is used to calibrate the pull-up replica unit RU3 included in each of the four replica blocks 101. In this case, since the four pull-up replica units RU3 are connected in parallel, the impedance code RPCODE is generated so that the potential of the calibration terminal ZQ substantially matches the reference potential ZQVREF (4/5 × VDDQ). The

  Next, with the impedance code RPCODE reflected in the pull-up replica unit RU7 included in each of the four replica blocks 102, calibration of the pull-down replica unit RU6 included in the replica block 103 is performed using the control circuit 112. Do. Again, since the four pull-up replica units RU7 are connected in parallel, the impedance code RNCODE is generated so that the potential of the node N4 substantially matches the reference potential ZQVREF (= 4/5 × VDDQ). .

  Next, in a state where the impedance code RNCODE is reflected in the pull-down replica unit RU11 included in the replica block 104, the termination replica unit RU10 included in each of the four replica blocks 105 is calibrated using the control circuit 113. . Again, since the four terminal replica units RU10 are connected in parallel, the impedance code OPCODE is generated so that the potential of the node N6 substantially matches the reference potential ZQVREF (= 4/5 × VDDQ).

  Then, when the obtained impedance codes RPCODE, RNCODE, and OPCODE are supplied into the output unit OB, a read operation centered on the 4/5 × VDDQ level can be performed.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2 External substrate 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 21 Address terminal 22 Command terminal 23 Clock terminal 24, 25 Power supply terminal 31 Address input circuit 32 Address control circuit 33 Command input circuit 34 Command decode circuit 35 Clock Input circuit 36 Internal clock generation circuit 37 Timing generator 38 Internal power generation circuit 50 Data input / output circuit 51 FIFO circuit 52 Data output circuits 53 to 55 Logic circuits 56 to 58 Selection circuit 100 Calibration circuits 101 to 105 Replica blocks 111 to 113 Control Circuit BL, / BL Bit line CNT1, CNT2 Control circuit DQ Data input / output terminal LIOT / LIOB Local IO lines LT1-LT3 Latch circuit MAMP Main MC memory cell MIOT / MIOB main IO lines N01, N02, N1-N9 nodes OB1-OB7 output unit ODTPU termination unit OPT0-OPTn transistor PD pull-down unit PU pull-up unit RNT0-RNTn transistor RPT0-RPTn transistors RU01, RU02, RU3 , RU5, RU7, RU15, RU17 Pull-up replica unit RU03, RU4, RU6, RU8, R11, RU18 Pull-down replica unit RU10, RU12 to RU14, RU16 Termination replica unit RWBS Read / write bus RZQ Reference resistor SAMP Sense amplifier TG Switch circuit WL Word line ZQ calibration terminals r01-r06, r1-r12 resistance elements

Claims (16)

First and second external terminals;
A first node, a first resistance element connected between the first node and the first external terminal, and a first conductivity type transistor connected to the first node, according to a first code An output unit comprising: a first unit whose impedance is controlled; and a second unit including a second conductivity type transistor connected to the first node;
A first resistance type transistor connected to the second node; a second resistance element connected between the second node and the second external terminal; and the first conductivity type transistor connected to the second node; A third unit whose impedance is controlled in accordance with the second unit, a fourth unit including the second conductivity type transistor connected to the second node and made non-conductive, and a potential of the second external terminal And a calibration circuit having a first control circuit for generating the first code. The impedance of the second unit is controlled according to the second cord,
The calibration circuit includes third and fourth nodes, a third resistance element connected between the third node and the fourth node, and the non-conductive state connected to the third node. A fifth unit including a transistor of one conductivity type, a sixth unit including a transistor of the second conductivity type connected to the third node, the impedance of which is controlled according to the second code, and the fourth unit The semiconductor device according to claim 1, further comprising a second control circuit that generates the second code in accordance with a potential of a node.   The calibration circuit includes a fifth node, a fourth resistance element connected between the fourth node and the fifth node, and a transistor of the first conductivity type connected to the fifth node, And a seventh unit whose impedance is controlled according to the first code, and an eighth unit including the second conductivity type transistor connected to the fifth node and made non-conductive. The semiconductor device according to claim 2.   4. The semiconductor device according to claim 3, wherein the second control circuit generates the second code by referring to a potential of the fourth node in a state where the first code is fixed. 5.   The output unit further includes a ninth unit including the first conductivity type transistor connected to the first external terminal, the impedance of which is controlled according to a third code. The semiconductor device as described in any one of thru | or 4.   6. The semiconductor device according to claim 5, wherein the first, second and ninth units are activated exclusively.   7. The semiconductor device according to claim 6, wherein the first or second unit is activated during a read operation, and the ninth unit is activated during an ODT operation.   8. The semiconductor device according to claim 5, wherein an impedance of the ninth unit is different from impedances of the first and second units. 9.   9. The semiconductor device according to claim 8, wherein the impedance of the ninth unit is higher than the impedance of the first and second units.   The semiconductor device according to claim 5, wherein the output unit further includes a fifth resistance element connected between the ninth unit and the first external terminal.   The semiconductor device according to claim 10, wherein the ninth unit is connected to a connection point between the first resistance element and the fifth resistance element.   12. The semiconductor according to claim 11, wherein a combined impedance of the ninth unit and the fifth resistor element is equal to a combined impedance of the first or second unit and the first and fifth resistor elements. apparatus.   The semiconductor device according to claim 11, wherein a reference resistor equal to the combined impedance is connected to the second external terminal.   The calibration circuit includes sixth to eighth nodes, a sixth resistance element connected between the sixth node and the seventh node, and a sixth resistor connected between the sixth node and the eighth node. A tenth unit including a first resistance type transistor connected to the sixth node, the impedance of which is controlled according to the third code, and the eighth node connected to the eighth node. An eleventh unit including a transistor of a second conductivity type, the impedance of which is controlled according to the second code; and a third control circuit that generates the third code according to the potential of the sixth node. The semiconductor device according to claim 5, wherein the semiconductor device is a semiconductor device.   15. The calibration circuit according to claim 5, further comprising a twelfth unit including the first conductivity type transistor connected to the second external terminal and made non-conductive. The semiconductor device according to item.   The semiconductor device according to claim 1, wherein a plurality of the third units are connected in parallel.

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