JP2015153760A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing on-resistance of a vertical MOSFET or a vertical IGBT having electrodes on the same surface.SOLUTION: A semiconductor device comprises: a semiconductor substrate having a first semiconductor layer on a first surface, a second semiconductor layer of a first conductivity type on a second surface, and a third semiconductor layer of the first conductivity type and a fourth semiconductor layer of a second conductivity type between the first semiconductor layer and the second semiconductor layer; a gate layer provided while interposing an insulating film between itself and the fourth semiconductor layer; a second surface side first electrode conductive with the first semiconductor layer and having a first wide region and a first linear region with a narrow width; a second electrode conductive to the second semiconductor layer, having a second wide region, and provided on the same plane as the first electrode; and a gate electrode conductive to the gate layer, having a third wide region and a second linear region with a narrow width, and provided on the same plane as the first electrode. The first linear region and the second linear region are adjacent to each other in parallel, and sandwiched by two wide regions.

Description

  Embodiments described herein relate generally to a semiconductor device.

  In recent years, a semiconductor package technique called a wafer level chip size package (WL-CSP) has attracted attention. In the WL-CSP, the size of the finally cut semiconductor chip becomes the size of the package as it is. Therefore, this is an ideal technique from the viewpoint of reducing the size and weight of the semiconductor package.

  When a vertical MOSFET (Metal Oxide Field Effect Transistor Transistor) or IGBT (Insulated Gate Bipolar) is used as a BGA (Ball Grid Array) or LGA (Land Grid Array) chip in the WL-SP side. It is necessary to form a drain electrode and a collector electrode for applying a potential to the drain layer and collector layer to be formed on the surface side of the semiconductor chip. For this reason, a drain layer or collector layer lead-out structure is provided in the semiconductor chip. In this case, the resistance of the drain layer or the contact layer becomes a parasitic resistance, which may increase the on-resistance of the MOSFET or IGBT.

  In addition, although not limited to the BGA or LGA structure, for example, when the MOSFET or IGBT has a trench gate structure, if the trench length is increased, the resistance of the gate layer in the trench may be increased and the switching characteristics may be deteriorated.

JP 2002-353252 A

  The problem to be solved by the present invention is to provide a semiconductor device capable of reducing the on-resistance of a vertical MOSFET or a vertical IGBT having electrodes on the same surface.

  The semiconductor device of the embodiment has a first surface and a second surface opposite to the first surface, the first surface has a first semiconductor layer, and the second surface has A first conductivity type second semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, wherein the impurity concentration of the first conductivity type is higher than that of the first semiconductor layer; A semiconductor substrate having a low first conductivity type third semiconductor layer, and a second conductivity type fourth semiconductor layer provided between the third semiconductor layer and the second semiconductor layer; A gate layer provided between the fourth semiconductor layer and an insulating film; and provided on the second surface side of the semiconductor substrate and electrically connected to the first semiconductor layer; A wide region, a first electrode having a first linear region that is narrower than the first wide region and extends from the first wide region, and A second electrode provided on the same plane as the first electrode on the second surface side of the conductive substrate, electrically conducting to the second semiconductor layer, and having a second wide region; and the semiconductor Provided in the same plane as the first electrode on the second surface side of the substrate, electrically conducting to the gate layer, a third wide region, and a width narrower than the third wide region, A gate electrode having a second linear region extending from the third wide region, wherein the first linear region and the second linear region are adjacent in parallel, and the first line And the second linear region are sandwiched between two wide regions selected from the first wide region, the second wide region, and the third wide region.

1 is a schematic top view of a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view of an element region of a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The schematic top view of the semiconductor device of a comparison form. The schematic cross section of the element area | region of the semiconductor device of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are denoted by the same reference numerals, and the description of the members and the like once described is omitted as appropriate. In the following embodiment, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

In the present specification, the notation of n ⁺ type, n type, and n ⁻ type means that the n-type impurity concentration decreases in this order. Similarly, the notation of p ⁺ type, p type, and p ⁻ type means that the p-type impurity concentration decreases in this order.

  The n-type impurity is, for example, phosphorus (P) or arsenic (As). The p-type impurity is, for example, boron (B).

(First embodiment)
The semiconductor device of the present embodiment has a first surface and a second surface opposite to the first surface, has a first semiconductor layer on the first surface, and has a first surface on the second surface. A first conductivity type having a second semiconductor layer of conductivity type, provided between the first semiconductor layer and the second semiconductor layer, and having a lower impurity concentration of the first conductivity type than the first semiconductor layer A semiconductor substrate having a third semiconductor layer, a fourth semiconductor layer of a second conductivity type provided between the third semiconductor layer and the second semiconductor layer, and a fourth semiconductor layer A gate layer provided with an insulating film interposed therebetween, and provided on the second surface side of the semiconductor substrate, and is electrically connected to the first semiconductor layer; from the first wide region and the first wide region; The first electrode having a first linear region extending from the first wide region and the first electrode on the second surface side of the semiconductor substrate are provided on the same plane as the first electrode. The second electrode having a second wide region and the first electrode on the second surface side of the semiconductor substrate are provided in the same plane and are electrically connected to the gate layer. And a third wide region and a gate electrode having a second linear region that is narrower than the third wide region and extends from the third wide region. The first linear region and the second linear region are adjacent in parallel, and the first linear region and the second linear region are the first wide region, the second wide region, and the third wide region. It is sandwiched between two wide regions selected from the region.

  FIG. 1 is a schematic top view of the semiconductor device of this embodiment. FIG. 1A is a diagram showing the arrangement of electrodes. FIG. 1B is a diagram showing the arrangement of the element region and the lead region to the electrode. FIG. 2 is a schematic cross-sectional view of an element region of the semiconductor device of this embodiment.

  The semiconductor device of this embodiment is a vertical MOSFET in which a source layer and a drain layer are provided with a semiconductor substrate interposed therebetween. The semiconductor device of this embodiment is a trench gate type MOSFET in which a gate electrode is provided in a trench. The semiconductor device of this embodiment is a WL-CSP having a BGA structure.

  As shown in FIG. 2, the semiconductor device (MOSFET) of this embodiment includes a semiconductor substrate 100 having a first surface and a second surface. The semiconductor substrate 100 is, for example, single crystal silicon.

An n ⁺ -type drain layer (first semiconductor layer) 10 is provided on the first surface of the semiconductor substrate 100. An n ⁺ type source layer (second semiconductor layer) 12 is provided on the second surface.

Further, in the semiconductor substrate 100, an n ⁻ type drift layer (third semiconductor layer) 14 in contact with the n ⁺ type drain layer 10 is provided between the n ⁺ type drain layer 10 and the n ⁺ type source layer 12. . The n ⁻ type drift layer 14 has a lower n type impurity concentration than the n ⁺ type drain layer 10. Further, a p-type channel layer (fourth semiconductor layer) 16 is provided between the n ⁻ -type drift layer 14 and the n ⁺ -type source layer 12.

  A trench 18 is formed in the semiconductor substrate 100 on the second surface side. A gate insulating film (insulating film) 20 and a gate layer 22 are provided in the trench 18. The gate layer 22 is provided between the p-type channel layer 16 and the insulating film 20.

  The insulating film 20 is, for example, a silicon thermal oxide film. The gate layer 22 is, for example, polycrystalline silicon doped with n-type impurities.

  As shown in FIG. 1A, the semiconductor device of this embodiment includes a drain electrode (first electrode) 31 and two source electrodes (second electrodes) on the same plane on the second surface side of the semiconductor substrate 100. Electrode) 32 and a gate electrode 33. On the drain electrode (first electrode) 31, the two source electrodes (second electrode) 32, and the gate electrode 33, a total of six solder balls 34 are provided.

  The semiconductor device of this embodiment is a 6-pin type BGA. Moreover, this embodiment is WL-CSP, and the semiconductor substrate 100 is exposed on the first surface side and the side surface.

  The drain electrode 31, the source electrode 32, and the gate electrode 33 are so-called pad electrodes for establishing electrical connection with the outside of the semiconductor device. The drain electrode 31, the source electrode 32, and the gate electrode 33 are made of metal. The metal is, for example, aluminum (Al).

  The drain electrode 31 includes a first wide region 31a and a first linear region 31b that is narrower than the first wide region 31a. The first linear region 31b is a so-called drain finger.

  The two source electrodes 32 include a second wide region 32a.

  The gate electrode 33 includes a third wide region 33a and a second linear region 33b that is narrower than the third wide region. The second linear region 33b is a so-called gate finger.

  FIG. 3 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 3 is a schematic diagram for explanation only, and does not necessarily show a specific cross section.

The drain electrode 31 is electrically connected to the n ⁺ -type drain layer 10 on the first surface side. Specifically, for example, conduction is made through a through electrode (conductive plug) 40 provided through the semiconductor substrate 100. A region where the n ⁺ -type drain layer 10 is electrically extracted to the drain electrode 31 by the through electrode 40 is referred to as a drain extraction region.

The source electrode 32 is electrically connected to the n ⁺ type source layer 12. Specifically, for example, the source electrode 32 is in direct contact with the n ⁺ -type source layer 12.

  The gate electrode 33 is electrically connected to the gate layer 22 in the trench 18. Specifically, the gate electrode 33 and the gate layer 22 are electrically connected to each other through a gate lead layer 36 drawn from the gate layer 22 in the trench 18 at a location not shown. A region where the gate layer 22 is electrically extracted to the gate electrode 33 by the gate extraction layer 36 is referred to as a gate extraction region.

  The drain electrode 31 and the gate electrode 33 are provided on the semiconductor substrate 100 via an interlayer insulating film 44. The drain electrode 31, the source electrode 32, and the gate electrode 33 are covered with, for example, a polyimide protective layer 46, leaving some openings.

  In the present embodiment, as shown in FIG. 1A, the first linear region 31 b and the second linear region 33 b are adjacent to each other in parallel and are sandwiched between the wide regions 32 a of the two source electrodes 32.

  As shown in FIG. 1B, two element regions 50 are provided immediately below the two wide regions 32 a of the source electrode 32. In the element region 50, the plurality of gate layers 22 extend in a direction perpendicular to the first linear region 31b and the second linear region 33b. Since this embodiment has a trench gate structure, the trench extends in a direction perpendicular to the first linear region 31b and the second linear region 33b.

  The gate layer 22 is cut off immediately below the first linear region 31b and the second linear region 33b. In other words, the trench is cut off immediately below the first linear region 31b and the second linear region 33b.

  A gate lead-out region 52 is provided at each end of the two element regions 50. Further, the gate layer 22 is electrically extracted from the gate extraction region 52 between the two element regions 50 to the wide region 33a of the gate electrode 33 through the second linear region 33b.

Further, a drain lead region 54 is formed in a region sandwiched between the gate lead regions 52 between the two element regions 50. The n ⁺ -type drain layer 10 is electrically extracted from the drain extraction region 54 between the two element regions 50 to the wide region 31a of the drain electrode 31 through the first linear region 31b. Further, a drain extraction region 54 is also provided immediately below the wide region 31 a of the drain electrode 31.

  Next, the operation and effect of this embodiment will be described. FIG. 4 is a schematic top view of a semiconductor device of a comparative form. FIG. 4A is a diagram showing the arrangement of electrodes. FIG. 4B is a diagram showing the arrangement of the element region and the lead region to the electrode.

  In the semiconductor device of the comparative form, unlike the present embodiment, the first linear region and the second linear region adjacent in parallel do not exist, and the element region 50 is one large region. For this reason, the element region 50 is cut into pieces. There is no gate extraction region or drain extraction region.

For this reason, for example, in the element at the position indicated by x in FIG. 4B, the length of the path from the element to the drain electrode 33 occupied by the n ⁺ -type drain layer 10 becomes long. Therefore, a large parasitic resistance is inserted between the element and the drain electrode 31. Therefore, the on-resistance of the MOSFET increases.

  In addition, the element at the position indicated by x is present in the vicinity of the center of the element region 50 with respect to the extending direction of the gate layer 22. Therefore, the distance from the element to the gate extraction region 52 is increased, and the resistance of the gate layer 22 is increased. Therefore, switching characteristics are deteriorated.

  In the semiconductor device of this embodiment, as shown in FIGS. 1A and 1B, a first linear region 31b and a second linear region 33b are provided adjacent to each other in parallel. Then, the element region 50 is divided immediately below the first linear region 31b and the second linear region 33b, and a drain extraction region 54 and a gate extraction region 52 region are provided in the divided region.

With this configuration, the distance from the element at the position marked with x in FIG. 1B to the drain lead region 54 is reduced, and the parasitic resistance of the n ⁺ -type drain layer 10 is reduced. Therefore, the on-resistance of the MOSFET is reduced.

  Further, the distance from the element at the position of the x mark in FIG. 1B to the gate lead-out region 52 is reduced, and the resistance of the gate layer 22 is reduced. Therefore, deterioration of switching characteristics is suppressed.

  The first linear region 31b and the second linear region 33b are provided adjacent to each other in parallel, and as a result, the drain extraction region 54 and the gate extraction region 52 are provided adjacent to each other, so that the element region 50 is formed. Dead space that cannot be formed can be reduced. When the first linear region 31b and the second linear region 33b are provided separately, the drain extraction region 54 and the gate extraction region 52 region are also provided separately. In this case, a dead space is formed on both sides of each of the drain lead region 54 and the gate lead region 52, and the dead space becomes larger than that in the present embodiment.

  Therefore, according to the present embodiment, the dead space in which the element region 50 cannot be formed is reduced, and the element region 50 can be widened. Therefore, the on-current of the entire MOSFET can be increased.

  As described above, according to the present embodiment, it is possible to realize a vertical MOSFET that includes electrodes on the same surface, reduces on-resistance, improves switching characteristics, and increases on-current.

(Second Embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that the first semiconductor layer is of the second conductivity type, that is, the semiconductor device is not a MOSFET but an IGBT. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 5 is a cross-sectional view of the element region of the semiconductor device of this embodiment.

  The semiconductor device of this embodiment is a vertical IGBT in which an emitter layer and a collector layer are provided with a semiconductor substrate interposed therebetween. Further, the semiconductor device of this embodiment is a trench gate type IGBT in which a gate electrode is provided in a trench. The semiconductor device of this embodiment is a WL-CSP having a BGA structure.

  As shown in FIG. 5, the semiconductor device (IGBT) of the present embodiment includes a semiconductor substrate 200 having a first surface and a second surface. The semiconductor substrate 200 is, for example, single crystal silicon.

An n ⁺ -type collector layer (first semiconductor layer) 60 is provided on the first surface of the semiconductor substrate 200. An n ⁺ -type emitter layer (second semiconductor layer) 62 is provided on the second surface.

Further, in the semiconductor substrate 200, an n ⁻ type drift layer (third semiconductor layer) 14 is provided between the n ⁺ type collector layer 60 and the n ⁺ type emitter layer 62 in contact with the n ⁺ type collector layer. . The n ⁻ type drift layer 14 has a lower n type impurity concentration than the n ⁺ type collector layer 60. Further, a p-type base layer (fourth semiconductor layer) 66 is provided between the n ⁻ -type drift layer 14 and the n ⁺ -type emitter layer 62.

  A trench 18 is formed in the semiconductor substrate 200 on the second surface side. In the trench 18, an insulating film (gate insulating film) 20 and a gate layer 22 are provided. The gate layer 22 is provided between the p-type base layer 66 and the insulating film 20.

  The insulating film 20 is, for example, a silicon thermal oxide film. The gate layer 22 is, for example, polycrystalline silicon doped with n-type impurities.

This embodiment is different from the first embodiment in that the n ⁺ type drain layer 10 is an n ⁺ type collector layer 60, the n ⁺ type source layer 12 is an n ⁺ type emitter layer 62, and the p type channel layer 16 is a p type base. The layer 66 has a configuration in which the drain electrode is read as a collector electrode, the source electrode is read as an emitter electrode, and the drain lead region is read as a collector lead region.

  As described above, according to the present embodiment, it is possible to realize a vertical IGBT having electrodes on the same surface, reduced on-resistance, improved switching characteristics, and increased on-current.

  As described above, in the embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the first conductivity type is p-type and the second conductivity type is n-type. Is also possible.

  In the embodiment, single crystal silicon has been described as an example of the material of the semiconductor substrate and the semiconductor layer, but other semiconductor materials such as silicon carbide and gallium nitride can be applied to the present invention.

  In the embodiments, the trench gate type MOSFET and the IGBT have been described as an example. However, the present invention can be applied to a planar type MOSFET and an IGBT.

  In the embodiment, the case where the first linear region and the second linear region are sandwiched between the wide regions of the two source electrodes has been described as an example. However, the first linear region and the second linear region are described. The wide region sandwiching the region can be any two wide regions selected from the wide region of the drain electrode, the source electrode, and the gate electrode.

  Further, in the embodiment, a 6-pin type BGA WL-CSP has been described as an example of the package. However, if the package structure has three electrodes of a vertical MOSFET or a vertical IGBT on the same plane, It is not limited to the structure. For example, it is possible to apply a package having an LGA structure. A package having more pins than 6 pins may be used.

  Moreover, although the case where the semiconductor substrate is exposed on the first surface side and the side surface has been described as an example, for example, a metal layer for reducing resistance is formed on the first semiconductor layer on the first surface side. It is also possible to provide a configuration. In addition, an insulating layer or the like for protecting the side surface may be provided on the side surface.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 n ⁺ type drain layer (first semiconductor layer)
12 n ⁺ type source layer (second semiconductor layer)
14 n ⁻ type drift layer (third semiconductor layer)
16 p-type channel layer (fourth semiconductor layer)
20 Gate insulating film (insulating film)
22 Gate layer 31 Drain electrode (first electrode)
31a First wide region 31b First linear region 32 Source electrode (second electrode)
32a Second wide region 33 Gate electrode (third electrode)
33a Third wide region 33b Second linear region 100 Semiconductor substrate

Claims (5)

A first surface; a second surface opposite to the first surface; a first semiconductor layer on the first surface; and a first conductivity type second on the second surface. Of the first conductivity type, which is provided between the first semiconductor layer and the second semiconductor layer and has an impurity concentration of the first conductivity type lower than that of the first semiconductor layer. A semiconductor substrate having a third semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided between the third semiconductor layer and the second semiconductor layer,
A gate layer provided through an insulating film between the fourth semiconductor layer;
Provided on the second surface side of the semiconductor substrate, electrically connected to the first semiconductor layer, having a first wide region and a width narrower than the first wide region; A first electrode having a first linear region extending from a wide region;
A second electrode provided in the same plane as the first electrode on the second surface side of the semiconductor substrate, electrically conducting to the second semiconductor layer, and having a second wide region;
The semiconductor substrate is provided on the same plane as the first electrode on the second surface side, is electrically connected to the gate layer, and has a third wide region and a width wider than the third wide region. A gate electrode having a second linear region that is narrow and extends from the third wide region,
The first linear region and the second linear region are adjacent to each other in parallel, and the first linear region and the second linear region are the first wide region and the second wide region. A semiconductor device characterized by being sandwiched by two wide regions selected from the region and the third wide region.   2. The semiconductor device according to claim 1, wherein the first linear region and the second linear region are sandwiched between two second wide regions.   The semiconductor device according to claim 1, wherein the semiconductor substrate is exposed on the first surface side.   The gate layer extends directly below the second wide region in a direction perpendicular to the first linear region and the second linear region, and the gate layer extends from the first linear region. 3. The semiconductor device according to claim 2, wherein the semiconductor device is cut right below.   The semiconductor device according to claim 1, wherein the first semiconductor layer is of a first conductivity type.

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