JP2015028424A - Semiconductor integrated circuit, design program for semiconductor integrated circuit, and design method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a transition fault test for an asynchronous transfer circuit of an LSI including a plurality of mutually asynchronous clock domains in a normal operation.SOLUTION: In a semiconductor integrated circuit, a transmission flip-flop, a reception flip-flop, and a combination circuit connected from an output of the transmission flip-flop to an input of the reception flip-flop, which propagate signals between asynchronous clock domains, are extracted from an LSI net list as a path to be tested. To the path to be tested, a test clock supply circuit is inserted for performing a transition fault test. The test clock supply circuit supplies a launch clock pulse to the transmission flip-flop and a capture clock pulse to the reception flip-flop, respectively, in a transition fault test operation for the path to be tested. A delay time from the launch clock pulse to the capture clock pulse can be arbitrarily set.

Description

  The present invention relates to a semiconductor integrated circuit, a semiconductor integrated circuit design program, and a semiconductor integrated circuit design method, and is particularly suitable for testing an asynchronous transfer circuit included in a semiconductor integrated circuit.

  The test for selecting whether a semiconductor integrated circuit such as an LSI (Large Scale Integrated circuit) is a good product or a defective product is a test for transition faults in addition to the conventional test for stuck-at faults. The tendency to use together has increased. The test for stuck-at fault is a test of whether or not a combinational circuit between flip-flops has an expected logic function, and is generally executed by a scan test technique. The test for the transition fault is a test of whether or not the delay of the combinational circuit between the flip-flops can withstand the operation at a speed actually used, and this is also generally performed by a scan test technique.

  Patent Document 1 discloses a test circuit that supplies a test clock having an appropriate pulse width in accordance with a circuit to be tested in a semiconductor integrated circuit capable of a delay fault (synonymous with transition fault) test.

  Patent Document 2 discloses a test circuit for measuring a delay amount of a combinational circuit in a manufacturer-provided circuit at a connection portion between the manufacturer-provided circuit whose internal circuit information is not disclosed and a circuit designed on the customer side. ing.

  Patent Documents 3 and 4 disclose a test circuit for a transition fault test in a semiconductor integrated circuit having a plurality of asynchronous clock domains.

JP 2008-300799 A JP 2010-216903 A JP 2003-222656 A JP 2008-275480 A

  As a result of examination of Patent Documents 1, 2, 3, and 4, the inventors have found that there are the following new problems.

  When the semiconductor integrated circuit to be tested includes a synchronous circuit and an asynchronous transfer circuit, the synchronous circuit is tested for both stuck-at faults and transition faults, and for the asynchronous transfer circuit. In many cases, only tests for stuck-at faults are performed.

  Patent Document 1 presupposes a transition fault test for a combinational circuit between a plurality of flip-flops operating with clocks having different frequencies (paragraph 0012 in the same document). Since clocks with different division ratios generated from the same clock are mixed, the delay amount allowed for the combinational circuit between the flip-flops is 1 cycle, 2 cycles, 3 cycles with the period of the original clock as a unit. There are multiple types such as 4 cycles. Since a plurality of clocks are generated from the same clock, a delay amount to be satisfied is defined even between flip-flops synchronized with clocks of different frequencies while not asynchronous transfer.

  In Patent Document 2, it is assumed that the manufacturer-provided circuit whose internal circuit information is not disclosed and the circuit designed on the customer side operate in synchronism with each other, but a separate scan chain is formed for each test. Sometimes, the problem that the transition fault test becomes difficult at the connected portion is solved.

  The techniques disclosed in Patent Document 1 and Patent Document 2 are both related to a transition fault test for a combinational circuit in a synchronous clock domain, and a transition fault for a combinational circuit between asynchronous clock domains. The test is neither described nor suggested.

  The technology disclosed in Patent Document 3 and Patent Document 4 is a technology related to a test circuit for a transition fault test in a semiconductor integrated circuit having an asynchronous clock domain. A transition fault test is independently performed for each clock domain. Is what you do. As described in paragraph 0010 of Patent Document 4, a path between asynchronous clock domains (signal propagation path) is not required to perform a delay fault test.

  This is because the asynchronous transfer circuit is asynchronous, so that there is no satisfactory specification for timing such as delay, and there is no criterion for selecting good / defective products. In other words, since the asynchronous transfer circuit is asynchronous, it is designed to realize a desired function no matter what timing the manufactured semiconductor integrated circuit operates. There is no need to select good / defective products. That is, there is no criterion for selecting good / defective products. Therefore, there is no need to perform a delay fault test, or there is no point in performing a delay fault test. For example, in a handshake circuit that is an example of an asynchronous transfer circuit, the transmission side waits for a response from the reception side and proceeds to the transmission of the next signal. Even if the delay is abnormally large, the data transfer functions normally. As described above, a satisfactory timing specification is not defined for a signal propagation path between asynchronous clock domains.

  However, as a result of investigations by the inventors of the present application, it has been found that it is effective to perform a delay fault test even on an asynchronous transfer circuit.

  As described above, the timing specification to be satisfied is not defined in the signal propagation path between the asynchronous clock domains included in the asynchronous transfer circuit. However, when the delay amount of the signal propagation path between asynchronous clock domains becomes abnormally large, the timing specification is not specified, and normal data transfer is systematically guaranteed for any timing specification. However, there is a risk that it may appear as performance degradation such as data transfer rate (throughput). Furthermore, an abnormal increase in the delay amount of the signal propagation path may be caused by the same cause that causes deterioration over time, and if left untreated, there is a risk that reliability may be lowered. A circuit that does not have a timing specification as described above and constitutes a signal propagation path between asynchronous clock domains is also configured with a finite number of logic stages in the actually designed circuit. If the actually manufactured circuit has a delay that is significantly greater than the expected delay due to manufacturing variations with respect to the delay value that can occur in the gate with the designed number of logic stages, it will function normally. Even if it is, it is better to treat it as some sort of failure. This is because a remarkably large delay may lead to deterioration in performance and reliability as described above.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, from the LSI netlist including a plurality of clock domains that are asynchronous with each other during normal operation, signals are transmitted between the asynchronous clock domains from the output of the transmission flip-flop, the reception flip-flop, and the transmission flip-flop. A combinational circuit connected to the input is extracted as a test path. A test clock supply circuit for performing a transition fault test is inserted into the path under test. The test clock supply circuit supplies a launch clock pulse to the transmission flip-flop and a capture clock pulse to the reception flip-flop at the time of the transition failure test operation of the path under test. The delay time from the launch clock pulse to the capture clock pulse can be set.

  The effect obtained by the one embodiment will be briefly described as follows.

  In other words, by setting the delay time from the launch clock pulse to the capture clock pulse based on the judgment criteria of the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit, the transition fault of the asynchronous transfer circuit Tests can be performed.

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit (LSI) according to the first embodiment. FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit (LSI) according to the first embodiment. FIG. 3 is a circuit diagram illustrating a detailed configuration example of the test clock supply circuit according to the first embodiment. FIG. 4 is a timing chart showing the operation of the test clock supply circuit of FIG. FIG. 5 is a circuit diagram showing another configuration example of the pulse width adjustment circuit. FIG. 6 is a circuit diagram showing another configuration example of the double pulse generation circuit. FIG. 7 is a timing chart showing the operation of the test clock supply circuit according to the second embodiment. FIG. 8 is a circuit diagram showing still another configuration example of the pulse width adjustment circuit. FIG. 9 is a circuit diagram showing still another configuration example of the double pulse generation circuit. FIG. 10 is a block diagram illustrating a configuration of the test clock supply circuit according to the first to third embodiments. FIG. 11 is an explanatory diagram of a launch / capture selection function (embodiment 4) in the test clock supply circuit. FIG. 12 is a block diagram illustrating a configuration example when a scan test circuit is added to a semiconductor integrated circuit (LSI) including a test clock supply circuit (Embodiment 5). FIG. 13 is a block diagram showing another configuration example when a scan test circuit is added to a semiconductor integrated circuit (LSI) including a test clock supply circuit (Embodiment 5). FIG. 14 is a timing chart illustrating an operation of a semiconductor integrated circuit (LSI) including the test clock supply circuit according to the fifth embodiment. FIG. 15 is a flowchart showing the operation of the design tool for incorporating the test clock supply circuit according to the first to fifth embodiments into the LSI to be designed. FIG. 16 is a flowchart showing the operation of the design tool for giving a test pattern to the test clock supply circuit incorporated in the LSI to be designed. FIG. 17 is an explanatory diagram for explaining the operation of the design tool shown in FIG. 15 (net list before incorporating the test clock supply circuit) in which the test clock supply circuit is incorporated into the LSI to be designed. FIG. 18 is an explanatory diagram for explaining the operation of the design tool shown in FIG. 15 (the net list after incorporation of the test clock supply circuit) in which the test clock supply circuit is incorporated into the LSI to be designed. FIG. 19 is an explanatory diagram for explaining the operation (net list after scanning) of the design tool of FIG. 15 in which the test clock supply circuit is incorporated in the LSI to be designed, such as the delay time of the launch clock pulse and the capture clock pulse. It is explanatory drawing (circuit) explaining the calculation method of this adjustment value. FIG. 20 is an explanatory diagram for explaining a method of calculating adjustment values such as the delay time of the launch clock pulse and the capture clock pulse in the operation of the design tool of FIG. 15 in which the test clock supply circuit is incorporated in the LSI to be designed (timing chart). ). FIG. 21 is an explanatory diagram for explaining another operation example of the design tool of FIG. 15 in which the test clock supply circuit is incorporated in the LSI to be designed.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <LSI including a transition fault test circuit for an asynchronous transfer circuit>
A semiconductor integrated circuit (LSI) (10) according to a representative embodiment disclosed in the present application is configured as follows.

  The semiconductor integrated circuit (10) operates in synchronization with a first flip-flop (1_1) that operates in synchronization with a first clock (CLK1) during normal operation and a second clock (CLK2) that is asynchronous with the first clock. A second flip-flop (2_1), a combinational circuit (4) connected from an output of the first flip-flop to an input of the second flip-flop, and a test clock supply circuit (6).

  The test clock supply circuit is configured to be able to supply a launch clock pulse (TCKL) to the first flip-flop and a capture clock pulse (TCCK) to the second flip-flop during a transition fault test operation of the combinational circuit. The delay time from the launch clock pulse to the capture clock pulse can be set.

  As a result, the transition fault test of the asynchronous transfer circuit can be performed in the semiconductor integrated circuit including the asynchronous transfer circuit between a plurality of clock domains that operate asynchronously during normal operation. The delay time from the launch clock pulse (TCKL) to the capture clock pulse (TCCK) can be arbitrarily set based on the judgment criterion of the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit. .

[2] <Double pulse generation circuit + launch clock / capture clock selection circuit>
In item 1, the test clock supply circuit includes a double pulse generation circuit (7), a first launch clock / capture clock selection circuit (81), and a second launch clock / capture clock selection circuit (82). Composed.

  The double pulse generation circuit receives a test pulse (TP) and generates a double pulse signal (TDP) including the launch clock pulse and the capture clock pulse from the rising edge and falling edge of the test pulse.

  The first launch clock / capture clock selection circuit is configured to be able to extract the launch clock pulse from the double pulse signal and supply it to the first flip-flop.

  The second launch clock / capture clock selection circuit is configured to extract the capture clock pulse from the double pulse signal and supply it to the second flip-flop.

  Thereby, a launch clock pulse (TCKL) and a capture clock pulse (TCLC) can be generated from a single test pulse (TP) inputted. Since the pulse width of the test pulse can be set as the delay time of the signal propagation path in the asynchronous transfer circuit from the first flip-flop to the second flip-flop, the test device that inputs the test pulse can use the launch clock pulse and the capture clock. A low-speed test apparatus may be used rather than a test apparatus that inputs pulses.

[3] <Launch clock / capture clock selection circuit>
In Item 2, at least one of the first launch clock / capture clock selection circuit and the second launch clock / capture clock selection circuit selects the launch clock pulse or the capture clock pulse from the double pulse signal. It is configured to be extractable.

  Thus, when the first flip-flop is also a capture flip-flop of a combinational circuit that forms another signal propagation path in the asynchronous transfer circuit, or the second flip-flop forms another signal propagation path in the asynchronous transfer circuit The transition fault test of the other signal propagation path can also be performed in one or both of the cases where it is also a launch flip-flop of the combinational circuit.

[4] <Pulse width adjustment circuit of input pulse>
In Item 2 or 3, the test clock supply circuit further includes a pulse width adjusting circuit (9) capable of adjusting the pulse width of the input pulse (TIN) to be output and outputting the test pulse.

  Thereby, the pulse width of the input pulse set as the delay time of the transition fault test can be adjusted inside the test circuit, and a test pulse (TP) with an accurate pulse width can be generated.

[5] <Pulse width adjustment circuit>
In Item 2 or 3, the test clock supply circuit further includes a pulse width adjustment circuit (9) capable of setting a pulse width of the test pulse based on an input test clock (TCK).

  As a result, the launch clock pulse and the capture clock pulse, which are set to the mutual delay time, can be generated based on the input test clock, so that the test apparatus can generate the test clock based on the cycle of the input test clock. The pulse width of the test pulse (TP) can be set. In item 4, the test apparatus supplies an input pulse having a pulse width accurately set based on the criterion of the transition fault test, and the pulse width can be adjusted. The device only needs to be set. Further, the pulse width may be finely adjusted.

[6] <Adjustment of pulse width (high width) in double pulse generation circuit>
In Item 2, Item 3 or Item 4, the double pulse generation circuit is configured to be able to adjust pulse widths of the launch clock pulse and the capture clock pulse.

  Thereby, the launch clock pulse (TCKL) and the capture clock pulse (TCCK) can be adjusted to appropriate pulse widths.

[7] <Scan test circuit>
Item 1 further includes a first scan chain including the first flip-flop, a second scan chain including the second flip-flop, and a scan test circuit.

  The scan test circuit supplies a first shift clock (TSCK1) to the first flip-flop during a scan test operation, shifts the first scan chain, and a second shift clock (TSCK2) to the second flip-flop. ) To shift the second scan chain.

  As a result, the stuck-at fault test can be executed in each clock domain during the scan test operation, and further, the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit using the scan test operation. Test pattern input and test result output can be performed. In other words, the first flip-flop (1_1) that is the launch flip-flop (TC) is supplied via the first scan chain, and the result of the transition fault test is sent from the second flip-flop (2_1) that is the capture flip-flop (RC). It can be output via the second scan chain.

[8] <Scan chain including launch flip-flop and capture flip-flop>
In item 1, further comprising a scan chain including the first flip-flop and the second flip-flop, and a scan test circuit,
The scan test circuit supplies a shift clock to each of the first flip-flop and the second flip-flop during a scan test operation to shift the scan chain.

  As a result, at the time of the scan test operation, the stuck-at fault test can be executed collectively for the asynchronous clock domains. Furthermore, using a scan test operation, it is possible to input a test pattern and output a test result for a transition fault test of a combinational circuit that constitutes a signal propagation path in an asynchronous transfer circuit. That is, the test pattern for the transition fault test is supplied to the first flip-flop (1_1) which is the launch flip-flop (TC) via the scan chain, and the result of the transition fault test is the capture flip-flop (RC). The second flip-flop (2_1) can output the same scan chain. The stuck-at fault test for the combinational circuit in the asynchronous transfer path between the asynchronous clock domains can be more easily performed.

[9] <Design program for inserting a transition fault test circuit of an asynchronous transfer circuit>
A design program (20) of a semiconductor integrated circuit (10) according to a representative embodiment disclosed in the present application is obtained by an electronic computer including a data processing unit (21, 23, 24) and a data storage unit (22). Can be implemented and is structured as follows.

  The design program (20) extracts a test path from a first netlist (netlist-1) including a plurality of clock domains asynchronous with each other during normal operation (S1), and adds a test clock to the first netlist. And inserting a supply circuit (6) to generate a second netlist (S2 to S4).

  The step (S1) of extracting a path under test is based on the first netlist (netlist-1) and the clock source information corresponding to the first netlist stored in the data storage unit. A transmission flip-flop (TC) and a reception flip-flop (RC) that are included in the netlist and propagate a signal between the asynchronous clock domains are extracted. Further, the path to be tested is extracted from the output of the transmission flip-flop including the combinational circuit (4) connected to the input of the reception flip-flop.

  The test clock supply circuit is configured to be able to supply a launch clock pulse (TCKL) to the transmission flip-flop and a capture clock pulse (TCCK) to the reception flip-flop during a transition fault test operation of the combinational circuit, A delay time from the launch clock pulse to the capture clock pulse can be set.

  As a result, in a semiconductor integrated circuit including an asynchronous transfer circuit between a plurality of clock domains that operate asynchronously during normal operation, the transition fault test circuit that enables a transition fault test of the asynchronous transfer circuit to be performed on the semiconductor integrated circuit. Can be inserted. The delay time from the launch clock pulse (TCKL) to the capture clock pulse (TCCK) can be arbitrarily set based on the judgment criterion of the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit. .

[10] <Calculation of transition failure test criteria>
In item 9, the design program (20) further includes a step (S8) of estimating a signal propagation delay in the combinational circuit extracted as the test path.

  Thereby, based on the estimated signal propagation delay of the path under test, the delay time from the launch clock pulse to the capture clock pulse to be set in the test clock supply circuit can be calculated.

[11] <Inserting scan circuit into netlist>
In item 9, the design program (20) replaces the included flip-flop with the scan-compatible flip-flop (11) for the second netlist, inserts a scan circuit, and inserts a third netlist (netlist-2). ) Is further included (S5).

  As a result, the stuck-at fault test using the normal scan test technology and the transition fault test in each clock domain can be performed on the semiconductor integrated circuit to be tested, and the transition to the asynchronous transfer circuit can be performed. In the failure test, it is possible to input a test pattern (scan in) and output a test result (scan out) using the same scan path.

[12] <Use of layout information>
In item 11, the design program (20) executes layout by using the third netlist as input, and generates a fourth netlist (netlist-3) including the parasitic resistance and parasitic capacitance after layout (S6). And calculating a signal propagation delay in the combinational circuit extracted as the test path based on the fourth netlist (S7).

  Accordingly, the delay time from the launch clock pulse to the capture clock pulse to be set in the test clock supply circuit based on the signal propagation delay of the path under test estimated more accurately using the layout information Can be calculated.

[13] <Double pulse generation circuit + pulse width adjustment circuit>
In item 9, the test clock supply circuit includes a double pulse generation circuit (7), a first launch clock / capture clock selection circuit (81), a second launch clock / capture clock selection circuit (82), a pulse width, And an adjustment circuit (9).

  The double pulse generation circuit receives a test pulse (TP), and generates the launch clock pulse and the capture clock pulse from the rising edge and falling edge of the test pulse. The first launch clock / capture clock selection circuit is configured to extract the launch clock pulse from the double pulse signal and supply it to the transmission flip-flop. The second launch clock / capture clock selection circuit is configured to extract the capture clock pulse from the double pulse signal and supply it to the reception flip-flop. The pulse width adjustment circuit is configured to be capable of adjusting a pulse width of the test pulse.

  As a result, a launch clock pulse (TCKL) and a capture clock pulse (TCCK) can be generated from a single test pulse (TP) that is input, and the delay time between them can be set as a single test pulse that is input. Can be adjusted and set inside the test circuit on the basis of the pulse width. Therefore, the test apparatus that inputs a single test pulse may be a low-speed test apparatus and the accuracy of the pulse width is not necessarily higher than the test apparatus that inputs the launch clock pulse and the capture clock pulse.

[14] <Use of layout information in pulse width adjustment circuit>
In item 13, the design program (20) further includes a step (S6) of executing layout by inputting the netlist based on the first netlist and generating a fourth netlist (netlist-3) after layout. . Further, a step (S8) of calculating a signal propagation delay in the combinational circuit extracted as the test path based on the fourth netlist, and a pulse width adjusting circuit based on the fourth netlist And calculating an adjustable pulse width amount (S10).

  Thus, the delay time from the launch clock pulse to the capture clock pulse to be set in the test clock supply circuit is set based on the signal propagation delay of the path under test calculated more accurately using the layout information. Further, the pulse width of the test pulse can be adjusted more accurately by the pulse width adjusting circuit.

[15] <Design method for inserting transition fault test circuit of asynchronous transfer circuit>
A design method (20) of a semiconductor integrated circuit (10) according to a representative embodiment disclosed in the present application is performed by an electronic computer including a data processing unit (21, 23, 24) and a data storage unit (22). Can be implemented and is structured as follows.

  The design method (20) includes a step (S1) of extracting a test path from a first netlist (netlist-1) including a plurality of clock domains asynchronous with each other during normal operation, and a test clock is added to the first netlist. And inserting a supply circuit (6) to generate a second netlist (S2 to S4).

  The step (S1) of extracting a path under test is based on the first netlist (netlist-1) and the clock source information corresponding to the first netlist stored in the data storage unit. A transmission flip-flop (TC) and a reception flip-flop (RC) that are included in the netlist and propagate a signal between the asynchronous clock domains are extracted. Further, the path to be tested is extracted from the output of the transmission flip-flop including the combinational circuit (4) connected to the input of the reception flip-flop.

  The test clock supply circuit is configured to be able to supply a launch clock pulse (TCKL) to the transmission flip-flop and a capture clock pulse (TCCK) to the reception flip-flop during a transition fault test operation of the combinational circuit, A delay time from the launch clock pulse to the capture clock pulse can be set.

  As a result, in a semiconductor integrated circuit including an asynchronous transfer circuit between a plurality of clock domains that operate asynchronously during normal operation, the transition fault test circuit that enables a transition fault test of the asynchronous transfer circuit to be performed on the semiconductor integrated circuit. Can be inserted. The delay time from the launch clock pulse (TCKL) to the capture clock pulse (TCCK) can be arbitrarily set based on the judgment criterion of the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit. .

[16] <Calculation of transition failure test criteria>
In item 15, the design method (20) further includes a step (S8) of estimating a signal propagation delay in the combinational circuit extracted as the test path.

  Thereby, based on the estimated signal propagation delay of the path under test, the delay time from the launch clock pulse to the capture clock pulse to be set in the test clock supply circuit can be calculated.

[17] <Insertion of scan circuit into netlist>
In the item 15, the design method (20) replaces the flip-flop included in the second netlist with a scan-compatible flip-flop (11), and inserts a scan circuit into the third netlist (netlist-2). Is further included (S5).

  As a result, the stuck-at fault test using the normal scan test technology and the transition fault test in each clock domain can be performed on the semiconductor integrated circuit to be tested, and the transition to the asynchronous transfer circuit can be performed. In the failure test, it is possible to input a test pattern (scan in) and output a test result (scan out) using the same scan path.

[18] <Use of layout information>
In item 17, the design method (20) executes layout by using the third netlist as an input, and generates a fourth netlist (netlist-3) including the parasitic resistance and parasitic capacitance after layout (S6). And calculating a signal propagation delay in the combinational circuit extracted as the test path based on the fourth netlist (S7).

  Accordingly, the delay time from the launch clock pulse to the capture clock pulse to be set in the test clock supply circuit based on the signal propagation delay of the path under test estimated more accurately using the layout information Can be calculated.

[19] <Double pulse generation circuit + pulse width adjustment circuit>
In item 15, the test clock supply circuit includes a double pulse generation circuit (7), a first launch clock / capture clock selection circuit (81), a second launch clock / capture clock selection circuit (82), a pulse width, And an adjustment circuit (9).

  The double pulse generation circuit receives a test pulse (TP), and generates the launch clock pulse and the capture clock pulse from the rising edge and falling edge of the test pulse. The first launch clock / capture clock selection circuit is configured to extract the launch clock pulse from the double pulse signal and supply it to the transmission flip-flop. The second launch clock / capture clock selection circuit is configured to extract the capture clock pulse from the double pulse signal and supply it to the reception flip-flop. The pulse width adjustment circuit is configured to be capable of adjusting a pulse width of the test pulse.

  As a result, a launch clock pulse (TCKL) and a capture clock pulse (TCCK) can be generated from a single test pulse (TP) that is input, and the delay time between them can be set as a single test pulse that is input. Can be adjusted and set inside the test circuit on the basis of the pulse width. Therefore, the test apparatus that inputs a single test pulse may be a low-speed test apparatus and the accuracy of the pulse width is not necessarily higher than the test apparatus that inputs the launch clock pulse and the capture clock pulse.

[20] <Use of layout information in pulse width adjustment circuit>
In item 19, the design method (20) further includes a step (S6) of executing a layout by using the netlist based on the first netlist as an input, and generating a fourth netlist (netlist-3) after the layout. . Further, a step (S8) of calculating a signal propagation delay in the combinational circuit extracted as the test path based on the fourth netlist, and a pulse width adjusting circuit based on the fourth netlist And calculating an adjustable pulse width amount (S10).

  Thus, the delay time from the launch clock pulse to the capture clock pulse to be set in the test clock supply circuit is set based on the signal propagation delay of the path under test calculated more accurately using the layout information. Further, the pulse width of the test pulse can be adjusted more accurately by the pulse width adjusting circuit.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1] <Transition fault test of asynchronous transfer circuit>
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit (LSI) 10 according to the first embodiment.

  The LSI 10 includes a clock domain that operates in synchronization with the user clock 1 (CLK1) during normal operation, and a clock domain that operates in synchronization with the user clock 1 (CLK1) and the asynchronous user clock 2 (CLK2). The clock domain that operates in synchronization with the user clock 1 (CLK1) includes flip-flops 1_1 and 1_2, and the clock domain that operates in synchronization with the user clock 2 (CLK2) includes flip-flops 2_1 and 2_2. Will be described as being included. Since the user clock 1 (CLK1) and the user clock 2 (CLK2) are asynchronous, any data transfer between them is asynchronous transfer. Now, assuming that there is asynchronous data transfer between the flip-flop 1_1 and the flip-flop 2_1, the combinational circuit 4 between them is the test target logic circuit of this embodiment. The flip-flop 1_1 is the start point of the asynchronous transfer path, and is called a launch flip-flop or a transmission flip-flop (TC). The flip-flop 2_1 is the end point of the asynchronous transfer path, and the capture flip-flop or the reception flip-flop (RC). be called. The clock supply path to the flip-flop 1_1 and the flip-flop 1_2 includes a test clock supply circuit 6.

  The test clock supply circuit 6 can supply the launch clock pulse TCKL to the flip-flop 1_1 and the capture clock pulse TCCC to the flip-flop 1_2 during the transition fault test operation of the combinational circuit 4 that is the test target logic circuit. It is configured. The test clock supply circuit 6 is configured such that the delay time from the launch clock pulse TCKL to the capture clock pulse TCCC can be set arbitrarily.

  The test clock supply circuit 6 includes, but is not limited to, a launch clock pulse / capture clock pulse generation circuit 7, a launch clock extraction / user clock switching circuit 81, and a capture clock extraction / user clock switching circuit 82. The The launch clock extraction / user clock switching circuit 81 supplies the user clock 1 to the flip-flop 1_1 during the normal operation, and extracts the launch clock pulse TCKL from the clock pulse generated by the generation circuit 7 during the transition fault test operation. 1_1. The capture clock extraction / user clock switching circuit 82 supplies the user clock 2 to the flip-flop 1_2 during the normal operation, and extracts the capture clock pulse TCKL from the clock pulse generated by the generation circuit 7 during the transition fault test operation. 1_2. The generation circuit 7 is configured to be able to set the delay time of the launch clock pulse TCKL and the capture clock pulse TCCC.

  Thereby, in the semiconductor integrated circuit (LSI) 10 including an asynchronous transfer circuit between a plurality of clock domains that operate asynchronously during normal operation, a transition failure test of the asynchronous transfer circuit can be performed. The delay time from the launch clock pulse TCKL to the capture clock pulse TCCC can be arbitrarily set based on the judgment criterion of the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit.

  The combinational circuit 4 in the same clock domain is a target of a normal stuck-at fault test, and may be a target of a transition fault test. In the transition fault test in the same clock domain, the determination criteria for non-defective / defective products are determined based on the operating frequency of each clock during normal operation. On the other hand, there is generally no non-defective / defective criterion in the asynchronous signal propagation path from the flip-flop 1_1 to the flip-flop 2_1. This is because the user clock 1 (CLK1) and the user clock 2 (CLK2) are asynchronous, and the phase relationship between the clocks fluctuates sequentially, so there is no point in defining the signal propagation delay.

  However, in the present embodiment, a transition fault is defined in which a specification of a signal propagation delay that should be satisfied by an asynchronous signal propagation path from the flip-flop 1_1 to the flip-flop 2_1 is determined, and a non-defective product / defective product is determined based on the specification. Tests can be performed. If the delay specifications that can be satisfied with the asynchronous signal propagation path can be specified systematically, the delay time from the launch clock pulse TCKL to the capture clock pulse TCCC is set accordingly, and a transition fault test is performed. can do. In addition, the gate circuit design for the asynchronous signal propagation path from the flip-flop 1_1 to the flip-flop 2_1 has been completed even if the specification of the delay to be satisfied in the asynchronous signal propagation path cannot be specified in a systematic manner. Subsequent stages include a finite number of logic gates. For this reason, the specifications of the delay that should be allowed are specified for the circuits that are actually designed and exist in consideration of manufacturing variations, and the delay time from the launch clock pulse TCKL to the capture clock pulse TCCC is adjusted accordingly. Can be set up to perform transition fault tests. Products that deviate from the expected range due to manufacturing variations can be selected as defective products.

  FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit (LSI) according to the first embodiment. The horizontal axis is time. (A) shows user clock 1 (CLK1) and user clock 2 (CLK2) supplied to flip-flop 1_1 and flip-flop 2_1, respectively, during normal operation. (B) shows the launch clock pulse TCKL supplied to the flip-flop 1_1 that is the launch flip-flop (TC) at the start point of the asynchronous transfer path and the capture flip-flop that is the end point during the asynchronous transfer path transition failure test. The capture clock pulse supplied to the flip-flop 2_1 that is (RC) is shown. The launch clock pulse TCKL has a high period from time t1 to t2, and the capture clock pulse TCCC has a high period from time t3 to t4. The delay time from time t1 to time t3 is the delay time from the launch clock pulse TCKL to the capture clock pulse TCCC, and is configured to be arbitrarily set.

<Double pulse generation circuit + launch clock / capture clock selection circuit>
FIG. 3 is a circuit diagram illustrating a detailed configuration example of the test clock supply circuit 6 according to the first embodiment.

  The test clock supply circuit 6 is not particularly limited, and includes, for example, a double pulse generation circuit 7_1, a first launch clock / capture clock selection circuit 8_1, and a second launch clock / capture clock selection circuit 8_2. .

  The test clock supply circuit 6 uses the asynchronous transfer circuit 4 from the flip-flop 1_1 that is the launch flip-flop (TC) to the flip-flop 2_1 that is the capture flip-flop (RC) as a transition failure test target at the start point of the asynchronous transfer path. This is a test clock supply circuit. During the transition fault test, the launch clock pulse TCKL is input to the flip-flop 1_1 that is the launch flip-flop (TC), and the capture clock pulse TCCC is input to the flip-flop 2_1 that is the capture flip-flop (RC). Further, it may be configured to include a pulse width adjustment circuit 9_1.

  The test clock supply circuit 6 is supplied with a user clock 1 and a user clock 2 during normal operation from PLL1 (18_1) and PLL2 (18_2) which are clock supply sources. The PLL1 (18_1) and the PLL2 (18_2) may be configured by using a phase locked loop (PLL), and may be a circuit that generates a clock by any other method. It may be a clock supplied from the outside.

  The clock output from the output node I of the first launch clock / capture clock selection circuit 8_1 is a flip-flop that is synchronized with the user clock 1 (CLK1) during normal operation, and a launch flip-flop at the start point of the asynchronous transfer path during a transition fault test. Is supplied to the flip-flop 1_1 which is a TC (TC). The clock output from the output node K of the second launch clock / capture clock selection circuit 8_2 is a flip-flop that is synchronized with the user clock 2 (CLK2) during normal operation, and a capture flip-flop at the end of the asynchronous transfer path during a transition fault test. Is supplied to the flip-flop 2_1 which is a loop (RC).

  A test pulse TP is input to the double pulse generation circuit 7_1, and a double pulse signal TDP including a launch clock pulse TCKL and a capture clock pulse TCKC is generated from a rising edge and a falling edge of the test pulse TP. The double pulse generation circuit 7_1 is configured using, for example, a delay buffer 13_5 and an exclusive OR gate 12_2. Two pulses having a high period corresponding to the delay time by the delay buffer 13_5 are output as the double pulse signal TDP from the rising edge and the falling edge of the input test pulse TP. The two generated pulses are a launch clock pulse TCKL and a capture clock pulse TCCC. Depending on the pulse width of the test pulse TP, the delay time from the launch clock pulse TCKL to the capture clock pulse TCCC can be arbitrarily set.

  The first launch clock / capture clock selection circuit 8_1 supplies the user clock 1 (CLK1) to the flip-flop 1_1 during normal operation. At the time of the transition fault test, the launch clock pulse TCKL is extracted from the double pulse signal TDP and supplied to the flip-flop 1_1 which is a launch flip-flop (TC) at the start point of the asynchronous transfer path. The second launch clock / capture clock selection circuit 8_2 supplies the user clock 2 (CLK2) to the flip-flop 1_2 during normal operation. During the transition fault test, the capture clock pulse TCKC is extracted from the double pulse signal TDP and supplied to the flip-flop 2_1 that is the end point of the asynchronous transfer path and is the capture flip-flop (RC). The launch clock / capture clock selection circuits 8_1 and 8_2 are configured to be switchable so that appropriate clock pulses can be supplied during normal operation and during a transition fault test.

  In FIG. 3, a launch clock / clock that can specify whether to extract the launch clock pulse TCKL or the capture clock pulse TCCC by using the same logic circuit and the control signals of the capture selection 1 and the capture selection 2, respectively. Capture clock selection circuits 8_1 and 8_2 are shown. The selectors 14_2 and 14_4 allow the user clock 1 (CLK1) and the user clock 2 (CLK2) to pass through during the normal operation and the double pulse signal TDP during the transition fault test according to the input test enable signal. The test enable signal may be configured to be used also as the scan enable signal. The scan enable signal F is captured and delayed by the anti-phase flip-flops 16_1 and 16_2, and the launch clock pulse TCKL or the capture clock pulse TCCC is generated as a double pulse signal using the logic gates 12_3 and 12_4, 12_6 and 12_7, and the selectors 14_3 and 14_5. Mask signals H and J for extraction from the TDP are generated. Which one of the launch clock pulse TCKL and the capture clock pulse TCCC is masked and which is extracted is designated by the capture selection signals 1 and 2, respectively. When the launch clock pulse TCKL is designated by the capture selection signal 1, the launch clock / capture clock selection circuit 8_1 masks one of the double pulse signals TDP with the AND gate 12_5, thereby performing the launch clock pulse TCKL during the transition fault test. To node I. When the capture clock pulse TCCC is designated by the capture selection signal 2 in the launch clock / capture clock selection circuit 8_2, one of the double pulse signals TDP is masked by the AND gate 12_8, so that the capture clock pulse TCCC is detected during the transition fault test. Is output to node K.

  As described above, during the transition fault test, the launch clock pulse TCKL is input to the flip-flop 1_1 that is the launch flip-flop (TC) at the start point of the asynchronous transfer path, and the capture is performed to the flip-flop 2_1 that is the capture flip-flop (RC). A clock pulse TCKC is input. On the other hand, it is not necessary to use the test clock supply circuit 6 having the configuration as shown in FIG. 3, and the launch clock pulse TCKL, the capture clock pulse TCCC, and the user clocks 1 and 2 (CLK1 and CLK2) supplied from the outside. Switching may be performed using a selector. In that case, the input launch clock pulse TCKL and the capture clock pulse TCLC are supplied to the flip-flop 1_1 and the flip-flop 2_1 in a state in which the delay time is accurately managed by the test apparatus and the influence of noise and the like is eliminated. It is necessary to On the other hand, in the example shown in FIG. 3, the double clock generation circuit 7_1 can generate the launch clock pulse TCKL and the capture clock pulse TCLC from the single test pulse TP input through one signal line. . The pulse width of the test pulse TP is set as the delay time of the signal propagation path in the asynchronous transfer circuit from the flip-flop 1_1 that is the launch flip-flop (TC) to the flip-flop 2_1 that is the capture flip-flop (RC) at the start point of the asynchronous transfer path. Can be set. Therefore, the test apparatus that inputs the test pulse TP may be a test apparatus that is slower than the test apparatus that inputs the launch clock pulse TCKL and the capture clock pulse TCCC.

<Pulse width adjustment circuit (adjustment using delay element)>
As shown in FIG. 3, the test clock supply circuit 6 may further include a pulse width adjustment circuit 9_1 that can adjust the pulse width of the input pulse TIN to be output as a test pulse TP. Thus, the pulse width of the input pulse set as the delay time of the transition fault test can be adjusted inside the test clock supply circuit 6 to generate a test pulse with an accurate pulse width. A detailed logic circuit design example and operation of the pulse width adjustment circuit 9_1 shown in FIG. 3 will be described.

  The pulse width adjusting circuit 9_1 receives one delay signal selected by the selector 14_1 from each of the taps of the plurality of delay buffers 13_1 to 13_4 for delaying the input pulse TIN, together with the original input pulse TIN, the OR gate 12_1. Is input. The input pulse TIN is processed so that the high width becomes longer by the delay time of the selected delay buffers 13_1 to 13_4. Thereby, the width of the test pulse TP can be adjusted inside the LSI 10.

  FIG. 4 is a timing chart showing the operation of the test clock supply circuit of FIG. The horizontal axis represents time, and the vertical axis represents the waveforms of nodes A to K in the pulse width adjustment circuit 9_1, the double pulse generation circuit 7_1, and the launch clock / capture clock selection circuits 8_1 to 8_2.

  The input pulse TIN input to the node A has a width from time t2 to time t5. In the pulse width adjustment circuit 9_1, a signal delayed from the TIN is generated at the node B in accordance with the set test timing setting. The delay from time t2 to t3 and the delay from time t5 to t6 are the delay amounts set by the test timing setting. By taking a logical sum with the OR gate 12_1, a test pulse TP, in which the pulse width of the TIN is increased by the delay amount, is output to the node C. As a result, the test pulse TP has a pulse width from time t2 to time t6. The double pulse generation circuit 7_1 takes the exclusive OR of the test pulse TP inputted from the node C and the signal of the node D delayed by the delay buffer 13_5 at the gate 12_2, and outputs it to the node E as the double pulse signal TDP. . The double pulse signal TDP of the node E includes a launch clock pulse TCKL from time t2 to t4 and a capture clock pulse TCCC from time t6 to t7. A scan enable signal input to the launch clock / capture clock selection circuits 8_1 to 8_2 is shown as a waveform of the node F. The scan enable signal, which is a control signal for the scan test, changes to low at time t1 as shown at node F, and the waveform of the test enable signal is not shown, but the double pulse signal TDP is sent to the selectors 14_2 and 14_4. It is fixed on the passing side. In the launch clock / capture clock selection circuit 8_1, the node G is an output in which the scan enable signal indicated by the node F is taken into the flip-flop 16_1. The flip-flop 16_1 is a reverse-phase flip-flop, and takes in the scan enable signal at the falling edge of the double pulse signal TDP at time t4 and outputs it to the node G. The logic gates 12_3 and 12_4 perform the logical operation of the node F and the node G, and the side selected by the capture selection 1 signal by the selector 14_3 is output to the node H. On the other hand, the launch clock / capture clock selection circuit 8_2 operates in the same manner, and the side selected by the capture selection 2 signal by the selector 14_5 is output to the node J. The capture selection 1 signal is designated so that the launch clock pulse TCKL is output to the node I. The waveform of the node H is high from time t4 to low from time t4 to t8, and the double clock signal TDP is masked for the period from time t4 to t8, thereby allowing the launch clock pulse TCKL from time t2 to t4 to pass and the capture clock. The pulse TCKC is not passed. As a result, the launch clock pulse TCKL is extracted and output to the node I. On the other hand, the capture selection 2 signal is designated so that the capture clock pulse TCKC is output to the node K. The waveform of the node J is low at times t1 to t4 and high after time t4, and the double clock signal TDP is masked for a period from time t1 to t4, thereby masking the launch clock pulse TCKL from time t2 to t4. The capture clock pulse TCKC from t6 to t7 is passed. As a result, the capture clock pulse TCKC is extracted and output to the node K.

[Embodiment 2] <Pulse width adjustment circuit>
As shown in the first embodiment, the pulse width adjustment circuit 9_1 that adjusts the pulse width of the test pulse TP is provided in the test clock supply circuit 6, so that the pulse width of the input pulse TIN that is input can be increased within the LSI 10. The width of the test pulse TP can be adjusted. The width of the test pulse TP is the delay time of the signal propagation path in the asynchronous transfer circuit from the flip-flop 1_1 that is the launch flip-flop (TC) to the flip-flop 2_1 that is the capture flip-flop (RC) at the start point of the asynchronous transfer path. Therefore, it is set as the delay time of the combinational circuit 4 that is the signal propagation path of the asynchronous transfer circuit.

<Adjustment with delay element>
FIG. 3 shows a pulse width adjusting circuit in which delay buffers 13_1 to 4 are connected in series in multiple stages, a signal having a desired delay amount is selected and output from the tap, and the high width can be expanded by the OR gate 12_1. 9_1 was shown. The delay amount per one of the delay buffers 13_1 to 4 can be adjusted step by step in increments (resolution or minimum unit).

<Adjustment by counter circuit>
FIG. 5 is a circuit diagram showing another configuration example of the pulse width adjustment circuit. The test clock supply circuit 6 includes a pulse width adjustment circuit 9_2 that can set the pulse width of the test pulse TP based on the input test clock TCK, instead of the pulse width adjustment circuit 9_1 that performs adjustment using the delay element. . As shown in FIG. 5, the pulse width adjustment circuit 9_2 includes a counter circuit 17_1 to which the test clock TCK is input. This is a circuit to which a function of extending the pulse width (high period) of the test clock TCK to an arbitrary multiple by the counter circuit 17_1 is added. A signal whose pulse width is set by a plurality of cycles of the test clock TCK is output to the node A. By making the count value of the counter circuit 17_1 variable, the pulse width can be set. Similarly to the pulse width adjustment circuit 9_1 shown in FIG. 3, the counter circuit 17_1 further includes a circuit capable of finely adjusting the pulse width by the number of stages of delay elements specified by the delay adjustment control signal. You may comprise so that the test pulse TP may be output. The delay buffers 13_6 to 9_9 and the selector 14_6 are included. A selector 14_7 that is selectively controlled by a clock selection signal may be further provided. It is possible to selectively control whether the output of the counter circuit 17_1 is directly output to the node C as the test pulse TP, or is output to the node C as the test pulse TP through a circuit whose pulse width can be finely adjusted by the delay element.

  The pulse width of the test pulse TP is the delay time of the signal propagation path in the asynchronous transfer circuit from the flip-flop 1_1 that is the launch flip-flop (TC) to the flip-flop 2_1 that is the capture flip-flop (RC) at the start point of the asynchronous transfer path. is there. By outputting the output of the counter circuit 17_1 as it is to the node C as the test pulse TP, fluctuations in the set value of the delay time due to manufacturing variations, including the delay values of the delay buffers 13_6 to 9, can be suppressed. On the other hand, the test pulse TP can be adjusted with a resolution finer than the cycle of the test clock TCK by outputting through a circuit capable of finely adjusting the pulse width by the delay element.

  Thereby, the delay time of the signal propagation path in the asynchronous transfer circuit from the launch flip-flop (TC) to the capture flip-flop (RC) is set at the start point of the asynchronous transfer path based on the cycle of the input test clock TCK. The launch clock pulse TCKL and the capture clock pulse TCLC can be generated. The test apparatus can set the pulse width of the test pulse (TP) based on the cycle of the input test clock TCK.

<Add selector>
FIG. 5 shows whether the selector 14_7 outputs the output of the counter circuit 17_1 as it is to the node C as a test pulse TP, or outputs it to the node C as a test pulse TP through a circuit whose pulse width can be finely adjusted by a delay element. A pulse width adjustment circuit 9_2 that is selectively controlled is shown.

  FIG. 8 is a circuit diagram showing still another configuration example of the pulse width adjustment circuit. The pulse width adjustment circuit 9_4 further includes an external input terminal. Similar to the pulse width adjustment circuit 9_2 shown in FIG. 5, the pulse width of the test pulse TP is defined by the counter circuit 17_3, and the pulse width can be finely adjusted by the delay buffers 13_13 to 16 of the number of stages specified by the delay adjustment control signal. A simple circuit. The output of the counter circuit 17_1 is output as it is to the node C as a test pulse TP by the selector 14_10 that can be selectively controlled by the clock selection signal, or is output to the node C as a test pulse TP through a circuit whose pulse width can be finely adjusted by the delay element It is selectively controlled. The selector 14_10 also selectively controls whether a signal input from an external input is output to the node C as a test pulse TP. The width of the test pulse TP corresponds to the delay time of the signal propagation path in the asynchronous transfer circuit from the flip-flop 1_1 that is the launch flip-flop (TC) to the flip-flop 2_1 that is the capture flip-flop (RC) at the start point of the asynchronous transfer path. To do. The width of the test pulse TP is not affected by manufacturing variations when the output of the counter circuit 17_1 is directly output as the test pulse TP, but the resolution is defined by the cycle of the test clock TCK. When the test pulse TP is output through a circuit capable of finely adjusting the pulse width by the delay element, the resolution can be increased to the delay values of the delay buffers 13_13 to 16, but the delay values of the delay buffers 13_13 to 16 vary due to manufacturing variations. To do. By outputting the external input as it is as the test pulse TP, the resolution is defined by the cycle of the test clock TCK, and the delay values of the delay buffers 13_13 to 16-16 do not fluctuate due to manufacturing variations. A test pulse TP having the same pulse width can be input. By providing the selector 14_10, the method of generating the test pulse TP can be changed in accordance with the specifications of the test apparatus that can be used for the transition fault test.

[Embodiment 3] <High width adjustment circuit>
The double pulse generation circuit 7 is configured to be able to adjust the pulse width of the launch clock pulse TCKL and the capture clock pulse TCCC, that is, the high width. FIG. 6 is a circuit diagram showing a configuration example of a double pulse generation circuit that performs adjustment by a reverse phase flip-flop. FIG. 9 is a circuit diagram illustrating a configuration example of a double pulse generation circuit that performs adjustment using a delay element.

<Adjustment by reversed-phase flip-flop>
FIG. 6 also shows the pulse width adjustment circuit 9_3. The pulse width adjustment circuit 9_3 adopts a configuration in which the selector 14_7 is omitted from the pulse width adjustment circuit 9_2 shown in FIG. The double pulse generation circuit 7_2 has a structure in which a reverse-phase flip-flop of the test clock TCK input to the pulse width adjustment circuit 9_3 is inserted instead of the delay element. The other parts are the same as those of the pulse width adjustment circuit 9_2 (FIG. 5), and thus description thereof is omitted. The double pulse generation circuit 7_2 includes a reverse-phase flip-flop 16_3 and an exclusive OR gate 12_11. The anti-phase flip-flop 16_3 captures the input test pulse TP with the anti-phase of the test clock TCK. The exclusive OR gate 12_11 calculates the exclusive OR of the test pulse TP and the output of the anti-phase flip-flop 16_3 and outputs the result to the node E as the double pulse signal TDP. The test pulse TP is taken into the anti-phase flip-flop 16_3 with a delay by the high period of the test clock TCK. The output of the exclusive OR gate 12_11 becomes a double pulse signal TDP including a launch clock pulse TCKL and a capture clock pulse TCKC having a high period corresponding to the high period of the test clock TCK.

  FIG. 7 is a timing chart showing the operation of the test clock supply circuit according to the second embodiment. Similar to FIG. 4, but the input test clock TCK is shown. The node A of the pulse width adjustment circuit 9_3 has a waveform generated by dividing the input test clock TCK by the counter 17_2. FIG. 7 shows an example of dividing by 4 and has an on-state period from time t2 to t4. The output waveform D of the reverse-phase flip-flop 16_3 has a waveform with a delay corresponding to the on-state period of the test clock TCK with respect to the double-pulse input signal C, and has an on-state period from time t3 to t5. Since the test pulse TP of the node C has an on-state period from time t2 to t5, and the output waveform D of the reverse phase flip-flop 16_3 has an on-state period from time t3 to t6, the output of the exclusive OR gate 12_11 The double pulse signal output from the node E is a signal having a launch clock pulse (TCKL) and a capture clock pulse (TCCK) at times t2 to t3 and t5 to t6.

  As shown in FIG. 3, in the double pulse generation circuit 7_1 that defines the on-state period according to the delay amount by the delay buffer 13_5, the on-state period of the input test pulse TP is always larger than the delay amount by the delay buffer 13_5. There is a need to. On the other hand, since the test pulse TP of the node C of this embodiment is a pulse generated by dividing the test clock TCK, it always has an on-state period longer than the on-state period of the test clock TCK. Accordingly, it is possible to always generate a double pulse having an interval of the on-state period of the test pulse TP.

  Thereby, the launch clock pulse (TCKL) and the capture clock pulse (TCCK) can be adjusted to appropriate pulse widths.

<Adjustment with delay element>
FIG. 9 is a circuit diagram showing still another configuration example of the double pulse generation circuit. A double pulse generation circuit 7_3 illustrated in FIG. 9 is a circuit to which a function capable of adjusting the delay element 13_5 of the double pulse generation circuit 7_1 illustrated in FIG. 3 to an arbitrary delay value is added. The test pulse TP is input from the node C and input to delay buffers 13_17 to 20 connected in series in multiple stages. The selector 14_11 selects and outputs a signal having a desired delay amount from the tap and outputs it to the node D. A double pulse signal TDP is generated by taking the exclusive OR of the test pulse TP of the node C and the signal of the node D after a desired delay by the exclusive OR gate 12_13. The pulse width (on-state period) of the launch clock pulse (TCKL) and the capture clock pulse (TCCK) of the double pulse signal TDP can be adjusted by the number of stages of delay elements specified by the delay adjustment control signal. The operation waveform is the same as that of the timing chart shown in FIG. The width of the time t2 to t4 and the time t6 to t7 is configured to be adjustable by the circuit.

  Thereby, the on-state period of the double pulse signal TDP can be arbitrarily determined for each delay element.

  In the double pulse generation circuit 7_1 in the first embodiment shown in FIG. 3, the test pulse TP is turned on by giving a constant delay to the test pulse TP output from the pulse width adjustment circuit 9_1 using the delay element 13_5. A double pulse is generated in which the state period is the rising interval of two pulses included in the double pulse signal TDP. The test pulse TP is required to have an on-state period larger than the delay amount of the delay element 13_5. Further, since the delay amount of the delay element 13_5 is an on-state period of the double pulse signal TDP, if this is extremely small, the pulse widths of the launch clock pulse (TCKL) and the capture clock pulse (TCCK) may be significantly reduced. is there.

  When the double pulse generation circuit 7_3 of the third embodiment is used, various delay values can be selected for the test pulse TP. Therefore, by selecting a delay value that is an on-state period of the double pulse signal TDP, the test can be performed. A double pulse having a timing interval can be stably generated.

[Embodiment 4] <Launch / Capture Selection Function>
As described above, in the first to third embodiments, one asynchronous transfer path from the flip-flop 1_1 that is the launch flip-flop (TC) to the flip-flop 2_1 that is the capture flip-flop (RC) with respect to the test target logic circuit 4. It explained focusing on. In practice, there may be a transfer path from a plurality of flip-flops in the clock domain of the user clock 1 (CLK1) to a plurality of flip-flops in the clock domain of the user clock 2 (CLK2). Conversely, there may be a case where transfer paths from a plurality of flip-flops in the clock domain of the user clock 2 (CLK2) to a plurality of flip-flops in the clock domain of the user clock 1 (CLK1) coexist.

  FIG. 10 relates to the first to third embodiments when there are transfer paths from a plurality of flip-flops in the clock domain of user clock 1 (CLK1) to a plurality of flip-flops in the clock domain of user clock 2 (CLK2). It is a block diagram which shows the structure of a test clock supply circuit.

  The test clock supply circuit 6 includes a pulse width adjustment circuit 9, a double pulse generation circuit 7, a launch clock extraction / user clock switching circuit 81, and a capture clock extraction / user clock switching circuit 82. The launch clock extraction / user clock switching circuit 81 may be configured by using the launch clock / capture clock selection circuit 8 shown in FIG. 3 and specifying launch selection by a capture selection signal, or fixed to launch selection. Alternatively, it may be configured with a launch extraction dedicated logic circuit. The capture clock extraction / user clock switching circuit 82 may be configured by using the launch clock / capture clock selection circuit 8 shown in FIG. 3 and specifying capture selection by a capture selection signal, or is fixed to capture selection. Alternatively, it may be composed of a logic circuit dedicated to capture extraction.

  Even if the flip-flops 1_1 and 1_2 included in the clock domain of CLK1 are launch flip-flops of different asynchronous transfer paths, the flip-flops 1_1 and 1_2 may be connected to the same launch clock extraction / user clock switching circuit 81. Even if the flip-flops 2_1 and 2_2 included in the clock domain of CLK2 are capture flip-flops of different asynchronous transfer paths, the flip-flops 2_1 and 2_2 may be connected to the same capture clock extraction / user clock switching circuit 82. When flip-flops 1_1 and 1_2 are launch flip-flops, launch selection is input to launch clock extraction / user clock switching circuit 81. When flip-flops 2_1 and 2_2 are capture flip-flops, capture clock extraction / user clock switching circuit 82 is input. Is the capture selection. When performing a transition fault test in which a certain asynchronous transfer path and another asynchronous transfer path have different delay times as determination values, the respective transition fault tests may be executed at different timings. For example, an asynchronous transfer path in which the flip-flop 1_1 is a launch flip-flop and the flip-flop 2_1 is a capture flip-flop is different from an asynchronous transfer path in which the flip-flop 1_2 is a launch flip-flop and the flip-flop 2_2 is a capture flip-flop. This is a case where the delay time is used as a determination value.

  FIG. 11 is an explanatory diagram of a launch / capture selection function (embodiment 4) in the test clock supply circuit.

  There are transfer paths from a plurality of flip-flops in the clock domain of user clock 1 (CLK1) to a plurality of flip-flops in the clock domain of user clock 2 (CLK2), and a plurality of clock domains in the clock domain of user clock 2 (CLK2) There are cases where transfer paths from the flip-flop to a plurality of flip-flops in the clock domain of the user clock 1 (CLK1) coexist. FIG. 11 shows an example in which two asynchronous transfer paths coexist in addition to the asynchronous transfer path in which the flip-flop 1_1 is the launch flip-flop and the flip-flop 2_1 is the capture flip-flop. The other two asynchronous transfer paths are a path in which flip-flop 2_1 is a launch flip-flop, flip-flop 1_2 is a capture flip-flop, flip-flop 1_2 is a launch flip-flop, and flip-flop 2_2 is a capture flip-flop. is there. Since the flip-flop 2_1 is both a capture flip-flop and a launch flip-flop, the launch clock / capture clock selection circuit 8_1 is configured to be selectable by a launch / capture selection 1 signal. Similarly, since the flip-flop 2_2 becomes both a capture flip-flop and a launch flip-flop, the launch clock / capture clock selection circuit 8_2 is configured to be selectable by a launch / capture selection 2 signal.

  As described above, at least one of the launch clock / capture clock selection circuits 8_1 and 8_2 extracts either the launch clock pulse TCKL or the capture clock pulse TCCC from the double pulse signal TDP output from the double pulse generation circuit 7. It is configured so that it can be selected.

  Thus, if one launch flip-flop is also a capture flip-flop of another asynchronous transfer path, or if one capture flip-flop is also a launch flip-flop of another asynchronous transfer path, either or both In addition, the transition fault test of the other signal propagation path can be performed.

[Embodiment 5] <Scan test>
FIG. 12 is a block diagram illustrating a configuration example when a scan test circuit is added to a semiconductor integrated circuit (LSI) including a test clock supply circuit (fifth embodiment).

  The flip-flops 1_1, 1_2, 2_1, and 2_2 are replaced with scan-compatible flip-flops, respectively. The scan-compatible flip-flop is a flip-flop including a selector that switches data input during normal operation and scan-in during a scan test as inputs according to a scan enable signal. The scan chain 1 is formed in a plurality of flip-flops in the clock domain of the user clock 1 (CLK1) including the flip-flop 1_1 and the flip-flop 1_2, and the clock domain of the user clock 2 (CLK2) including the flip-flop 2_1 and the flip-flop 2_2 is formed. The scan chain 2 is formed in a plurality of flip-flops. A scan enable signal is further input to the test clock circuit 6 to constitute a scan test circuit.

  During the scan test operation, the scan test circuit included in the test clock circuit 6 supplies the shift clock 1 (TSCK1) to the flip-flop 1_1 and the flip-flop 1_2 to shift the scan chain 1, and the flip-flop 2_1 and the flip-flop 2_2 Is supplied with a shift clock 2 (TSCK2) to shift the scan chain 2.

  FIG. 14 is a timing chart illustrating an operation of a semiconductor integrated circuit (LSI) including the test clock supply circuit according to the fifth embodiment. Time is taken on the horizontal axis, and the input pulse TIN from the top in the vertical axis direction, the test pulse TP output from the pulse width adjustment circuit 9, the TDP output from the double pulse generation circuit 7, the scan enable, the shift clock 1, the capture clock The output of the selection circuit 8_1, the scan chain 1, the shift clock 2, the output of the capture clock selection circuit 8_2, and the waveform of the scan chain 2 are shown. Times t0 to t1 when the scan enable signal is high and after time t5 are periods of a shift operation using the scan chain, and times t1 to t5 are periods in which a transition failure test of the asynchronous transfer circuit is performed. During the period from time t0 to t1 when the scan enable signal is high and after time t5, a stuck-at fault test or a transition fault test for each clock domain may be performed as in the conventional test.

  At time t0 to t1, the shift clock 1 is output from the capture clock selection circuit 8_1, the scan chain 1 shifts in synchronization with the shift clock 1, and the input data is transferred to the launch flip-flop. The shift clock 2 is output from the capture clock selection circuit 8_2, and the scan chain 2 performs a shift operation in synchronization with the shift clock 2. If the previous test result is held in the flip-flop in the clock domain of the user clock 2, it is output by this shift operation.

  The transition fault test of the asynchronous transfer circuit is started from time t1. An input pulse TIN having a width from time t2 to t3 is input, the pulse width is adjusted based on the test timing setting designated by the pulse width adjustment circuit 9, and a test pulse TP having a width from time t2 to t4 is output. . The double pulse generation circuit 7 outputs two pulses having an on-state period specified by the high width setting from the rising edge and falling edge of the test pulse TP at time t2 and time t4. A launch clock pulse TCKL is output from the capture clock selection circuit 8_1 at time t2. From the launch flip-flop, the input data transferred by the shift operation up to time t1 is output. A capture clock pulse TCKC is output from the capture clock selection circuit 8_2 at time t4. In the capture flip-flop, the signal transition starting from the transition of the input data output from the launch flip-flop propagates through the asynchronous transfer path in the test target logic circuit 4 and is captured as output data. If the signal propagation delay is shorter than the time width between times t2 and t4, the correct result is captured by the capture flip-flop, but if it is longer, the result is incorrect. The result captured by the capture flip-flop is output via the scan chain 2 by a shift operation after time t5.

  As a result, during the scan test operation, the stuck-at fault test and the transition fault test of the synchronous circuit can be executed in each clock domain. Further, the signal propagation path in the asynchronous transfer circuit can be performed using the shift operation of the scan test. The test pattern for the transition fault test of the combinational circuit that constitutes can be supplied, and the result of the transition fault test can be output.

  FIG. 13 is a block diagram showing another configuration example when a scan test circuit is added to a semiconductor integrated circuit (LSI) including a test clock supply circuit (Embodiment 5). The difference from the semiconductor integrated circuit (LSI) 10 shown in FIG. 12 is that the scan-corresponding flip-flop 11_1 that constitutes a register that gives the test timing setting to the pulse width adjusting circuit 9 and the high width setting to the double pulse generation circuit 7 are given. The scan-corresponding flip-flop 11_2 constituting the register is further provided. Each of the flip-flops 11_1 and 11_2 may be composed of a plurality of flip-flops, and constitutes a scan chain 3 that performs a shift operation in synchronization with the shift clock 3.

  Similarly to the scan chain 1 and the scan chain 2, the scan chain 3 performs a shift operation during the period of time t0 to t1 shown in FIG. 14, and the test timing setting value and the high width setting value are respectively set to the flip-flop 11_1 and the flip-flop. Forward to step 11_2.

  Thereby, it is not necessary to provide separate writing means for the test timing setting and the high width setting, and an appropriate value can be set in alignment with the scan test.

  The scan chain 1, the scan chain 2, and the scan chain 3 are shown as examples that are configured independently of each other. You can also

[Sixth Embodiment] <Design Method and Design Program>
A design method using a design tool for inserting a transition fault test circuit of an asynchronous transfer circuit described in the above embodiment into a semiconductor integrated circuit (LSI) including a plurality of clock domains that operate asynchronously, and The design program will be described.

  FIG. 15 is a flowchart showing the operation of the design tool for incorporating the test clock supply circuit according to the first to fifth embodiments into the LSI to be designed. FIG. 16 is a flowchart showing the operation of the design tool for giving a test pattern to the test clock supply circuit incorporated in the LSI to be designed.

  A design program 20 of a semiconductor integrated circuit 10 according to a representative embodiment disclosed in the present application includes a circuit mounting tool 21, which is a data processing unit, a layout tool 23, a STA (Static Timing Analysis) tool 24, data This can be executed by an electronic computer including the storage unit 22 and is configured as follows.

  The data storage unit 22 stores a netlist netlist-1 including a plurality of clock domains that are asynchronous with each other during normal operation, clock source information, and product specifications. The design program 20 uses the circuit mounting tool 21 to execute a step (S1) of extracting a test path that is a logic circuit with asynchronous data transfer from netlist-1. Here, the circuit implementation tool 21 traces netlist-1 based on the clock source information, recognizes the clock domain, extracts a logic circuit having asynchronous data transfer based on the product specification, and the result is tested. The data is output to the data storage unit 22 as a path.

  The circuit mounting tool 21 refers to the extracted test path, and transmits a clock source (TCLK) on the transmission circuit side that is a transmission flip-flop (TC) and a clock source (TCLK) on the reception circuit side that is a reception flip-flop (RC). RCLK) is extracted (S2), and the test clock supply circuit 6 is inserted into netlist-1. More specifically, launch clock / capture clock selection circuits 8_1 and 8_2 are inserted into the clock on the transmission circuit side and the clock on the reception circuit side (S3), and the pulse width adjustment circuit 9 and the double pulse generation circuit 7 are further inserted. The double pulse signal TDP is inserted and wired to the launch clock / capture clock selection circuits 8_1 and 8_2 (S4). After that, the scan in the netlist-1 is replaced with a scan-compatible flip-flop to form a scan chain, and a switching circuit for inputting a shift clock and an input / output circuit for shift data are inserted. (S5), and outputs the scanned netlist netlist-2 to the data storage unit 22. The netlist-2 is input to the layout tool 23, and the layout step (S6) is executed. This is the same as the normal layout process. As a result, a netlist netlist-3 including parasitic resistance and parasitic capacitance such as wiring resistance and wiring capacitance is output to the data storage unit 22. The netlist-3 is input to the STA tool 24, delay information in the circuit is calculated (S7), and layout information is output to the data storage unit 22.

  Next, the circuit mounting tool 21 refers to the netlist netlist-3 including parasitic resistance and parasitic capacitance, the layout information, the clock source information, the product specification, and the path under test with reference to the path under test. Is estimated as a test timing α (S8). The circuit mounting tool 21 refers to the layout information and delays δTC from the clock source (TCLK) on the transmission circuit side to the transmission flip-flop (TC) and from the clock source (RCLK) on the reception circuit side to the reception flip-flop (RC). ) Until the delay δRC is calculated and acquired (S9).

  When the pulse width adjustment circuit 9 is a circuit that adjusts the pulse width by adjusting the number of stages of delay by a plurality of delay buffers connected in series as shown in FIG. The delay per buffer stage is calculated and acquired as a delay unit δ1 (S10).

  When the double pulse generation circuit 7 is a circuit that adjusts the number of stages of delay by a plurality of delay buffers connected in series as shown in FIG. 9 and adjusts the high width, the circuit mounting tool 21 has a delay buffer. The delay per stage is calculated and acquired as a delay unit δ2 (S11).

  Adjustment values (the pulse width of the input pulse TIN and the pulse width adjustment circuit 9) for generating the launch clock pulse TCKL and the capture clock pulse TCCC at the timing closest to α on the stricter side than the test timing α defined in step S8. The test timing setting value input to (1) is calculated (S12). The high width setting value input to the double pulse generation circuit 7 may be calculated together. A test pattern generation condition (such as an initialization sequence) is created from the calculated adjustment value (S13), and a test pattern is generated by ATPG (Automatic Test Pattern Generator) and stored in the data storage unit 22 (S14).

  The operation of the design tool will be described in more detail.

  17, 18, and 19 are explanatory diagrams for explaining the operation of the design tool in FIG. 15 in which the test clock supply circuit 6 is incorporated in the LSI to be designed. Asynchronous transfer is performed in the net list of the LSI to be designed. A flip-flop and a clock supply circuit 6 related to the circuit are shown. FIG. 17 shows a netlist before the test clock supply circuit 6 is incorporated, which corresponds to netlist-1 in the flowchart shown in FIG. FIG. 18 is a netlist after the test clock supply circuit 6 is incorporated. In the flowchart shown in FIG. 15, the netlist is in a state before being scanned (S5). FIG. 19 is a scan (S5) netlist, which corresponds to netlist-2 in the flowchart shown in FIG.

  The netlist before incorporating the test clock supply circuit 6 shown in FIG. 17 includes PLL1 (18_1) and PLL2 (18_2), clock trees 19_1 and 19_2, flip-flops 1_1, 1_2, 2_1, 2_2, and combinations. Circuits 4, 5_1, and 5_2 are included. Each of PLL1 (18_1) and PLL2 (18_2) is a clock supply source of user clock 1 (CLK1) and user clock 2 (CLK2) which are asynchronous with each other. The flip-flops 1_1 and 1_2 are included in the clock domain that operates in synchronization with the user clock 1 (CLK1) during normal operation, and the flip-flops 2_1 and 2_2 are included in the clock domain of the user clock 2 (CLK2). The clock tree 19_1 is a clock tree that supplies a clock to flip-flops included in the clock domain of CLK1, such as flip-flops 1_1 and 1_2, and the clock tree 19_2 is included in the clock domain of CLK2 such as flip-flops 2_1 and 2_2. It is a clock tree which supplies a clock with respect to a flip-flop. The combinational circuit 5_1 is included in the clock domain of CLK1 and is configured with a synchronous transfer path synchronized with CLK1, and the combinational circuit 5_2 is included in the clock domain of CLK2 and configured with a synchronous transfer path synchronized with CLK2. 4 includes an asynchronous transfer path from the clock domain of CLK1 to the clock domain of CLK2. The asynchronous transfer path included in the combinational circuit 4 is the tested path of this embodiment. The flip-flop_1_1 is a transmission flip-flop (launch flip-flop) of this asynchronous transfer path, and the flip-flop 2_1 is a reception flip-flop (capture flip-flop).

  In step S1 of the flowchart shown in FIG. 15, it is input from the clock source information that PLL1 (18_1) and PLL2 (18_2) are clock sources of asynchronous clocks, and the asynchronous transfer path included in the combinational circuit 4 is tested. Extracted as a path. In step S2, the clock tree 19_1 that supplies a clock to the transmission flip-flop (launch flip-flop) of the path under test is traced, and PLL1 (18_1) is extracted as the transmission-side clock source TCLK. Further, the clock tree 19_2 that supplies a clock to the reception flip-flop (capture flip-flop) is traced, and PLL2 (18_2) is extracted as the reception-side clock source RCLK. In step S3, launch clock / capture clock selection circuits (TCKL / TCKC selection circuits) 8_1 and 8_2 are inserted into the extracted clock sources on the transmission side and the reception side as shown in FIG. In step S4, the pulse width adjustment circuit 9 and the double pulse generation circuit 7 are further inserted, and the double pulse signal TDP is wired to the launch clock / capture clock selection circuits 8_1 and 8_2. Thereby, the insertion of the test clock supply circuit 6 is completed.

  Next, scanning (S5) is performed, and the netlist shown in FIG. 19 is output as netlist-2. The flip-flops 1_1, 1_2, 2_1, and 2_2 are replaced with scan-compatible flip-flops to form a scan chain. Selectors (14_12, 14_13) for switching between user clocks (CLK1, CLK2) and shift clocks (TSCK1, TSCK2) are inserted in the clock source. Further, the scan enable signal is connected to the flip-flops 1_1, 1_2, 2_1, 2_2 and the selectors 14_12, 14_13.

  A method for calculating the delay time from the launch clock pulse to the capture clock pulse will be described. FIGS. 19 and 20 explain how to calculate an adjustment value such as a delay time from the launch clock pulse to the capture clock pulse in the operation of the design tool of FIG. 15 in which the test clock supply circuit is incorporated in the LSI to be designed. FIG. In the timing chart shown in FIG. 20, the horizontal axis is time, and in the vertical axis direction, from the top, the input pulse TIN, the test pulse TP that is the output of the pulse width adjustment circuit, and the double pulse signal that is the output of the double pulse generation circuit The launch clock pulse TLCK and the capture clock pulse RLCK, which are the outputs of the TD and launch clock / capture clock selection circuits 8_1 and 8_2, are shown. The launch clock pulse TLCK and the capture clock pulse RLCK are waveforms on the root side of the clock trees 19_1 and 19_2, and the launch clock pulse TCKL reaching the transmission flip-flop (launch flip-flop) and the reception flip-flop (capture flip-flop) It is distinguished from the capture clock pulse TCCC.

  In step S8, the signal propagation delay of the test path that is an asynchronous transfer path included in the combinational circuit 4 is estimated and defined as the test timing α. At this time, the netlist shown in FIG. 19 is netlist-3 by adding parasitic resistance and parasitic capacitance with reference to the layout information. In step S9, the clock tree 19_1 is traced to obtain the propagation delay δTC of the clock from the transmission side clock source TCLK to the flip-flop 1_1 which is a transmission flip-flop (launch flip-flop). Further, the clock tree 19_2 is traced to obtain the propagation delay δRC of the clock from the receiving clock source RCLK to the flip-flop 2_1 that is the receiving flip-flop (capture flip-flop). As described above, the delay unit δ1 for adjustment in the pulse width adjustment circuit 9 and the delay unit δ2 for high width adjustment in the double pulse generation circuit 7 are calculated in steps S10 and S11.

  In step 12, the test timing set value X inputted to the pulse width adjusting circuit 9 and the high width set value Y inputted to the double pulse generating circuit 7 can be calculated by the following equations.

  Here, β is the pulse width of the input pulse TIN input to the pulse width adjustment circuit 9. In FIG. 20, it corresponds to the time t0 to t1.

  When the test timing α is shorter than the time from the arrival of the launch clock pulse TCKL at the transmission flip-flop (launch flip-flop) to the arrival of the launch clock pulse TCKL at the reception flip-flop (capture flip-flop) It is a criterion for determining. α− (δRC−δTC) is a delay time from the launch clock pulse TLCK to the capture clock pulse RLCK at the roots of the clock trees 19_1 and 19_2. This corresponds to the high width of the test pulse TP output from the pulse width adjustment circuit 9. As shown in FIG. 20, adjustment is performed so that the launch clock pulse TLCK rises at time t0 and the capture clock pulse RLCK rises at time t3. A value obtained by subtracting the pulse width β of the input pulse TIN from the high width (time t0 to t3) α− (δRC−δTC) of the test pulse TP is used as an adjustment delay unit δ1 in the pulse width adjusting circuit 9 in steps. It is given as a set value X. In order to judge more strictly, X should be obtained by truncation.

  The high periods t0 to t2 and t3 to t4 of the double pulse signal TDG generated by the double pulse generation circuit 7 can be set to the same value as the low periods t2 to t4 by the value of Y calculated by the above formula. . The high width of the launch clock pulse TLCK at times t0 to t2 and the high width of the capture clock pulse RLCK at times t3 to t4 are both set to α / 2. Y is calculated in increments of the adjustment delay unit δ 2 in the double pulse generation circuit 7.

  As a result, in a semiconductor integrated circuit including an asynchronous transfer circuit between a plurality of clock domains that operate asynchronously during normal operation, the transition fault test circuit that enables a transition fault test of the asynchronous transfer circuit to be performed on the semiconductor integrated circuit. Can be inserted. The delay time from the launch clock pulse (TCKL) to the capture clock pulse (TCCK) can be arbitrarily set based on the judgment criterion of the transition fault test of the combinational circuit constituting the signal propagation path in the asynchronous transfer circuit. .

  The design program 20 is configured to include a step S8 for estimating the signal propagation delay in the combinational circuit 4 extracted as the test path, so that the test clock is supplied based on the estimated signal propagation delay of the test path. An adjustment value to be set in the circuit can be calculated. The signal propagation delay in the combinational circuit 4 extracted as the test path can be estimated by the STA in step S7. Furthermore, it is possible to estimate more accurately using layout information after layout.

  Also, by performing scanning in step S5, it becomes easy to perform the stuck-at fault test and the transition fault test for the synchronous transfer combination circuits 5_1 and 5_2 in each clock domain. This scan circuit can perform an operation of giving an input pattern to a path under test by scan-in and outputting a test result by scan-out for a transition fault test of the asynchronous transfer circuit.

  FIG. 21 is an explanatory diagram for explaining another operation example of the design tool of FIG. 15 in which the test clock supply circuit is incorporated in the LSI to be designed. In FIG. 19, launch clock / capture clock selection circuits 8_1 and 8_2 are inserted at the roots of the clock trees 19_1 and 19_2, whereas in FIG. 21, a transmission flip-flop (launch flip-flop) and a reception flip-flop (capture flip-flop) are inserted. Insert into each clock pin. Since the test clock supply circuit 6 is inserted for each path to be tested, a transition fault test can be performed on a plurality of paths to be tested simultaneously in parallel.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although the case where the number of clock domains included in a semiconductor integrated circuit (LSI) is two has been described, each embodiment can be applied to a case where the number of clock domains is three or more. The flip-flop may be a storage element that holds the data and state of the pipeline stage in synchronization with the clock, and widely includes latches, registers, and the like. The clock supply method, the logic circuit method, and the like can be arbitrarily combined.

DESCRIPTION OF SYMBOLS 1 Flip-flop in clock domain of user clock 1 2 Flip-flop in clock domain of user clock 2 3 Flip-flop in clock domain of user clock 3 4 Combinational circuit in asynchronous transfer circuit (logic to be tested)
5 Combinational circuit in the synchronous circuit)
6 Test clock supply circuit 7 Double pulse generation circuit 8 Launch clock / capture clock selection circuit (TCKL / TCKC selection circuit)
81 launch clock extraction / user clock switching circuit 82 capture clock extraction / user clock switching circuit 9 pulse width adjustment circuit 10 semiconductor integrated circuit (LSI)
11 flip-flop 12 corresponding to scan 12 logic gate 13 buffer 14 selector 15 flip-flop 16 reverse phase flip-flop 17 counter circuit 18 clock supply source (PLL)
19 Clock Tree 20 Design Program (Design Tool)
21 circuit mounting tool 22 data storage unit 23 layout tool 24 STA tool TC transmission flip-flop (launch flip-flop)
RC reception flip-flop (capture flip-flop)
CLK1 User clock 1
CLK2 User clock 2
TCK Test clock TSCK Shift clock TIN Input pulse TP Test pulse TDP Double pulse signal TLCK, TCKL Launch clock pulse RLCK, TCCC Capture clock pulse

Claims (20)

A first flip-flop that operates in synchronization with the first clock during normal operation, a second flip-flop that operates in synchronization with the second clock asynchronous with the first clock during normal operation, and an output of the first flip-flop A combinational circuit connected to the input of the second flip-flop, and a test clock supply circuit,
The test clock supply circuit is configured to be able to supply a launch clock pulse to the first flip-flop and a capture clock pulse to the second flip-flop during a transition fault test operation of the combinational circuit. A semiconductor integrated circuit configured so that a delay time from the capture clock pulse to the capture clock pulse can be set. The test clock supply circuit according to claim 1,
A double pulse generation circuit that receives a test pulse and generates a double pulse signal including the launch clock pulse and the capture clock pulse from a rising edge and a falling edge of the test pulse;
A first launch clock / capture clock selection circuit capable of extracting the launch clock pulse from the double pulse signal and supplying it to the first flip-flop;
A semiconductor integrated circuit comprising: a second launch clock / capture clock selection circuit capable of extracting the capture clock pulse from the double pulse signal and supplying it to the second flip-flop.   3. The method of claim 2, wherein at least one of the first launch clock / capture clock selection circuit and the second launch clock / capture clock selection circuit selects the launch clock pulse or the capture clock pulse from the double pulse signal. A semiconductor integrated circuit that can be extracted.   3. The semiconductor integrated circuit according to claim 2, wherein the test clock supply circuit further includes a pulse width adjustment circuit capable of adjusting the pulse width of an input pulse to be input and outputting the pulse as the test pulse.   3. The semiconductor integrated circuit according to claim 2, wherein the test clock supply circuit further includes a pulse width adjustment circuit capable of setting a pulse width of the test pulse based on an input test clock.   3. The semiconductor integrated circuit according to claim 2, wherein the double pulse generation circuit is configured to be capable of adjusting a pulse width of the launch clock pulse and the capture clock pulse. In Claim 1, further comprising a first scan chain including the first flip-flop, a second scan chain including the second flip-flop, and a scan test circuit,
The scan test circuit supplies a first shift clock to the first flip-flop to shift the first scan chain during a scan test operation, and supplies a second shift clock to the second flip-flop. A semiconductor integrated circuit for shifting the second scan chain. In Claim 1, further comprising a scan chain including the first flip-flop and the second flip-flop, and a scan test circuit,
The scan test circuit is a semiconductor integrated circuit that shifts the scan chain by supplying a shift clock to each of the first flip-flop and the second flip-flop during a scan test operation. A design program for a semiconductor integrated circuit, which is executed by an electronic computer including a data processing unit and a data storage unit, and includes a plurality of clock domains that are asynchronous with each other during normal operation by being executed by the data processing unit. The signal is propagated between the asynchronous clock domains included in the first netlist based on the first netlist stored in the data storage unit and the clock source information corresponding to the first netlist. A step of extracting a transmission flip-flop, a reception flip-flop, and a combinational circuit connected to an input of the reception flip-flop from an output of the transmission flip-flop, and being executed by the data processing unit , A test clock supply circuit is inserted into the first netlist. And a step of generating a net list,
The test clock supply circuit is configured to be able to supply a launch clock pulse to the transmission flip-flop and a capture clock pulse to the reception flip-flop during a transition fault test operation of the combinational circuit. A program for designing a semiconductor integrated circuit that is configured so that a delay time until a capture clock pulse can be set.   10. The program for designing a semiconductor integrated circuit according to claim 9, further comprising a step of estimating a signal propagation delay in the combinational circuit extracted as the test path.   10. The design of a semiconductor integrated circuit according to claim 9, further comprising the step of replacing a flip-flop included in the second netlist with a scan-compatible flip-flop and inserting a scan circuit to generate a third netlist. program.   12. The step of executing layout with the third netlist as input and generating a fourth netlist including parasitic resistance and parasitic capacitance after layout, and based on the fourth netlist, the test target And a step of calculating a signal propagation delay in the combinational circuit extracted as a path.   10. The double pulse generation circuit according to claim 9, wherein the test clock supply circuit receives a test pulse and generates the launch clock pulse and the capture clock pulse from a rising edge and a falling edge of the test pulse; A first launch clock / capture clock selection circuit capable of extracting the launch clock pulse from a double pulse signal and supplying it to the transmission flip-flop; and extracting the capture clock pulse from the double pulse signal to the reception flip-flop A design program for a semiconductor integrated circuit, comprising: a second launch clock / capture clock selection circuit that can be supplied; and a pulse width adjustment circuit capable of adjusting a pulse width of the test pulse.   14. The step of executing layout by inputting a net list based on the first net list and generating a post-layout fourth net list, and extracting the test path based on the fourth net list according to claim 13. A step of calculating a signal propagation delay in the combinational circuit, and a step of calculating an amount of a pulse width adjustable by the pulse width adjustment circuit based on the fourth netlist. Design program. A method for designing a semiconductor integrated circuit, which is executed by an electronic computer including a data processing unit and a data storage unit, and includes a plurality of clock domains that are asynchronous with each other during normal operation by being executed by the data processing unit. The signal is propagated between the asynchronous clock domains included in the first netlist based on the first netlist stored in the data storage unit and the clock source information corresponding to the first netlist. A step of extracting a transmission flip-flop, a reception flip-flop, and a combinational circuit connected to an input of the reception flip-flop from an output of the transmission flip-flop, and being executed by the data processing unit , A test clock supply circuit is inserted into the first netlist, and the second netlist is inserted. And generating a list,
The test clock supply circuit is configured to be able to supply a launch clock pulse to the transmission flip-flop and a capture clock pulse to the reception flip-flop during a transition fault test operation of the combinational circuit. A method for designing a semiconductor integrated circuit, in which a delay time until a capture clock pulse can be set.   16. The method for designing a semiconductor integrated circuit according to claim 15, further comprising a step of estimating a signal propagation delay in the combinational circuit extracted as the test path.   16. The design of a semiconductor integrated circuit according to claim 15, further comprising the step of replacing a flip-flop included in the second netlist with a scan-compatible flip-flop and inserting a scan circuit to generate a third netlist. Method.   18. The step of executing layout by using the third netlist as an input to generate a fourth netlist including post-layout parasitic resistance and parasitic capacitance, and based on the fourth netlist, the test target And a step of calculating a signal propagation delay in the combinational circuit extracted as a path.   16. The double pulse generation circuit according to claim 15, wherein the test clock supply circuit receives a test pulse and generates the launch clock pulse and the capture clock pulse from a rising edge and a falling edge of the test pulse, A first launch clock / capture clock selection circuit capable of extracting the launch clock pulse from a double pulse signal and supplying it to the transmission flip-flop; and extracting the capture clock pulse from the double pulse signal to the reception flip-flop A method for designing a semiconductor integrated circuit, comprising: a second launch clock / capture clock selection circuit that can be supplied; and a pulse width adjustment circuit capable of adjusting a pulse width of the test pulse.   20. The step of executing layout by inputting a netlist based on the first netlist as an input to generate a fourth netlist after layout, and extracting as the path under test based on the fourth netlist A step of calculating a signal propagation delay in the combinational circuit, and a step of calculating an amount of a pulse width adjustable by the pulse width adjustment circuit based on the fourth netlist. Design method.

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