JP2015018897A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents the occurrence of voids in a resin part between a chip and a substrate or between chips even when flip-chip bonding is used.SOLUTION: A semiconductor device 200 is manufactured by holding by a bonding tool 39, one surface of a memory chip 207 having a rear face bump 293 on the other surface and stacking the memory chip 207b via an insulating adhesive layer 227, on the memory chip 207a on which surface bumps 273 are formed and filling up a gap between the memory chip 207a and the memory chip 207b with the insulating adhesive layer 227. When a bonding tool 39 holds the memory chip 207b, the memory chip 207b is arched in a manner such that a central part of the other surface becomes higher than a peripheral part and when the memory chip 207b is stacked, the memory chip 207b is stacked on the memory chip 207a via the insulating adhesive layer 227 in a state where the memory chip 207b is arched.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a BGA (Ball Grid Array) type semiconductor device, a semiconductor chip is mounted on one surface of a wiring board, and balls such as solder are arranged as electrodes on the other surface so as to have a predetermined array shape. The chip is electrically connected via a wiring board, and the semiconductor chip is sealed with a resin.

  Here, as a structure for electrically connecting the ball and the semiconductor chip via the wiring substrate, a structure using wire bonding is known.

  On the other hand, as a structure other than wire bonding, FC-BGA in which a semiconductor chip is mounted on a wiring board by flip chip bonding has been studied.

  For example, in Patent Document 1, NCP (Non Conductive Film, insulating adhesive layer) is pre-applied on a wiring board, and a semiconductor chip having bump electrodes is held on the back surface with a flat suction surface bonding tool, A technique for flip-chip mounting a semiconductor chip on a wiring board is disclosed (Patent Document 1).

  Also, in Patent Document 2, a semiconductor chip having a through electrode with NCF attached to the back surface is held by a bonding tool having a flat suction surface, and the semiconductor chip has NCF attached to another semiconductor chip. A technique for flip-chip mounting is disclosed (Patent Document 2).

JP 2005-191053 A JP 2013-016577 A

  Here, in the techniques such as Patent Documents 1 and 2, since the bump electrodes are formed on both surfaces, depending on the interval between the bump electrode groups, the portion between the bump electrodes is sucked and held by the bonding tool. There is a case.

  However, when the central portion of the semiconductor chip is recessed, there is a problem that voids are trapped in the recessed portion when the semiconductor chip is flip-chip mounted on the previously applied NCP.

  If a void is trapped in the resin portion between the chip and the substrate or between the chips, the void expands when the temperature rises, causing a crack, which may reduce the reliability of the semiconductor device.

  Therefore, even when flip chip bonding is used, there has been a demand for a method of manufacturing a semiconductor device in which no void is generated in the resin portion between the chip and the substrate or between the chips.

  According to a first aspect of the present invention, (a) the other surface of the first substrate having a plurality of bump electrodes formed on one surface is held by a bonding tool, and (b) is held by the bonding tool. The first substrate is laminated on a second substrate having a plurality of electrodes formed on one surface via a resin adhesive layer, and the plurality of bump electrodes of the first substrate are stacked on the second substrate. Electrically connecting to the plurality of electrodes, and filling the resin adhesive layer in a gap between the first and second substrates, wherein (a) The other surface is held by a bonding tool in a state where the central portion of one surface is warped so as to be higher than the peripheral portion, and (b) shows the first substrate held by the bonding tool. The resin adhesive layer is left in a state where the substrate is warped. To be stacked on the second substrate, a manufacturing method of a semiconductor device.

  According to the present invention, it is possible to provide a method of manufacturing a semiconductor device in which no void is generated in a resin portion between a chip and a substrate or between chips even when flip chip bonding is used.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. It is an expanded sectional view of the surface bump vicinity of FIG. It is a figure which shows the procedure of manufacture of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the procedure of manufacture of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the procedure of manufacture of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the chip laminated body which concerns on 1st Embodiment, Comprising: (a) is a top view, (b) is AA sectional drawing of (a). It is a figure which shows the procedure of manufacture of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the procedure of manufacture of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the procedure of manufacture of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail based on the drawings.

  First, a schematic configuration of a semiconductor device 200 according to the first embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, the semiconductor device 200 includes a wiring board 201 having a plurality of connection pads 217, a logic chip 203 connected to the connection pads 217, and a chip stack 205 stacked on the logic chip 203. doing.

  The chip stack 205 is formed by stacking a plurality of memory chips 207.

  In addition, the semiconductor device 200 includes a sealing body 212 as a sealing resin provided so as to cover one surface of the wiring substrate 201, the logic chip 203, and the chip stacked body 205.

  Next, with reference to FIG. 1 and FIG. 2, details of members constituting the semiconductor device 200 will be described.

  The wiring board 201 includes a base material 213 such as glass epoxy having a rectangular planar shape, and an insulating film 218 such as a solder resist provided on both surfaces of the base material 213.

  In addition, a plurality of connection pads 217 are formed on a portion exposed from the insulating film 218 of the wiring pattern (not shown) on one side of the base material 213 (the side on which the logic chip 203 and the chip stack 205 are provided) A plurality of lands 219 are formed on the other surface of the base 213 exposed from the insulating film 218 of the wiring pattern (not shown).

  The connection pad 217 and the land 219 corresponding thereto are electrically connected by a wiring pattern (not shown).

  Further, a solder ball 216 as an external terminal is mounted on the land 219.

  On the other hand, the logic chip 203 and the chip stacked body 205 are mounted on one surface of the base material 213 by flip chip mounting.

  As shown in FIG. 2, the memory chip 207 constituting the chip stack 205 includes a silicon substrate 202, and a circuit forming layer 209 on which a predetermined memory circuit (not shown) is formed on one surface of the silicon substrate 202. Have.

  A plurality of electrode pads 271 electrically connected to the memory circuit are formed in a predetermined arrangement on one surface side of the silicon substrate 202.

  An insulating protective film 283 is formed on the circuit formation layer 209 to protect the circuit formation layer 209. The protective film 283 has an opening so that the electrode pad 271 is exposed.

  Further, on one surface of the silicon substrate 202, surface bumps 273 are formed as a plurality of bump electrodes formed on the electrode pads 271 via a seed layer (not shown).

  The surface bump 273 is a columnar body such as Cu, and is formed so as to protrude from the chip surface. Further, an Ni plating layer 275 for preventing Cu diffusion and an Au plating layer 277 for preventing oxidation are formed on the surface bump 273.

  Further, a through hole is formed at a position corresponding to the electrode pad 271 in the silicon substrate 202, and the through electrode 279 is configured by filling the through hole with a conductor layer such as Cu. An insulating ring 222 is provided around the through electrode 279.

  On the other hand, a back surface bump 293 as a plurality of bump electrodes is formed on the other surface of the silicon substrate 202 via a seed layer 282, and each of the plurality of back surface bumps 293 has a corresponding front surface bump 273 via a through electrode 279. Are electrically connected.

  The back surface bump 293 is, for example, a Cu columnar body, and is formed so as to protrude from the back surface of the chip.

  A back solder layer 295 such as a Sn / Ag solder plating layer is formed on the surface of the back bump 293. The back surface solder layer 295 is arranged in a hemispherical shape on the back surface bump 293.

  Note that, among the memory chips 207, the memory chip 207a (second substrate) arranged at the top in FIG. 1 does not form the back bump 293 and the through electrode 279, so that the other memory chip 207b (first substrate) The chip thickness is larger than that of the substrate. For example, the memory chip 207a has a thickness of 100 μm, and the memory chip 207b has a thickness of 50 μm.

  The memory chip 207a and the plurality of memory chips 207b are stacked via an insulating adhesive layer 227 as a resin adhesive layer such as NCF (Non Conductive Film), for example, to constitute a chip stacked body 205.

  As shown in FIG. 1, the chip stacked body 205 is stacked and mounted on the logic chip 203 mounted on the wiring substrate 201. A chip stack 205 is stacked and mounted on the logic chip 203 so that the back surface bump 293 of the uppermost memory chip 207 is bonded to the front surface bump 273 of the logic chip 203.

  As a result, the memory chip 207a is a semiconductor chip arranged at a position farthest from the wiring board 201.

  Note that, in the structure in which the through electrodes 279 are arranged in a straight line like the chip stacked body 205, stress is generated when the through electrodes 279 expand or contract due to a temperature change in the manufacturing process, and the maximum stress is There is a possibility that chip cracks may be generated by being added to the portion of the through electrode of the semiconductor chip disposed at the position farthest from the wiring substrate 201.

  However, the memory chip 207a, which has no through electrode and no backside bump and is thicker than the other chips, is a chip disposed farthest from the wiring substrate 201 in the chip stack 205, and the through electrode of the memory chip 207a Since stress can be received on a surface that is not present, generation of chip cracks can be suppressed and the reliability of the semiconductor device 200 can be improved.

Next, a procedure for manufacturing the semiconductor device 200 will be described with reference to FIGS.
First, the memory chip 207b is manufactured by the following procedure.

  First, a semiconductor wafer 400 corresponding to the silicon substrate 202 shown in FIG.

  The semiconductor wafer 400 has a plurality of product forming portions 401 arranged in a matrix, and each product forming portion 401 corresponds to the memory chip 207b. Individual product forming portions 401 are partitioned by dicing lines 403.

  Next, as shown in FIG. 3A, a circuit formation layer 209 is formed on the silicon substrate 202, and a surface bump 273 is further formed on the surface of the circuit formation layer 209.

  Next, as shown in FIG. 3B, the semiconductor wafer 400 is inverted from the state shown in FIG. 3A, and the surface on which the circuit forming layer 209 is formed is supported on the support substrate via the adhesive layer 313. Adhere to 261. As a material for the adhesive layer 313, it is desirable to use a material that foams or has a reduced adhesive force by reacting with a specific light source (for example, laser light or UV light (ultraviolet light)).

  Further, the semiconductor wafer 400 is thinned by grinding or polishing the semiconductor wafer 400 from the surface opposite to the surface bonded to the support substrate 261 of the semiconductor wafer 400 (see the dotted line in FIG. 3B). .

  Next, a through-hole penetrating a portion of the circuit formation layer 209 and the silicon substrate 202 that faces the surface bump 273 is formed. The through hole is formed so as to expose the electrode pad 271 on which the surface bump 273 is formed.

  Next, an insulating layer (not shown) that covers the side surfaces of the through holes and the silicon substrate 202 is formed. Next, a plating mask (not shown) having an opening exposing the through hole is formed on the insulating layer.

  Next, a seed layer (for example, a Cu layer) (not shown) that covers the inner surface of the through hole, the surface of the plating mask (including the side surface of the opening), and the upper surface of the insulating layer exposed in the opening is formed. Then, a plating film (not shown) (for example, a Cu plating film) that fills the through hole and the opening is formed by electrolytic plating using the seed layer as a power feeding layer.

  Next, the plating resist film is removed, and then the seed layer not covered with the plating film is removed, whereby the through electrode 279 having one end connected to the surface bump 273 as shown in FIG. Then, a back surface bump 293 configured integrally with the other end of the through electrode 279 is formed in a lump.

  Next, as shown in FIG. 3D, an insulating adhesive layer 227 that covers the back bumps 293 is formed on the surface of the silicon substrate 202 located on the side where the back bumps 293 are provided.

  Next, as shown in FIG. 3E, a dicing tape 231 is attached to the surface of the insulating adhesive layer 227.

  Next, as shown in FIG. 3F, after the semiconductor wafer 400 is turned upside down from the state of FIG. 3E, light (for example, laser light) emitted from a specific light source via the support substrate 261 Alternatively, the adhesive layer 313 is irradiated with UV light (ultraviolet light), and the adhesive layer 313 is foamed or the adhesive force is reduced, whereby the adhesive layer 313 and the support substrate 261 are removed.

  Next, as shown in FIG. 3G, the semiconductor wafer 400 is held on a stage of a dicing apparatus (not shown), and then a surface bump 273 is formed by a dicing blade (not shown). Then, the semiconductor wafer 400 attached to the dicing tape 231 is cut along the dicing line 403 to divide the plurality of memory chips 207b into individual pieces.

  Next, a plurality of memory chips 207b (and memory chips 207a) are stacked to form a chip stacked body 205. The specific procedure is as follows.

  First, as shown in FIG. 4A, a plurality of memory chips 207b attached to the dicing tape 231 are mounted on the stage 46 of the pickup device.

  The stage 46 includes a stage main body 41 on which the dicing tape 231 is placed and a chip push-up mechanism 44.

  The stage main body 41 has a stage-side suction portion 41a on the surface.

  The tip push-up mechanism 44 includes a first push-up member 47, a second push-up member 48, and a push-up mechanism side adsorption portion 49.

  The first push-up member 47 is disposed at the center of the chip push-up mechanism 44. The first push-up member 47 has a rectangular planar shape, for example.

  The first push-up member 47 is configured to be movable in the vertical direction by a driving means (not shown). By moving the first push-up member 47 upward from the state shown in FIG. 4A (specifically, the surface of the stage main body 41 and the surface of the chip push-up mechanism 44 are substantially on the same plane). The first push-up member 47 pushes up the central portion of the memory chip 207b through the dicing tape 231 and the insulating adhesive layer 227.

  The second push-up member 48 has, for example, a frame shape in plan view, and is disposed outside the position where the first push-up member 47 is disposed.

  The second push-up member 48 is configured to be movable in the vertical direction by a driving means (not shown). By moving the second push-up member 48 upward from the state shown in FIG. 4 (a), the second push-up member 48 is placed on the outer periphery of the semiconductor chip 207b via the dicing tape 231 and the insulating adhesive layer 227. Push up the part.

  Further, the outer shape of the second push-up member 48 is configured to be slightly smaller than the size of the outer shape of the memory chip 207b to be picked up.

  Thus, when the second push-up member 48 is pushed up, a portion of the insulating resin layer 227 provided on the memory chip 207b that is located outside the second push-up member 48 is peeled off from the dicing tape 231. be able to.

  The stage side suction part 41a is a suction part formed on the stage, and is connected to a vacuum pump (not shown). As a result, the stage-side suction portion 41a also sucks the dicing tape 231.

  The push-up mechanism side suction portion 49 is a groove-like suction portion formed between the first push-up member 47 and the second push-up member 48, and is connected to a vacuum pump (not shown). Thereby, the push-up mechanism side suction part 49 sucks the dicing tape 231 disposed at a position facing the outer peripheral part of the semiconductor chip 207b.

  On the other hand, as shown in FIG. 4C, the bonding tool 39 has a suction portion 43 that sucks the memory chip 207b. The adsorbing portion 43 is an elastic body, for example, rubber having high thermal conductivity and heat resistance, and the cross section is formed in an arc shape so that the central portion of the bonding tool 39 is higher than the peripheral portion. Further, the bonding tool 39 includes a heating unit 55 that heats the adsorbed memory chip 207b.

  Next, a chip stack 205 is formed.

  First, as shown in FIG. 4B, one of the memory chips 207b is pushed up from the back side so that the first push-up member 47 and the second push-up member 48 have the same push-up amount.

  Next, as shown in FIG. 4C, the first push-up member 47 is pushed up further upward, so that the dicing tape 231 outside the first push-up member 47 is peeled off from the memory chip 207b.

  Next, the bonding tool 39 is brought into contact with the memory chip 207b from the state shown in FIG. 4C, and the bonding tool 39 is depressurized in the suction portion 43 of the bonding tool 39 as shown in FIG. The memory chip 207b is vacuum-sucked.

  Here, the adsorbing portion 43 of the bonding tool 39 is formed of an arc-shaped elastic body, and the memory chip 207b having a thin thickness of 50 μm is along the arc-shaped adsorbing portion, with the central portion on the back side being more than the periphery. Adsorbed and held to be high.

  Next, as shown in FIG. 4D, the bonding tool that has attracted the memory chip 207 b is peeled from the dicing tape 231 and moved to the bonding stage 51. Here, the memory chip 207b is held such that the difference between the central back surface bump 293 and the peripheral back surface bump 293 is about 15 μm, for example.

  Further, since the back surface bump 293 of the memory chip 207b is covered with the insulating adhesive layer 227, the back surface bump 293 is easily peeled off from the dicing tape 231 without being anchored to the adhesive layer (not shown) of the dicing tape 231. .

  Next, the attracted and held memory chip 207b is stacked on the memory chip 207a.

  First, as shown in FIG. 5A, the memory chip 207a is held on the bonding stage 51 by vacuum suction so that the surface faces upward. The bonding stage 51 is provided with a heater 53 as a heating mechanism, and the memory chip 207a is heated to a predetermined temperature.

  Next, the bonding tool 39 that has attracted the memory chip 207 b is placed on the bonding stage 51. Further, the memory chip 207 b is also heated to a predetermined temperature by the heating unit 55 of the bonding tool 39.

  Next, after the position of the memory chip 207a is recognized by a recognition unit (not shown) of the bonding apparatus, the bonding tool 39 is lowered to flip-chip mount the memory chip 207b on the memory chip 207a. It electrically connects to the corresponding surface bump 273 of the memory chip 207a.

  Here, since the memory chip 207b is held by the bonding tool 39 in a state of being warped so that the central portion is higher than the periphery, as shown in FIG. 5B, the insulating adhesive layer 227 of the memory chip 207b. The center part of the first contacts the memory chip 207a first. Thereafter, the insulating adhesive layer 227 spreads so as to push air outward from the center. At this time, the suction portion 43, which is an elastic body, receives a load directed toward the memory chip 207b, thereby deforming into a flat shape, and the memory chip 207b receives a load in a substantially flat state as shown in FIG. Thus, the electrodes are joined. Further, the insulating adhesive layer 227 pushes air so as to protrude beyond the ends of the memory chip 207a and the memory chip 207b, and the space between the chips is filled with the insulating adhesive layer 227.

  This makes it difficult for voids to be trapped between the chips, and the generation of voids can be reduced.

  Further, as shown in FIG. 5D, by stacking and mounting two memory chips 207b by flip chip mounting, a chip stack 205 having, for example, four memory chips 207 is formed as shown in FIG. .

  Next, the chip stack 205 is mounted on the wiring board 201 according to the following procedure.

  First, a wiring mother board 300 as shown in FIG.

  The wiring mother board 300 has a plurality of product forming parts 301 arranged in a matrix, and each product forming part 301 corresponds to the wiring board 201. Further, a dicing line 307 corresponding to a cut surface when separating the product forming portions 301 is provided between the product forming portions 301.

  Next, as shown in FIG. 7B, an insulating adhesive layer 227 such as NCF is applied so as to cover the connection pads 217 using a dispenser 61 or the like.

  Next, as illustrated in FIG. 7C, the logic chip 203 is mounted on the product forming unit 301, and the connection pads 217 of the product forming unit 301 and the surface bumps 273 of the logic chip 203 are connected.

  Next, as shown in FIG. 7D, an insulating adhesive layer 227 is further applied on the logic chip 203 to cover the back bumps 293.

  Next, as shown in FIG. 7E, the chip stack 205 is mounted on the logic chip 203, and the back bump 293 of the logic chip 203 and the front bump 273 of the chip stack 205 are connected.

  Next, the wiring mother board 300 is sent to a molding apparatus (not shown).

  Thereafter, molten sealing resin is injected in a state where the upper mold and the lower mold of the molding apparatus are closed, and the sealing resin is cured by curing at a predetermined temperature, for example, 180 ° C.

  Furthermore, the upper mold and the lower mold are separated, the wiring mother board 300 is taken out, and the sealing resin is completely cured by reflowing at a predetermined temperature, for example, 240 ° C., as shown in FIG. A sealing body 212 that covers the wiring mother substrate 300 is formed.

  Next, as shown in FIG. 8B, solder balls 216 are mounted on lands 219 on the other surface side of the wiring mother board 300.

  Specifically, for example, using a suction mechanism (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 219 on the wiring board 201, the solder balls 216 are held in the suction holes, and the held solder balls 216 are held. Are collectively mounted on the lands 219 of the wiring board 201 via a flux.

  After the solder balls 216 are mounted on all product forming portions 301, the solder balls 216 are fixed by reflowing the wiring board 201.

  Next, as shown in FIG. 8C, the sealing body 212 is bonded to the dicing tape 231, and the sealing body 212 and the wiring mother board 300 are supported on the dicing tape 231. Thereafter, using the dicing blade 311, the wiring mother board 300 and the sealing body 212 are cut vertically and horizontally along the dicing line 307 (see FIG. 7A). Thereby, the wiring mother board 300 is separated into pieces for each product forming portion 301.

  Finally, by picking up the separated product forming portion 301 and sealing body 212 from the dicing tape 231, a semiconductor device 200 as shown in FIG. 1 is obtained.

  As described above, according to the first embodiment, the semiconductor device 200 holds the other surface facing the one surface of the memory chip 207b having the back surface bump 293 as a plurality of bump electrodes formed on one surface by the bonding tool 39. Then, the memory chip 207b held by the bonding tool 39 is stacked on the memory chip 207a having a plurality of front surface bumps 273 formed on one surface via the insulating adhesive layer 227, and the back surface bump 293 of the memory chip 207b is formed. The memory chip 207a is manufactured by being electrically connected to the plurality of surface bumps 273 and filling the gap between the memory chip 207a and the memory chip 207b with the insulating adhesive layer 227, and the bonding tool 39 holds the memory chip 207b. When the memory chip 207b is Is held in a state of being warped so as to be higher than the portion, and when stacking, the memory chip 207b held by the bonding tool 39 is warped and the memory chip 207a is placed on the memory chip 207a via the insulating adhesive layer 227. Laminate to.

  Therefore, even when flip chip bonding is used, the semiconductor device 200 can be manufactured so that no void is generated in the resin portion between the chip and the substrate or between the chips.

  Next, a second embodiment will be described with reference to FIG.

  In the second embodiment, the memory chips are stacked from the state in which the insulating adhesive layer 227 is not attached to the back surface of the memory chip 207b in the first embodiment.

  Note that, in the second embodiment, elements having the same functions as those in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.

  First, as in the first embodiment, the memory chip 207b is manufactured and singulated, but at this time, the insulating adhesive layer 227 is not provided.

  Next, as illustrated in FIG. 9, the memory chip 207 b is stacked on the memory chip 207 a to form a chip stacked body 205.

  Specifically, first, an insulating adhesive layer 227 is first applied on the surface of the memory chip 207a using a dispenser 61 or the like as shown in FIG. 9A, and thereafter, FIGS. ), The memory chip 207b is flip-chip mounted on the memory chip 207a, and the back surface bump 293 of the memory chip 207b is electrically connected to the corresponding front surface bump 273 of the memory chip 207a.

  Also in this case, since the memory chip 207b is held by the bonding tool 39 in a state of being warped so that the central portion is higher than the periphery, the central portion of the memory chip 207b is the memory chip as shown in FIG. The insulating adhesive layer 227 on 207a is first contacted. Furthermore, the insulating adhesive layer 227 spreads out from this state so as to push air outward from the center of the chip. As a result, the insulating adhesive layer 227 pushes out air so as to protrude beyond the end portion of the chip, and the space between the chips is filled with the insulating adhesive layer 227, so that generation of voids between the chips can be reduced.

  Thus, the insulating adhesive layer 227 does not necessarily need to be applied to the memory chip 207b first.

  Furthermore, by similarly stacking and mounting two memory chips 207b by flip chip mounting, a chip stack 205 having, for example, four memory chips 207 is formed as in FIG.

  Thereafter, as in the first embodiment, the chip stack 205 is mounted on the wiring mother board 300, resin-sealed, the solder balls 216 are mounted, and the wiring mother board 300 is singulated to complete the semiconductor device 200. To do.

As described above, according to the second embodiment, the semiconductor device 200 holds the other surface facing the one surface of the memory chip 207b on which the back surface bump 293 as a plurality of bump electrodes is formed by the bonding tool 39. Then, the memory chip 207b held by the bonding tool 39 is stacked on the memory chip 207a having a plurality of front surface bumps 273 formed on one surface via the insulating adhesive layer 227, and the back surface bump 293 of the memory chip 207b is formed. The memory chip 207a is manufactured by being electrically connected to the plurality of surface bumps 273 and filling the gap between the memory chip 207a and the memory chip 207b with the insulating adhesive layer 227, and the bonding tool 39 holds the memory chip 207b. When the memory chip 207b is Is held in a state of being warped so as to be higher than the portion, and when stacking, the memory chip 207b held by the bonding tool 39 is warped and the memory chip 207a is placed on the memory chip 207a via the insulating adhesive layer 227. Laminate to.
Accordingly, the same effects as those of the first embodiment are obtained.

  Next, a third embodiment will be described with reference to FIG.

  In the third embodiment, the logic chip 203 and the chip stack 205 are juxtaposed on the silicon interposer 208 mounted on the wiring substrate 201 in the first embodiment.

  Note that in the third embodiment, elements that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.

  As shown in FIG. 10, in the semiconductor device 200 a according to the third embodiment, a logic chip 203 and a chip stack 205 are juxtaposed on a silicon interposer 208 mounted on a wiring board 201.

  Thus, the logic chip 203 and the chip stack 205 are not necessarily stacked in series, and may be juxtaposed.

  Note that the manufacturing method of the semiconductor device 200a is the same as that of the first embodiment, and thus the description thereof is omitted.

As described above, according to the third embodiment, the semiconductor device 200a holds the other surface facing the one surface of the memory chip 207b on which the back surface bump 293 as a plurality of bump electrodes is formed by the bonding tool 39. The memory chip 207b held by the bonding tool 39 is stacked on the silicon interposer 208 having a plurality of front surface bumps 273 formed on one surface via the insulating adhesive layer 227, and the back surface bump 293 of the memory chip 207b. Is electrically connected to the plurality of surface bumps 273 of the silicon interposer 208 and the insulating adhesive layer 227 is filled in the gap between the silicon interposer 208 and the memory chip 207b. When holding 207b, the memory 207b is held in a state of being warped so that the central portion of the surface is higher than the peripheral portion, and when stacking, the insulating adhesive is left in a state of warping the memory chip 207b held by the bonding tool 39 It is laminated on the silicon interposer 208 through the layer 227.
Accordingly, the same effects as those of the first embodiment are obtained.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, and can be variously changed in the range which does not deviate from the summary.

  For example, in the above-described embodiment, the manufacturing method of the semiconductor device 200 in which the four memory chips 207 and one logic chip 203 are stacked has been described. However, the manufacturing method of the present invention can be used when a memory chip or a logic chip is used. The method is not limited, and any semiconductor chip manufacturing method can be used. The number of stacked semiconductor chips is not limited to five, but may be four or less or six or more.

39: Bonding tool 41: Stage main body 41a: Stage side suction part 43: Suction part 44: Chip push-up mechanism 46: Stage 47: First push-up member 48: Second push-up member 49: Push-up mechanism side suction part 51: Bonding Stage 53: Heater 55: Heating unit 61: Dispenser 200: Semiconductor device 200a: Semiconductor device 201: Wiring substrate 202: Silicon substrate 203: Logic chip 205: Chip stack 207: Memory chip 207a: Memory chip 207b: Memory chip 208: Silicon interposer 209: Circuit forming layer 212: Sealing body 213: Base material 216: Solder ball 217: Connection pad 218: Insulating film 219: Land 222: Insulating ring 227: Insulating adhesive layer 231: Dicing tape 2 1: Support substrate 271: Electrode pad 273: Surface bump 275: Ni plating layer 277: Au plating layer 279: Through electrode 282: Seed layer 283: Protection film 293: Back bump 295: Back solder layer 300: Wiring mother board 301: Product forming section 307: Dicing line 311: Dicing blade 313: Adhesive layer 400: Semiconductor wafer 401: Product forming section 403: Dicing line

Claims (10)

(A) holding the other surface facing the one surface of the first substrate having a plurality of bump electrodes formed on one surface with a bonding tool;
(B) The first substrate held by the bonding tool is stacked on a second substrate having a plurality of electrodes formed on one surface via a resin adhesive layer, and the plurality of the first substrates are stacked. Electrically connecting the bump electrodes to the plurality of electrodes of the second substrate, and filling the resin adhesive layer in the gap between the first and second substrates,
Have
(A) holding the other surface by a bonding tool in a state in which the first substrate is warped so that the central portion of the one surface is higher than the peripheral portion,
(B) is a method of laminating the first substrate held by the bonding tool on the second substrate through the resin adhesive layer while keeping the first substrate warped. A method for manufacturing a semiconductor device. The bonding tool is an elastic material having heat resistance and high thermal conductivity, and has a suction portion configured in an arc shape so that the central portion is higher than the peripheral portion in cross-sectional shape,
(A) is characterized in that the first substrate is held by suction by holding the first substrate to the suction portion configured in the arc shape, and the first substrate is held by the bonding tool in a warped state. A method for manufacturing a semiconductor device according to claim 1.   In (b), the central portion of the first substrate held by the bonding tool in a warped state is brought into contact with the second substrate via the resin adhesive layer, and the bonding tool is contacted with the bonding tool. The load is applied toward the second substrate to deform the suction portion and the first substrate from an arc shape to a flat shape, and the first substrate is stacked on the second substrate. The manufacturing method of the semiconductor device as described in any one of.   The said (b) attaches the said adhesive resin layer to a said 1st board | substrate, Then, the said 1st board | substrate is laminated | stacked on a said 2nd board | substrate, The description in any one of Claims 1-3. Semiconductor device manufacturing method.   The said (b) is a thing as described in any one of Claims 1-3 which laminates | stacks a said 1st board | substrate on a said 2nd board | substrate after apply | coating the said adhesive resin layer on a said 2nd board | substrate. Semiconductor device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the first substrate and / or the second substrate is a semiconductor chip.   The method for manufacturing a semiconductor device according to claim 1, wherein the first substrate and / or the second substrate is a memory chip.   The semiconductor device manufacturing method according to claim 1, wherein a plurality of the first substrates are juxtaposed on the second substrate. (C) mounting the first substrate and the second substrate on a wiring substrate;
(D) sealing the first substrate and the second substrate with a sealing resin;
The manufacturing method of the semiconductor device as described in any one of Claims 1-8 which has these. (E) mounting an external terminal on a surface of the wiring substrate opposite to the surface on which the first substrate and the second substrate are provided;
A method for manufacturing a semiconductor device according to claim 9.

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