JP2015097447A - Power supply and image formation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply a large current without reducing power supply efficiency even when a device is operating in a standby mode.SOLUTION: A power supply is operable in either a normal mode, in which a first DC voltage of a first DCDC converter 20 is supplied to a drive system circuit 80, or a standby mode, in which the first DC voltage from the first DCDC converter is reduced and an FET 62 of a second DCDC converter 60 is set to be a continuous conduction state to output an output voltage from the first DCDC converter 20 through the second DCDC converter 60. The power supply includes an error amplifier 72 for detecting an increased output current of the second DCDC converter 60. When the error amplifier 72 detects the increase of the output current of the second DCDC converter 60 during operation in the standby mode, the power supply increases the output voltage of the first DCDC converter 20.

Description

  The present invention relates to a power supply apparatus and an image forming apparatus, and more particularly, to a power supply that generates a DC voltage from an AC voltage of an AC power supply suitable for a power supply of an apparatus that can operate in a normal operation mode and an energy-saving standby mode. .

  In many cases, a power supply device for an electronic device that mainly includes a driving unit outputs two systems of voltages, a first DC voltage and a second DC voltage. Here, the first DC voltage is a voltage when a voltage required for operation is output to a drive system having a relatively high voltage, such as a motor or a solenoid. The second DC voltage is a voltage when a voltage required for operation is output to a control system such as a CPU or ASIC, which is relatively low. In such a power supply device, the following configuration is often adopted. First, a first DC voltage to the drive system is generated by a first DC / DC converter based on a DC voltage obtained by rectifying and smoothing an AC voltage of a commercial power source. Then, a second DC voltage to the control system is generated by the second DC / DC converter based on the first DC voltage. Further, since the drive system is not operated when the apparatus is operating in the energy saving state standby mode, the supply of output voltage to the drive system is interrupted by, for example, a load switch.

  In such a power supply device, the load current of the control system is also reduced in the standby mode in which the device is in an energy saving state, but the efficiency of the second DCDC converter described above is reduced at a light load. Therefore, in Patent Document 1, in order to improve the efficiency in the standby mode in the energy saving state, the output voltage of the first DCDC converter is lowered from the first DC voltage to a third DC voltage lower than the second DC voltage. A configuration is proposed. In the configuration of Patent Document 1, since the switching means of the second DCDC converter is driven in a continuous conduction state, there is no loss due to the switching operation, and the power supply efficiency in the standby mode can be improved.

JP 2010-142071 A

  However, the configuration of Patent Document 1 has a problem that a large current cannot be output in the standby mode. In the configuration of Patent Document 1, the output voltage of the first DCDC converter is output via the second DCDC converter that drives the switching means in a continuous conduction state after controlling to the third DC voltage. As a result, when a large current is output, the series resistance component of the second DCDC converter drops the output voltage. For this reason, in the conventional power supply apparatus, when operating a device that consumes a relatively large amount of current in the standby mode, it is necessary to change the power supply apparatus to the normal mode in advance. For this reason, devices that require a quick electrical response due to a delay when changing the operation mode and that consume a large amount of current, for example, devices that have a wireless LAN communication module, a USB host function, or the like, are operated during the standby mode. Is difficult.

  The present invention has been made under such circumstances, and an object of the present invention is to supply a large current without deteriorating the power supply efficiency even when the apparatus is operating in the standby mode.

  In order to solve the above-described problems, the present invention has the following configuration.

  (1) Rectifying and smoothing means for rectifying and smoothing an AC voltage, a first DCDC converter for converting the voltage rectified and smoothed by the rectifying and smoothing means and outputting a first DC voltage, and a second switching means And a second DCDC converter that outputs a second DC voltage lower than the first DC voltage by switching the first DC voltage by the first DCDC converter, and the first DCDC converter A first operation mode for outputting a DC voltage; a first DC voltage of the first DC-DC converter is lowered; a second switching means of the second DC-DC converter is set in a continuous conduction state; Power supply operable in a second operation mode in which the voltage output from the DCDC converter is output via the second DCDC converter. And detecting means for detecting that the output current of the second DCDC converter has increased, and when operating in the second operation mode, the detecting means causes the second DCDC converter to A power supply apparatus characterized by increasing the output voltage of the first DCDC converter when it is detected that the output current has increased.

  (2) An image forming apparatus comprising: an image forming unit for forming an image; and the power supply device according to (1).

  According to the present invention, even when the apparatus is operating in the standby mode, a large current can be supplied without reducing the power supply efficiency.

1 is a circuit diagram showing a configuration of a power supply device according to Embodiment 1 The figure which shows the waveform at the time of standby mode of the power supply device of Example 1. The circuit diagram which shows the structure of the power supply device of Example 2. FIG. 4 is a block diagram illustrating a configuration of an image forming apparatus according to a third embodiment.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the constituent elements described in this embodiment are merely examples, and are not intended to limit the scope of the present invention only to them.

[Configuration of power supply unit]
FIG. 1 is a circuit diagram illustrating a configuration of the power supply device according to the first embodiment. The power supply apparatus according to the present embodiment includes, for example, a control system having a relatively low voltage necessary for operation, such as a first direct current voltage to a drive system having a relatively high voltage necessary for operation, such as a motor and a solenoid. It is the structure which supplies the voltage of two systems with the 2nd DC voltage to.

  The rectifying / smoothing circuit 10 is a circuit that rectifies and smoothes the AC voltage of the AC power supply 11. The first DCDC converter 20 supplies a first DC voltage such as 24V to the drive system circuit 80. The second DCDC converter 60 supplies the control circuit 90 with a second DC voltage such as 3.3V. The power supply device according to the present embodiment can operate in two states, a normal mode that is a first operation mode and a standby mode that is a second operation mode, according to the state of a device in which the power supply device is mounted. Can be switched. The normal mode is a state where a DC voltage is supplied to the drive system circuit 80, and the standby mode is a state where the supply of the DC voltage to the drive system circuit 80 is interrupted. The control circuit 90 controls the state of the device and the operation mode of the power supply device, that is, the operation in the normal mode and the standby mode. When the power supply device shifts to the normal mode, the control circuit 90 outputs a low level signal from both the control terminal 91 and the control terminal 92. On the other hand, when the power supply device shifts to the standby mode, a high level signal is output from the control terminal 91 and the control terminal 92 is set to high impedance.

[Operation in normal mode]
(Operation of rectifying and smoothing circuit, first DCDC converter)
The operations of the rectifying / smoothing circuit 10 and the first DCDC converter 20 in the normal mode will be described. The rectifier 12 charges the capacitor 13 by rectifying the AC voltage applied from the AC power supply 11. When the capacitor 13 is charged and the voltage rises, a voltage as a power supply is supplied to the power supply control IC 22 via the starting resistor 21, and the power supply control IC 22 turns on a field effect transistor (hereinafter referred to as FET) 23. When the FET 23 is turned on, a current flows from the rectifying / smoothing circuit 10 to the primary winding Np of the transformer 24, and a voltage also appears in the secondary winding Ns and the auxiliary winding Nb by the voltage applied to the primary winding Np. At this time, the voltage appearing in the secondary winding Ns is blocked by the diode 31 so that no current flows. Similarly, the voltage appearing in the auxiliary winding Nb is also blocked by the diode 25 so that no current flows.

  The FET 23 is turned off after a predetermined time determined by the internal circuit of the power supply control IC 22 has elapsed. Then, although the voltage of the FET 23 side terminal of the primary winding Np increases, the FET 23 prevents the current from flowing. At this time, a current flows in the secondary winding Ns in the direction of charging the capacitor 32 via the diode 31, and the voltage of the capacitor 32 rises. Similarly, in the auxiliary winding Nb, a current flows in the direction of charging the capacitor 26 via the diode 25, and the voltage of the capacitor 26 increases. Then, after a predetermined time determined by the internal circuit of the power supply control IC 22, the FET 23 is turned on again, and current is supplied from the rectifying / smoothing circuit 10 to the transformer 24. Further, after a predetermined time determined by the internal circuit of the power supply control IC 22 has elapsed, the FET 23 is turned off again, and current is supplied from the transformer 24 to the capacitor 32 and the capacitor 26.

  In this way, the power supply control IC 22 repeatedly turns on and off the FET 23 and gradually increases the voltages of the capacitor 32 and the capacitor 26. The voltage of the capacitor 32 is the output voltage of the first DCDC converter 20. The power supply control IC 22 is designed so that the voltage consumed via the starting resistor 21 is consumed from the capacitor 26 when the voltage of the capacitor 26 increases. This is because if the voltage is consumed from the starting resistor 21, the loss is large and the efficiency is lowered.

  Here, the output voltage of the first DCDC converter 20 is divided by the resistors 33 and 34 and connected to the inverting input terminal of the error amplifier 35 as the third detecting means. The non-inverting input terminal of the error amplifier 35 is connected to the reference voltage Vref generated by the resistor 36 and the shunt regulator 37, and the output terminal is connected to the light emitting side element 39 of the photocoupler via the resistor 38. The light-receiving side element 27 of the photocoupler is configured to pass a current through the resistor 28 when receiving light and feed back the voltage generated in the resistor 28 to the power supply control IC 22. The resistors 33 and 34 are set to values at which the voltages of the inverting input terminal and the non-inverting input terminal of the error amplifier 35 are equal when the output voltage of the first DCDC converter 20 becomes the first DC voltage. . That is, the error amplifier 35 functions as detection means, and is controlled so that the first DCDC converter 20 outputs the first DC voltage based on the detection result. Therefore, when the output voltage of the first DCDC converter 20 is higher than the first DC voltage, the error amplifier 35 outputs a low level signal, and the light emitting side element 39 of the photocoupler emits light. Then, a current is passed through the light receiving side element 27 of the photocoupler, and the feedback voltage of the power supply control IC 22 rises. At this time, the power supply control IC 22 operates to reduce the output voltage by reducing the ON width or the ON duty of the FET 23 (which means the time for turning on the FET 23).

  Conversely, when the output voltage of the first DCDC converter 20 is lower than the first DC voltage, the error amplifier 35 outputs a high level signal, and the light-emitting side element 39 of the photocoupler is turned off. Then, the current of the light receiving side element 27 of the photocoupler decreases, and the feedback voltage of the power supply control IC 22 decreases. At this time, the power supply control IC 22 operates to increase the output voltage by increasing the ON width or the ON duty of the FET 23. In this way, the power supply control IC 22 controls the ON width or the ON duty of the FET 23 to control the output voltage to a stable first DC voltage.

  The load switch 50 includes an FET 51 and resistors 52 and 53. In the normal mode, by outputting a low level signal from the control terminal 92 of the open collector output, the FET 51 of the load switch 50 is turned on, and the first DC voltage is supplied to the drive system circuit 80 from the first DCDC converter. .

  Further, the FET 44 connected to the light emitting side element 39 of the photocoupler via the resistor 45 is not turned on in the normal mode, and does not affect the above-described operation. This is due to the following reason. That is, the gate terminal of the FET 44 is connected to the output terminal of the error amplifier 41 having an open collector output as the first detecting means, the drain terminal of the FET 73, and the pull-up resistor 40. This is because a low level signal is output from the control terminal 91 that drives the pull-up resistor 40 in the normal mode, and the gate terminal of the FET 44 is in the low level state.

(Operation of the second DCDC converter)
Next, the operation of the second DCDC converter 60 in the normal mode will be described. When the output voltage of the first DCDC converter 20 is input, the second DCDC converter control IC 61 (hereinafter simply referred to as the control IC 61) intermittently drives the FET 62 and supplies a pulse voltage to the inductor 64. This pulse voltage is converted into a direct current by the inductor 64, the regenerative diode 68 and the capacitor 65, and the output voltage of the second DCDC converter 60 is generated. The output voltage of the second DCDC converter 60 is divided by resistors 63 and 64 and fed back to the control IC 61. The control IC 61 has a reference voltage inside, and controls the on-duty of the FET 62 so that the output voltage of the second DCDC converter 60 divided by this reference voltage is equal, thereby stabilizing the output voltage. Control to a secondary DC voltage.

[Operation when entering standby mode]
Next, the operation at the time of transition from the normal mode to the standby mode will be described. When shifting from the normal mode to the standby mode, the control circuit 90 first turns off the load switch 50 to cut off the supply of the power supply voltage to the drive system circuit 80. Specifically, the control circuit 90 sets the control terminal 92 to high impedance and turns off the FET 51. Thereafter, the control circuit 90 switches the signal output from the control terminal 91 from the low level to the high level. As a result, the control circuit 90 pulls up the gate terminal of the FET 44 by the resistor 40, and makes the FET 44 in a state where it can be turned on from the state fixed in the off state.

  Here, first, as an operation when the load current is relatively small, the circuit operation will be described on the premise that the FET 73 is not turned on, and the operation of the FET 73 will be described later. In the error amplifier 41, a voltage obtained by dividing the output voltage of the first DCDC converter 20 by the resistors 42 and 43 is input to the non-inverting input terminal, and the above-described reference voltage Vref is connected to the inverting input terminal. The resistors 42 and 43 are set so that the voltages at the inverting input terminal and the non-inverting input terminal of the error amplifier 41 become equal when the output voltage of the first DCDC converter 20 becomes the third DC voltage. Here, the third DC voltage is a voltage required by the control circuit 90 in the standby mode. The error amplifier 41 is an open collector output. When the output voltage is higher than the third DC voltage, the error amplifier 41 becomes a high impedance output, and the pull-up resistor 40 sets the gate terminal of the FET 44 to a high level to turn on the FET 44. When the FET 44 is turned on, the light-emitting side element 39 of the photocoupler emits light, and a current flows through the light-receiving side element 27 of the photocoupler, and the feedback voltage of the power supply control IC 22 increases. The power supply control IC 22 operates to reduce the output voltage by reducing the on width or the on duty of the FET 23.

  Therefore, the error amplifier 35 and the FET 44 (the error amplifier 41 that turns on the FET 44) are configured to reduce the output of the first DCDC converter 20 when one of the light-emitting side elements 39 of the photocoupler emits light. . Thus, either the error amplifier 35 or the FET 44 (the error amplifier 41 that turns on the FET 44) causes the light-emitting side element 39 of the photocoupler to emit light. One of the error amplifier 41 and the error amplifier 41 via the FET 44, that is, the FET 44, is in a state in which a feedback signal (output signal) for “decreasing the output voltage” is wired or connected. That is, when the output voltage of the first DCDC converter 20 becomes equal to or higher than the first DC voltage, or when the output of the first DCDC converter 20 becomes equal to or higher than the third DC voltage, the light emitting side element of the photocoupler 39 is caused to emit light. Then, when the light emitting side element 39 of the photocoupler emits light, the output voltage of the first DCDC converter 20 is controlled to decrease. Therefore, the output of the error amplifier 41 that detects the third DC voltage that is lower than the first DC voltage is fed back preferentially, and the output of the first DCDC converter 20 is changed to the third DC voltage. Be controlled.

  At this time, the second DCDC converter 60 is configured to generate the second DC voltage from the output voltage of the first DCDC converter 20 as described above. Therefore, when the output voltage of the first DCDC converter 20 decreases during the transition to the standby mode, the FET 62 operates to increase the ON time (increase the ON duty) and maintain the output voltage at the second DC voltage. When the output voltage of the first DCDC converter 20 drops to a third DC voltage that is lower than the second DC voltage, the FET 62 of the second DCDC converter 60 is fixed in the ON state (on-duty 100% state). (Also called continuous conduction state)).

[Operation when load increases in standby mode]
Next, the operation when the load increases in the standby mode will be described. In the circuit operation up to the above, when the output current of the second DCDC converter 60 increases in the standby mode, the output voltage of the second DCDC converter 60 drops due to the DC resistance component of the FET 62 and the like. In this embodiment, the output voltage of the second DCDC converter 60 is detected and the result is fed back to the first DCDC converter 20. In the error amplifier 72 as the second detection means, a voltage obtained by dividing the output voltage of the second DCDC converter 60 by the resistors 70 and 71 is input to the inverting input terminal, and the above-described reference voltage Vref is input to the non-inverting input terminal. Is connected. The resistors 70 and 71 are set so that the voltages of the inverting input terminal and the non-inverting input terminal of the error amplifier 72 become equal when the output voltage of the second DCDC converter 60 becomes the fourth DC voltage. Here, the fourth DC voltage is a threshold voltage at which the control circuit 90 cannot operate when the output voltage of the second DCDC converter 60 becomes low. As a result, when the output voltage of the second DCDC converter 60 is lower than the fourth DC voltage, the error amplifier 72 outputs a high level signal and turns on the FET 73. When the FET 73 is turned on, the FET 44 is turned off. Accordingly, when either one of the error amplifier 41 and the FET 73 (the error amplifier 72 that turns on the FET 73) turns off the FET 44, the light emitting side element 39 of the photocoupler is turned off to increase the output of the first DCDC converter 20. It is configured.

  Thus, one of the error amplifier 41 and the FET 73 (the error amplifier 72 that turns on the FET 73) turns off the FET 44. As a result, the light emitting side element 39 of the photocoupler is turned off to form a state in which the feedback signal “increasing the output voltage” is wired or connected. That is, when the output of the first DCDC converter 20 becomes equal to or lower than the third DC voltage or when the output of the second DCDC converter 60 becomes equal to or lower than the fourth DC voltage, the FET 44 is turned off and the photocoupler is turned off. The light emitting side element 39 is turned off. Then, when the light emitting side element 39 of the photocoupler is turned off, the output voltage of the first DCDC converter 20 is controlled to increase.

(Off delay circuit)
A diode 74, a capacitor 75, and a resistor 76 connected between the error amplifier 72 and the FET 73 are an off-delay circuit that is a delay unit. When the output voltage of the second DCDC converter 60 becomes lower than the fourth DC voltage and the signal from the error amplifier 72 is switched to the high level, the capacitor 75 is quickly charged via the diode 74 and the FET 73 is turned on. Let On the other hand, when the output voltage of the second DCDC converter 60 becomes higher than the fourth DC voltage and the signal from the error amplifier 72 is switched to the low level, the diode 74 is turned off. For this reason, the capacitor 75 is gradually discharged by the resistor 76, and the FET 73 can be delayed from being turned off. The time from when the signal of the error amplifier 72 is switched to the low level until the FET 73 is turned off is determined by the time constant of the capacitor 75 and the resistor 76.

[Operation waveform in standby mode (when load current is small)]
Next, operation waveforms in the standby mode of this embodiment will be described with reference to FIG. FIGS. 2A and 2A illustrate a waveform 100 a that indicates ON (ON) or OFF (OFF) of the FET 23 of the first DCDC converter 20. FIGS. 2A and 2B illustrate a waveform 101 a that indicates ON (ON) or OFF (OFF) of the FET 62 of the second DCDC converter 60. FIGS. 2A and 2C illustrate the waveform 102a of the output voltage (voltage) of the first DCDC converter 20 and the waveform 103a of the output voltage (voltage) of the second DCDC converter 60. 2B corresponds to FIG. 2A, FIG. 2B and FIG. 2A show the waveform 100b indicating ON / OFF of the FET 23, and FIG. 2B and FIG. Waveforms 101b indicating on or off are respectively illustrated. 2B and 2C illustrate a waveform 102b of the output voltage of the first DCDC converter 20 and a waveform 103b of the output voltage of the second DCDC converter 60. Each horizontal axis indicates time. 2A, 2C, and 2C, V2 indicates a second DC voltage, V3 indicates a third DC voltage, V4 indicates a fourth DC voltage, and V2 The relationship of>V3> V4 is established.

  First, FIG. 2A is a waveform showing an operation example when the load current is relatively small in the standby mode. Each time the output voltage (waveform 102a) of the first DCDC converter 20 falls below the third DC voltage (V3), a low level signal is output from the error amplifier 41, and the FET 23 (waveform 100a) of the first DCDC converter 20 is output. Turns on. Thereby, the output voltage (waveform 102a) of the first DCDC converter 20 is controlled to be the third DC voltage (V3). Since the third DC voltage (V3) is lower than the second DC voltage (V2) controlled by the second DCDC converter 60, the FET 62 (waveform 101a) of the second DCDC converter 60 is continuously turned on (ON). ) State. Then, the output voltage (waveform 103a) of the second DCDC converter 60 slightly drops from the third DC voltage (V3) due to the DC resistance component of the second DCDC converter 60, and is smoothed by the inductor 64 and the capacitor 65. Outputs the normalized voltage. When the load current is small, the output (waveform 103a) of the second DCDC converter 60 does not fall below the fourth DC voltage (V4), and the FET 73 is fixed in the off state.

[Operation waveform in standby mode (when load current is large)]
Next, FIG. 2 (B) is a waveform showing an operation example of this embodiment when the load current is increased from FIG. 2 (A) in the standby mode. Since the load current is large, the output (waveform 103b) of the second DCDC converter 60 becomes the first at time T121 before the output (waveform 102b) of the first DCDC converter 20 falls below the third DC voltage (V3). Below four DC voltages (V4). Then, the error amplifier 72 outputs a high level signal and quickly turns on the FET 73.

  As described above, when the FET 73 is turned on, the FET 44 is turned off, the light emitting side element 39 of the photocoupler is turned off, and the power supply control IC 22 is feedback controlled so as to increase the output voltage of the first DCDC converter 20. Accordingly, the switching operation in which the FET 23 (waveform 100b) of the first DCDC converter 20 is repeatedly turned on and off is started from time T121, and the output (waveform 102b) of the first DCDC converter 20 is increased. In the feedback control for increasing the output of the first DCDC converter 20, it is preferable to make the delay time as short as possible in order to avoid a decrease in the output voltage of the second DCDC converter 60. The delay time here is the time from when the output of the second DCDC converter 60 falls below the fourth DC voltage until the FET 23 starts switching. Then, the output (waveform 103b) of the second DCDC converter 60 increases slightly after time T121 due to the influence of the inductor 64 and the capacitor 65, and again exceeds the fourth DC voltage (V4) at time T122.

  At this time, the error amplifier 72 is switched to output a low level signal immediately. However, the FET 73 is turned off after the time T124 by the off-delay circuit including the diode 74, the capacitor 75, and the resistor 76, and the FET 23 (waveform 100b) of the first DCDC converter 20 stops the switching operation. That is, the delay time by the off-delay circuit is included in the time from time T122 to time T124. During this time T122 to time T124, the output (waveform 102b) of the first DCDC converter 20 continues to rise.

  Here, the output (waveform 103b) of the second DCDC converter 60 rises to the second DC voltage (V2) at time T123. Then, the FET 62 (waveform 101b) of the second DCDC converter 60 is controlled to resume the switching operation and maintain the second DC voltage (V2). After time T124, the output (waveform 102b) of the first DCDC converter 20 releases the charge stored in the capacitor 32 and gradually decreases the output voltage. In this state, the output of the first DCDC converter 20 (waveform 102b) is lower than the third DC voltage (V3) or the output of the second DCDC converter 60 (waveform 103b) is the fourth DC voltage (V4). Continue until below. Here, at time T125, the output (waveform 103b) of the second DCDC converter 60 falls below the fourth DC voltage (V4) again, and thereafter, the same intermittent operation from time T121 to time T125 is repeated. In this way, the intermittent operation period from time T121 to T125 can be adjusted by the time constant of the off-delay circuit including the diode 74, the capacitor 75, and the resistor 76 described above.

[Operation when returning to normal mode]
Next, the operation when returning to the normal mode will be described. When returning to the normal mode, the output voltage of the first DCDC converter 20 is first increased from the third DC voltage to the first DC voltage. Specifically, the control circuit 90 fixes the FET 44 in the OFF state by switching the signal from the control terminal 91 to a low level. As a result, the control circuit 90 controls the light emitting side element 39 of the photocoupler so that the outputs of the error amplifier 41 and the error amplifier 72 are not fed back, that is, due to the outputs of the error amplifier 41 and the error amplifier 72. Do not be. Thereafter, the control circuit 90 turns on the load switch 50 and supplies the first DC voltage to the drive system circuit 80. Specifically, the control circuit 90 sets the signal from the control terminal 92 to a low level and turns on the FET 51.

  As described above, the power supply apparatus of this embodiment includes a feedback circuit, and the feedback circuit includes the error amplifier 35, the error amplifier 41, the error amplifier 72, the FET 44, and the FET 73. According to the configuration of this embodiment, in the standby mode, when the load current of the second DCDC converter 60 is small, the switching operation of the second DCDC converter 60 is stopped, so that high conversion efficiency can be realized. it can. Further, when the load current of the second DCDC converter 60 increases, the output voltage of the first DCDC converter is immediately increased from the output change of the second DCDC converter. Thereby, it is possible to output a large load current without switching the operation mode in advance. Further, when this embodiment is applied to a power supply device used for an image forming apparatus or the like, the period in which the first DCDC converter 20 shown in FIG. 2B intermittently operates adjusts the time constant of the off-delay circuit. It is possible to set to about several hundred Hz. This also has an effect of making it difficult to generate an operating sound of several kHz to several tens of kHz that is likely to be an audible vibration sound generated from the transformer 24.

  As described above, according to the present embodiment, even when the apparatus is operating in the standby mode, a large current can be supplied without reducing the power supply efficiency.

[Configuration of power supply unit]
FIG. 3 is a circuit diagram illustrating a configuration of the power supply device according to the second embodiment. The same components as those in FIG. 1 according to the first embodiment are denoted by the same reference numerals and description thereof is omitted. Further, the operation waveform of the present embodiment is the same as the operation waveform described in FIG. The difference from the power supply circuit shown in FIG. 1 of the first embodiment is the configuration of the feedback circuit. In the first embodiment, the error amplifier 35 controlled in the normal mode and the error amplifier 41 controlled in the standby mode are separately provided, and their output terminals are wired-or connected via the FET 44, whereas in the present embodiment, The number of error amplifiers used is one less. The feedback circuit of this embodiment includes an error amplifier 235, an error amplifier 272, an FET 273, and an FET 244 described later.

[Operation in normal mode]
The normal mode of the present embodiment will be described. In the normal mode, the control circuit 90 outputs a high level signal from the control terminal 293 to turn on the FET 243. The reference voltage Vref described above is input to the inverting input terminal of the error amplifier 235, and the voltage obtained by dividing the output of the first DCDC converter 20 by the resistors 233, 234, and 242 is input to the non-inverting input terminal. Further, the resistors 233, 334, and 242 have the voltages at the inverting input terminal and the non-inverting input terminal of the error amplifier 235 when the output voltage of the first DCDC converter 20 becomes the first DC voltage when the FET 243 is on. It is set to an equal value. Therefore, when the output of the first DCDC converter 20 falls below the first DC voltage, the signal output from the error amplifier 235 becomes low level, and the FET 244 is turned off via the resistor 238. When the FET 244 is turned off, similarly to the first embodiment, the light-emitting side element 39 of the photocoupler is turned off and the output voltage of the first DCDC converter 20 is controlled to increase. As a result, the output voltage of the first DCDC converter 20 is controlled to the first DC voltage. In the normal mode, since the control terminal 91 of the control circuit 90 outputs a low level signal and the error amplifier 272 is an open collector output, the FET 273 is fixed in the OFF state, and the above-described operation is performed. Does not affect.

[Operation in standby mode]
Next, the standby mode of the present embodiment will be described. In the standby mode, the control circuit 90 outputs a low level signal from the control terminal 293 to turn off the FET 243. As a result, a voltage obtained by dividing the output of the first DCDC converter 20 using only the resistors 233 and 234 is input to the non-inverting input terminal of the error amplifier 235. Thus, in this embodiment, the resistance value of the voltage dividing resistor is switched between the normal mode and the standby mode. Here, the resistors 233 and 234 have the same voltage at the inverting input terminal and the non-inverting input terminal of the error amplifier 235 when the output voltage of the first DCDC converter 20 becomes the third DC voltage when the FET 243 is off. Is set to a value. Therefore, when the output of the first DCDC converter 20 falls below the third DC voltage, the signal output from the error amplifier 235 becomes low level, and the FET 244 is turned off via the resistor 238. When the FET 244 is turned off, the light-emitting side element 39 of the photocoupler is turned off, and the output voltage of the first DCDC converter 20 is controlled to increase. As a result, the output voltage of the first DCDC converter 20 is controlled to the third DC voltage.

  In addition to this, in the standby mode, the control circuit 90 outputs a high level signal from the control terminal 91, so that the error amplifier 272 having an open collector output can turn on the FET 273. The error amplifier 272 receives the voltage obtained by dividing the output of the second DCDC converter 60 by the resistors 70 and 71 at the inverting input terminal, and operates in the same manner as the error amplifier 72 of the first embodiment. The operation of the off-delay circuit including the diode 74, the capacitor 75, and the resistor 76 is the same as that in the first embodiment. However, since the error amplifier 272 is an open collector output unlike the first embodiment, a delay time for the resistor 240 to charge the capacitor 75 occurs when the signal is switched from the low level to the high level. As described in the first embodiment, in order to avoid a decrease in the output voltage, it is better to make this delay time as short as possible.

  Here, the error amplifier 235 and the FET 273 (the error amplifier 272 that turns on the FET 273) are configured to turn off the FET 244 and increase the output of the first DCDC converter 20 when either one becomes a low level output. Then, the error amplifier 272 and the FET 273, that is, the FET 273 via the error amplifier 272 form a state in which a feedback signal “increasing the output voltage” is wired or connected. In other words, when the output of the first DCDC converter 20 is equal to or lower than the third DC voltage, or when the output of the second DCDC converter 60 is equal to or lower than the fourth DC voltage, the light emitting side element 39 of the photocoupler. Turn off the light. Then, the output voltage of the first DCDC converter 20 is controlled to increase. According to the present embodiment, the number of necessary error amplifiers is small, and it is possible to configure a smaller and lower cost.

  In the first and second embodiments, the reference voltage Vref generated using the shunt regulator 37 may be generated using another means such as a Zener diode. Each FET may be configured using a transistor.

  As described above, according to the present embodiment, even when the apparatus is operating in the standby mode, a large current can be supplied without reducing the power supply efficiency.

  The power supply apparatus described in the first and second embodiments can be applied as, for example, a low-voltage power supply for an image forming apparatus, that is, a power supply that supplies power to a drive unit such as a controller (control unit) or a motor. The configuration of the image forming apparatus to which the power supply apparatus according to the first and second embodiments is applied will be described below.

[Configuration of Image Forming Apparatus]
A laser beam printer will be described as an example of the image forming apparatus. FIG. 4A shows a schematic configuration of a laser beam printer which is an example of an electrophotographic printer. The laser beam printer 300 includes a photosensitive drum 311 as an image carrier on which an electrostatic latent image is formed, a charging unit 317 (charging unit) that uniformly charges the photosensitive drum 311, and an electrostatic latent image formed on the photosensitive drum 311. A developing unit 312 (developing unit) that develops an image with toner is provided. The toner image developed on the photosensitive drum 311 is transferred to a sheet (not shown) as a recording material supplied from the cassette 316 by a transfer unit 318 (transfer means), and the toner image transferred to the sheet is fixed to the fixing device 314. Then, the toner is fixed and discharged onto the tray 315. The photosensitive drum 311, the charging unit 317, the developing unit 312, and the transfer unit 318 are image forming units. The laser beam printer 300 includes the power supply device 400 described in the first and second embodiments. The image forming apparatus to which the power supply device 400 according to the first and second embodiments can be applied is not limited to the one illustrated in FIG. 4, and may be an image forming apparatus including a plurality of image forming units, for example. Further, the image forming apparatus may include a primary transfer unit that transfers the toner image on the photosensitive drum 311 to the intermediate transfer belt and a secondary transfer unit that transfers the toner image on the intermediate transfer belt to the sheet. The image forming apparatus is provided with a USB connector 401, and a USB memory can be connected to an external device such as a camera via a USB cable. Further, the image forming apparatus is provided with a wireless LAN interface 402, which can transmit and receive signals and information by communicating with external devices by wireless signals.

  As shown in the block diagram of FIG. 4B, the laser beam printer 300 includes a controller as a control circuit 90 that controls an image forming operation by the image forming unit and a sheet conveying operation. And the 2nd DCDC converter 60 of the power supply device 400 described in Example 1, 2 supplies electric power to the controller 90, for example. Further, the first DCDC converter 20 of the power supply device 400 described in the first and second embodiments is driven as a driving unit such as a motor for rotating the photosensitive drum 311 or driving various rollers for conveying the sheet. Power is supplied to the system circuit 80. The controller (control circuit 90) is configured to communicate with a USB connector 401 (including a USB interface circuit and a communication circuit), and can exchange signals and information with a connected external device. The controller is configured to communicate with a wireless LAN interface (including a communication circuit), and transmits and receives signals and information to and from an external computer.

  When the image forming apparatus according to the present exemplary embodiment operates in a standby mode that realizes power saving, the supply of voltage to the drive system circuit 80 is interrupted to reduce power consumption. Moreover, high power supply efficiency can be obtained by making FET62 of the 2nd DCDC converter 60 into a continuous conduction state. In the image forming apparatus according to the present exemplary embodiment, the operation described in the first and second exemplary embodiments is performed in the standby mode, so that even when the load current increases, a large current is supplied to the load without shifting to the normal mode. can do. Here, when the image forming apparatus is operating in the standby mode, the load current becomes large, for example, the communication via the wireless LAN interface 402 or the function that can be connected to the USB connector 401 operates. This is the case. When the image forming apparatus is operating in the standby mode, a device with a large current consumption such as a wireless LAN interface or a USB function can be immediately operated without reducing the power efficiency at the time of low current consumption. The usability of the image forming apparatus, which is a device that uses the power supply device, can be improved.

  In this embodiment, the wireless LAN interface and the USB device have been described as an example when the load current increases. However, the present invention is not limited to this, and the case where the load current increases includes a case where an image forming condition setting change of the image forming apparatus is received from an operation panel or an operation unit (not shown). Even when the controller executes such a setting change, the processing load increases, so the load current may increase.

  As described above, according to the present embodiment, even when the apparatus is operating in the standby mode, a large current can be supplied without reducing the power supply efficiency.

10 rectifying and smoothing circuit 20 first DCDC converter 60 second DCDC converter 62 FET

Claims (14)

Rectifying and smoothing means for rectifying and smoothing an alternating voltage;
A first DCDC converter that converts the voltage rectified and smoothed by the rectifying and smoothing means and outputs a first DC voltage;
A second DC / DC converter that outputs a second DC voltage lower than the first DC voltage by switching the first DC voltage by a second switching means;
With
A first operation mode for outputting the first DC voltage of the first DCDC converter; and a reduction of the first DC voltage of the first DCDC converter to reduce the second DCDC converter A power supply apparatus operable in a second operation mode in which the switching means is continuously connected and the voltage output from the first DCDC converter is output via the second DCDC converter.
Detecting means for detecting an increase in output current of the second DCDC converter;
When the detection means detects that the output current of the second DCDC converter has increased while operating in the second operation mode, the output voltage of the first DCDC converter is increased. A power supply characterized by. The detection means includes first detection means for detecting that an output voltage from the first DCDC converter is equal to or lower than a third DC voltage, and an output voltage from the second DCDC converter is the third voltage. A second detection means for detecting that the voltage is equal to or lower than a fourth DC voltage lower than the DC voltage of
When the first detection means detects that the voltage is less than or equal to the third DC voltage, or when the second detection means detects that the voltage is less than or equal to the fourth DC voltage, The power supply apparatus according to claim 1, wherein the output voltage of the first DCDC converter is increased.   The power supply apparatus according to claim 2, wherein the third DC voltage is lower than the second DC voltage.   4. The power supply device according to claim 2, wherein the output of the first detection unit and the output of the second detection unit are wired-OR connected. 5. The first DCDC converter has first switching means for switching the voltage rectified and smoothed by the rectifying and smoothing means,
5. The power supply device according to claim 2, wherein an output voltage of the first DCDC converter is increased by starting a switching operation of the first switching means. 6.   The second detection means is configured to detect the first DCDC converter even if the output voltage of the second DCDC converter exceeds the fourth DC voltage due to an increase in the output voltage of the first DCDC converter. 6. The power supply apparatus according to claim 5, further comprising delay means for delaying the stop of the switching operation of the switching means. A third detecting means for detecting that the output voltage from the first DCDC converter is equal to or lower than the first DC voltage;
When operating in the first operation mode, the first DCDC converter is controlled to output the first DC voltage based on a detection result of the third detection means. The power supply device according to any one of claims 1 to 6. The first detection means has a first error amplifier,
The third detection means has a third error amplifier,
The power supply apparatus according to claim 7, wherein the output of the first error amplifier and the output of the third error amplifier are wired or connected. The first detection means and the third detection means are constituted by one error amplifier,
A resistor for dividing the output voltage of the first DCDC converter input to the one error amplifier;
The power supply device according to claim 7, wherein a resistance value of the resistor is switched between the first operation mode and the second operation mode. A switch for supplying or cutting off the first DC voltage to a load connected to the first DCDC converter;
When the switch to the second operation mode, the switch cuts off the supply of the first DC voltage to the load,
10. The power supply device according to claim 1, wherein the first DC voltage is supplied to the load by the switch when the mode is shifted to the first operation mode. 11. An image forming means for forming an image;
The power supply device according to any one of claims 1 to 10,
An image forming apparatus comprising: A driving unit for driving the image forming unit;
The image forming apparatus according to claim 11, wherein the driving unit is the load. A control unit for controlling the operation of the image forming unit;
The image forming apparatus according to claim 11, wherein the control unit is supplied with the second DC voltage from the second DCDC converter. An image forming means for forming an image;
Driving means for driving the image forming means;
Control means for controlling the image forming means and the driving means;
The power supply device according to claim 10, wherein power is supplied to the image forming unit, the driving unit, and the control unit;
With
The image forming apparatus, wherein the control unit controls the switch.

Images