JP2015088557A - Multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board which inhibits addition of connection resistance and occurrence of connection failure.SOLUTION: A multilayer wiring board includes: an electronic component; electrodes provided at the electronic component; an adhesion layer with which the electronic component is overlapped; and vias which are formed at the adhesion layer, each of the vias having an end part connected with the electrode. At least a part of a side surface of each electrode of the electronic component contacts with the via. Thus, even if misalignment between the via and the electrode occurs, reduction of a contact area between the via and the electrode is inhibited.

Description

  The present invention relates to a multilayer wiring board that is interlayer-connected through vias.

  In recent years, with the increase in the number of functions of portable devices, further enhancement of functions of semiconductor devices has been demanded. In order to satisfy this requirement, the wiring technology of semiconductor devices has been improved and the miniaturization of wiring has been advanced. As a high-density wiring technique, a multilayer wiring board is known. For example, as described in the cited document 1, generally, the wiring is connected to the end of the via with respect to the diameter of the via connecting the layers. The diameter of the land is set large. Similarly, the diameter of the electrode of the electronic component connected to the end of the via is set larger than the diameter of the via.

JP 2004-31531 A

  However, in the structure in which the land diameter is larger than the via diameter as in the above cited reference 1, or in the structure in which the diameter of the electrode of the electronic component is larger than the via diameter, the space between the land and the electrode is narrowed. Therefore, when connecting a semiconductor device having an electrode pad with a narrow pitch, such as WLCSP, it may be difficult to route wiring from a via connected to the electrode pad. Therefore, it may be possible to secure the space between the lands and electrodes by minimizing the diameter of the lands and electrodes. However, if the diameter of the lands and electrodes is reduced, the contact area between the vias and the lands and electrodes is reduced. Connection failure occurs due to an increase in resistance or a slight misalignment between the land or electrode and the via.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring board that can solve the problems caused by the prior art described above and can suppress an increase in connection resistance and occurrence of connection failure.

  One multilayer wiring board according to the present invention is formed on an electronic component, an electrode provided on the electronic component, an adhesive layer on which the electronic component is stacked, and the adhesive layer, and an end portion is connected to the electrode. In the multilayer wiring board including the via, at least a part of the side surface of the electrode is in contact with the via.

  According to one multilayer wiring board of the present invention, a via is formed in an adhesive layer on which an electronic component on which an electrode is formed is stacked, and at least a part of the side surface of the electrode is in contact with the via. Therefore, even if misalignment between the via and the electrode occurs, it is possible to suppress a decrease in the contact area between the via and the electrode. For this reason, increase in connection resistance and occurrence of connection failure can be suppressed.

  In addition, another multilayer wiring board according to the present invention includes a built-in component, an electrode provided in the built-in component, an adhesive layer on which the built-in component is overlapped, an adhesive layer, and an end portion formed on the electrode. In the multilayer wiring board including the vias to be connected, at least a part of the side surface of the electrode is in contact with the via.

  According to another multilayer wiring board according to the present invention, it is possible to achieve the same effects as the one multilayer wiring board.

  In one embodiment of the invention, the electrode is embedded in the via. Thereby, the contact area between the via and the electrode can be increased.

  In another embodiment of the present invention, the diameter of the electrode is smaller than the diameter of the via. Thereby, the occupation area of an electrode can be made small and the pitch between electrodes can also be made small. Therefore, the electrodes can be laid out with high density.

  In still another embodiment of the present invention, a wiring pattern having a land provided on a resin base material is provided, and an end of the via that is not connected to the electrode is connected to the land.

  According to the present invention, connection resistance and connection failure of a multilayer wiring board can be reduced.

It is sectional drawing which shows the structure of the multilayer wiring board which concerns on the 1st Embodiment of this invention. It is a top view which shows the relationship between the electrode and via | veer concerning 1st Embodiment. It is a flowchart which shows the manufacturing process of the multilayer wiring board which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the structure of the multilayer wiring board which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the manufacturing process of the multilayer wiring board which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the outline of the manufacturing process of the multilayer wiring board. It is sectional drawing which shows the relationship between the electrode and via | veer concerning other embodiment of this invention.

  Hereinafter, a multilayer wiring board according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a sectional view showing the structure of a multilayer wiring board according to the first embodiment of the present invention. As shown in FIG. 1, the multilayer wiring board according to the first embodiment includes a first printed wiring substrate 10, a second printed wiring substrate 20, a protective layer 40, and a third printed wiring substrate 30. Are laminated by thermocompression bonding (adhesive layers 51 to 53), and the electronic component 90 is mounted.

  The adhesive layer 51 adheres between the first printed wiring substrate 10 and the second printed wiring substrate 20. The adhesive layer 52 adheres between the second printed wiring board 20 and the protective layer 40. The adhesive layer 53 adheres between the protective layer 40 and the third printed wiring substrate 30. The protective layer 40 is made of an insulating film (PET, polyimide, liquid crystal polymer (LCP), etc.) in order to prevent an interlayer short circuit during thermocompression bonding. The adhesive layers 51 to 53 are made of, for example, an organic adhesive such as an epoxy adhesive or an acrylic adhesive.

  Further, the multilayer wiring board has an electronic component 90 and a via 70 as shown in FIG. The electronic component 90 is mounted in a state of being directly attached to the adhesive layer 53 in the opening 39 formed in the third printed wiring substrate 30. The via 70 extends in the stacking direction and penetrates the protective layer 40, and is provided between the electronic component 90 and the second printed wiring substrate 20, that is, in the adhesive layer 53, the protective layer 40, and the adhesive layer 52.

  The via 70 is made of an alloy including a low melting point metal filler and a high melting point metal filler, and the surface thereof is covered with a thermosetting resin. Here, the metal filler is, for example, nickel, gold, silver, copper, aluminum, iron, tin, bismuth, indium, lead or the like. The thermosetting resin is a paste mainly composed of epoxy, acrylic, urethane, or the like.

  As shown in FIG. 1, each of the first to third printed wiring base materials 10 to 30 includes first to third resin base materials 11 to 31 and signal wirings 12 to 32. The signal wiring 12 is formed on the lower surface (one surface) of the first resin base material 11. The signal wiring 22 is formed on the lower surface and the upper surface (both surfaces) of the second resin base material 21. The signal wiring 32 is formed on the lower surface and the upper surface (both surfaces) of the third resin base material 31.

  The 1st-3rd resin base materials 11-31 are comprised with the resin film. Here, the resin film is, for example, polyimide, polyolefin, liquid crystal polymer (LCP), thermosetting epoxy resin, or the like. The signal wirings 12 to 32 are made of a conductive material such as a patterned copper foil.

  The third printed wiring board 30 has signal vias 33 filled in via holes H penetrating the third resin base 31. The signal vias 33 are respectively connected to the signal wirings 32 formed on both surfaces of the third resin base material 31. The signal via 33 is formed by plating, for example.

  The electronic component 90 is configured by WLP (Wafer Level Package). As shown in FIG. 1, an electrode 61 such as a rewiring electrode connected to the pad 61 a and a resin 62 are provided on the lower surface of the electronic component 90. The electrode 61 is electrically connected to the upper end of the via 70. The resin 62 covers the lower surface of the electronic component 90 so that the electrode 61 is exposed.

  Here, FIG. 2 is a top view showing the relationship between the electrode 61 and the via 70 according to the first embodiment. As shown in FIG. 2, the diameter of the electrode 61 is smaller than the diameter of the via 70, and the electrode 61 is embedded in the via 70. Therefore, the electrode 61 is in contact with the via 70 not only on its lower surface but also on its side surface. The electrode 61 is made of a conductive material such as Cu, Ni, Au, or Al, and forms an alloy with the via 70.

  If the via 70 is in contact with the lower surface of the electrode 61 and the diameter of the electrode 61 is larger than the diameter of the via 70, the interval between the electrodes 61 is narrowed, and the number of the electrodes 61 in the electronic component 90 is reduced. . On the other hand, in the multilayer wiring board according to the first embodiment, the electrodes 61 of the electronic component 90 can be laid out with high density.

  When the diameter of the electrode 61 is smaller than the diameter of the via 70 as described above, the contact area between the via 70 and the electrode 61 is reduced, and when the misalignment between the via 70 and the electrode 61 occurs. The possibility of connection failure is increased. However, in this regard, in the multilayer wiring board according to the first embodiment, the electrode 61 is embedded in the upper end of the via 70, and not only the lower surface of the electrode 61 but also the side surface of the electrode 61 is in contact with the via 70. For this reason, the contact area can be sufficiently increased, and even if the misalignment between the via 70 and the electrode 61 occurs, the decrease in the contact area between the via 70 and the electrode 61 and the poor connection can be suppressed. .

  Next, a manufacturing method of the multilayer wiring board according to the first embodiment will be described along FIG. 3 with reference to FIGS. FIG. 3 is a flowchart showing manufacturing steps of the multilayer wiring board according to the first embodiment. 4-8 is sectional drawing which shows the outline of the manufacturing process of a multilayer wiring board.

  First, as shown in FIG. 4, the 1st-3rd printed wiring base materials 10-30 are prepared (step S100 of FIG. 3). Here, the signal wirings 12 to 32 of the first to third printed wiring substrates 10 to 30 are formed by a subtractive method or a semi-additive method. Further, the opening 39 of the third printed wiring board 30 is formed by laser processing, drilling, or die processing.

  Next, as shown in FIG. 5, the adhesive layer 51 is laminated on the upper surface of the first printed wiring substrate 10 (step S <b> 102 in FIG. 3), and the adhesive layer 52 is further protected on the upper surface of the second printed wiring substrate 20. The layer 40 and the adhesive layer 53 are laminated (step S104 in FIG. 3).

  Then, as shown in FIG. 6, the 3rd printed wiring base material 30 is laminated | stacked on the upper surface of the contact bonding layer 53, and the 1st-3rd printed wiring base materials 10-30 are temporarily crimped | bonded (step S106 of FIG. 3). . After that, as shown in FIG. 7, a hole H ′ penetrating the adhesive layer 53, the protective layer 40, and the adhesive layer 52 is formed by laser processing, for example, and as shown in FIG. The via 70 is formed by filling (step S108 in FIG. 3).

  Finally, the electronic component 90 is positioned so as to be accommodated in the opening 39 of the third printed wiring substrate 30, and the electronic component 90 is mounted on the upper surface of the adhesive layer 53 (step S110 in FIG. 3). The first to third printed wiring substrates 10 to 30 are thermocompression bonded. Thus, the electronic component 90 is mounted in the opening 39 so that the electrode 61 is embedded in the upper end portion of the via 70, and the first to third printed wiring substrates 10 to 30 are pressure-bonded, as shown in FIG. A multilayer wiring board is manufactured.

  The lower end of the via 70 not connected to the electrode 61 is connected to a land of the signal wiring 22 formed on the upper surface of the second resin base 21 of the second printed wiring base 20. When the electrode 61 and the via 70 are pressure-bonded, the low melting point metal filler and the thermosetting resin in the via 70 are melted. The molten low melting point metal filler is alloyed with copper or the like of the electrode 61.

[Second Embodiment]
Next, a multilayer wiring board according to the second embodiment of the present invention will be described with reference to FIG. Although the multilayer wiring board according to the first embodiment is a multilayer wiring board on which the electronic component 90 is mounted, the multilayer wiring board according to the second embodiment functions as a component built-in board in which the built-in component 60 is built. .

  FIG. 9 is a cross-sectional view showing the structure of the multilayer wiring board according to the second embodiment of the present invention. As shown in FIG. 9, the multilayer wiring board according to the second embodiment includes a first printed wiring substrate 10, a second printed wiring substrate 20, a protective layer 40, and a third printed wiring substrate 30. Are laminated by thermocompression bonding (adhesive layers 51 to 53), and a built-in component 60 is built in.

  The basic configurations of the adhesive layers 51 to 53, the protective layer 40, the first to third printed wiring substrates 10 to 30, and the built-in component 60 are the adhesive layers 51 to 53, the protective layer 40, and the protective layer 40 described in the first embodiment. Since it is the same as that of the 1st-3rd printed wiring base materials 10-30 and the electronic component 90, below, the point which is fundamentally different from 1st Embodiment is demonstrated.

  As shown in FIG. 9, the multilayer wiring board according to the second embodiment includes a built-in component 60 and a via 70. The built-in component 60 is built in the opening 29 formed in the second printed wiring substrate 20 in a state of being sandwiched between the first and third printed wiring substrates 10 and 30. The via 70 extends in the stacking direction and penetrates the protective layer 40, and between the built-in component 60 and the signal wiring 32 on the upper surface of the third printed wiring substrate 30, that is, the adhesive layer 52, the protective layer 40, and the adhesive layer. 53 and the third resin base material 31.

  The built-in component 60 is made of WLP like the electronic component 90, and an upper surface thereof is provided with an electrode 61 such as a rewiring electrode connected to the pad 61a and a resin 62, as shown in FIG. Is electrically connected to the lower end of the via 70. The resin 62 covers the upper surface of the built-in component 60 so that the electrode 61 is exposed.

  The diameter of the electrode 61 of the built-in component 60 is configured to be smaller than the diameter of the via 70. The upper end of the via 70 is connected to the land of the signal wiring 32 formed on the upper surface of the third resin base 31 of the third printed wiring base 30 so as to penetrate the third resin base 31. Also in the multilayer wiring board according to the second embodiment configured as described above, the same operational effects as those of the multilayer wiring board according to the first embodiment can be obtained.

  Next, a method for manufacturing a multilayer wiring board according to the second embodiment will be described along FIG. 10 with reference to FIGS. FIG. 10 is a flowchart showing manufacturing steps of the multilayer wiring board according to the second embodiment. 11 to 14 are cross-sectional views illustrating an outline of the manufacturing process of the multilayer wiring board.

  First, as shown in FIG. 11, the 1st and 3rd printed wiring base materials 10 and 30 are prepared with the 2nd printed wiring base material 20 in which the opening part 29 was formed (step S120 of FIG. 10). Next, as shown in FIG. 12, an adhesive layer 51 is laminated on the upper surface of the first printed wiring substrate 10 (step S122 in FIG. 10), and an adhesive layer 53 and a protective layer are formed on the lower surface of the third printed wiring substrate 30. 40 and the adhesive layer 52 are laminated (step S124 in FIG. 10).

  Subsequently, as shown in FIG. 13, the adhesive layer 52 laminated on the third printed wiring substrate 30 is laminated on the upper surface of the second printed wiring substrate 20, and the adhesive layer 52, the protective layer 40, the adhesion are bonded by laser processing. Holes H ′ penetrating the layer 53 and the third resin base material 31 are formed, and as shown in FIG. 14, the vias 70 are formed by filling the holes H ′ with a conductive paste (step S126 in FIG. 10).

  Then, the built-in component 60 is mounted on the upper surface of the adhesive layer 51 laminated on the first printed wiring substrate 10 (step S128 in FIG. 10), and the built-in component 60 is accommodated in the opening 29 so as to be accommodated in the opening 29. After the second printed wiring substrate 20 is laminated on the upper surface, the first to third printed wiring substrates 10 to 30 are heat-pressed (Step S130 in FIG. 10).

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, A various change, addition, etc. are possible in the range which does not deviate from the meaning of invention. For example, as shown in FIGS. 15A to 15C, only a part of the side surface of the electrode 61 may be in contact with the via 70.

  In the example shown in FIG. 15A, only part of the side surface and part of the lower surface of the electrode 61 are in contact with the via 70. In the example shown in FIG. 15B, only a part of the side surface and the entire lower surface of the electrode 61 are in contact with the via 70. In the example shown in FIG. 15C, the entire lower surface of the electrode 61 and only the lower part of the side surface are in contact with the via 70.

DESCRIPTION OF SYMBOLS 10-30 1st-3rd printed wiring base material 11-31 1st-3rd resin base material 12-32 Signal wiring 29,39 Opening part 33 Signal via 40 Protective layer 51-53 Adhesive layer 60 Built-in component 61 Electrode 61a Pad 62 Resin 70 Via 90 Electronic component

Claims (5)

Electronic components,
An electrode provided on the electronic component;
An adhesive layer on which the electronic components are stacked;
In a multilayer wiring board formed in the adhesive layer and having an end connected to the electrode,
A multilayer wiring board, wherein at least a part of a side surface of the electrode is in contact with the via. Built-in parts,
An electrode provided in the built-in component;
An adhesive layer on which the built-in components are stacked;
In a multilayer wiring board formed in the adhesive layer and having an end connected to the electrode,
A multilayer wiring board, wherein at least a part of a side surface of the electrode is in contact with the via. The multilayer wiring board according to claim 1, wherein the electrode is embedded in the via. The multilayer wiring board according to claim 1, wherein a diameter of the electrode is smaller than a diameter of the via. Provided with a wiring pattern having lands provided on a resin substrate,
The multilayer wiring board according to claim 1, wherein an end of the via that is not connected to the electrode is connected to the land.

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