JP2015084270A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cancel coupling noise while suppressing increase of chip area in an open-bit line type semiconductor storage device.SOLUTION: A semiconductor storage device includes: a plurality of memory mats arranged in a line; and a sense amplifier column SAA disposed between neighboring memory mats, and activates a dummy word line DWL in the memory mats neighboring to the selected memory mat by responding to activation of a word line WL in the selected memory mat. The dummy word line DWL is not connected to dummy cells, so that it is not needed that a circuit for storing midpoint potential in the dummy cell.

Description

  The present invention relates to a semiconductor memory device, and more particularly to an open bit line type semiconductor memory device.

  A semiconductor memory device typified by a DRAM includes a sense amplifier connected to a pair of bit lines, and a potential difference generated in the bit line pair is amplified by the sense amplifier. As the bit line pair wiring method, a folded bit line method in which bit line pairs are wired in the same direction as viewed from the sense amplifier and an open bit line method in which bit line pairs are wired in opposite directions from the sense amplifier are known. ing.

  In the folded bit line system, since a pair of bit lines intersect with the same word line, the same coupling noise is superimposed on these bit lines when the word line is activated. For this reason, the noise accompanying the activation of the word line is cancelled. On the other hand, in the open bit line system, since a pair of bit lines intersects with different word lines, coupling noise is superimposed only on one bit line when the word line is activated. For this reason, the operation margin of the sense amplifier is reduced, and data may be inverted in some cases.

  As a method of solving the above problem in the open bit line system, a method of canceling noise using a dummy word line is known (see Patent Document 1).

JP-A-6-103754

  However, in the semiconductor memory device described in Patent Document 1, since a dummy cell is connected to a dummy word line, a memory cell to be read is connected to one bit line, and a dummy cell is connected to the other bit line. Will be. Therefore, in order not to interfere with the sensing operation, it is necessary to correctly control the potential stored in the dummy cell. In general, since one dummy cell is shared by many memory cells, in order to make the influence equal to a memory cell storing a high level and a memory cell storing a low level, The potential to be stored must be exactly at the intermediate level (intermediate potential between high level and low level). For this reason, a circuit for generating an accurate intermediate level is required, which increases the chip size.

  Further, in Patent Document 1, since it is necessary to form an active region for forming a dummy cell in a memory mat, there is a problem in that the chip size is increased.

  A semiconductor memory device according to the present invention includes at least one of a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at the intersections of these word lines and bit lines, and a dummy cell. A plurality of memory mats having dummy word lines and a plurality of sense amplifier rows arranged between adjacent memory mats, one connected to the bit line of the adjacent memory mat and the other adjacent A sense amplifier array having a plurality of sense amplifiers each including a pair of input / output nodes respectively connected to the bit line of the memory mat on the other side, and a word line in the selected memory mat among the plurality of memory mats Means for activating a dummy word line in a memory mat adjacent to the selected memory mat in response to activation; Characterized in that it comprises a.

  According to the semiconductor memory device of the present invention, since it is not necessary to store an intermediate potential or the like in the dummy cell, it is not necessary to provide a circuit for generating such a potential. Further, since the dummy cell itself is unnecessary, there is no need to form an active region for forming the dummy cell in the memory mat. For this reason, according to the present invention, it is possible to cancel coupling noise generated in the open bit line system while suppressing an increase in chip size.

1 is a layout diagram showing a configuration of a memory cell array portion of a semiconductor memory device according to a preferred embodiment of the present invention. It is a figure which shows the circuit structure of memory mats MAT1-MAT7 other than the memory mats MAT0 and MAT8 located at both ends. It is a figure which shows the circuit structure of the memory mats MAT0 and MAT8 located in both ends. It is a figure which shows the layout of the active region in a Morimat. 3 is a circuit diagram of a memory cell MC. FIG. It is a circuit diagram of sense amplifier SA. 3 is a circuit diagram of a decoder circuit 40. FIG. 3 is a circuit diagram of a decoder circuit 50. FIG. It is a table | surface which shows the relationship between the value of the mat | matte selection signals M0-M2, the selection signals SELECT0-SELECT7 activated, and the dummy selection signals DUMMY0-DUMMY8. FIG. 6 is a timing chart showing a potential change of a bit line BL, where (a) shows a case where a high level is held in the cell capacitor C of a memory cell MC to be read, and (b) shows a low level is held. Shows the case.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a layout diagram showing a configuration of a memory cell array portion of a semiconductor memory device according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the memory cell array portion of the semiconductor memory device according to the present embodiment has nine memory mats MAT0 to MAT8 arranged in the Y direction. A sense amplifier array SAA is arranged between adjacent memory mats. In addition, word line driver columns WLDA are arranged on both sides in the X direction of each of the memory mats MAT0 to MAT8. In this embodiment, nine memory mats are arranged in a line, but the number of memory mats arranged in a line in the present invention is not particularly limited.

  Memory mats MAT0 to MAT8 are selected by corresponding selection signals SELECT0 to SELECT7, respectively. However, the memory mats MAT0 and MAT8 located at both ends are selected by the same selection signal SELECT0. This is because the number of bit lines included in the memory mats MAT0 and MAT8 located at both ends is half the number of bit lines included in the other memory mats MAT1 to MAT7, and the two memory mats MAT0 and MAT8 are combined. This is because it is equivalent to one of the mats MAT1 to MAT7.

  Also, dummy selection signals DUMMY0 to DUMMY8 are assigned to the memory mats MAT0 to MAT8. The dummy selection signals DUMMY0 to DUMMY8 are signals for activating dummy word lines described later. As shown in FIG. 1, individual dummy selection signals DUMMY0 and DUMMY8 are assigned to the memory mats MAT0 and MAT8 located at both ends, respectively.

  FIG. 2 is a diagram showing a circuit configuration of memory mats MAT1 to MAT7 other than memory mats MAT0 and MAT8 located at both ends. FIG. 3 is a diagram showing a circuit configuration of the memory mats MAT0 and MAT8 located at both ends.

  As shown in FIGS. 2 and 3, the memory mats MAT0 to MAT8 include a plurality of word lines WL wired in the X direction, a plurality of bit lines BL wired in the Y direction, and the word lines WL and bit lines BL. Memory cells MC arranged at the respective intersections. The number of word lines WL and bit lines BL shown in FIGS. 2 and 3 is merely an example, and the present invention is not limited to this.

  Of the plurality of word lines WL, half are connected to the word line driver column WLDA arranged on one side in the X direction, and the other half are connected to the word line driver column WLDA arranged on the other side in the X direction. It is connected. The word line driver column WLDA is composed of a plurality of word line drivers WLD that drive the corresponding word lines WL.

  However, some word lines (two word lines on one side in this embodiment) located at the end in the Y direction are not used, and these become unused word lines WLZ. This is because the process conditions at the time of manufacture are slightly different between the end portion and the central portion of the memory mat, so that defective cells are likely to occur at the end portion of the memory mat. Therefore, the memory cells connected to these unused word lines WLZ are handled as dummy cells DC. Since the unused word line WLZ is fixed in an inactive state, the dummy cell DC is not connected to the bit line BL.

  In addition, the memory mats MAT0 to MAT8 are further provided with dummy word lines DWL that are wired in the X direction and arranged every two word lines WL. That is, the unit configuration is repeatedly arranged in the Y direction with two word lines WL and one dummy word line DWL as a unit configuration. As shown in FIGS. 2 and 3, one of the dummy word lines DWL is connected to a dummy word line driver DWLD included in the word line driver column WLDA. The dummy word line driver DWLD is a circuit that activates the dummy word line DWL in response to corresponding dummy selection signals DUMMY0 to DUMMY8. Of the plurality of dummy word lines DWL, which dummy word line DWL is connected to the dummy word line driver DWLD is not particularly limited. Other dummy word lines DWL not connected to the dummy word line driver DWLD are fixed to the ground potential.

No memory cell MC or dummy cell DC is arranged at the intersection of the dummy word line DWL and the bit line BL. That is, the dummy word line DWL is a dummy wiring that does not originally contribute to the actual operation. The reason why such a dummy word line DWL is provided is that a layout in which the occupation area of the memory cell MC is 6F ² is adopted when the minimum processing dimension is F.

  FIG. 4 is a diagram showing the layout of the active region in the memory mat, and shows the region P in FIG. 2 in an enlarged manner.

  As shown in FIG. 4, in the present embodiment, the longitudinal direction of the active region 10 has a slight angle with respect to the Y direction. Such active regions 10 are arranged along the X direction, thereby forming an active region row 10A extending in the X direction. A plurality of active region rows 10A are provided in the Y direction.

  With this configuration, two adjacent word lines WL always pass over the same active region. In such a layout, since the wiring density of the word lines WL is not constant, the wiring including the word lines WL and the dummy word lines DWL is provided by arranging the dummy word lines DWL every two word lines WL. The density is constant. The reason for keeping the wiring density constant is to ensure good process conditions. Thereby, the dummy word line DWL is wired along the element isolation region 20 existing between the adjacent active region columns 10A.

The active region 10 includes three diffusion regions 10a to 10c, and a word line WL passes through an upper portion between these three diffusion regions. Thus, a cell transistor of the memory cell MC is configured by two adjacent diffusion regions and the word line WL. The diffusion region 10a located at the center is connected to the corresponding bit line BL via the bit contact 11, and the diffusion regions 10b and 10c located at both ends are connected to the corresponding cell capacitor via the cell contact 12. . As described above, the memory cell MC is arranged at each intersection of the two adjacent bit lines BL and the two adjacent word lines WL, and the area occupied by the memory cell MC is 6F ^2. Is realized.

  FIG. 5 is a circuit diagram of the memory cell MC.

  As shown in FIG. 5, the memory cell MC has a circuit configuration in which a cell transistor T and a cell capacitor C are connected in series between a bit line BL and a plate wiring PL. The gate electrode of the cell transistor T is connected to the corresponding word line WL (in practice, the word line WL itself constitutes the gate electrode). Thus, when the word line WL is activated, the cell capacitor C is electrically connected to the corresponding bit line BL. One diffusion region of the cell transistor T and the bit line BL are connected via the bit contact 11 shown in FIG. The other diffusion region of the cell transistor T and the cell capacitor C are connected via the cell contact 12 shown in FIG.

  Returning to FIG. 2, the bit lines BL in the memory mats MAT1 to MAT7 are alternately arranged in a sense amplifier array SAA arranged on one side in the Y direction and a sense amplifier array SAA arranged on the other side in the Y direction. It is connected. The sense amplifier array SAA includes a plurality of sense amplifiers SA. One input / output node is connected to the bit line BL of the adjacent memory mat on the other side, and the other input / output node is connected to the other adjacent side. It is connected to the bit line BL of the memory mat. That is, an open bit line system is adopted.

  On the other hand, in the memory mats MAT0 and MAT8 located at the end portions, the bit lines BL and the dummy bit lines DBL are alternately arranged as shown in FIG. The bit line BL is connected to the sense amplifier array SAA arranged on one side in the Y direction, and the dummy bit line DBL is connected to the potential supply circuit VPC arranged on the other side in the Y direction. ing. The potential supply circuit VPC is a circuit that supplies the precharge potential (VBLP) of the bit line BL to the dummy bit line DBL.

  FIG. 6 is a circuit diagram of the sense amplifier SA.

  As shown in FIG. 6, the sense amplifier SA includes flip-flop-connected transistors 31 to 34. A connection point between the transistors 31 and 33 forms one input / output node N1, and the transistors 32 and 34 The connection point constitutes the other input / output node N2. Input / output node N1 is connected to bit line BL of one adjacent memory mat MATi (i = 0 to 7), and input / output node N2 is connected to bit line BL of the other adjacent memory mat MATi + 1. ing.

  The above is the layout of the memory cell array portion of the semiconductor memory device according to the present embodiment. Next, the selection of the memory mat and the activation of the dummy word line DWL associated therewith will be described.

  FIG. 7 is a circuit diagram of the decoder circuit 40 that generates the selection signals SELECT0 to SELECT7.

  As shown in FIG. 7, the decoder circuit 40 is configured by eight AND gates having different combinations of inversion / non-inversion of input mat selection signals M0 to M2. As a result, the decoder circuit 40 decodes the mat selection signals M0 to M2 in binary format, and activates any one of the selection signals SELECT0 to SELECT7. The relationship between the values of the mat selection signals M0 to M2 and the selection signals SELECT0 to SELECT7 to be activated is as shown in FIG.

  As shown in FIG. 1, among the selection signals SELECT0 to SELECT7, the selection signal SELECT0 is supplied in common to the memory mats MAT0 and MAT8 located at both ends. Therefore, when the values of the mat selection signals M0 to M2 are “000”, the memory mats MAT0 and MAT8 are selected simultaneously. On the other hand, when the values of the mat selection signals M0 to M2 are “001” to “111”, only one of the memory mats MAT1 to MAT7 is selected according to the value.

  In the selected memory mat, one of the word line drivers WLD included in the word line driver column WLDA is selected based on the row address, and the corresponding word line WL is activated. As a result, all the memory cells MC connected to the word line WL are connected to the corresponding bit line BL, and the potential of the bit line BL changes according to the charge held in the cell capacitor C. At this time, coupling noise due to activation of the word line WL is superimposed on the bit line BL.

  FIG. 8 is a circuit diagram of the decoder circuit 50 that generates the dummy selection signals DUMMY0 to DUMMY8.

  As shown in FIG. 8, the decoder circuit 50 includes two sets (16 in total) of eight AND gates having different inversion / non-inversion combinations of the input mat selection signals M0 to M2, and outputs of the two AND gates. Is formed by seven OR gates. With the circuit configuration shown in FIG. 8, the decoder circuit 50 decodes the mat selection signals M0 to M2 in binary format and activates any two of the dummy selection signals DUMMY0 to DUMMY8. The relationship between the values of the mat selection signals M0 to M2 and the activated dummy selection signals DUMMY0 to DUMMY8 is also shown in FIG.

  As shown in FIG. 9, when a mat is selected by the selection signals SELECT0 to SELECT7, two dummy selection signals corresponding to the memory mat adjacent to the selected memory mat are activated. Since the memory mats MAT0 and MAT8 located at both ends are simultaneously selected by the selection signal SELECT0, in this case, the dummy selection signals DUMMY1 and DUMMY7 are activated.

  When any two of the dummy selection signals DUMMY0 to DUMMY8 are activated, the dummy word line driver DWLD is selected and the dummy word line DWL is activated in the corresponding memory mat. Thereby, coupling noise due to activation of the dummy word line DWL is superimposed on all the bit lines BL intersecting with the dummy word line DWL. As described above, since neither the memory cell MC nor the dummy cell DC is connected to the dummy word line DWL, the influence of the dummy word line DWL on the bit line BL is substantially only coupling noise.

  As a result, the potential appearing at the input / output nodes N1 and N2 of the sense amplifier SA is a potential where coupling noise is superimposed, so that the noise is cancelled. In addition, since neither the memory cell MC nor the dummy cell DC is connected to the dummy word line DWL, the coupling noise is accurately canceled.

  FIG. 10 is a timing chart showing the potential change of the bit line BL. FIG. 10A shows a case where the high level is held in the cell capacitor C of the memory cell MC to be read, and FIG. 10B shows the low level. The case that was held is shown. In FIG. 10, the bit line connected to the memory cell MC to be read is represented as BLT, and the bit line serving as the reference side is represented as BLB. The bit line BLT is a bit line connected to one of the input / output nodes N1 and N2 of the sense amplifier SA, and the bit line BLB is a bit line connected to the other side.

  As shown in FIG. 10A, when the cell capacitor C holding the high level is connected to the bit line BLT, the potential of the bit line BLT rises from the precharge level VBLP by ΔV + α. Here, ΔV is a rising component due to the electric charge flowing out from the cell capacitor C, and α is a coupling noise accompanying the activation of the word line WL. On the other hand, the bit line in the adjacent memory mat, that is, the bit line BLB on the reference side rises by α as the dummy word line DWL is activated. As a result, the potential difference generated between the pair of bit lines BLT and BLB is ΔV, which coincides with the rising component due to the charge outflow from the cell capacitor C. If the dummy word line DWL is not activated, the potential of the bit line BLB on the reference side remains at the precharge level VBLP, so the potential difference is ΔV + α.

  On the other hand, when the cell capacitor C holding the low level is connected to the bit line BLT, the potential of the bit line BLT is lowered by ΔV−α from the precharge level VBLP as shown in FIG. Here, ΔV is a lowering component due to the inflow of charge into the cell capacitor C. On the other hand, the bit line BLB on the reference side rises by α as the dummy word line DWL is activated. As a result, the potential difference generated between the pair of bit lines BLT and BLB becomes ΔV, which coincides with the reduced component due to the charge inflow into the cell capacitor C. If the dummy word line DWL is not activated, the potential of the bit line BLB on the reference side remains at the precharge level VBLP, so the potential difference becomes ΔV−α, and the potential difference is reduced. End up. On the other hand, in this embodiment, since the dummy word line DWL in the adjacent memory mat is activated, the decrease in potential difference generated between the pair of bit lines BLT and BLB is corrected, and the potential difference of ΔV is corrected. It can be secured.

  As described above, according to the present embodiment, the potential difference generated between the pair of bit lines BLT and BLB is always ΔV regardless of the contents of the data held in the memory cell MC. A sufficient operating margin can be secured. In addition, as described above, since neither the memory cell MC nor the dummy cell DC is connected to the dummy word line DWL, the coupling noise can be canceled accurately. Further, a circuit for supplying an intermediate potential or the like to the dummy cell is not necessary. Further, since the coupling noise is canceled using the dummy word line DWL which is not used originally, the occupied area of the memory mat is not increased. Therefore, it is possible to cancel the coupling noise generated in the open bit line system while suppressing the increase in chip size.

  In the present embodiment, the memory mats MAT0 and MAT8 located at both ends are simultaneously selected by the selection signal SELECT0, while the dummy selection signals DUMMY0 and DUMMY8 corresponding thereto are not activated simultaneously. Specifically, when the memory mat MAT1 is selected, the dummy selection signals DUMMY0 and DUMMY2 are activated, but the dummy selection signal DUMMY8 is not activated. Similarly, when the memory mat MAT7 is selected, the dummy selection signals DUMMY6 and DUMMY8 are activated, but the dummy selection signal DUMMY0 is not activated. Thus, although the memory mats MAT0 and MAT8 at both ends are simultaneously selected, the dummy selection signals DUMMY0 and DUMMY8 corresponding thereto are selectively activated, so that the dummy in the memory mats that are not adjacent to each other is selectively activated. The word line DWL is not unnecessarily activated, and generation of useless power consumption can be prevented.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the case where the present invention is applied to a DRAM has been described as an example. However, the scope of application of the present invention is not limited to this, and various semiconductor memory devices adopting an open bit line system are used. It is possible to apply.

DESCRIPTION OF SYMBOLS 10 Active region 10A Active region row | line | column 10a-10c Diffusion region 11 Bit contact 12 Cell contact 20 Element isolation region 31-34 Transistor 40, 50 Decoder circuit BL Bit line DBL Dummy bit line DC Dummy cell DWL Dummy word line DWLD Dummy word line driver MAT0 MAT8 Memory mat MC Memory cell N1, N2 Input / output node SA Sense amplifier SAA Sense amplifier column VPC Potential supply circuit WL Word line WLD Word line driver WLDA Word line driver column WLZ Unused word line

Claims (12)

Multiple memory arrays;
A plurality of memory cells;
Multiple word line drivers;
One or more dummy word line drivers,
Each of the plurality of memory arrays includes a plurality of word lines and a plurality of bit lines intersecting with each of the plurality of word lines,
There are dummy word lines every two word lines, and word lines other than the dummy word lines are active word lines,
Each of the plurality of memory cells is provided where a corresponding active word line and a corresponding bit line intersect,
Each of the plurality of word line drivers is connected to a corresponding active word line,
The one or more dummy word line drivers are connected to one or more corresponding dummy word lines;
A plurality of dummy word lines not connected to the one or more dummy word line drivers are connected to a fixed potential;
When a word line driver of one memory array of the plurality of memory arrays is activated, one dummy word line driver of the one or more dummy word line drivers is activated in an adjacent memory array. A semiconductor memory device configured as described above.   The semiconductor memory device according to claim 1, wherein the fixed potential is a ground potential.   2. The semiconductor memory device according to claim 1, wherein the fixed potential is a negative potential. An unused word line provided at each end of each of the plurality of memory arrays;
4. The semiconductor memory device according to claim 1, further comprising: a plurality of memory cells provided where the corresponding unused word line and the corresponding bit line intersect each other. 5. .   The semiconductor memory device according to claim 4, further comprising a plurality of word line drivers each connected to a corresponding unused word line. Two unused word lines provided at each end of each of the plurality of memory arrays;
4. The semiconductor memory device according to claim 1, further comprising: a plurality of memory cells provided where the corresponding unused word line and the corresponding bit line intersect each other. 5. .   The semiconductor memory device according to claim 6, further comprising a plurality of word line drivers each connected to a corresponding unused word line.   8. The semiconductor memory device according to claim 1, further comprising a plurality of sense amplifiers provided between adjacent memory arrays.   9. The semiconductor memory device according to claim 8, wherein each of the plurality of sense amplifiers is connected to one corresponding bit line and the other corresponding bit line of the adjacent memory array.   9. A potential supply circuit provided on the one side of the plurality of memory arrays not having an adjacent memory array on one side and connected to a bit line not connected to a sense amplifier. Or the semiconductor memory device according to 9;   11. The semiconductor memory device according to claim 10, wherein the potential supply circuit supplies a precharge potential to the bit line not connected to a sense amplifier.   12. The semiconductor memory device according to claim 1, wherein the plurality of memory arrays are a plurality of open bit line memory arrays.

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