JP2015069688A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of improving the reliability of data.SOLUTION: A semiconductor storage device of an embodiment includes: a plurality of memory cells capable of holding data; a plurality of word lines connected to the plurality of memory cells; and a control unit. The control unit performs: a first step for applying a first write voltage to a word line which is selected out of the plurality of word lines and applying a first verify voltage and a second verify voltage higher than the first verify voltage; and a second step for applying a third verify voltage lower than the first verify voltage and a fourth verify voltage lower than the second verify voltage and higher than the third verify voltage to the word line which is selected out of the plurality of word lines after the first step.

Description

  The present embodiment relates to a semiconductor memory device.

  2. Description of the Related Art NAND flash memories are known as semiconductor memory devices that can hold multi-value data.

JP 2003-273291 A

  The present embodiment provides a semiconductor memory device that can improve data reliability.

  The semiconductor memory device according to the embodiment includes a plurality of memory cells capable of holding data, a plurality of word lines connected to the plurality of memory cells, and a control unit. The control unit applies a first write voltage to a selected word line among the plurality of word lines, and applies a first verify voltage and a second verify voltage higher than the first verify voltage. A third verify voltage lower than the first verify voltage and lower than the second verify voltage are applied to a word line selected from the plurality of word lines after the first step and the first step. A second step of applying a fourth verify voltage higher than the third verify voltage is executed.

1 is a diagram showing a configuration of a semiconductor memory device according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor memory device according to a first embodiment. The figure which shows the threshold voltage distribution and write-in system of a memory cell. 3 is a flowchart showing the operation of the semiconductor memory device of the first embodiment. 3 is a flowchart showing the operation of the semiconductor memory device of the first embodiment. 3 is a timing chart showing the operation of the semiconductor memory device according to the first embodiment.

(First embodiment)
As shown in FIG. 1, the semiconductor memory device 1 according to the first embodiment includes a memory cell array 2, row data 3, a voltage generation circuit 4, a control unit 5, a data input / output circuit 6, a first latch circuit 7, and a first latch circuit 7. 2 latch circuits 8 are provided.

1-1. Memory cell array 2 1-1-1. FIG. 2 is a diagram illustrating the configuration of the memory cell array 2. The memory cell array 2 has a plurality of memory cells MT and is connected by a word line WL. The word line WL is connected to the row decoder 3. The memory cell MT is connected to the bit line BL, and data is output via each bit line BL.

1-1-2. Threshold voltage distribution of the memory cell MT The threshold voltage distribution of the memory cell MT will be described with reference to FIG. FIG. 3 is a diagram showing the threshold voltage distribution and the write method of the memory cell MT. As shown in the figure, the horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells MT.

  In the present embodiment, it is assumed that the memory cell MT stores multilevel data, for example, quaternary data (2 bits / cell). In this case, the data in the memory cell MT is composed of upper page data and lower page data.

  A method of writing quaternary data to the memory cell MT will be described with reference to FIG. As a writing method, the lower page is written and then the upper page is written.

  First, the lower page write operation will be described. It is assumed that all memory cells MT have a threshold voltage of an erase voltage (E level) before the lower page is written.

  As shown in the figure, when writing the lower page, the control unit 5 sets the data of the lower page to the E level or the LM level. It is assumed that “1” data is stored when the threshold voltage of the memory cell MT is the erase voltage (E level), and “0” data is stored when the threshold voltage is the LM level.

  Next, the upper page write operation will be described. The upper page is written by writing 2-bit data. Further, the upper page is written based on a write command input from the host and data “0” or “1” of the lower page already written in the memory cell MT.

  At the time of writing the upper page, if the data of the lower page is “1”, the threshold voltage of the data is set to the erase voltage (E level) or the A level that is higher than the E level. On the other hand, when the data of the lower page is “0”, the threshold voltage is set to the B level or the C level higher than the B level in the upper page write. In the case of A level data, data of “10” = (lower page data, upper page data) is stored, “00” data is stored in the B level, and “01” data is stored in the C level. Assume that each is remembered.

1-2. About Row Decoder 3 Returning to FIG. 1, the row decoder 3 will be described. The row decoder 3 includes a block decoder and a transfer transistor (N channel MOS transistor). The block decoder decodes the block address given from the control unit 5 at the time of data write operation, read operation, and erase, and selects the block BLK based on the result.

  The row decoder 3 decodes the row address given from the control unit 5 and selects a desired word line WL among the plurality of word lines WL in the selected block based on the result.

1-3. Voltage Generation Circuit 4 The voltage generation circuit 4 generates a voltage necessary for data writing, reading, and erasing by boosting or stepping down a voltage Vcc applied from the outside.

1-4. Control Unit 5 The control unit 5 controls the operation of the entire semiconductor memory device 1. That is, the write program, erase program, and program verify in the data write operation, read operation, and erase operation are executed based on the address, command, and data given from the host via the data input / output circuit 6. The control unit 5 generates a block selection signal, a column selection signal, and a row selection signal based on the address and the operation sequence.

  The control unit 5 outputs the block selection signal and the row selection signal described above to the row decoder 3. In addition, the control unit 5 outputs a column selection signal to a column decoder (not shown). The column selection signal is a signal for selecting the column direction of the first latch circuit 7.

  The control unit 5 is given a control signal supplied from a memory controller connected to the semiconductor memory device 1. Based on the supplied control signal, the control unit 5 distinguishes whether the signal supplied from the host to the data input / output circuit 6 via the I / O terminal is an address or data.

  It is assumed that the control unit 5 can hold data for one page, can perform the second to fifth verify calculation processes, and can hold the data after the calculation.

1-5. Data Input / Output Circuit 6 The data input / output circuit 6 outputs an address (a row address, a column address, a block address; a row address and a block address together called a page address) and a command and a command supplied from the host to the control unit 5. To do. The data input / output circuit 6 outputs write data to the first latch circuit 7 and the second latch circuit 8 via the data line Dline.

  Further, when outputting data read from the memory cell MT to the host, the data input / output circuit 6 outputs the data amplified by the first and second latch circuits 7 and 8 based on the control of the control unit 5. , Output to the host via Dline.

1-6. Column Decoder The column decoder (not shown) decodes the column address given from the control unit 5 and outputs a column selection signal to the first and second latch circuits 7 and 8.

1-7. About the 1st and 2nd latch circuits 7 and 8 The 1st and 2nd latch circuits 7 and 8 are connected to Dline. The first and second latch circuits 7 and 8 also have a function of a sense amplifier (not shown). In this case, the first and second latch circuits 7 and 8 sense and amplify data read from the memory cell transistor MT to the bit line BL when reading data.

  Specifically, after the bit line BL is precharged to a predetermined voltage, the bit line BL is discharged by the NAND string selected by the row decoder 3, and the discharge state of the bit line BL is sensed. That is, the first and second latch circuits 7 and 8 amplify the voltage of the bit line BL and sense data stored in the memory cell transistor MT. Note that a cell current flowing from the memory cell MT may be sensed, and data written in the memory cell MT may be detected as to whether the threshold voltage distribution is the A level, the B level, or the C level. Further, when data is written, a voltage corresponding to the write data is applied to the corresponding bit line BL.

  An operation of the semiconductor memory device 1 according to the first embodiment will be described. 4 and 5 are flowcharts showing the operation of the semiconductor memory device 1 of the first embodiment. FIG. 4 is a flowchart when the lower page data is written, and FIG. 5 is a flowchart when the upper page data is written. Here, the writing described below refers to writing of data “11”, “10”, “00”, or “01”.

  First, the control unit 5 writes a lower page for executing a write program, which will be described later, and the first program verify. This operation is a lower page write operation.

  As shown in FIG. 4, the control unit 5 initializes the data write count m for each block, and sets the write count to zero. (Step S1). It is assumed that the control unit 5 stores the number of times of writing m and the upper limit m (max) of the number of times of writing in, for example, a register in advance. The upper limit m (max) of the number of times of writing means the maximum number of times of writing in which the memory cell MT can be written.

  In step S2, the control unit 5 increments the number of times of writing (step S2).

  In step S3, the control unit 5 executes a lower page writing program and writes data (step S3). At this time, the control unit 5 first controls the row decoder 3 to select a block BLK of the target memory cell array 2. Further, the control unit 5 controls the voltage generation circuit 4 to further select a desired word line WL connected to the selected memory cell MT in the selected block BLK, and this selected word line WL (hereinafter referred to as the selected word line WL). The voltage Vpgm is applied to the selected word line. On the other hand, the control unit 5 applies the voltage Vpass to the non-selected word line WL. The control unit 5 sets data in the first and second latch circuits 7 and 8, and applies a desired voltage to each bit line BL based on the data. For example, when a potential difference occurs between each word line WL and the channel, writing is performed to the memory cell MT connected to each word line WL and bit line BL. That is, the writing program is executed.

  In step S4, the control unit 5 controls the row decoder 3 and the voltage generation circuit 4, and applies the first verify voltage VR1 to the selected word line WL to perform the first verify (step S4). Thereby, data in the memory cell MT is read. The operation of the first verify will be described. First, the control unit 5 controls the voltage generation circuit 4 and the row decoder 3 to apply the first verify voltage VR1 to the selected word line WL. The control unit 5 applies a voltage Vread lower than the write voltage Vpgm to the non-selected word line WL. At this time, it is assumed that a desired voltage has already been applied to the bit line BL under the control of the control unit 5. The first verify voltage VR1 is a voltage lower than the voltage Vread.

  Based on the data read in the first verify operation, the first and second latch circuits 7 and 8 calculate the number of fail bits. When the number of fail bits is smaller than the desired number, the control unit 5 determines that the first verify pass. The desired number is, for example, a number that can be corrected by ECC.

  When the number of fail bits is larger than the desired number, the control unit 5 determines that the first verify fail.

  In the case of the first verify fail, that is, when the threshold voltage of the memory cell MT does not reach the first verify voltage VR1, the selected memory cell MT is turned on, and the voltage of the bit line BL is discharged. On the other hand, in the case of the first verify pass, that is, when the threshold voltage of the memory cell MT has reached the first verify voltage VR1, the selected memory cell MT is turned off and the voltage of the bit line BL is not discharged. . The sensing method is not limited to voltage sensing, and may be current sensing, for example.

  In the case of a failure, it is determined in step S5 whether the number of writings has reached the upper limit number m (max) (step S5), and if not, the process returns to step S2.

  In step S2, the control unit 5 increments the number of times of writing (step S2).

  In step S3, the control unit 5 performs writing by applying a write voltage Vpgm that is higher by (m−1 times) × ΔVpgm (step S3). In the following description, the write voltage (Vpgm and ΔVpgm) and the upper limit of the number of write times (m (max)) are optimum values in consideration of the time required for write and the controllability of the width of the threshold voltage distribution of the memory cell after write. Set. The control unit 5 repeats the write operation in steps S2 to S5 until the verification is passed.

  When the threshold voltage of the memory cell MT reaches the first verify voltage VR1, that is, when the first verify is passed, the potential of the bit line connected to the memory cell MT is held. For example, the control unit 5 holds data of “1” in the first or second latch circuit 7 or 8 based on the potential of the bit line, assuming that the first verification is passed. Data of “0” is assumed to have not been passed. The result of the first verification can be read by outputting “1” or “0” data held in the first or second latch circuit 7 or 8 to the host after writing.

  If the threshold voltage distribution of the memory cell MT does not reach the first verify voltage VR1 after m (max) writing, that is, if the threshold voltage distribution LM level is not obtained, the result of the first verify is failed. To finish writing the lower page.

  In step S6, the upper page data is written. First, the controller 5 initializes the upper page data write count n in the same manner as the lower page data write, and sets the write count to 0 (step S6). Note that the control unit 5 stores the number of times of writing n and the upper limit of the number of times of writing as the number of times of writing n (max) in advance in a register, for example. When the number of times of writing n reaches the upper limit number of times n (max), writing is failed without writing the upper page.

  In step S7, the control unit 5 increments the number of times of writing (step S7).

  FIG. 6 is a timing chart showing the operation of the semiconductor memory device 1 of the first embodiment. FIG. 6 shows an example of the voltage waveform when applied to the selected word line when writing the upper page data.

  The control unit 5 executes a write program, a second program verify, and a third program verify, which will be described later, and writes the upper page. This operation is an upper page write operation.

  In step S8, the control unit 5 applies the write voltage Vpgm to the selected word line WL, executes the upper page write program, and writes data (step S8). As for the writing method, the control unit 5 performs the same method as when writing the data of the lower page.

  In step S9, the control unit 5 applies the second verify voltage VR2 to the selected word line WL, and then applies the third verify voltage VR3 in the same manner, so that the second verify and the third verify are performed. Is performed (step S9). The second and third verifications identify whether the threshold voltage distribution is B level or C level. As a result, an upper page data write failure is detected. Data as a result of the second and third verification is held in the first or second latch circuit 7 or 8 for each page unit. As shown in FIG. 6, the third verify voltage VR3 is higher than the second verify voltage VR2. The voltage application method and operation during the second and third verifications are the same as those during the first verification. The method for applying the non-selected word WL and the bit line is the same as in the first verification. In this embodiment, the control unit 5 applies the third verify voltage VR3 after applying the second verify voltage VR2, but applies the third verify voltage VR3 before applying the second verify voltage VR2. May be.

  When performing the second verification, the control unit 5 outputs 1-bit data of the lower page data in the memory cell array 2 to the second latch circuit 8 through the data line Dline. On the other hand, the control unit 5 outputs 1-bit data of the upper page data to the first latch circuit 7. Thereafter, the control unit 5 performs an arithmetic process using the data of the first latch circuit 7 and the data of the second latch circuit 8, and the result of the verification is latched in the control unit 5 as “1” or “0” data. Output to the circuit. If the data in the memory cell MT matches the write data output from the host, the control unit 5 sets the write data output from the memory cell MT as write inhibit data. By this operation, only write data that is insufficiently written in the page remains, and data of the memory cell MT that has already been written is maintained from the next write operation. Thereby, it is possible to reduce a load generated in the memory cell MT at the time of writing. Note that the second latch circuit 8 may hold data written in the memory cell MT, and the first latch circuit 7 may hold data output from the host.

  In the upper page write operation, if the desired threshold voltage is not obtained even though the threshold voltage of the B level or the C level should have been written, the control unit 5 obtains the results of the second and third verifications. And write again. At this time, if the result of verification is fail, for example, data “1” is held in the first and second latch circuits 7 and 8. The verification result data is held as one page of data.

  If the results of the second and third verifications are failures, the control unit 5 determines whether the number of writings is within m (max) times in step S10.

  If the number of times of writing is within m (max), the process returns to step S7. The control unit 5 increments the number of writing (step S7). Thereafter, the control unit 5 performs the upper page write operation again.

  In step S8, the control unit 5 applies the write voltage to the word line WL as a voltage obtained by adding (n-1 times) × ΔVpgm (additional voltage) to Vpgm (step S8), and performs the second and third verifications. The data of the upper page is repeatedly written n (max) times until it passes.

  If the threshold voltage distribution of the memory cell MT is higher than either the second verify voltage VR2 or the third verify voltage VR3 in the upper page write operation within n (max) times, that is, at the B level. When the B level data is obtained in an attempt to obtain data or the C level data is obtained in an attempt to obtain the C level data, the control unit 5 determines that the upper page data has been normally written, The result of the second or third verification is output as a pass, and the upper page writing is terminated. In this case, the threshold voltage distribution of the memory cell MT is at the E level, A level, B level or C level.

  If the second or third verify is not passed in step S10 and the number of upper page write operations reaches n (max) (step S10), the write is terminated as a write failure. That is, if there is a memory cell MT in which writing is extremely slow or cannot be written, the writing operation is not passed. The data of the second and third verify results are held in the first or second latch circuit 7 or 8 for each page.

  When the results of the second and third verify are “fail”, the control unit 5 performs the fourth and fifth verify, and the write failure of the memory cell MT affects the data of the upper page or the lower page. Detect whether the data is affected.

  Here, the write failure is caused by the fact that the desired threshold voltage has been raised in the lower page write but cannot be raised to the desired threshold voltage in the upper page write. Although the fifth verify is performed after the fourth verify, the fourth verify and the fifth verify may be performed in the reverse order.

  Further, it is assumed that a write failure due to raising the threshold voltage to a desired threshold value or higher does not occur. For example, the threshold voltage is at the E level before the upper page is written, and should have been raised to the A level threshold voltage in the upper page write operation, but this is a failure when the threshold voltage is raised to the B level. .

In step S11, the controller 5 performs the fourth verify by applying the fourth verify voltage VR4 to the selected word line WL, and performs the fifth verify by applying the fifth verify voltage VR5 (step S11). S11).

  The fourth verify is for identifying whether or not the threshold voltage of the memory cell MT that failed in the second and third verify has reached the E level. The fourth verify voltage VR4 is lower than the second verify voltage VR2 and the third verify voltage VR3. That is, the fourth verify voltage VR4 is located between the threshold voltage distributions of the E level and the LM level.

  The fifth verify is for identifying whether or not the threshold voltage of the memory cell that has failed in the second and third verify has reached the B level. The fifth verify voltage VR5 is substantially the same voltage as the second verify voltage VR2. Therefore, the fifth verify voltage VR5 is higher than the fourth verify voltage VR4 and lower than the third verify voltage VR3.

  The voltage application method for the unselected word lines WL and bit lines BL is the same as in the first verification. After the voltage application, the results of the fourth and fifth verify are held in the first or second latch circuit 7 or 8 for each page unit.

In step S12, the defective memory cells MT in the page regarded as defective are sorted (step S12). The control unit 5 includes first and second latch circuits 7 and 8,
After reading the results of the second to fifth verifications, the location information of the failure of each memory cell MT indicating which memory cell MT has a write failure, and the threshold value of which threshold voltage each memory cell MT has Based on the voltage information, the defective memory cells MT are sorted.

  For example, the control unit 5 performs arithmetic processing on the data of the third page of the second and third verify results, the fourth verify result, and the fifth verify result, and performs the second and third verify operations. Position information of the memory cell MT that has failed and the memory cell MT that has failed in the fourth verify, that is, the memory cell MT whose threshold voltage is lower than the fourth verify voltage VR4, is stored in the latch circuit in the control unit 5. Output. When lower than the fourth verify voltage, the threshold voltage of the memory cell MT is at the E level. The defect at the E level (“11”) should have been written to the A level (“10”), but occurred because the upper page write operation could not be performed normally. The defect is common because the data of the lower page is “1”. That is, the data of the lower page is held before and after the writing of the upper page, and the defect is a defect that occurs only in the data of the upper page.

  Further, the control unit 5 performs arithmetic processing on the data of the third page of the second and third verify results, the fourth verify result, and the fifth verify result, and fails in the second and third verify. The position information of the memory cell MT that has become the pass and the pass of the fifth verify, that is, the memory cell MT whose threshold voltage is equal to or higher than the fifth verify voltage VR5 is transferred to the latch circuit in the control unit 5 Output. When the threshold voltage is higher than the fifth verify voltage, the threshold voltage of the memory cell MT is located at the B level. The defect at the B level (“00”) should have been written at the C level (“01”), but the defect occurred because the upper page write operation could not be performed normally. The defect is common because the data of the lower page is “0”. That is, the lower page data is retained before and after the upper page write operation, and the defect is caused only by the upper page data.

  Further, the control unit 5 performs arithmetic processing on the data of the third page of the second and third verify results, the fourth verify result, and the fifth verify result, and performs the second and third verify operations. The memory cell MT that has failed and the memory cell MT that has failed in the fourth verify pass, that is, the threshold voltage is equal to or higher than the fourth verify voltage and lower than the fifth verify voltage VR5. The position information of the memory cell MT is output to the latch circuit in the control unit 5. The defect is a defect whose threshold voltage is at the A level, and the memory cell MT has a write defect not only in the upper page but also in the lower page data. For a defect whose threshold voltage is at the A level (“10”), the lower page should be written to the LM level and then the B level (“00”). Is a write failure in which the threshold voltage is regarded as A level (“10”). That is, the defect is that the lower page data is not held, and the lower page data differs before and after the upper page write operation.

  After the upper page data write operation and the fourth and fifth verify operations are completed, upon receiving a status command from an external host device or controller, the control unit 5 displays the position information of the memory cell MT having the write failure as “ The data is output to the host device or controller as “1” or “0” data.

  The effect of the semiconductor memory device 1 of the first embodiment will be described.

  The semiconductor memory device 1 of this embodiment reads the pass / fail results of the second to fifth verify after the end of writing. As a result, it is possible to detect whether a write failure has occurred in the upper page, or whether a failure has occurred not only in the upper page but also in the lower page.

  In the semiconductor memory device 1 of the present embodiment, when the semiconductor memory device 1 having a multi-level NAND flash memory performs writing, a defect newly generated not only on the page on which writing is performed but also on another page in the same block Can also be output as status. This writing failure often occurs when the oxide film has deteriorated after repeated rewriting. For this reason, when a failure is detected in the second to fifth verifications, the location where the data failure occurs is fixed to the predetermined memory cell MT. Therefore, the upper page data and the lower page data are included in the same page. If there are many memory cells MT in which write failure has occurred in both, data may be rewritten to another page. Thereby, the reliability of the data written in the memory cell array 2 can be improved.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Memory cell array 3 Row decoder 4 Voltage generation circuit 5 Control part 6 Data input / output circuit 7 1st latch circuit 8 2nd latch circuit 9 Memory | storage part MT Memory cell

Claims (6)

A plurality of memory cells capable of holding data;
A plurality of word lines connected to the plurality of memory cells;
A first step of applying a first write voltage to a selected word line of the plurality of word lines and applying a first verify voltage and a second verify voltage higher than the first verify voltage; A third verify voltage lower than the first verify voltage and a third verify voltage lower than the second verify voltage are applied to a selected word line among the plurality of word lines after the first step. A control unit that executes a second step of applying a higher fourth verify voltage;
A semiconductor memory device.   The semiconductor memory according to claim 1, wherein the control unit executes a third step of applying a second write voltage higher than the first write voltage after the first step and before the second step. apparatus.   3. The semiconductor memory device according to claim 1, wherein the fourth verify voltage is substantially the same voltage as the first verify voltage. 4. The semiconductor according to claim 1, wherein the control unit performs writing of binary data after applying a third writing voltage and writing binary data. 5. Storage device. The third verify voltage is a voltage between a first threshold voltage of the memory cell and a second threshold voltage higher than the first threshold voltage,
5. The first verify voltage according to claim 1, wherein the fourth verify voltage is a voltage between the second threshold voltage of the memory cell and a third threshold voltage higher than the second threshold voltage. The semiconductor memory device according to item.   The semiconductor memory device according to claim 1, wherein the first threshold voltage is an erase threshold voltage.

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