JP2014229623A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device which employs flip-chip connection having a columnar electrode.SOLUTION: A semiconductor device manufacturing method comprises: providing when bonding a second surface of a Cu pillar CB formed on a principal surface of a semiconductor chip with a top face of a lead electrode LE formed on a top face of a wiring board IS by using a solder, between a first inter-metal compound layer IMC1 formed on the second surface of the Cu pillar CB and a second inter-metal compound layer IMC2 formed on the top face of the lead electrode LE, an intermediate layer ISO as a tin(Sn)-rich layer formed on the top face of the lead electrode LE; further providing constriction to the intermediate layer ISO. By doing this, deformation due to external stress caused by a difference in thermal expansion between the semiconductor chip and the wiring board IS is received by the intermediate layer ISO thereby to reduce stress applied to a bottom and the like of the Cu pillar CB and avoid breaking at a bonded part of the Cu pillar CB and the lead electrode LE.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and can be suitably used for, for example, a semiconductor device employing flip-chip connection.

  There is a flip chip connection in which a plurality of chip electrodes formed on a main surface of a semiconductor chip and a plurality of lead electrodes formed on an upper surface of a wiring substrate are connected via solder.

  For example, in Japanese Patent Application Laid-Open No. 2006-005322 (Patent Document 1), a wiring substrate on which bumps made of a truncated cone-shaped copper core and a spherical shell-shaped solder covering the same are formed, and a paste-like flux resin film is used. A technique is disclosed in which a semiconductor chip on which a covered electrode pad is formed is aligned and then heated to cause the flux resin film to hang and harden. Thereby, the mechanical strength of a junction part can be enlarged.

  Japanese Patent Laying-Open No. 2006-202969 (Patent Document 2) discloses a columnar electrode provided on a semiconductor substrate having a first columnar portion having a first diameter and a first columnar portion disposed on an upper surface of the first columnar portion. The first columnar part is composed of a second columnar part having a second diameter smaller than the diameter, and a low melting point layer having a lower melting point than the first and second columnar parts is bonded to the upper surface of the second columnar part. A technique for preventing the low-melting point layer from getting wet on the side surface is disclosed.

  Japanese Patent Application Laid-Open No. 7-193099 (Patent Document 3) discloses that the electrode pad provided on the semiconductor chip and the mounting pad provided on the wiring board are higher than the warp between the wiring board and the semiconductor chip. A technique for preventing the occurrence of connection failure by connecting with bumps is disclosed.

JP 2006-005322 A JP 2006-202969 A JP-A-7-193099

  In recent years, since flip-chip connection allows narrow pitch connection, a columnar electrode, for example, CPB (Copper Pillar Bump) is adopted as a chip electrode formed on the main surface of a semiconductor chip. . However, when the columnar electrode and the lead electrode formed on the wiring board are connected via solder, stress is generated at the joint between the columnar electrode and the lead electrode due to the difference in thermal expansion between the semiconductor chip and the wiring board. However, there has been a problem that the joint portion between the columnar electrode and the lead electrode is broken, for example, at the base of the columnar electrode.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a columnar electrode facing a lead electrode at a joint portion via a solder layer between a columnar electrode formed on a main surface of a semiconductor chip and a lead electrode formed on an upper surface of a wiring board. An intermediate layer that is a Sn-rich layer between the first intermetallic compound layer formed on the lower surface of the first electrode and the second intermetallic compound layer formed on the upper surface of the lead electrode facing the columnar electrode; A constriction is provided in the intermediate layer.

  According to one embodiment, the reliability of a semiconductor device that employs flip-chip connection having columnar electrodes can be improved.

It is a principal part top view which shows the semiconductor device by one Embodiment. FIG. 2 is a main part sectional view showing a semiconductor device according to one embodiment (main part sectional view taken along the line AA ′ in FIG. 1); It is a principal part top view which shows the semiconductor chip before flip chip connection by one Embodiment. FIG. 4 is an essential part cross-sectional view showing an enlarged part of a semiconductor chip before flip-chip connection according to an embodiment (main part cross-sectional view taken along line DD ′ in FIG. 3). It is a principal part top view which shows arrangement | positioning of the several lead electrode formed in the upper surface of the wiring board before flip-chip connection by one Embodiment. It is a principal part top view which shows the some external connection terminal formed in the lower surface of the wiring board by one Embodiment. It is a principal part top view which shows the modification of the some lead electrode formed in the upper surface of the wiring board before flip-chip connection by one Embodiment. A region in which a plurality of Cu pillars formed on the main surface of a semiconductor chip and a plurality of lead electrodes formed on the upper surface of the wiring substrate are connected when the semiconductor chip and the wiring substrate are flip-chip connected according to one embodiment It is a principal part top view which expands and shows a part of. It is principal part sectional drawing which expands and shows a part of semiconductor device which mounted the semiconductor chip on the upper surface of the wiring board by one Embodiment. FIG. 3 is an enlarged cross-sectional view of a main part illustrating a joint portion between a Cu pillar and a lead electrode according to an embodiment, and is a cross-sectional view of the main part along a direction orthogonal to the extending direction of the lead electrode and the upper surface of the wiring board (FIG. 1); It is principal part sectional drawing in the BB 'line of. FIG. 3 is an enlarged cross-sectional view of a main part showing a joint part between a Cu pillar and a lead electrode according to an embodiment, and is a cross-sectional view of the main part along the extending direction of the lead electrode (main part along the line CC ′ in FIG. FIG. It is principal part sectional drawing which expands and shows the junction part of Cu pillar and lead electrode for demonstrating the constriction shape of the solder by one Embodiment, (a) is a position shift of Cu pillar and lead electrode. FIG. 4B is a cross-sectional view of the main part when the positional deviation between the Cu pillar and the lead electrode is relatively large. It is principal part sectional drawing which shows the modification of Cu pillar and the lead electrode along the direction orthogonal to the extending | stretching direction of the lead electrode and the upper surface of a wiring board by one Embodiment, (a) is the 1st modification of solder material FIG. 6B is a cross-sectional view of a main part for explaining a second modification of the solder material. It is principal part sectional drawing which shows the modification of the semiconductor device by one Embodiment. It is principal part sectional drawing which shows the semiconductor device in the manufacturing process of the semiconductor device by one Embodiment. It is a figure explaining the shape of the lead electrode by one Embodiment, (a) is a top view of a lead electrode, (b) is principal part sectional drawing (FIG. 14 (a)) along the extending | stretching direction of a lead electrode. ) In FIG. 14A is a cross-sectional view of the main part of the lead electrode along the direction perpendicular to the extending direction of the lead electrode and the upper surface of the wiring board. It is principal part sectional drawing in the FF 'line | wire. FIG. 14 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process following FIG. 13; FIG. 16 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process following FIG. 15; It is a figure explaining the shape of Cu pillar by one Embodiment, (a) is a top view of Cu pillar, (b) is principal part sectional drawing of the Cu pillar along the extending direction of a lead electrode (FIG. 17 (a) ) In FIG. 17A is a cross-sectional view of the main part of the Cu pillar along the direction orthogonal to the extending direction of the lead electrode and the upper surface of the wiring board. It is principal part sectional drawing in HH 'line. FIG. 17 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process following FIG. 16; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; It is a figure explaining a series of operation | movement of the flip chip connection by one Embodiment. FIG. 20 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process following FIG. 19; FIG. 22 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; (A) And (b) is principal part sectional drawing of the junction part explaining formation of the intermetallic compound and solder between the lower surface of Cu pillar and the upper surface of a lead electrode, respectively when a solder supply amount is relatively small FIG. 5 is a cross-sectional view of a principal part of a joint portion for explaining the formation of an intermetallic compound and solder between the lower surface of the Cu pillar and the upper surface of the lead electrode when the solder supply amount is relatively large. It is a figure for demonstrating the modification of Cu pillar by one Embodiment, (a) is a top view of Cu pillar, (b) is principal part sectional drawing of Cu pillar (II of Fig.25 (a)) It is principal part sectional drawing in a 'line. It is principal part sectional drawing which shows the modification of the semiconductor device by one Embodiment. (A) and (b) are cross-sectional views of the main part showing an enlarged joint portion between the Cu pillar and the lead electrode when a through silicon via is provided immediately below the land pad (before mounting on the substrate). Cross-sectional view of the main part), and a cross-sectional view of the main part showing an enlarged joint part between the Cu pillar and the lead electrode when the position of the land pad and the through silicon via is shifted (before mounting on the substrate) It is principal part sectional drawing). (A) And (b) shows the principal part sectional view of the lead electrode in the 1st example, and the principal part sectional view of the lead electrode which joined Cu pillar, respectively. (A) And (b) shows the principal part sectional drawing of the lead electrode in a 2nd example, and the principal part sectional drawing of the lead electrode which joined Cu pillar, respectively. (A) And (b) shows the principal part sectional view of the lead electrode in the 3rd example, and the principal part sectional view of the lead electrode which joined Cu pillar, respectively.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

(Detailed explanation of the issue)
Basically, a land mask (a part of a lead electrode, which is a part to which a chip electrode formed on the main surface of a semiconductor chip is connected) is formed with a solder mask definition ( There are Solder Mask Defined (SMD) pads and Non Solder Mask Defined (NSMD) pads.

  In the SMD pad structure, the opening formed in the solder mask is made smaller than the diameter of the land pad, and the opening is formed in the solder mask so that the solder mask overlaps the peripheral edge of the land pad. It is formed. In the SMD pad structure, solder does not wrap around the side surface of the land pad. However, since an opening is formed for each land pad, it is difficult to realize a joint portion having a narrow pitch of, for example, 100 μm or less. Further, since the solder mask overlaps with the peripheral edge of the land pad, the wetted area of the solder becomes relatively small.

  In contrast, in the NSMD pad structure, the opening formed in the solder mask is made larger than the diameter of the land pad so that the solder mask does not overlap the peripheral edge of the land pad. An opening is formed in the mask. In the NSMD pad structure, since the solder is also wet on the peripheral edge and the side surface of the land pad, the wet area of the solder is relatively large.

  In the NSMD pad structure, a plurality of land pads may be exposed from the opening of one solder mask. An opening is not formed for each land pad, in other words, an insulator such as a solder mask is not formed between adjacent bonding portions, so that, for example, a bonding portion having a narrow pitch of about 60 μm is realized. Can do.

  Accordingly, the inventors of the present application have studied flip-chip connection using a wiring board having a plurality of pads in an opening of one solder mask and a Cu pillar in order to realize a narrow pitch joint. However, it has become clear that there are various technical problems described below.

  As described above, in the NSMD pad structure, the Cu pillar formed on the main surface of the semiconductor chip and the land pad that is a part of the lead electrode (portion to which the Cu pillar is connected) formed on the upper surface of the wiring substrate. Are connected to the side surfaces of the land pads. Therefore, it is necessary to adjust the supply amount of solder so that adjacent land pads are not connected by solder.

  However, as shown in FIG. 24A, when the supply amount of solder decreases, the distance between the lower surface of the Cu pillar CB and the upper surface of the land pad LP becomes shorter. In particular, in the load-controlled flip-chip connection that is adopted because it is advantageous for productivity, or in the flip-chip connection in which the pushing amount is set to be large in order to avoid the bonding failure, the distance between the two becomes remarkably short.

  At the time of flip-chip connection, due to the thermal history, an intermetallic compound containing tin (Sn) and copper (Cu) as main components is formed on the lower surface of the Cu pillar CB and the upper surface and side surfaces of the land pads LP. ) Layer IMC is formed. An intermetallic compound is a compound in which the atomic ratio of the constituent metal elements is an integer ratio (however, the actual atomic ratio is not a perfect integer ratio, and an atomic ratio deviating from the integer ratio exists), and is a solid solution ( It is harder and more brittle than tin (Sn) in which the added metal is dissolved. In addition, intermetallic compounds have a higher melting point and higher electrical resistance than solid solutions. In addition, tin (Sn) contained in the intermetallic compound is derived from solder, and copper (Cu) is derived from any one or more of an additive element in the solder, a Cu pillar CB, or a copper (Cu) lead electrode. To do.

  Therefore, when the intermetallic compound formed from the lower surface side of the Cu pillar CB and the intermetallic compound formed from the upper surface side of the land pad LP overlap each other, the lower surface of the Cu pillar CB and the upper surface of the land pad LP In the meantime, one intermetallic compound layer IMC harder than the solid solution is formed. In such a state, the stress generated in the joint portion between the Cu pillar CB and the land pad LP due to the difference in thermal expansion between the semiconductor chip and the wiring substrate is, for example, the bottom surface of the Cu pillar CB (the surface opposite to the lower surface, The risk of the Cu pillar CB peeling off at the bottom increases.

  Therefore, as shown in FIG. 24B, it was studied to increase the distance between the lower surface of the Cu pillar CB and the upper surface of the land pad LP by increasing the solder supply amount. However, in the structure in which the plurality of land pads LP are exposed from the opening of one solder mask, no solder mask or the like is formed between the adjacent land pads LP. The risk of connection between pillar CBs increases. Further, in the NSMD pad structure, since the solder wraps around the side surface of the land pad LP, only a part of the increased solder supply amount contributes to securing the distance between the lower surface of the Cu pillar CB and the upper surface of the land pad LP. do not do. Under such a restriction, the solder SOL is between the first intermetallic compound layer IMC1 formed on the lower surface of the Cu pillar CB and the second intermetallic compound layer IMC2 formed on the upper surface of the land pad LP. Since it is difficult to sufficiently increase the ratio of thickness to width (thickness / width), a sufficient stress relaxation effect by the solder SOL cannot be obtained.

  Further, in order to reduce the capacitance between wirings of a semiconductor chip, the use of a low-k film having a low dielectric constant instead of a silicon oxide film as a wiring interlayer film has been studied. Are easily broken by stress. Therefore, when a low-k film is used, if a stress is generated at the joint between the Cu pillar and the lead electrode, the low-k film adjacent to the portion where the Cu pillar is connected is destroyed, and the Cu pillar is It peels easily at the bottom.

  In PoP (Package On Package), the heat history applied to the semiconductor device increases, so the problem of Cu pillar peeling is serious.

(Embodiment)
In the present embodiment, a plurality of columnar electrodes arranged at the center and outer periphery of the main surface of a semiconductor chip (a part inside from the edge of the semiconductor chip) and a plurality of lead electrodes formed on a wiring board The present invention relates to a technique for flip chip connection via solder, and is particularly characterized by the shape of the solder layer and the flip chip connection process. Here, the columnar electrode refers to a protruding electrode made of a metal having a melting point higher than that of solder, protruding from a surface protective film covering the main surface of the semiconductor chip. In the present embodiment, a Cu pillar is exemplified as the columnar electrode, but the present invention is not limited to this.

≪Semiconductor device≫
A semiconductor device according to the present embodiment will be described with reference to FIGS. FIG. 1 is a main part plan view showing a semiconductor device. FIG. 2 is a main part cross-sectional view (a main part cross-sectional view taken along the line AA ′ of FIG. 1) showing the semiconductor device. FIG. 3 is a plan view of an essential part showing the semiconductor chip before flip chip connection. 4 is an essential part cross-sectional view (a main part cross-sectional view taken along the line DD ′ of FIG. 3) showing a part of the semiconductor chip before flip-chip connection. FIG. 5A is a main part plan view showing the arrangement of a plurality of lead electrodes formed on the upper surface of the wiring board before flip-chip connection, and FIG. 5B shows the plurality of external connection terminals formed on the lower surface of the wiring board. It is a principal part top view. FIG. 6 is a plan view of a principal part showing a modification of a plurality of lead electrodes formed on the upper surface of the wiring board before flip chip connection. FIG. 7 shows a region in which a plurality of Cu pillars formed on the main surface of the semiconductor chip and a plurality of lead electrodes formed on the upper surface of the wiring substrate are connected when the semiconductor chip and the wiring substrate are flip-chip connected. It is a principal part top view which expands and shows a part. FIG. 8 is an enlarged cross-sectional view showing a main part of a semiconductor device in which a semiconductor chip is mounted on the upper surface of the wiring board. FIG. 9A is an enlarged cross-sectional view of a main part showing a joint portion between a Cu pillar and a lead electrode, and is a cross-sectional view of the main part along a direction orthogonal to the extending direction of the lead electrode and the upper surface of the wiring board (in FIG. FIG. 9B is an enlarged cross-sectional view of the main portion showing the joint portion between the Cu pillar and the lead electrode, and is a cross-sectional view of the main portion along the extending direction of the lead electrode. It is principal part sectional drawing in the CC 'line of FIG. 10 (a) and 10 (b) are enlarged cross-sectional views showing the main part of the joint between the Cu pillar and the lead electrode for explaining the constricted shape of the solder, and FIG. 10 (a) is the Cu pillar and the lead electrode. FIG. 6B is a cross-sectional view of the main part when the positional deviation between the Cu pillar and the lead electrode is relatively large.

1. 1. Structure of Semiconductor Device FIG. 1 shows a plan view of the main part of the semiconductor device, and FIG. 2 shows a cross-sectional view of the main part of the semiconductor device (a cross-sectional view of the main part taken along the line AA ′ in FIG. 1).

  The semiconductor device SM has a semiconductor chip SC mounted on the upper surface side of the upper surface and the lower surface located on the opposite sides of the wiring board IS, and a plurality of ball-shaped external connection terminals (also referred to as outer balls) BS on the lower surface side. It has an arranged package structure.

  The semiconductor chip SC is mounted on the upper surface of the wiring substrate IS so that the main surface of the semiconductor chip SC and the upper surface of the wiring substrate IS face each other. On the main surface of the semiconductor chip SC, a plurality of electrode pads CP electrically connected to the semiconductor elements are arranged. The plurality of electrode pads CP are composed of the uppermost layer wiring of the multilayer wiring of the semiconductor chip SC, and are exposed through openings formed in the surface protective film PI of the semiconductor chip SC corresponding to the respective electrode pads CP. ing.

  Further, columnar electrodes, for example, Cu pillars CB, are connected to the surfaces of the plurality of electrode pads CP, respectively, and the plurality of Cu pillars CB and the wiring board formed on the main surface of the semiconductor chip SC via the solder layer SO. A plurality of lead electrodes LE formed on the upper surface of the IS are electrically connected.

  An underfill resin UF is filled between the upper surface of the wiring board IS and the main surface of the semiconductor chip SC, and a plurality of electrode pads CP, a plurality of Cu pillars CB, a plurality of solder layers SO, and a plurality of leads. The electrode LE and the like are protected.

2. Semiconductor Chip FIG. 3 is a plan view of a main part of a semiconductor chip before flip chip connection, and FIG. 4 is an enlarged cross-sectional view of a main part of the semiconductor chip before flip chip connection (D-- in FIG. 3). The principal part sectional drawing in D 'line is shown.

  The semiconductor chip SC has a main surface on which a semiconductor element is formed and a back surface opposite to the main surface, and the planar shape intersecting the thickness direction is a quadrangle.

  The semiconductor chip SC is not limited to this, but mainly includes a semiconductor substrate SS made of single crystal silicon (Si), an internal circuit IC made of a plurality of semiconductor elements formed on the main surface of the semiconductor substrate SS, and this It has a fixed potential input / output circuit to which a power source, a ground, etc. connected to the central portion and the peripheral portion of the main surface of the semiconductor substrate SS are connected, and an input / output buffer circuit (Input Output Buffer) IO to which signals are connected. ing. The input / output buffer circuit IO is a functional block specialized for input / output operations, and includes an input / output circuit and an ESD (Electro Static Discharge) protection element.

Furthermore, the semiconductor chip SC has a multilayer wiring ML in which a plurality of insulating layers and wiring layers are stacked on the main surface of the semiconductor substrate SS, and a surface protective film PI formed so as to cover the multilayer wiring ML. It is configured. The insulating layer is formed of, for example, a low dielectric constant (Low-k) film having a relative dielectric constant of 3.0 or less. The wiring layer is formed of a metal film such as aluminum (Al) or copper (Cu). The surface protective film PI includes, for example, an organic insulating film such as polyimide, an inorganic insulating film containing silicon (Si) such as a silicon oxide (SiO ₂ ) film or a silicon nitride (SiNx) film, or the silicon (Si). It is formed of a laminated structure in which an organic insulating film such as polyimide is formed on an inorganic insulating film.

  A central portion and an outer peripheral portion of the main surface of the semiconductor chip SC are a plurality of electrode pads (part of the uppermost layer wiring, which is a portion to which the Cu pillar CB is connected). ) CP is arranged. In the present embodiment, the electrode pad CP is configured by a part of the uppermost layer wiring, but is not limited to this. For example, an electrode electrically connected to the uppermost layer wiring is formed on the uppermost layer wiring by a conductive material different from the conductive material constituting the uppermost layer wiring, and this is used as an electrode pad CP. You can also

  The electrode pad CP is electrically connected to the lower layer wiring of the uppermost layer wiring via the other portion of the uppermost layer wiring and the lead via CV in which the conductive material is embedded. The lead-out via CV is formed through an insulating layer formed between the uppermost layer wiring and one lower layer wiring, and the conductive material embedded in the lead via CV is the uppermost layer wiring. The connection member may be formed integrally with the uppermost wiring, or may be a connection member that is not formed integrally with the uppermost wiring and is embedded only inside the lead-out via CV.

  Further, the electrode pad CP is electrically connected to the input / output buffer circuit IO via each wiring below the uppermost wiring and a conductive material embedded in a via formed in each insulating layer. Has been. The input / output buffer circuit IO and the internal circuit IC are electrically connected by a lower layer wiring than the uppermost layer wiring.

  The electrode pad CP is exposed from the opening CRO formed in the surface protective film PI. Cu pillars CB are electrically connected to the electrode pads CP via a base film UCB having an adhesion improving effect or a metal element diffusion barrier function. The base film UCB is made of, for example, titanium (Ti) or copper (Cu).

  The Cu pillar CB is a protruding electrode and has a cylindrical shape or a rectangular parallelepiped shape. The height of the Cu pillar CB from the surface of the surface protective film PI is, for example, about 30 μm, and its diameter in a plan view in the case of a cylindrical shape is, for example, about 30 μm to 35 μm, and its one side in a plan view in the case of a rectangular parallelepiped shape. The length of is, for example, about 30 μm to 35 μm.

  In the present embodiment, the opening diameter of the opening CRO formed in the surface protective film PI is smaller than the diameter of the Cu pillar CB. As a result, as shown in FIG. 4, the peripheral portion of the Cu pillar CB can have a structure in which at least a part thereof rides on the surface protective film PI. It can be relieved by deformation.

  The Cu pillar CB has a first surface (bottom surface) CBS1 connected to the electrode pad CP through the base film UCB, and a second surface (bottom surface) CBS2 opposite to the first surface (bottom surface) CBS1. Lead (Pb) -free solder (for example, tin (Sn) -1.5 wt.% Silver (Ag) solder) SO1 is formed on the second surface (lower surface) CBS2. The thickness of the solder SO1 from the second surface (lower surface) CBS2 of the Cu pillar CB is, for example, about 12 μm to 15 μm.

3. Wiring board FIG. 5A shows a plan view of a main part for explaining the arrangement of a plurality of lead electrodes formed on the upper surface of the wiring board before flip-chip connection, and FIG. 5B shows a plurality of wiring electrodes formed on the lower surface of the wiring board. The principal part top view explaining arrangement | positioning of an external connection terminal is shown.

  The wiring board IS has an upper surface and a lower surface opposite to the upper surface, and has a multilayer wiring structure. The wiring board IS has a quadrangular planar shape intersecting the thickness direction, the first side LS1, the second side LS2 orthogonal to the first side LS1, and the third side facing the first side LS1. It has LS3 and a fourth side LS4 facing the second side LS2.

  As shown in FIG. 5A, the upper surface of the wiring board IS is covered with a protective film SR1 (region shown by hatching in FIG. 5A), and a plurality of lead electrodes are respectively formed from the openings SRO1 formed in the protective film SR1. LE is exposed. However, the opening SRO1 is not formed for each of the plurality of lead electrodes LE, but the plurality of lead electrodes LE are exposed from one opening SRO1.

  In the present embodiment, the wiring board IS in which two openings SRO1 are formed is illustrated, and one opening SRO1 is formed in the central portion, separated from the one opening SRO1, and one opening. Another opening SRO1 is formed so as to surround SRO1. Note that the number and shape of the openings SRO1 are not limited to this. For example, one opening SRO1 is formed along each side of the wiring board IS, and a plurality of leads is formed from each opening SRO1. The electrode LE may be exposed.

  The width in the direction in which the lead electrode LE extends (first direction) and the direction orthogonal to the upper surface of the wiring board IS (second direction) is constant, and the width is, for example, the electrical resistance of the lead electrode LE and the semiconductor chip SC. It is set from the viewpoint of connection reliability with the Cu pillar CB formed on the main surface of the. Here, the constant width includes a range in consideration of variations due to processing accuracy and the like.

  From the one opening SOR1, the lead electrode LE extending from the second side LS2 side to the fourth side LS4 side or from the fourth side LS4 side to the second side LS2 of the wiring board IS is exposed.

  Also, from the portion of the other opening SOR1 that is close to the first side LS1 of the wiring board IS, in a direction orthogonal to the first side LS1 in plan view (from the first side LS1 side to the third side LS3 side) Or a plurality of lead electrodes LE extending from the third side LS3 side to the first side LS1 side are exposed.

  Similarly, from the portion of the other opening SOR1 that is close to the second side LS2 of the wiring board IS, in a direction orthogonal to the second side LS2 in plan view (from the second side LS2 side to the fourth side LS4). A plurality of lead electrodes LE extending to the side or from the fourth side LS4 side to the second side LS2 side are exposed.

  Similarly, from the portion of the other opening SOR1 that is close to the third side LS3 of the wiring board IS, in a direction orthogonal to the third side LS3 in plan view (from the third side LS3 side to the first side LS1). A plurality of lead electrodes LE extending to the side or from the first side LS1 side to the third side LS3 side are exposed.

  Similarly, from the part close to the fourth side LS4 of the wiring board IS in the other opening SOR1, the second side LS2 from the fourth side LS4 side in a direction orthogonal to the fourth side LS4 in plan view. A plurality of lead electrodes LE extending to the side or from the second side LS2 side to the fourth side LS4 side are exposed.

  Further, the plurality of Cu pillars CB shown in FIG. 3 are electrically connected to the plurality of lead electrodes LE, respectively. Therefore, portions of the plurality of lead electrodes LE that are connected to the plurality of Cu pillars CB, so-called land pads LP, are disposed when the main surface and the back surface of the semiconductor chip SC are inverted. It will be the same.

  Lead (Pb) -free solder (for example, tin (Sn) solder) SO2 is formed on the exposed surfaces (upper surface and side surfaces) of the plurality of lead electrodes LE. The thickness of the solder SO2 from the upper surface of the lead electrode LE in the land pad LP which is a part of the lead electrode LE is larger than the thickness of the solder SO2 from the upper surface of the lead electrode LE in the other part of the lead electrode LE. It is about 12 μm to 15 μm.

  Further, as shown in FIG. 5B, the lower surface of the wiring board IS is covered with the protective film SR2, and a plurality of land pads BLR are exposed from the opening SRO2 formed in the protective film SR2. An external connection terminal BS is connected to each of the plurality of land pads BLR.

  FIG. 6 is a plan view of a principal part for explaining a modification example of a plurality of lead electrodes.

  In FIG. 5A described above, the lead electrode LE in which the width of the direction in which the lead electrode LE extends and the direction orthogonal to the upper surface of the wiring board IS is constant (including a range in which variation due to processing accuracy and the like is taken into consideration) is illustrated. It is not limited to. For example, only the width of the land pad LP in the direction orthogonal to the extending direction of the lead electrode LE and the direction orthogonal to the upper surface of the wiring board IS may be made larger than the width of the other part of the lead electrode LE. Thereby, connection reliability with Cu pillar CB formed in the main surface of semiconductor chip SC improves more. In particular, by making the width of the land pad LP larger than 1.5 times and smaller than 3.0 times the width of the other part of the lead electrode LE, high connection reliability can be obtained in connection with a narrow pitch. Can do.

4). FIG. 7 shows a semiconductor device in which a semiconductor chip and a wiring board are flip-chip connected. In FIG. 7, a plurality of Cu pillars formed on the main surface of the semiconductor chip and a plurality of lead electrodes formed on the upper surface of the wiring board are connected via a plurality of solders. The principal part top view which expanded a part of area | region which connected respectively is shown.

  For example, as shown in FIG. 1 described above, a plurality of Cu pillars CB are arranged in each of the central portion and the outer peripheral portion of the semiconductor chip SC. The plurality of Cu pillars CB are electrically connected to the plurality of lead electrodes LE exposed from the opening SRO1 formed in the protective film SR1 covering the upper surface of the wiring board IS via a plurality of solders.

  FIG. 8 shows an enlarged cross-sectional view of a main part of a semiconductor device in which a semiconductor chip is mounted on the upper surface of the wiring board.

  The wiring board IS includes a core material (base material) C, wirings formed on the surface Cx of the core material C (wiring in the second layer from the top (second wiring ML2) in the wiring board IS), and the second It has an upper insulating film IU formed so as to cover the wiring ML2, and a wiring (the uppermost wiring (first wiring ML1) in the wiring board IS) formed on the surface of the upper insulating film IU. Here, a plurality of lead electrodes LE made of a part of the first wiring ML1 are exposed from the protective film SR1 formed so as to cover the first wiring ML1.

  Furthermore, the wiring board IS includes a wiring (third wiring (third wiring ML3) from the top in the wiring board IS) formed on the back surface Cy opposite to the front surface Cx of the core material C, and the third wiring. It has a lower insulating film ID formed so as to cover ML3, and wiring (lowermost wiring (fourth wiring ML4) in the wiring board IS) formed on the surface of the lower insulating film ID. Here, a plurality of land pads BLR made of a part of the fourth wiring ML4 are exposed from the protective film SR2 formed so as to cover the fourth wiring ML4.

  Here, the core material C includes a resin having an epoxy group. A glass cloth is formed inside the resin. The upper insulating film IU and the lower insulating film ID include a resin having an epoxy group. Similar to the core material C, the upper insulating film IU and the lower insulating film ID may also have a glass cloth formed inside the resin. The thickness of the core material C is larger than the thickness of the upper insulating film IU and larger than the thickness of the lower insulating film ID.

  In addition, each of the wirings ML1, ML2, ML3, and ML4 of the wiring board IS is formed of, for example, a metal film containing copper (Cu) as a main component. The protective film SR1 on the upper surface side of the wiring board IS is, for example, a solder resist mainly composed of an insulating resin, and the first wiring formed on the uppermost layer of the wiring board IS from an external environment such as dust, heat, or moisture. It has a function of protecting ML1 and maintaining the insulation of the first wiring ML1. Similarly, the protective film SR2 on the lower surface side of the wiring board IS is, for example, a solder resist mainly composed of an insulating resin, and is formed in the lowermost layer of the wiring board IS from an external environment such as dust, heat, or moisture. It has a function of protecting the fourth wiring ML4 and maintaining the insulation of the fourth wiring ML4.

  The first wiring ML1 and the second wiring ML2 are electrically connected via a through hole (via) VU formed in the upper insulating film IU. The second wiring ML2 and the third distribution layer ML3 are electrically connected via a through-hole (via) VI formed from the front surface Cx of the core material C toward the rear surface Cy. The third wiring ML3 and the fourth wiring ML4 are electrically connected via a through hole (via) VD formed in the lower insulating film ID.

  Also, as shown in FIG. 1 described above, a plurality of lead electrodes LE are formed on the upper surface of the wiring board IS at positions facing the central portion and the outer peripheral portion of the semiconductor chip SC, respectively. The plurality of lead electrodes LE are respectively exposed through openings SRO1 formed in the protective film SR1 corresponding to the plurality of lead electrodes LE.

  Further, as described above, a plurality of land pads BLR are formed on the lower surface of the wiring board IS. The plurality of land pads BLR are exposed through a plurality of openings SRO2 formed in the protective film SR2 corresponding to the plurality of land pads BLR, and the external connection terminals BS are connected to the respective openings.

  The semiconductor chip SC is mounted on the upper surface of the wiring substrate IS such that the upper surface of the wiring substrate IS and the main surface of the semiconductor chip SC are opposed to each other, and a plurality of electrode pads CP formed on the main surface of the semiconductor chip SC. A plurality of Cu pillars CB connected to each other and a plurality of lead electrodes LE formed on the upper surface of the wiring board IS are electrically connected to each other by a plurality of solder layers SO.

5. Junction between Cu Pillar and Lead Electrode FIGS. 9A and 9B are enlarged cross-sectional views of the main part of the junction between the Cu pillar and the lead electrode.

  The Cu pillar CB connected to the electrode pad CP formed on the main surface of the semiconductor chip SC via the base film UCB and the lead electrode LE formed on the upper surface of the wiring board IS are mainly composed of tin (Sn). Are connected via a solder layer SO. A distance L1 between the second surface (lower surface) CBS2 of the Cu pillar CB and the upper surface of the lead electrode LE is, for example, about 10 μm.

  Below, the specific structure of the junction part of Cu pillar CB and the lead electrode LE is demonstrated.

  On the second surface (lower surface) CBS2 of the Cu pillar CB, a first intermetallic compound layer IMC1 mainly composed of an intermetallic compound composed of tin (Sn) and copper (Cu) is formed, and the lead electrode LE is formed. A second intermetallic compound layer IMC2 mainly composed of an intermetallic compound composed of tin (Sn) and copper (Cu) is formed on the upper surface of the substrate.

  The intermetallic compounds constituting the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2 are formed by, for example, a thermal history at the time of flip chip connection. Moreover, the composition is Cu3Sn or Cu6Sn5, for example, and has an atomic ratio of copper (Cu) in which the Cu / intermetallic compound is 0.5 or more. In addition, the melting point is higher (for example, 400 ° C. or higher) and the hardness is higher than the intermediate layer ISO described below.

  However, the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2 are not connected, and between the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2 and on the side surface of the lead electrode LE. An intermediate layer ISO made of tin (Sn) in which tin (Sn), copper (Cu), silver (Ag), or the like is dissolved is formed. A part of the intermediate layer ISO may contain isolated intermetallic compound grains.

  The atomic ratio of tin (Sn) contained in the intermediate layer ISO is larger than the atomic ratio of tin (Sn) contained in the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2, for example 0.84 As described above, the Sn / Cu atomic ratio is preferably 0.9 or more. Thus, the intermediate layer ISO has a property that is more extendable than the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2.

  By the way, when the junction between the Cu pillar CB and the lead electrode LE is viewed in one cross section even though it is actually connected to the first intermetallic compound layer IMC1 or the second intermetallic compound layer IMC2, the intermediate layer ISO. In some cases, a lump of intermetallic compounds separated from the first intermetallic compound layer IMC1 or the second intermetallic compound layer IMC2 appears in a floating island shape. This is because the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2 may contain needle-like or plate-like precipitates. Here, the lump of intermetallic compound observed in a floating island shape can be regarded as a part of the first intermetallic compound layer IMC1 or the second intermetallic compound layer IMC2 to which the lump is connected. Since the influence of the precipitate on the mechanical strength of the entire solder layer SO is small, it is considered here as a part of the intermediate layer ISO.

  In the present embodiment, a portion composed of the first intermetallic compound layer IMC1, the intermediate layer ISO, and the second intermetallic compound layer IMC2 is referred to as a solder layer SO. For example, the second portion of the Cu pillar CB shown in FIG. The solder SO1 formed on the surface (lower surface) CBS2 is different from the solder SO2 formed on the upper surface of the lead electrode LE shown in FIG. 5A. Note that the boundary between the first intermetallic compound layer IMC1 or the second intermetallic compound layer IMC2 and the intermediate layer ISO can be easily confirmed by, for example, observation with a scanning electron microscope (SEM) or an optical microscope.

  As described above, by providing the intermediate layer ISO, which is a tin (Sn) -rich layer having excellent extensibility, between the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2, the semiconductor chip SC and the wiring board IS. The intermediate layer ISO can relieve the stress generated at the joint between the Cu pillar CB and the lead electrode LE due to the difference in thermal expansion from the intermediate layer ISO.

  Further, the intermediate layer ISO has a “neck”. That is, the intermediate layer ISO has a portion that narrows in the middle between the second surface (lower surface) CBS2 of the Cu pillar CB and the upper surface of the lead electrode LE.

  FIG. 10 is an enlarged cross-sectional view of a main part illustrating a joint portion between the Cu pillar and the lead electrode for explaining the constricted shape of the solder.

  As shown in FIG. 10A, the shape of the solder layer SO is not a barrel shape as shown by a dotted line, but has a constriction in a part of the intermediate layer ISO (indicated by an arrow in FIG. 10A). portion). Here, the constriction means that one side surface of the intermediate layer ISO has two points on one side surface in a cross section in a direction orthogonal to the extending direction of the lead electrode LE and the upper surface of the wiring board IS (width direction of the lead electrode LE). It means that the other side surface of the intermediate layer ISO is located on the one side surface side than the line circumscribing two points on the other side surface with respect to the other side surface side with respect to the circumscribing line.

  As shown in FIG. 10B, even when the positions of the Cu pillar CB and the lead electrode LE are shifted, the intermediate layer ISO has a constriction (portion indicated by an arrow in FIG. 10B). Similar to the solder layer SO shown in FIG. 10A, this constriction occurs in the cross section in the direction (width direction of the lead electrode LE) perpendicular to the extending direction of the lead electrode LE and the upper surface of the wiring board IS. One side surface is positioned on the other side surface than the line circumscribing two points on the one side surface, and the other side surface of the intermediate layer ISO is one side surface than the line circumscribing the two points on the other side surface. Located on the side.

  As described above, by providing the constriction in the intermediate layer ISO, the constriction in which the stress generated in the joint portion between the Cu pillar CB and the lead electrode LE due to the difference in thermal expansion between the semiconductor chip SC and the wiring board IS is provided in the intermediate layer ISO. Can be relaxed.

  Therefore, providing the intermediate layer ISO, which is a tin (Sn) -rich layer with excellent spreadability, between the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2, and providing a constriction in the intermediate layer ISO Thus, the intermediate layer ISO can be deformed (reversible) due to external stress. As a result, the stress applied to the bottom of the Cu pillar CB and the like can be reduced, and breakage at the joint between the Cu pillar CB and the lead electrode LE due to peeling of the Cu pillar CB or the like can be avoided.

≪Semiconductor device modification≫
A modification of the solder material according to this embodiment will be described with reference to FIG. FIG. 11 is an enlarged cross-sectional view of the main part showing the Cu pillar and the lead electrode along a direction orthogonal to the extending direction of the lead electrode and the direction orthogonal to the upper surface of the wiring board (width direction of the lead electrode LE). The principal part sectional view explaining the 1st modification of solder material, (b) is the principal part sectional view explaining the 2nd modification of solder material.

  In the Cu pillar CB shown in FIG. 4 described above, the solder SO1 is formed directly on the second surface (lower surface) CBS2 of the Cu pillar CB. However, in the first modification shown in FIG. Solder SO1 is formed on the second surface (lower surface) CBS2 via a nickel (Ni) film NI. The solder SO1 is, for example, tin (Sn) -1.5 wt. The solder SO2 formed on the upper surface and the side surface of the lead wiring LE is, for example, tin (Sn) solder.

  Thus, by forming the nickel (Ni) film NI between the Cu pillar CB and the solder SO1, the first surface formed on the second surface (lower surface) CBS2 of the Cu pillar CB when flip-chip connection is performed. Since the thickness of the intermetallic compound layer IMC1 (for example, refer to FIG. 9A described above) is thinner than the case where the nickel (Ni) film NI is not formed, the destruction of the joint portion between the Cu pillar CB and the lead electrode LE is suppressed. The effect is improved.

  Further, in the lead electrode LE shown in FIG. 5A described above, the solder SO2 made of tin (Sn) solder is used on the upper surface and side surfaces of the lead electrode LE. In the second modification shown in FIG. Solder to which nickel (Ni) is added, for example, tin (Sn) to which nickel (Ni) is added-3.5 wt. Solder SO3 made of% silver (Ag) solder is used.

  Thus, by using the solder SO3 in which nickel (Ni) is added to the upper surface and the side surface of the lead electrode LE, the thickness of the second intermetallic compound layer IMC2 formed on the upper surface and the side surface of the lead electrode LE is ( For example, refer to FIG. 9A described above), which is thinner than the case of using solder SO2 to which nickel (Ni) is not added, so that the effect of suppressing the breakage of the joint between the Cu pillar CB and the lead electrode LE is improved.

  Further, the second surface (lower surface) CBS2 of the Cu pillar CB is tin (Sn) -1.5 wt. Tin (Sn) -3.5 wt. 1 in which a solder SO1 made of% silver (Ag) solder is formed and nickel (Ni) is added to the upper surface and side surfaces of the lead electrode LE. Solder SO3 made of% silver (Ag) solder may be formed.

  Thereby, since both the thickness of 1st intermetallic compound layer IMC1 and 2nd intermetallic compound layer IMC2 becomes thin, destruction of the junction part of Cu pillar CB and the lead electrode LE can be suppressed more.

  A modification of the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 12 is a cross-sectional view of a principal part showing a semiconductor device.

  The semiconductor device SMP illustrated in FIG. 12 is an example of PoP in which a plurality of packages are stacked. A second package PK2 is stacked on the first package PK1, and external connection terminals (also referred to as outer balls) formed between the wiring board IS1 of the first package PK1 and the wiring board IS2 of the second package PK2. The two are electrically connected by the BSP.

  The first package PK1 is a semiconductor device SM1 similar to the semiconductor device SM (see FIGS. 1 and 2 described above), and includes a plurality of Cu pillars (not shown) formed on the main surface of the semiconductor chip SC1. A plurality of lead electrodes (not shown) formed on the upper surface of the wiring board IS1 are connected via a solder layer SO. The second package PK2 is, for example, a BGA (Ball Grid Array) type semiconductor device SM2 having a plurality of external connection terminals BSP on the lower surface of the wiring board IS2 (surface opposite to the upper surface on which the semiconductor chip SC2 is mounted). is there.

  An example of the structure of the semiconductor device SM2 will be briefly described below, but is not limited thereto.

  The semiconductor device SM2 has a structure in which the upper surface of the wiring board IS2 and the back surface of the semiconductor chip SC2 are opposed to each other, and the semiconductor chip SC2 is mounted on the upper surface of the wiring board IS2 via an adhesive CM. A plurality of chip electrodes (not shown) formed on the main surface of the semiconductor chip SC2 and a plurality of lead electrodes (not shown) formed on the upper surface of the wiring board IS2 are respectively connected via a plurality of conductive wires CW. It is connected. Further, a mold resin MR is formed on the upper surface of the wiring board IS2 so as to cover the semiconductor chip SC2 and the conductive wire CW. A plurality of land pads (not shown) electrically connected to a plurality of lead electrodes formed on the upper surface of the wiring board IS2 are formed on the lower surface of the wiring board IS2. A plurality of external connection terminals BSP are connected to each other.

  By adopting PoP, the mounting area can be reduced and the wiring length can be shortened. On the other hand, in PoP, a process of connecting the wiring board IS1 of the first package PK1 and the wiring board IS2 of the second package PK2 by the external connection terminal BSP, that is, heat treatment is necessary, and heat applied to stack the packages. The history is increased compared to a single-layer package. For this reason, the problem of peeling of the Cu pillar CB used in the semiconductor device SM1 constituting the first package PK1 becomes serious.

  However, in the present embodiment, as described above (for example, the above-described FIG. 9A) in the flip-chip connected solder joint portion (joint portion between the Cu pillar and the lead electrode) of the semiconductor device SM1 constituting the first package PK1. 9B), providing an intermediate layer ISO that is a tin (Sn) rich layer between the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2, and providing a constriction in the intermediate layer ISO. Thus, the joint can be deformed (reversible) due to external stress. Therefore, even when the semiconductor device SM1 having the Cu pillar CB in PoP is used, it is possible to avoid the destruction at the junction between the Cu pillar CB and the lead electrode LE due to the peeling of the Cu pillar CB or the like.

  A modification of the Cu pillar according to the present embodiment will be described with reference to FIG. FIGS. 25A and 25B are a top view of the Cu pillar and a cross-sectional view of the main part of the Cu pillar (a cross-sectional view of the main part taken along the line II ′ of FIG. 25A), respectively.

  In the modification, the opening diameter of the opening CRO formed in the surface protective film PI is formed larger than the diameter of the Cu pillar CB. Thereby, the bottom surface of the Cu pillar CB includes a region formed on the electrode pad CP without running on the surface protective film PI. In such a structure, since a part of the stress generated in the joint portion cannot be relieved by the deformation of the surface protective film PI, the intermediate layer provided with the constriction is destroyed by the peeling of the Cu pillar CB or the like. It is very effective to prevent the ISO from being deformed by external stress.

  A modification of the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 26 is a cross-sectional view of main parts showing a semiconductor device.

  FIG. 26 illustrates a semiconductor device in which the wiring substrate IS and the semiconductor chip SC are mounted on the organic substrate ORS. In the modification, the wiring board IS has a base portion made of silicon (Si), and a land pad is formed on the upper surface thereof. Even in this case, the wiring board IS undergoes thermal deformation such as warping due to a difference in thermal expansion coefficient between the wiring board IS and other members around the wiring board IS. Along with this deformation, stress is applied to the joint between the land pad formed on the upper surface of the wiring board IS and the Cu pillar CB formed on the main surface of the semiconductor chip SC.

  In such a configuration, both the electrode pad of the semiconductor chip SC and the land pad of the wiring board IS are formed on the base portion made of silicon (Si). Solder is not formed. On the other hand, wet solder is formed on the side surface of the land pad on the upper surface of the wiring board IS. As a result, since the land pad side on the upper surface of the wiring board IS is relatively firmly fixed, the Cu pillar CB is easily broken at the bottom on the electrode pad side of the semiconductor chip SC.

  More specifically, it can be considered that a beam composed of a Cu pillar CB, solder, and a land pad is formed between the wiring board IS and the semiconductor chip SC. When the deformation of the wiring board IS due to the stress cannot be absorbed by the slight deformation of the beam and the upper and lower base portions of the beam, the beam is broken or peeled off. In particular, the wiring board IS is harder (Young's modulus is larger) than the organic substrate ORS and has a narrow elastic deformation range. For this reason, the stress absorption effect due to the deformation of the base portion of the beam on the wiring board IS side becomes smaller than that of the organic substrate ORS. In addition, if the strength of one side of the beam is extremely greater than the strength of the other side, the deformation on the other side will be larger, so that the other side will break or peel off than if both are comparable. It becomes easy to do.

  For example, when the width of the land pad is larger than the width of the base portion of the Cu pillar CB, or when the solder is formed only on the side surface of the land pad, the solder is not formed on the side surface of the Cu pillar CB. Since the strength of the beam on the wiring board IS side becomes relatively large, there is a concern of accelerating the destruction at the base portion of the Cu pillar CB (on the semiconductor chip SC side). Alternatively, when the semiconductor chip SC side is a porous low-k film, the relative strength difference becomes large.

  Even in such a configuration, it is possible to suppress the breakage of the joint due to the peeling of the Cu pillar CB or the like by the intermediate layer ISO provided with the constriction.

  In particular, as shown in FIGS. 27A and 27B, when a plurality of through silicon vias (TSV) are formed on the wiring board IS, the thickness of the wiring board IS is small. Since it is smaller than the thickness of the semiconductor chip SC, the warping of the wiring board IS tends to increase, and this configuration including the intermediate layer ISO provided with the constriction is effective.

  FIG. 27 (a) is an enlarged cross-sectional view of the principal part showing a joint portion between the Cu pillar and the land pad when a through silicon via is provided immediately below the land pad. For example, FIG. It is principal part sectional drawing before mounting in the organic substrate ORS shown. In the figure, reference numeral TSV is a through silicon via, reference numeral SF is a seed metal film, reference numeral HBU is a bump base film, and reference numeral HB is a solder ball. FIG. 27 (b) is a cross-sectional view of the main part showing an enlarged joint portion between the Cu pillar and the land pad when the position of the land pad and the through silicon via is shifted. It is principal part sectional drawing before mounting in organic substrate ORS shown in above-mentioned FIG. In the figure, reference sign TSV is a through silicon via, reference sign SBL is a land, reference sign SB is solder, and reference sign MF is a wiring layer.

≪Semiconductor device manufacturing method≫
A method of manufacturing a semiconductor device according to the present embodiment will be described in the order of steps with reference to FIGS. 13, FIG. 15, FIG. 16, FIG. 18, FIG. 19, FIG. 21, FIG. 22, and FIG. 23 are fragmentary cross-sectional views showing the semiconductor device during the manufacturing process of the semiconductor device. 14A and 14B are diagrams for explaining the shape of the lead electrode, where FIG. 14A is a top view of the lead electrode, and FIG. 14B is a cross-sectional view of the main part of the lead electrode along the extending direction of the lead electrode (FIG. 14A). (C) is a cross-sectional view of the main part of the lead electrode along the direction orthogonal to the extending direction of the lead electrode and the upper surface of the wiring board (F in FIG. 14A). It is principal part sectional drawing in the -F 'line | wire. 17A and 17B are views for explaining the shape of the Cu pillar, where FIG. 17A is a top view of the Cu pillar, FIG. 17B is a cross-sectional view of the main part of the Cu pillar along the extending direction of the lead electrode, and FIG. It is principal part sectional drawing of the Cu pillar along the direction orthogonal to the extending | stretching direction of a lead electrode and the upper surface of a wiring board (essential sectional drawing in the HH 'line of Fig.17 (a)). FIG. 20 is a diagram for explaining a series of operations for flip chip connection.

  First, as shown in FIG. 13, a wiring board IS is prepared. A plurality of lead electrodes LE are formed on the upper surface of the wiring board IS, and a part of each of the plurality of lead electrodes LE is exposed from the opening SRO1 formed in the protective film SR1. Further, a second solder SOL2 is formed on a part of the upper surface and the side surface of each of the plurality of lead electrodes LE exposed from the opening SRO1 formed in the protective film SR1.

  Next, the wiring board IS is placed on the underfill stage ST1, and an underfill resin UF that is a liquid thermosetting resin is applied to the upper surface of the wiring board IS. The underfill resin UF is not limited to this, but is, for example, an epoxy resin having an oxide film removing function to which a filler is added.

  The plurality of lead electrodes LE formed on the main surface of the wiring board IS are the same as the lead electrodes LE shown in FIG. 6, for example. That is, here, as shown in FIGS. 14A, 14B, and 14C, the width W1 of the land pad LP (part of the lead electrode LE, to which the Cu pillar is connected) is A lead electrode LE larger than the width W2 of the other part of the lead electrode LE is used. However, the width W1 of the land pad LP is, for example, 15 μm, and the lead electrode LE is formed so that the width W1 of the land pad LP is narrower than the diameter of the Cu pillar. Note that a lead electrode LE having the same width as that of the other part of the lead electrode LE, that is, a constant width, may be used as shown in FIG. 5A.

  On the top and side surfaces of the lead electrode LE, for example, tin (Sn) or 3.5 wt. A second solder SOL2 made of% silver (Ag) is formed. Further, the second solder SOL2 formed on the upper surface of the land pad LP has a convex shape with a raised central portion, and the land of the thickest portion of the second solder SOL2 formed on the upper surface of the land pad LP is formed. The thickness from the upper surface of the pad LP (thickness T2 shown in FIGS. 14B and 14C) is, for example, about 12 μm to 15 μm.

  Next, as shown in FIG. 15, the wiring board IS is placed on the preheat stage ST2, and heat treatment is performed at a temperature of, for example, 50 ° C. or higher and 110 ° C. or lower, preferably 70 ° C. Reduce moisture in UF.

  Next, as shown in FIG. 16, the wiring board IS is placed on the bonding stage ST3. Further, for example, the semiconductor chip SC described with reference to FIGS. 3 and 4 is prepared.

  Subsequently, the semiconductor chip SC is held by the bonding tool BT and moved above the wiring board IS. Then, with the upper surface of the wiring board IS and the main surface of the semiconductor chip SC opposed to each other, the land pads LP that are part of the lead electrodes LE formed on the upper surface of the wiring board IS and the main surface of the semiconductor chip SC. Alignment (position control) is performed so that the position with the formed Cu pillar CB matches. A first solder SOL1 is formed on each of the second surfaces (lower surfaces) of the plurality of Cu pillars CB.

  As shown in FIGS. 17A, 17B, and 17C, the height H1 of the Cu pillar CB from the surface of the surface protective film PI is, for example, about 30 μm, and the Cu pillar CB has a cylindrical shape. The diameter in plan view is about 30 μm to 35 μm, for example, and the length of one side in plan view when the Cu pillar CB is a rectangular parallelepiped shape is about 30 μm to 35 μm, for example.

  The second surface (bottom surface) CBS2 opposite to the first surface (bottom surface) CBS1 connected to the electrode pad CP via the base film UCB of the Cu pillar CB has tin (Sn) -1.5 wt. A first solder SOL1 made of% silver (Ag) is formed. Further, the first solder SOL1 formed on the second surface (lower surface) CBS2 of the Cu pillar CB has a convex shape with a raised central portion, and the second Cu pillar CB at the thickest portion of the first solder SOL1. A thickness T1 from the surface (lower surface) CBS2 is, for example, about 12 μm to 15 μm. A nickel (Ni) film may be formed between the Cu pillar CB and the first solder SOL1.

  A thickness T1 from the second surface (lower surface) CBS2 of the Cu pillar CB at the thickest portion of the first solder SOL1 formed on the second surface (lower surface) CBS2 of the Cu pillar CB and the upper surface of the land pad LP. It is preferable to form the first solder SOL1 and the second solder SOL2 so that the thickness T2 from the upper surface of the land pad LP at the thickest portion of the second solder SOL2 is substantially the same.

  Next, as shown in FIG. 18, the semiconductor chip SC is lowered. Even after the first solder SOL1 formed on the second surface (lower surface) of the semiconductor chip SC contacts the underfill resin UF, the first solder SOL1 formed on the second surface (lower surface) of the Cu pillar CB and the land The semiconductor chip SC is lowered until physical contact with the second solder SOL2 formed on the upper surface of the pad LP is detected. The temperatures of the first solder SOL1 and the second solder SOL2 at this time are both below the solder melting point.

  Here, at least one of the first solder SOL1 and the second solder SOL2 has a surface shape of, for example, FIG. 4, FIG. 11 (a), FIG. 11 (b), FIG. 14 (b), FIG. As shown in either FIG. 17B or FIG. 17C, it is preferable to have a convex shape toward the other solder. As a result, in addition to the effects described later, the discharge of the underfill resin UF between the first solder SOL1 and the second solder SOL2 is facilitated, and the effect of preventing poor bonding is also obtained.

  Such a convex shape on the surface is obtained by, for example, melting a solder layer formed on the lead electrode LE or the Cu pillar CB by electrolytic plating or the like by reflowing, forming the convex shape by the surface tension, and then solidifying the solder layer. be able to. Or the surface of the area | region where the lead electrode LE or Cu pillar CB is solder-joined may be formed in a convex shape, and a solder layer may be formed so that the convex shape remains on it.

  28, 29, and 30 show examples in which the surface of the lead electrode in the region to be soldered has a convex shape. FIGS. 28A and 28B are a cross-sectional view of the main part of the lead electrode and a cross-sectional view of the main part of the lead electrode joined with the Cu pillar in the first example, respectively. 29 (a) and 29 (b) respectively show a cross-sectional view of the main part of the lead electrode and a cross-sectional view of the main part of the lead electrode joined with the Cu pillar in the second example. FIGS. 30A and 30B are a cross-sectional view of main parts of a lead electrode and a cross-sectional view of main parts of a lead electrode joined with a Cu pillar in the third example, respectively.

  In the first example, after the pattern formation of the lead electrode LE is performed by a known method such as a subtractive method or an additive method, a predetermined amount of corner portions are removed by etching to obtain the convex shape shown in FIG. Can do.

  In the second example, after the pattern formation of the lead electrode LE is performed by a known method such as a subtractive method or an additive method, a plating resist having an opening at a position corresponding to a region to be soldered is formed. And the convex shape shown in FIG. 29 can be obtained by selectively plating the opening.

  In the third example, an insulator pattern PIS such as an organic substance is selectively formed at a position corresponding to a region to be soldered on the upper surface of the base material or the prepreg layer. The formation of the insulator pattern PIS can be easily performed by, for example, a photolithography method or an ink jet method. Next, a seed layer is formed using an electroless plating technique including the upper surface of the insulator pattern PIS. Next, a plating resist having an opening corresponding to the pattern of the lead electrode LE is formed on the seed layer, and a material of the lead electrode LE, for example, copper (Cu) is formed by plating so as to fill the inside of the opening. Thus, the convex shape shown in FIG. 30 can be obtained.

  Next, as shown in FIG. 19, the temperature of the bonding stage ST3 holding the semiconductor chip SC is increased to, for example, 80 ° C. to 200 ° C., and the temperature of the bonding tool BT is increased to, for example, 300 ° C. The semiconductor chip SC is lowered by a predetermined distance while heating and melting the first solder SOL1 and the second solder SOL2. As a result, the first solder SOL1 and the second solder SOL2 are joined and integrated to form a solder joint. The distance between the second surface (lower surface) of the Cu pillar CB and the upper surface of the lead electrode LE is, for example, about 10 μm.

  Here, a series of operations of the Cu pillar positioning process described with reference to FIG. 16, the solder contact process described with reference to FIG. 18, and the solder heating / joining process described with reference to FIG. This will be described in detail with reference to FIG.

  First, in the Cu pillar positioning step shown in FIG. 20 (see FIG. 16 described above), the first solder SOL1 formed on the second surface (lower surface) of the Cu pillar CB and the second solder formed on the upper surface of the land pad LP. The first temperature of the first solder SOL1 and the second solder SOL2 is lower than the solder melting point.

  In the next solder contact step shown in FIG. 20 (see FIG. 18 described above), the semiconductor chip SC held by the bonding tool BT is lowered to gradually reduce the distance between the semiconductor chip SC and the wiring board IS. When the contact between the first solder SOL1 formed on the second surface (lower surface) of the Cu pillar CB and the second solder SOL2 formed on the upper surface of the land pad LP is detected, the semiconductor chip SC is lowered. It stops and maintains between the main surface of the semiconductor chip SC and the upper surface of the wiring board IS at a first interval. Also in the solder contact process, the temperature of the first solder SOL1 and the second solder SOL2 is the first temperature lower than the solder melting point.

  In the next solder heating step shown in FIG. 20 (see FIG. 19 described above), the temperature of the bonding tool BT holding the semiconductor chip SC is set while the first solder SOL1 and the second solder SOL2 are in contact with each other. By gradually raising the temperature, the temperature of the first solder SOL1 and the second solder SOL2 is gradually raised to a first temperature lower than the solder melting point to a second temperature higher than the solder melting point, for example, 300 ° C.

  When the temperature of the first solder SOL1 and the second solder SOL2 is gradually increased, the semiconductor chip SC is lowered by a predetermined distance after the temperature of the first solder SOL1 and the second solder SOL2 becomes equal to or higher than the solder melting point. The first solder SOL1 is pushed into the second solder SOL2 to a predetermined depth, and the space between the main surface of the semiconductor chip SC and the upper surface of the wiring board IS is maintained at a second interval. Here, not the load control for pushing with a predetermined load, but the position control for pushing to a predetermined depth is applied. Thus, the distance between the second surface (lower surface) of the Cu pillar CB and the upper surface of the land pad LP can be controlled.

  When the temperature of the first solder SOL1 and the second solder SOL2 is gradually increased, the temperature of the underfill resin UF is also gradually increased. As a result, a crosslinking reaction occurs to increase the viscosity, and the underfill resin UF is in a cured state.

  Next, in the solder joining step shown in FIG. 20 (see FIG. 19 described above), heating is performed for a predetermined time at a second temperature higher than the solder melting point, for example, 300 ° C., whereby the first solder SOL1 and the second solder SOL2 Are joined to form a solder layer SO.

  In the joining of the first solder SOL1 and the second solder SOL2, for example, as shown in FIGS. 9A and 9B described above, the first intermetallic compound layer IMC1 is formed on the second surface (lower surface) of the Cu pillar CB. The second intermetallic compound layer IMC2 is formed on the upper surface and the side surface of the land pad LP. An intermediate layer ISO having a constriction and containing tin (Sn) as a main component is formed between the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2.

  As described above, when the first solder SOL1 is pushed into the second solder SOL2 to a predetermined depth, the distance between the second surface (lower surface) of the Cu pillar CB and the upper surface of the land pad LP is not controlled by load but by position control. Therefore, the intermediate layer ISO can be reliably formed between the first intermetallic compound layer IMC1 and the second intermetallic compound layer IMC2.

  Further, as described above, since at least one of the first solder SOL1 and the second solder SOL2 has a convex surface shape toward the other solder, in the contact between the first solder SOL1 and the second solder SOL2, a convex shape is formed. The apex position of the shape comes into contact with the other solder prior to the peripheral portion. Therefore, a constriction can be formed at the position of the intermediate layer ISO.

  In addition, since the first solder SOL1 and the second solder SOL2 are covered with the underfill resin UF that has undergone a curing reaction, the first solder SOL1 and the second solder SOL2 are to be joined while leaving a part of their respective shapes. Therefore, it is possible to obtain a “neck” in the intermediate layer ISO.

  That is, when there is no underfill resin UF or when it is covered with an underfill resin UF in which the curing reaction has not progressed, the first solder SOL1 and the second solder SOL2 tend to be rounded due to surface tension, so that the constriction disappears. However, since the side surface of each of the first solder SOL1 and the second solder SOL2 is suppressed by the underfill resin UF whose viscosity has increased and the viscosity has increased, each of the first solder SOL1 and the second solder SOL2 Part of the shape can be left.

  Further, after the start of the curing reaction of the underfill resin UF, by completely melting both the first solder SOL1 and the second solder SOL2 (heating up to a temperature higher than the liquidus temperature of each solder material), A highly reliable and low resistance bonding state that does not leave the bonding interface between the first solder SOL1 and the second solder SOL2, and the intermediate layer ISO having “necking” can be obtained at the same time.

  Next, as shown in FIG. 21, after the temperature of the solder layer SO where the first solder SOL1 and the second solder SOL2 are joined is lowered to a third temperature below the freezing point, the semiconductor chip SC is released from the bonding tool BT. .

  Next, as shown in FIG. 22, the wiring board IS on which the semiconductor chip SC is mounted is unloaded from the bonding stage ST3.

  In order to shorten the time required for bonding the plurality of semiconductor chips SC, for example, the following steps may be used.

  First, the operation of the Cu pillar positioning process and the solder contact process described above is performed on each semiconductor chip SC, and a first gap is formed between the main surface of the plurality of semiconductor chips SC and the upper surface of the wiring board IS with an underfill resin. Maintain at intervals.

  Next, the bonding tool capable of sucking and heating the plurality of semiconductor chips SC at a time is lowered, and after detecting contact between the bonding tool and the back surface of the plurality of semiconductor chips SC, the bonding tool is lowered by a predetermined distance (soldering). Heating step).

  Next, the temperature of the first solder SOL1 and the second solder SOL2 is gradually raised to melt the first solder SOL1 and the second solder SOL2 and push them to a predetermined depth, and the main surface of the semiconductor chip SC and the wiring board IS. The first solder SOL <b> 1 and the second solder SOL <b> 2 may be joined by maintaining a distance between the first solder SOL <b> 1 and the upper surface of the solder (solder joining process). If the temperature of the bonding tool at this time is a constant temperature of, for example, 300 ° C., the temperature raising / lowering time can be shortened.

  Next, as shown in FIG. 23, a plurality of external connection terminals BS are respectively disposed on the surfaces of a plurality of land pads BLR formed on the lower surface of the wiring board IS via a flux or solder paste, and then heat treatment is performed. Apply. For example, solder having a lead (Pb) -free solder composition that does not substantially contain lead (Pb) is used for the external connection terminal BS. By the heat treatment, the oxide film on the surface of the external connection terminal BS is removed by the flux and the external connection terminal BS is melted, or the external connection terminal BS and the solder paste are melted and integrated to form a plurality of lands. A plurality of external connection terminals BS that are electrically and mechanically connected to the pad BLR are formed.

  Through the above steps, the semiconductor device SM is substantially completed.

  Thus, according to the present embodiment, the first intermetallic compound layer IMC1 formed on the second surface (lower surface) CBS2 of the Cu pillar CB and the second intermetallic compound formed on the upper surface of the land pad LP. By providing the intermediate layer ISO, which is a tin (Sn) rich layer, between the layer IMC2 and providing the constriction in the intermediate layer ISO, the joint can be deformed by external stress. As a result, it is possible to avoid breakage at the joint between the Cu pillar CB and the lead electrode LE due to peeling of the Cu pillar CB or the like, so that the reliability of the semiconductor device SM is improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the present invention can be applied to a semiconductor device manufacturing method using a batch molding method. In this batch molding method, first, a substrate is prepared in which, for example, product region units composed of wiring substrate patterns shown in FIGS. 5A and 5B are arranged in a matrix. Subsequently, using the bonding method according to the present embodiment, after mounting a plurality of semiconductor chips on the upper surface of the substrate, the upper surface of the substrate is covered with an epoxy resin so as to cover the plurality of semiconductor chips in order to protect the plurality of semiconductor chips. Then, mold sealing is performed. Thereafter, a plurality of external connection terminals are formed on the lower surface of the substrate, and the sealing body finally molded resin is diced to be cut into individual semiconductor devices (semiconductor packages).

  Further, in order to enhance the heat dissipation effect from the semiconductor chip, a package structure in which, for example, a copper (Cu) plate is disposed on the back surface of the semiconductor chip via a heat dissipation resin.

BLR Land pad BS, BSP External connection terminal (outer ball)
BT Bonding Tool C Core material (base material)
CB Cu pillar CBS1 Cu pillar first surface (bottom surface)
CBS2 Cu pillar second surface (lower surface)
CM Adhesive Material CP Electrode Pad CRO Opening CV Lead Via CW Conductive Wire Cx Core Material Surface Cy Core Material Back Surface H1 Cu Pillar Height HB Solder Ball HBU Bump Base Film IC Internal Circuit ID Lower Layer Insulation Film IMC Intermetallic Compound Layer IMC1 first intermetallic compound layer IMC2 second intermetallic compound layer IO input / output buffer circuit IS, IS1, IS2 wiring board ISO intermediate layer IU upper insulating film L1 distance from lower surface of Cu pillar to upper surface of lead electrode LE lead electrode LP land pad LS1 first side LS2 second side LS3 third side LS4 fourth side MF wiring layer ML multilayer wiring ML1 first wiring ML2 second wiring ML3 third wiring ML4 fourth wiring MR mold resin NI nickel film ORS organic Substrate PI Surface protective film PIS Insulator pattern PK1 First package PK2 First Package SB Solder SBL Land SC, SC1, SC2 Semiconductor chip SF Seed metal film SM, SM1, SM2, SMP Semiconductor device SO Solder layer SO1, SO2, SO3 Solder SOL Solder SOL1 First solder SOL2 Second solder SR1, SR2 Protective film SRO1 , SRO2 Opening SS Semiconductor substrate ST1 Underfill stage ST2 Preheat stage ST3 Bonding stage T1, T2 Solder thickness UCB Undercoat film UF Underfill resin VD, VI, VU Through hole (via)
TSV Through silicon via W1 Land pad width W2 Lead electrode width

Claims (19)

A wiring board having a first electrode extending in the first direction on the upper surface;
The main surface has a second electrode and a columnar electrode connecting the second electrode and the first surface, and the first electrode and the second surface opposite to the first surface of the columnar electrode are opposed to each other. A semiconductor chip arranged in
A solder layer formed between the second surface of the columnar electrode and the first electrode;
A resin formed between the upper surface of the wiring board and the main surface of the semiconductor chip;
A semiconductor device comprising:
The solder layer is
A first intermetallic compound layer formed on the second surface of the columnar electrode and mainly composed of an intermetallic compound composed of Sn and Cu;
A second intermetallic compound layer formed on the upper surface of the first electrode and mainly composed of an intermetallic compound composed of Sn and Cu;
An intermediate layer formed between the first intermetallic compound layer and the second intermetallic compound layer;
Have
The Sn atom number ratio contained in the intermediate layer is larger than the Sn atom number ratio contained in the first intermetallic compound layer and the second intermetallic compound layer,
The intermediate layer has one side surface and the other side surface opposite to the one side surface in a cross section along a second direction orthogonal to the first direction on the upper surface of the wiring board, One side surface is located on the other side surface than a line circumscribing two points on the one side surface, and the other side surface is located on the one side than a line circumscribing two points on the other side surface. A semiconductor device located on the side of the substrate. The semiconductor device according to claim 1,
A semiconductor device, wherein a Ni film is formed between the second surface of the columnar electrode and the first intermetallic compound layer. The semiconductor device according to claim 1,
The columnar electrode is a semiconductor device made of Cu. The semiconductor device according to claim 1,
The semiconductor device, wherein the resin is a thermosetting resin having an oxide film removing function. The semiconductor device according to claim 1,
The semiconductor device, wherein a width of the first electrode along the second direction is constant. The semiconductor device according to claim 1,
The first electrode includes a first portion facing the second surface of the columnar electrode and a second portion not facing the second surface of the columnar electrode, and the second direction of the first portion. A semiconductor device in which the width along the second portion is larger than the width along the second direction of the second portion. The semiconductor device according to claim 1,
A width of the columnar electrode along the second direction in the second surface is greater than a width of the first electrode along the second direction. The semiconductor device according to claim 1,
The said intermediate | middle layer is a semiconductor device which has a constriction in the cross section along the said 2nd direction. The semiconductor device according to claim 1,
A semiconductor device, wherein at least one of the second surface of the columnar electrode and the surface of the first electrode is convex. (A) a step of preparing a wiring board having an upper surface and a lower surface opposite to the upper surface, and having a first electrode on the upper surface;
(B) preparing a semiconductor chip having, on the main surface, a second electrode and a columnar electrode connecting the second electrode and the first surface;
(C) holding the semiconductor chip with a tool, and a first solder formed on the second surface opposite to the first surface of the columnar electrode, and a second solder formed on the first electrode A step of bringing the semiconductor chip and the wiring board close to each other,
(D) After the step (c), when the contact between the first solder and the second solder is detected, a first gap is formed between the main surface of the semiconductor chip and the upper surface of the wiring board. Maintaining the process in
(E) after the step (d), raising the temperature of the first solder and the second solder from a first temperature lower than the solder melting point to a second temperature higher than the solder melting point;
(F) After the step (e), the step of joining the first solder and the second solder at the second temperature;
(G) After the step (f), lowering the temperature of the first solder and the second solder from the second temperature to a third temperature lower than the solder melting point,
Have
In the step (e), the semiconductor chip and the wiring board are brought close to each other by a predetermined distance on the way from the first temperature to the second temperature, and the main surface of the semiconductor chip and the wiring board A method of manufacturing a semiconductor device, wherein a distance between the upper surface of the semiconductor device and the upper surface of the semiconductor device is maintained at a second interval smaller than the first interval. The method of manufacturing a semiconductor device according to claim 10.
Between the step (b) and the step (c),
(H) forming a resin on the main surface of the wiring board so as to cover the first electrode;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 11.
The method for manufacturing a semiconductor device, wherein the resin is a thermosetting resin having an oxide film removing function. The method of manufacturing a semiconductor device according to claim 10.
In the step (f),
A first intermetallic compound layer mainly composed of an intermetallic compound composed of Sn and Cu is formed on the second surface of the columnar electrode;
A second intermetallic compound layer mainly composed of an intermetallic compound composed of Sn and Cu is formed on the upper surface of the first electrode;
Between the first intermetallic compound layer and the second intermetallic compound layer, an Sn atomic ratio larger than the Sn atomic ratio included in the first intermetallic compound layer and the second intermetallic compound layer is set. A method for manufacturing a semiconductor device, wherein an intermediate layer is formed. The method of manufacturing a semiconductor device according to claim 10.
A method for manufacturing a semiconductor device, comprising a Ni film between the second surface of the columnar electrode and the first solder. The method of manufacturing a semiconductor device according to claim 10.
The first solder is a Sn-Ag solder.
The method for manufacturing a semiconductor device, wherein the second solder is Sn-based solder or Sn-Ag-based solder to which Ni is added. The method of manufacturing a semiconductor device according to claim 10.
Having a Ni film between the second surface of the columnar electrode and the first solder;
The first solder is a Sn-Ag solder.
The method for manufacturing a semiconductor device, wherein the second solder is Sn-based solder or Sn-Ag-based solder to which Ni is added. The method of manufacturing a semiconductor device according to claim 10.
The method for manufacturing a semiconductor device, wherein the columnar electrode is made of Cu. The method of manufacturing a semiconductor device according to claim 10.
The method of manufacturing a semiconductor device, wherein the first solder and the second solder have a thickness of 12 μm to 15 μm. The method of manufacturing a semiconductor device according to claim 10.
A method of manufacturing a semiconductor device, wherein at least one of the surface of the first solder, the surface of the second solder, the second surface of the columnar electrode, and the surface of the first electrode is convex.

Images