JP2014222555A - Control circuit of semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control drive capacity of a buffer that outputs an internal synchronization signal and address decode signal so as to exert optimal drive capacity on a memory capacity or speed regardless of variations in manufacture, so as to reduce noise and power consumption.SOLUTION: A control circuit of a semiconductor storage device performs reading and writing operation of an arbitrary memory cell in a memory cell array having a plurality of memory cells arranged in matrix, and includes a buffer that drives signals for performing the operation, where the buffer has a plurality of transmission circuits inserted in parallel into the output, and the plurality of transmission circuits are each supplied with an individual control signal.

Description

  The present invention relates to a control circuit for a semiconductor memory device, and more particularly to a control circuit for a semiconductor memory device including a buffer that needs to drive a large load capacity.

  Conventionally, in a synchronous SRAM, the load capacity to be driven differs depending on the memory capacity. Therefore, the buffer size is optimized by designing or corresponding to a CK (clock) buffer or an address decoder buffer suitable for the load capacity. It was done according to the maximum load capacity of the memory capacity. In addition, the driver at the maximum load is divided, and the wiring is changed by the mask at the time of chip manufacture according to the capacity to realize the optimum buffer size.

For example, Patent Document 1 proposes a method in which, in a 2-port SRAM, when the addresses input from two ports match, the auxiliary buffer is activated to adjust the drive capacity of the buffer.
Patent Document 2 proposes a semiconductor integrated circuit including a driver capable of detecting an operating frequency and changing a drive capability according to the detected frequency.
Also, a method of preparing a plurality of buffer transistors, such as an output buffer using a DDR (Double-Data-Rate) method, selecting a necessary buffer transistor by an external signal, and appropriately selecting a buffer size, etc. Is also known.

  In recent years, due to miniaturization of processes, transistor characteristics have become high performance and signal speed has been increased. However, since SRAMs form a single memory cell with a plurality of transistors, the number of development man-hours is large compared to other semiconductor memory devices. For this reason, it is difficult to optimize the buffer according to the capacity size, and the buffer size is designed with the maximum capacity that can be handled as a target. If a driver having an excessive buffer size with respect to the capacity is used, the internal signal speed is excessively increased for the required memory speed. This may be a noise source.

  Furthermore, since process variations accompanying miniaturization are increasing, the internal signal becomes excessively high due to the finish of the chip, and there is a problem in that it affects the nearby signal wiring such as crosstalk. Yes.

  A conventional synchronous SRAM includes, for example, a memory array and peripheral circuits such as a precharge circuit, a read / write circuit, an input / output circuit, a control circuit, a PORTA-address buffer, a row decoder, and a column decoder.

  When “H” (or “L”) is input as the external synchronization clock signal (CK), the designated address is accessed and a read or write operation is performed. That is, the internal synchronization signal operates in response to the external synchronization clock signal (CK), and the word line specified by the address is driven in accordance with the signal, and the read sense amplifier and the write circuit are operated. In this way, the internal synchronization signal is the address latch signal (ADL), sense enable signal (SEN), write signal (WEN), decoder signal (DEN), precharge enable signal (PE), precharge of the peripheral circuit. It becomes a reference signal such as an enable bar signal (PEB).

  The internal synchronization signal has a signal line in the entire SRAM, and requires a large wiring capacity. In order to drive the large-capacity wiring, a circuit that outputs an internal synchronization signal is configured by a buffer having a large driving capability. Even if the buffer is divided into signals, each buffer requires a large driving force.

Similarly, the address decode signal (ADEC) is composed of a large buffer for driving a wiring having a large capacity to the decode circuit in order to designate a word line. In the case of a large memory capacity, the capacity to be driven, such as the wiring capacity and the element capacity of the next stage to be driven, is large. That is, when the burden area is large, a large buffer size is required to drive the wiring capacity and the next circuit of the decoding destination.
If this buffer size is insufficient, it takes time to drive a heavy load capacity, so the speed of the memory itself is reduced. In some cases, malfunction occurs at the timing of other signals.

As described above, the buffer has been conventionally optimized according to the memory capacity. However, when multiple types of memories are mounted on the same chip, the design man-hours become large if the buffer capacity is individually optimized. For this reason, at present, it is configured to be driven by a common buffer circuit.
Further, in order to reduce the chip area as much as possible, the wiring interval cannot be increased. Therefore, there are concerns about noise such as crosstalk and power supply noise due to current consumption for driving a large buffer.

  Further, as described above, the transistor characteristics are improved by the miniaturization of the process, and the rising and falling slopes of the signal are steep, which causes the noise to increase. Further, the transistor size is set on the assumption that the fluctuation of the performance of the transistor is large due to the process variation accompanying the miniaturization and the performance is most deteriorated. For this reason, when the transistor characteristics fluctuate in a better direction due to process variations, the drive is performed with an excessive buffer size.

As described above, in semiconductor memory devices that require a large buffer size due to the wiring capacity to be driven and the capacity of the next stage, etc., the optimum driving capacity for the memory capacity and the optimum driving for the required speed It is required to realize the capability, cope with process variations, prevent malfunctions and performance degradation due to noise, and perform stable operations.
The present invention has been made in view of the above circumstances, and controls the buffer size so as to have an optimum driving capability regardless of manufacturing variations with respect to memory capacity or speed, and noise and power consumption are reduced. An object of the present invention is to provide a control circuit for a semiconductor memory device.

  In order to solve the above problems and achieve the object, a control circuit for a semiconductor memory device according to the present invention performs a read / write operation of an arbitrary memory cell in a memory cell array in which a plurality of memory cells are arranged in a matrix. A control circuit of the apparatus, and a buffer for driving a signal for performing the operation, wherein the buffer has a plurality of transmission circuits inserted in parallel at the output, and the plurality of transmission circuits have individual control signals Is supplied.

According to the control circuit of the semiconductor memory device of the present invention, the transmission circuit is inserted in parallel to the output of the buffer, and the control signal is supplied to the transmission circuit to control the drive number of the transmission circuit. Since it can be changed, noise due to excessive driving force and power consumption can be reduced.
Even if the transistor performance varies due to process variations, the buffer drive performance can be optimized by data collected after chip manufacture.

1 is a block diagram showing a circuit arrangement of a synchronous 1-port SRAM provided with an example of a control circuit of a semiconductor memory device of the present invention. It is a circuit diagram which shows the part relevant to the external clock signal (CK) in a control circuit. It is a circuit diagram which shows an example of the buffer in the control circuit of the semiconductor memory device of this invention. It is a circuit diagram which shows the part which produces | generates the control enable signal for controlling a transmission circuit from the signal from a non-volatile memory circuit, and a normal chip enable signal. FIG. 5 is a circuit diagram showing a portion for generating a control enable signal for controlling a transmission circuit from a signal from a fuse circuit and a normal chip enable signal. FIG. 6 is a circuit diagram illustrating an example of a fuse circuit illustrated in FIG. 5. It is a circuit diagram which shows the part which produces | generates the control enable signal for controlling a transmission circuit from the signal from a current detection circuit, and a normal chip enable signal. FIG. 8 is a circuit diagram illustrating an example of a current detection circuit illustrated in FIG. 7. FIG. 8 is a circuit diagram illustrating an example in which the current detection circuit illustrated in FIG. 7 includes a timer circuit and a holding circuit. It is a circuit diagram which shows the other example of a current detection circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 shows a block diagram of a circuit arrangement of a synchronous 1-port SRAM provided with an example of a control circuit of a semiconductor memory device of the present invention. The control circuit of the semiconductor memory device of this embodiment includes a nonvolatile memory circuit in which output data is stored in advance, and a control signal is supplied from the nonvolatile memory circuit. FIG. 2 shows a circuit diagram of a portion related to the clock of the control circuit 180. FIG. 3 is a circuit diagram showing an example of a buffer in the control circuit of the semiconductor memory device of this embodiment.

As shown in FIG. 1, the synchronous SRAM of this embodiment includes a memory cell array 110 in which memory cells are arranged in a matrix, a precharge circuit 150, a read / write circuit 160, an input / output circuit 170, a control circuit 180, A PORTA-address buffer 120A, a row decoder 130A, and a column decoder 140A are provided.
The control circuit 180 outputs a signal for performing read and write operations of an arbitrary memory cell of the memory cell array 110 based on the external synchronization clock signal (CK) and the address information.

  As shown in FIG. 2, the buffer of the part related to the clock of the control circuit 180 operates with an internal synchronization signal when “H” (or “L”) is input as the external synchronization clock signal (CK). The internal synchronization signals are address latch signal (ADL), sense enable signal (SEN), write enable signal (WEN), decode enable signal (DEN), precharge enable signal (PE), and precharge enable bar signal (PEB). And so on.

  The address latch signal (ADL) drives the PORTA-address buffer 120A. The decode signal (DEN) drives the row decoder 130A and the column decoder 140A, and selects a memory cell that performs read and write operations. The precharge enable signal (PE) and the precharge enable bar (PEB) drive the precharge circuit 150. The precharge circuit 150 charges the pair of bit lines of the memory cell to a predetermined level prior to the read operation. The sense enable signal (SE) and the write enable signal (WEN) drive the read / write circuit 160.

As shown in FIG. 3, the buffer 10 for driving each internal synchronization signal has four transmission circuits (11a, 11b, 11c, 11d) inserted in parallel at the output of the buffer 10. In FIG. 3, each internal synchronization signal is generically described as signal. Individual control signals (DE0, DE1, DE2, DE3) are supplied to the transmission circuits (11a to 11d), respectively.
As shown in FIG. 3, the transmission circuits (11a to 11d) are composed of a Pch transistor and an Nch transistor. An inverted signal of a control signal is input to the gate of the Pch transistor by an inverter, and the gate of the Nch transistor is The control signal is input at the same level.

Next, control signals supplied to the transmission circuit will be described.
FIG. 4 shows a circuit diagram of a part that generates a control enable signal (control signal) for controlling the transmission circuit from a signal from the nonvolatile memory circuit 21 and a normal chip enable signal.

  The nonvolatile memory circuit 21 is arranged inside or outside the semiconductor memory device. The nonvolatile memory circuit 21 stores necessary control signal information based on the test result after manufacturing the SRAM chip. As shown in FIG. 4, the final control enable signal (DE0 to DE3) is generated from the data (DO0 to DO3) from the nonvolatile memory circuit 21 and the normal enable signal (CE).

  The generated control enable signals (DE0 to DE3) are respectively input to the transmission circuits (11a to 11d) shown in FIG. 3, and the outputs from the transmission circuits (11a to 11d) are short-circuited. That is, each transmission circuit (11a to 11d) is controlled by an individual control enable signal (DE0 to DE3), and the capacity of the buffer 10 is adjusted by passing through the four transmission circuits (11a to 11d).

  For example, when “1” is output from one output terminal DO0 of the nonvolatile memory circuit 21 and “0” is output from the other output terminals (DO1 to DO3), “1” is input from DO0. Only the NAND circuit outputs “0”, is inverted by the inverter, and outputs “1” as the control enable signal DE0. “0” is output for the other control enable signals (DE1 to DE3). If it does so, only 11a will become ON among four transmission circuits (11a-11d), a transmission circuit becomes one resistance, and the capability of a buffer can be weakened.

Further, when “1” is output from all the output terminals (DO0 to DO3) of the nonvolatile memory circuit 21, all “1” are output for the control enable signals (DE0 to DE3). Then, all the four transmission circuits (11a to 11d) shown in FIG. 3 are turned on. As a result, the resistances of the four transmission circuits are connected in parallel, and the resistance component is lower than when one of the transmission circuits is turned on, so that the original drive capability of the buffer is improved.
As described above, the resistance value corresponding to the process can be set by changing the number of turning on the transmission circuits (11a to 11d). Further, if the sizes of the transmission circuits (11a to 11d) are made different, the setting variations of the resistance values are expanded.

Even SRAMs having memory cells with different memory capacities can be handled using the same control circuit.
Furthermore, even if transistor performance varies due to process variations after chip manufacture, data is collected by wafer test, etc., and the data is stored in a non-volatile memory circuit and inserted from this data in parallel. Control the number of transmission circuit controls. Thereby, the buffer output can be optimized, and unnecessary noise and power consumption can be reduced.
Even when the buffers are divided, a plurality of transmission circuits may be provided in parallel for each buffer.
Further, a resistance element may be provided in each transmission circuit (11a to 11d) to adjust the resistance value.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
The circuit arrangement of the SRAM provided with an example of the control circuit of the semiconductor memory device of the second embodiment of the present invention is the same as the circuit arrangement of the SRAM of the first embodiment, and the description of the same elements is omitted. . The control circuit according to the present embodiment includes a fuse circuit that determines whether or not a fuse is blown based on a preset current value, and a logic level determined based on whether or not the fuse is cut is used as a control signal from the fuse circuit. The point supplied is different from the first embodiment. FIG. 5 shows a circuit diagram of a portion for generating a control enable signal for controlling the transmission circuit from a signal from the fuse circuit and a normal chip enable signal.

When excessive drive capability occurs due to process variations, etc., the transistor current value is measured by a wafer test or the like, and “1” or “0” is set in the FUSE (fuse) cell of the fuse circuit 31 based on the measured value. To do. Then, fuse signals (FOUT0 to FOUT3) indicating whether to control the transmission circuits (11a to 11d) are output.
As shown in FIG. 5, control enable signals (DE0 to DE3) are generated from the FUSE signal (FOUT0 to FOUT3) signal output from the fuse circuit and the normal chip enable signal (CE). This control enable signal is supplied as a control signal for the transmission circuit, and the capacity of the buffer is adjusted.
Note that a resistance element may be separately provided in each transmission circuit to further adjust the resistance value.

FIG. 6 shows an example of the FUSE cell in the fuse circuit 31.
As shown in FIG. 6, “1” or “0” is output to the output FOUT in response to the read signal RFCK depending on whether or not the fuse (FU21) is cut. The contents of the outputs (FOUT0 to FOUT3) of the fuse circuit 31 are set as follows.
When the Nch transistor (Tr22) is manufactured in such a manner that the current flows relatively well due to process variations or the like, the state of the current value flowing through the Nch transistor (Tr22) is measured using, for example, a wafer test. Based on the measured value, “1” or 0 is set to be output.
That is, when a current exceeding the measured value flows through the Nch transistor, “1” is output to the FUSE signal (FOUT) if the fuse (FU21) is set to be blown.

  By providing such a fuse circuit 31, when the performance of the access transistor of the SRAM is manufactured in a favorable direction, when the current value of the Nch transistor (Tr22) reaches the above measured value, the fuse circuit 31 is “1”. "" Is set, and based on this, "1" is output to the signals (FOUT0 to FOUT3).

On the other hand, when the performance of the access transistor is manufactured in a bad direction, the current value of the Nch transistor constituting the SRAM does not reach the measured value. Then, the fuse circuit 31 remains set to “0”, and “0” is output to the signals (FOUT0 to FOUT3).
As described above, even when the performance of the transistors constituting the SRAM cell varies due to manufacturing variations, the driving capability of the buffer can be controlled. Therefore, since driving with an excessive buffer size does not occur, noise and power consumption can be reduced.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
The circuit arrangement of the SRAM including an example of the control circuit of the semiconductor memory device according to the third embodiment of the present invention is the same as the circuit arrangement of the SRAM according to the first embodiment shown in FIG. Is omitted. The control circuit of the semiconductor memory device of this embodiment includes a current detection circuit that detects a current flowing through a transistor, and a logic level determined by a detection result of the current detection circuit is supplied as a control signal from the current detection circuit. This is different from the first embodiment.
FIG. 7 shows a circuit diagram of a portion for generating a control enable signal for controlling the transmission circuit from a signal from the detection circuit and a normal chip enable signal.

  A current detection circuit 41 for detecting the current of the transistor is disposed inside or outside the semiconductor memory device, and detection is performed while power is supplied to the chip. Control enable signals (DE0 to DE3) are generated from the output signals (IOUT1 to IOUT3) of the current detection circuit 41 and the normal enable signal (CE). This control enable signal (DE0 to DE3) is input to the transmission circuit of the buffer, and the buffer capacity is optimized by controlling the control number of the transmission circuit. Thereby, unnecessary noise and power consumption can be reduced.

FIG. 8 shows a circuit diagram of an example of the current detection circuit.
As shown in FIG. 8, a resistor 61 and an Nch transistor 62 are connected in series between the power supply and GND, and the voltage value of the node N is determined by the resistance value of the Nch transistor 62 (that is, the ease of current flow). . Inverters (INV0 to INV4) having different logic thresholds are connected to the node N. Depending on the voltage value of the node N, a signal is propagated to the outputs (IOUT0 to IOUT3) depending on whether or not the logic threshold is exceeded. The drive capability of the Nch transistor 62 is set using this signal.
By controlling the control number of the transmission circuit according to the drive capability, it is possible to optimize the buffer, thereby reducing unnecessary noise and power consumption.
In the circuit shown in FIG. 8, the Nch transistor 62 is used. However, as a Pch transistor instead of the Nch transistor 62, a resistor and a Pch transistor are connected in series between the power supply and GND to set the drive capability of the Pch transistor. It is also possible.

(Fourth embodiment)
Next, a control circuit of the semiconductor memory device according to the fourth embodiment of the present invention will be described.
The control circuit of the semiconductor memory device of this embodiment includes a current detection circuit different from the control circuit of the semiconductor memory device of the third embodiment.

As described above, the current detection circuit 41 shown in FIG. 7 detects the current flowing through a predetermined transistor while the power supply is introduced, and the output is determined by the voltage ratio (resistance ratio) at a predetermined location. The Therefore, current in the current detection circuit continues to flow while the current detection circuit is enabled. For this reason, there is a problem that current consumption increases.
Therefore, in the present embodiment, a control circuit including a current detection circuit to which a timer circuit and a holding circuit are added will be described.

  The circuit arrangement of the SRAM that is the control circuit of the semiconductor memory device of this embodiment is the same as the circuit arrangement of the SRAM according to the first embodiment shown in FIG. 1, and the description of the same elements is omitted. FIG. 9 shows a circuit diagram including a timer circuit 52 and a holding circuit 53, which is a part that generates a control enable signal for controlling the transmission circuit from a signal from the detection circuit and a normal chip enable signal.

After power is supplied to the current detection circuit 51, the current detection circuit 51 is operated only for a certain period measured by the timer circuit 52, and the detection result is held in the holding circuit 53. When the current detection circuit is deactivated by the timer circuit 52 after power is supplied to the chip, the data is held by the holding circuit 53 that holds an output corresponding to the current. A final sense amplifier enable signal (DE0 to DE3) is generated from the held output signal and the normal sense enable signal (CE).
The generated sense-up enable signals (DE0 to DE3) are input as control signals for the transmission circuit.

FIG. 10 shows an example of a current detection circuit.
FIG. 10 is a diagram of a circuit example of the current detection circuit unit shown in FIG. Although the circuit configuration is substantially the same as the current detection circuit shown in FIG. 8, the TEN signal is input to the gate of the Nch transistor 72. That is, when the power is turned on, “H” is input to the time enable signal (TEN signal or power supply), so that “H” is input to the TEN signal only for the delay time by the timer circuit 52, thereby the current detection circuit. 51 is turned on and turned off after a predetermined time. When this is turned OFF, data is held in the holding circuit (latch) 53. When the current detection circuit 51 is turned off, no current flows through the current detection circuit 51, so that useless current is not consumed. Further, the current in the current detection circuit 51 can be cut off.

In the above four embodiments, four transmission circuits are inserted in parallel at the output of the buffer, and control signals are respectively input to the gates of the transmission circuits. However, an arbitrary number is selected as the parallel number. Can do.
In the above-described four embodiments, a synchronous 1-port SRAM has been described as an example. However, it is obvious that the present invention can be applied to a multi-port SRAM.
Further, the present invention is not limited to the synchronous type, and can be used for a semiconductor memory device having a buffer for driving a large capacity.

DESCRIPTION OF SYMBOLS 10 Buffer 11a, 11b, 11c, 11d Transmission circuit 21 Non-volatile memory circuit 31 Fuse circuit 41 Current detection circuit 51 Current detection circuit 52 Timer circuit 53 Holding circuit 61, 71 Resistance 62, 72 Nch transistor 110 Memory cell array 180 Control circuit

Japanese Patent No. 4408366 JP 2002-297260 A

Claims (5)

A control circuit of a semiconductor memory device that performs read and write operations of an arbitrary memory cell of a memory cell array in which a plurality of memory cells are arranged in a matrix,
A buffer for driving the signal for performing the operation, wherein the buffer has a plurality of transmission circuits inserted in parallel at the output, and an individual control signal is supplied to the plurality of transmission circuits; A control circuit for a semiconductor memory device. A nonvolatile memory circuit in which output data is stored in advance;
2. The control circuit for a semiconductor memory device according to claim 1, wherein the nonvolatile memory circuit outputs the output data as the control signal. A fuse circuit is provided that determines whether or not a fuse is cut according to a preset current value.
2. The control circuit for a semiconductor memory device according to claim 1, wherein the fuse circuit outputs a logic level determined by whether or not the fuse is cut as the control signal. It has a current detection circuit that detects the current flowing through the transistor,
2. The control circuit for a semiconductor memory device according to claim 1, wherein the current detection circuit outputs a logic level determined by a detection result of the current detection circuit as the control signal.   The current detection circuit includes a timer circuit that operates the current detection circuit only for a certain period after power is turned on, and a holding circuit that holds data detected by the current detection circuit. Item 5. A control circuit for a semiconductor memory device according to Item 4.