JP2014207471A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device.SOLUTION: In a semiconductor device 1, a semiconductor chip 8 mounted on a major surface of a package substrate 2 is sealed by a sealing member 11. On the major surface and a rear surface of the package substrate 2, wiring conductor patterns 4 are disposed and dummy conductor patterns 4 are also disposed in regions where the wiring conductor patterns 4 are not formed. Increasing the density of the conductor patterns 4 in the package substrate 2 in the above described manner reduces warpage and swell of the package substrate 2 which are caused by thermal treatment in the manufacturing processes of the semiconductor device 1.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device having a small package structure.

  CSP (Chip Size Package), etc., whose package dimensions are almost the same as or slightly larger than those of semiconductor chips, can be mounted with high density equivalent to bare chip mounting and is relatively inexpensive to manufacture. Demand is rapidly increasing in the field of small and light electronic devices such as information devices, digital cameras, and notebook computers.

  The CSP has various package forms. Generally, a ball grid array in which solder bumps are attached to one surface of a package substrate on which a semiconductor chip is mounted, and the solder bumps are reflow soldered to the surface of a printed wiring board. (Ball Grid Array; BGA) structure is adopted. In particular, in the case of a thin CSP having many pins, a TCP (Tape Carrier Package) type BGA (tape BGA) in which a package substrate on which a semiconductor chip is mounted is formed of an insulating tape such as polyimide is the mainstream. Incidentally, TCP using an insulating tape as a package substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-32248 (see Patent Document 1).

  Moreover, the present inventors investigated a well-known example from the viewpoint of a mold based on this invention. As a result, for example, Japanese Patent Application Laid-Open No. 10-256286 discloses a technique for forming a coating layer on the inner surface of a mold and releasing the mold part in order to smoothly release the mold. (See Patent Document 2). Further, for example, Japanese Patent Laid-Open No. 10-244556 discloses a technique for molding a resin package in a state where a release film is in close contact with the inner surface of the mold in order to easily take out the resin package from the mold. (See Patent Document 3). Further, for example, Japanese Patent Application Laid-Open No. 11-16930 discloses a technique for preventing sheet wrinkling by evacuating a sheet when molding using the sheet (see Patent Document 4). Further, for example, Japanese Patent Laid-Open No. 2000-12578 discloses a technique of mounting many chips on a substrate and performing transfer molding (see Patent Document 5). Further, for example, in Japanese Patent Laid-Open No. 2000-138246, an ejector pin is attached to each of a plurality of blocks using a versatile mold (see Patent Document 6).

Japanese Patent Laid-Open No. 7-32248 JP-A-10-256286 Japanese Patent Laid-Open No. 10-244556 Japanese Patent Laid-Open No. 11-16930 JP 2000-12578 A JP 2000-138246 A

  However, the present inventors have found that the CSP technology using the insulating tape as a package substrate has the following problems.

  That is, the first problem is that it is difficult to apply to products that require high reliability. This is because, in the CSP structure using the insulating tape as a package substrate, the material of the package substrate is sometimes called polyimide or the like, and the temperature cycle performance after mounting must be lower than the customer requirement, and further reliability can be achieved. This is because improvement cannot be achieved.

  The second problem is that the manufacturing cost of the semiconductor device is high. This is because the cost of polyimide tape, which is a package substrate material, is high, and in the manufacture of CSP using the above-mentioned insulating tape as a package substrate, each semiconductor chip is sealed, so products per unit area can be obtained. This is because the standard unit price is higher due to the small number.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a semiconductor device in which a semiconductor chip mounted on a first surface of a first substrate is sealed with a sealing member, and the first surface of the first substrate and the first surface thereof. The second surface is provided with a conductor pattern for wiring and a dummy conductor pattern disposed in a region other than the region where the conductor pattern is disposed.

  The following is a brief description of another outline of the invention disclosed in the present application.

  That is, according to the present invention, a first substrate on which a plurality of semiconductor chips are mounted on a first surface is set in a mold, and between the upper mold of the mold and the first surface of the first substrate. In a state in which the film is interposed and the film is vacuum-adsorbed to the upper mold, the plurality of semiconductor chips are collectively sealed with a resin to form a sealing member. A plurality of semiconductor devices are obtained by cutting the first substrate and the sealing member separated from the mold.

  In the present invention, a first substrate on which a plurality of semiconductor chips are mounted on a first surface is set in a mold, and a second surface on the back side of the first surface is set on the first substrate. The first substrate separated from the mold after molding the sealing member by collectively sealing the plurality of semiconductor chips with resin in a state where the mold is vacuum-adsorbed on the lower mold of the mold The sealing member is cut to obtain a plurality of semiconductor devices.

  The present invention also provides a sealing member formed by collectively sealing a plurality of semiconductor chips mounted on the first main surface of the first substrate having a structure resistant to thermal stress from a mold. After the separation, the first substrate and the sealing member separated from the mold are cut to obtain a plurality of semiconductor devices.

  In the present invention, the first substrate is mainly composed of the same insulating material as the second substrate on which the first substrate is mounted.

  In the present invention, the first substrate is mainly composed of an insulating material having a thermal expansion coefficient equal to that of the second substrate on which the first substrate is mounted.

  In the present invention, the first and second substrates are mainly composed of a glass / epoxy resin-based insulating material.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1). According to the present invention, a first substrate on which a plurality of semiconductor chips are mounted on a first surface is set in a mold, and the plurality of semiconductor chips are sealed together by resin sealing. After molding the stop member, the number of products obtained per unit area can be increased by cutting the first substrate and the sealing member separated from the mold to obtain a plurality of semiconductor devices. Therefore, it becomes possible to reduce the manufacturing cost of the semiconductor device.
(2) According to the present invention, the first substrate is mainly composed of an insulating material having a thermal expansion coefficient equal to that of the second substrate on which the first substrate is mounted. Can be improved.

1 is a perspective view of a semiconductor device according to an embodiment of the present invention. It is sectional drawing of the A1-A1 line | wire of FIG. (A) is a top view of the main surface of the strip board | substrate used at the manufacturing process of the semiconductor device of FIG. 1, (b) is a top view of the back surface of (a). It is sectional drawing of the A2-A2 line | wire of Fig.3 (a). It is a principal part enlarged plan view of the reinforcement pattern in the strip board | substrate of FIG. It is sectional drawing of the A4-A4 line | wire of FIG. (A) is a principal part enlarged plan view which shows the other modification of the reinforcement pattern in the strip board | substrate of FIG. 3, (b) is sectional drawing of the A5-A5 line of (a). (A) is a principal part enlarged plan view of the reinforcement pattern in the strip board | substrate of FIG. 3, (b) is sectional drawing of the A6-A6 line of (a). It is a top view which shows an example of the conductor pattern of the semiconductor device formation area in the main surface of the strip board | substrate of FIG. It is a principal part enlarged plan view of FIG. It is a top view which shows an example of the conductor pattern of the semiconductor device formation area in the back surface of the strip board | substrate of FIG. It is a principal part enlarged plan view of FIG. It is a top view which shows an example of the insulating film pattern of the semiconductor device formation area in the main surface of the strip board | substrate of FIG. (A) is an enlarged plan view of the central portion of FIG. 13, (b) is a cross-sectional view taken along line A7-A7 of (a), and (c) is an explanatory view of the operation due to the structure as shown in (a). is there. It is a top view which shows an example of the insulating film pattern of the semiconductor device formation area in the back surface of the strip board | substrate of FIG. It is sectional drawing of the strip board | substrate in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 17 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 18; It is sectional drawing of a surface perpendicular | vertical to FIG. It is explanatory drawing of an example of the shaping die used at the manufacturing process of the semiconductor device which is one embodiment of this invention. It is a principal part enlarged plan view of the molding surface in the lower mold of the molding die of FIG. FIG. 20 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 19; FIG. 24 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 23; FIG. 25 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 24; FIG. 26 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 27; FIG. 29 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 28; It is a top view of the mounting substrate which mounted the semiconductor device which is one embodiment of this invention. It is a side view of FIG. It is sectional drawing of the strip board | substrate in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is sectional drawing of a surface perpendicular | vertical to FIG. FIG. 33 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 32; FIG. 35 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 34; FIG. 36 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 35; FIG. 37 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 36; It is sectional drawing in the manufacturing process of the semiconductor device which is further another embodiment of this invention. FIG. 39 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 38; FIG. 40 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 39; FIG. 41 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 40; FIG. 42 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 41; FIG. 43 is a cross-sectional view of the strip substrate during a manufacturing step of the semiconductor device following that of FIG. 42; It is sectional drawing of the semiconductor device which is other embodiment of this invention. It is sectional drawing of the semiconductor device which is further another embodiment of this invention. (A) is a top view of the main surface in the modification of the strip board | substrate used at the manufacturing process of the semiconductor device of FIG. 1, (b) is a top view of the back surface of (a). (A) is a top view of the main surface in the further another modification of the strip board | substrate used at the manufacturing process of the semiconductor device of FIG. 1, (b) is a top view of the back surface of (a).

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  Temperature cycle test: A test performed to repeatedly expose a semiconductor device under test to high and low temperatures to cause changes in dimensions and other physical properties to determine operating characteristics and durability of physical damage.

  The main surface (chip mounting surface: first surface) and back surface (package mounting surface: second surface) of the strip substrate (first substrate) are classified into the following regions for convenience. A region in which a semiconductor device is formed is referred to as a “semiconductor device formation region”, and an entire region where a group of the semiconductor device formation regions is disposed is referred to as a “product region (first region)”. Is referred to as a “peripheral region (second region)”.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. Further, some of the drawings used in this embodiment are hatched in order to make the drawings easy to see even if they are plan views. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A1-A1 of FIG.

  The semiconductor device 1 of the present embodiment has, for example, an FBGA (Fine Pitch Ball Grid Array) structure. The package substrate 2 of the semiconductor device 1 is made of, for example, a flat rectangular thin plate, and includes a substrate body 3 and conductor patterns 4 and solder resist (Solder resist) formed on the main surface (chip mounting surface) and the back surface (package mounting surface). resist) 5, a vent hole 6 penetrating between the main surface and the back surface of the package substrate 2, and a bump electrode 7 bonded to the conductor pattern 4 on the back surface side of the package substrate 2.

  In the present embodiment, as the material of the substrate body 3, for example, a glass-epoxy resin single-layer plate equivalent to FR-5 having high heat resistance is employed. Thus, the manufacturing cost of the semiconductor device 1 can be minimized by making the material of the substrate body 3 a single layer plate of inexpensive glass / epoxy resin. That is, the cost of the semiconductor device 1 can be reduced.

  In addition, since the material of the substrate body 3 is the same glass / epoxy resin as the printed wiring board generally used as a substrate on which the semiconductor device 1 is mounted, the heat generated between the package substrate 2 and the printed wiring board. The stress applied to the bump electrode 7 of the semiconductor device 1 due to the difference in expansion coefficient can be alleviated. Thereby, the reliability after mounting the semiconductor device 1 can be improved.

  In addition, since the temperature cycle performance in the temperature cycle test can be improved by about twice or more compared to the case where the substrate body 3 is made of polyimide tape or the like, not only for portable devices and consumer applications, The semiconductor device 1 can be applied to products that require high reliability, such as those for equipment and automotive applications.

  However, the material of the substrate body 3 is not limited to this, and can be variously changed. For example, an organic insulating material such as a BT resin or an aramid nonwoven material may be used. Even if any of these materials is used, the same effect as that obtained when the above glass / epoxy resin is used is obtained. In addition, when BT resin is selected as the material of the substrate body 3, heat conductivity is high. Can be improved.

  The conductor pattern 4 of the package substrate 2 has a simple two-layer structure, for example. Thereby, the manufacturing cost of the semiconductor device 1 can be minimized, and the cost of the semiconductor device 1 can be reduced. In the present embodiment, the conductor pattern 4 has two types of patterns for wiring and dummy. In the present embodiment, the wiring conductor pattern 4 includes a general line pattern and, in addition, a wide pattern to which the bump electrode 7, a bonding wire, a through hole, or the like is bonded. The conductive patterns 4 for wiring on the main surface and the back surface of the package substrate 2 are electrically connected to each other through through holes penetrating between the main surface and the back surface of the package substrate 2. Such wiring and dummy conductor patterns 4 are like electrolytic copper foil (or rolled copper foil) attached to the main surface (chip mounting surface) and back surface (package mounting surface) of the substrate body 3. The conductive film is formed by etching, and the surface is plated with nickel (Ni), gold (Au), or the like. The reason for providing the dummy conductor pattern 4 is to increase the density of the conductor patterns 4 on the main surface and the back surface of the package substrate 2. This will be described later.

  The main surface and the back surface of the package substrate 2 are covered with a solder resist (insulating film) 5. A part of the solder resist 5 is removed, and a part of the conductor pattern 4 is exposed. The solder resist 5 is also called a solder mask or a stop-off, and is a heat-resistant coating material applied to specific regions on the main surface and the back surface of the package substrate 2 during soldering. This resist prevents solder from attaching to this portion. The main function of the solder resist 5 is a function as a protective film that prevents the conductor pattern 4 that is not required to be soldered from coming into contact with the molten solder during soldering, and protects the conductor pattern 4 other than the soldered portion. In addition, prevention of solder bridges between conductors, protection from contamination and moisture, damage prevention, environmental resistance, migration prevention, maintenance of insulation between circuits, and circuits and other components (semiconductor chips (hereinafter simply referred to as chips)) And a function of preventing a short circuit with a printed wiring board). Therefore, the solder resist 5 is made of an insulating material having these functions. In the present embodiment, for example, an epoxy resin and an acrylic resin are used as the material of the solder resist 5 in consideration of the thermal expansion coefficient. Further, in the present embodiment, the covering state (covering area, thickness, etc.) of the solder resist 5 is substantially uniform between the main surface and the back surface of the package substrate 2. This will be described later.

  In addition, the package substrate 2 is provided with a vent hole 6 penetrating the main surface and the back surface thereof. The vent hole 6 is used to release voids, moisture, and the like in the adhesive 9 for fixing the chip 8 to the package substrate 2 to the outside before or during the heat treatment in the assembly process (post process) of the semiconductor device 1. It is a hole. The vent hole 6 will also be described later.

  A bump electrode 7 is bonded to the wiring conductor pattern 4 on the back surface of the package substrate 2. The bump electrode 7 is a protruding electrode for mounting the semiconductor device 1 on a mounting substrate and electrically connecting the semiconductor device 1 and the wiring of the mounting substrate. The bump electrode 7 is made of, for example, a lead (Pb) / tin (Sn) alloy, and its diameter is, for example, about 0.3 to 0.5 mm. As a material for the bump electrode 7, for example, tin (Sn) -silver (Ag) -based lead-free solder can be used.

  The total thickness of the package substrate 2 (the total thickness of the substrate body 3, the conductor pattern 4, and the solder resist 5) is extremely thin, for example, 0.2 mm or less. Thereby, the thin design of the semiconductor device 1 is possible. Therefore, a small, thin, and lightweight design of an electronic device or an information processing device on which such a semiconductor device 1 is mounted becomes possible.

  At the center of the main surface of the package substrate 2, the chip 8 is mounted with the main surface (element formation surface) facing upward. The chip 8 is fixed to the main surface of the package substrate 2 with an adhesive 9 such as a paste containing silver (Ag) or an insulating paste without silver. An integrated circuit such as a microprocessor, ASIC, or memory is formed on the main surface of the chip 8. The integrated circuit on the main surface of the chip 8 is electrically connected to bonding pads (external terminals) provided in the uppermost wiring layer of the chip 8. The bonding pad is electrically connected to the wiring conductor pattern 4 on the main surface of the package substrate 2 through the bonding wire 10. The bonding wire 10 is made of, for example, a gold (Au) fine wire having a diameter of about 25 μm, and is brought into contact with and bonded to a region exposed from the solder resist 5 in the wiring conductor pattern 4 formed on the main surface of the package substrate 2. Yes. However, the mounting form of the chip 8 is not limited to that connected by the bonding wire 10. For example, the chip 8 is mounted on the main surface of the package substrate 2 via the bump electrode provided on the main surface. Also, a so-called face-down bonding mounting form that is electrically connected to the wiring of the package substrate 2 may be employed.

  The chip 8 and the bonding wire 10 are sealed by a sealing member 11 that covers the main surface of the package substrate 2. The sealing member 11 is made of, for example, an epoxy resin and a low molecular weight resin, and its side surface is formed to be substantially perpendicular to the main surface of the package substrate 2. The total height (height from the mounting surface of the mounting substrate to the upper surface of the semiconductor device 1) h1 of the semiconductor device 1 is, for example, about 1.2 to 1.4 mm.

  Next, a strip substrate used in the semiconductor device manufacturing method of the present embodiment will be described. 3 and 4 show the strip substrate 12. 3A is a plan view of the main surface (chip mounting surface) of the strip substrate 12, and FIG. 3B is a plan view of the back surface (package mounting surface) thereof. 4 shows a cross-sectional view taken along line A2-A2 of FIG. Although FIG. 3 is a plan view, the plating wiring is hatched.

  The strip substrate 12 is made of, for example, a thin plate having a substantially rectangular shape with a length of about 40 × 66 mm × 151 mm and a thickness of 0.2 mm or less. The strip substrate 12 is a base body of the package substrate 2 and includes the substrate body 3, the conductor pattern 4, and the solder resist 5. On the main surface and the back surface of the strip substrate 12, for example, 2 rows along the width direction and 9 rows along the longitudinal direction, a total of 2 × 9 = 18 semiconductor device formation regions DA are arranged. A broken line of each semiconductor device formation area DA on the main surface of the strip substrate 12 indicates an area where the chip 8 is mounted. Moreover, the adjacent boundary line of each semiconductor device formation area DA is also a cutting line described later.

  Reinforcing patterns 13 (13a, 13b, 13c) are provided in a peripheral region near the four sides on the main surface and the back surface of the strip substrate 12 so as to surround a group (product region) of the semiconductor device formation region DA. The reinforcing pattern 13 is a member for ensuring mechanical strength during transport of the strip substrate 12 and suppressing warpage, distortion, and the like due to heat treatment during manufacturing of the semiconductor device 1. By providing such a reinforcing pattern 13, the mechanical strength of the extremely thin strip substrate 12 can be secured, so that the strip substrate 12 can be transported with peace of mind. In addition, since warpage, distortion, and the like due to heat treatment during manufacturing of the semiconductor device 1 can be suppressed, the flatness thereof can be ensured. For this reason, good sealing becomes possible during the sealing process described later, and the yield of the semiconductor device 1 can be improved.

  The reinforcing pattern 13 is preferably formed by continuously extending along the outer periphery of the strip substrate 12 from the viewpoint of ensuring the mechanical strength. Here, the reinforcing pattern 13 (except for the reinforcing pattern 13b) is used. However, on both the main surface and the back surface of the strip substrate 12, the semiconductor device formation area DA is divided and arranged. This is because, during the heat treatment at the time of manufacturing the semiconductor device 1, the strip substrate 12 is warped or twisted due to differences in the thermal expansion coefficients of the materials of the strip substrate 12 (substrate body 3, conductor pattern 4 and solder resist 5). However, since the thermal stress is relatively strongly applied between adjacent semiconductor device regions DA, the entire flatness of the strip substrate 12 is ensured by dispersing and releasing the thermal stress. Further, if the reinforcing pattern 13 is not divided, an afterimage distortion may occur in the reinforcing pattern 13 portion between the adjacent semiconductor device formation areas DA. Further, by providing the reinforcing pattern 13 for each semiconductor device formation area DA, in addition to ensuring the overall flatness of the strip substrate 12, the flatness of each semiconductor device area DA that substantially becomes a semiconductor device is further increased. This is because the resin sealing can be performed satisfactorily and the yield of the semiconductor device 1 can be improved. In addition, since the reinforcing pattern 13a does not exist on the cutting line of the strip substrate 12, it is possible to prevent the occurrence of conductive foreign matter (flash) or the like of the reinforcing pattern 13a when the strip substrate 12 is cut, and to prevent a short circuit failure caused by the foreign matter. Can be prevented.

  The reinforcing pattern 13 is made of, for example, copper foil, and is formed in the same process as the conductor pattern 4. Among the reinforcing patterns 13, the reinforcing pattern 13a is not a solid pattern, but is formed in a tile shape, for example. FIG. 5 is an enlarged plan view of a main part of the reinforcing pattern 13a, and FIG. 6 is a sectional view taken along line A4-A4. The reinforcing pattern 13a is configured by arranging a plurality of rectangular fine patterns (first patterns) separated from each other regularly along the longitudinal direction and the width direction of the reinforcing pattern 13a. . However, in this reinforcing pattern 13a, adjacent rectangular fine patterns along the width direction are arranged in a state of being shifted from each other along the longitudinal direction of the reinforcing pattern 13a.

  The reason why the reinforcing pattern 13a is tiled in this way is to relieve thermal contraction due to the thermal stress by making the reinforcing pattern 13a stretchable during the heat treatment. That is, this can relieve the thermal stress due to the heat treatment during the manufacturing process of the semiconductor device 1 and can suppress or prevent the occurrence of afterimage distortion, so that the flatness of the strip substrate 12 can be further improved.

  However, the pattern shape of the reinforcing pattern 13a may basically be any shape that can expand and contract and absorb thermal stress, and is not limited to a tile shape, and can be variously changed. For example, as shown in FIG. It is good also as a structure. FIG. 7A is an enlarged plan view of a main part of the reinforcing pattern 13a, and FIG. 7B is a sectional view taken along line A5-A5 of FIG. Although FIG. 7A is a plan view, hatching is given to a conductor pattern for making the drawing easy to see.

  The reinforcing pattern 13a illustrated in FIG. 7 illustrates a dot pattern. The reinforcing pattern 13a is configured by arranging a plurality of rectangular conductor film removal regions 14 formed by removing a part of the conductor film. However, in the reinforcing pattern 13a, the plurality of rectangular conductor film removal regions 14 are arranged side by side on the same straight line in the width direction of the reinforcing pattern 13a.

  Any of the reinforcing patterns 13a shown in FIGS. 5 and 7 can provide the effect relating to the thermal stress. However, from the viewpoint of obtaining the mechanical strength of the strip substrate 12, the pattern shown in FIG. This is because, in the structure of the reinforcing pattern 13a in FIG. 5, the patterns (conductor film removal region 14, rectangular fine pattern) adjacent to each other in the width direction are shifted from each other along the longitudinal direction of the reinforcing pattern 13a. Because. Further, the use of the auxiliary pattern 13a of FIG. 5 is particularly effective in avoiding afterimage distortion as compared with other structures. This is because, in the case of the auxiliary pattern 13a having the tile-shaped pattern structure of FIG. 5, the rectangular fine patterns constituting the auxiliary pattern 13a are separated from each other, so that no distortion remains in the auxiliary pattern 13a itself.

  On the other hand, in the main surface (chip mounting surface) of the strip substrate 12 of FIGS. 3 and 4, the reinforcing pattern 13b disposed in the vicinity of one side in the longitudinal direction is not divided and is not tile-shaped and solid. It is formed with a pattern. FIG. 8A is an enlarged plan view of a main part of the reinforcing pattern 13b, and FIG. 8B is a sectional view taken along line A6-A6. Although FIG. 8A is a plan view, the conductor pattern is hatched to make the drawing easy to see.

  The reason why the reinforcing pattern 13b is not divided and is a solid pattern is that a portion where the reinforcing pattern 13b is arranged in a sealing process of the chip 8 and the like described later is a so-called gate of a sealing mold. This is because the case is illustrated. That is, since the sealing resin is poured into the cavity of the sealing mold in a state of being in direct contact with the reinforcing pattern 13b, if the reinforcing pattern 13b is divided or made into a mesh shape, a strip is formed after the sealing process. This is to avoid the problem that the substrate 12 cannot be peeled off from the sealing mold. Therefore, as long as the gate of the sealing mold is divided, the reinforcing pattern 13b may be divided.

  The reinforcing pattern 13c is also formed as a solid pattern. This is because the reinforcing pattern 13c is a portion that provides rigidity when the strip substrate 12 is conveyed. In FIG. 3, a conductor pattern 4m indicates a pattern for supplying a current when the conductor pattern 4 arranged in the semiconductor device formation area DA is plated.

  Next, the arrangement of the conductor pattern 4 in the semiconductor device formation area DA on the main surface and the back surface of the strip substrate 12 will be described. FIG. 9 shows an overall plan view of the semiconductor device formation area DA (that is, the main surface (chip mounting surface) of the package substrate 2) on the main surface of the strip substrate 12, and FIG. 10 shows the main part of FIG. An enlarged plan view is shown. 11 shows an overall plan view of the semiconductor device formation region DA (that is, the back surface (package mounting surface) of the package substrate 2) on the back surface of the strip substrate 12, and FIG. 12 shows the main part of FIG. An enlarged plan view is shown. 9 to 12, the conductor pattern 4 is hatched for easy understanding of the arrangement of the conductor pattern 4.

  As described above, in order to increase the density of the conductor pattern 4 in the semiconductor device formation region DA (that is, the main surface and the back surface of the package substrate 2) on the main surface and the back surface of the strip substrate 12, the wiring conductor pattern 4a ( In addition to 4), a dummy conductor pattern 4b (4) is arranged. As described above, by increasing the density of the conductor pattern 4 in each semiconductor device formation region DA, the substrate warp or undulation in the semiconductor device formation region DA, that is, in the package substrate 2 due to heat treatment during the manufacturing process of the semiconductor device 1 is caused. Can be reduced. Moreover, it is preferable that the conductive patterns 4 have substantially the same arrangement state (area, arrangement position, density, etc.) on the main surface and the back surface of the strip substrate 12 (package substrate 2). As a result, the amount of heat shrinkage between the main surface and the back surface can be made uniform, so that substrate warpage, undulation, and the like due to heat can be reduced. Thus, the flatness of the strip substrate 12 and the package substrate 2 can be improved. Moreover, since the crack of the solder resist 5 can be made difficult to occur by increasing the density of the conductor pattern 4, it becomes possible to prevent disconnection failure of the conductor pattern 4a for wiring. Further, by interposing the dummy conductor pattern 4 between the wiring conductor patterns 4 adjacent to each other, the stray capacitance between the adjacent wiring conductor patterns 4 can be eliminated, and the generation of induction noise can be prevented.

  However, if the density of the conductor pattern 4 is excessively increased, the contact area between the substrate body 3 and the solder resist 5 is reduced, resulting in a decrease in the adhesive force between the two members. It is divided at appropriate points. Thereby, since the area | region where the board | substrate main body 3 and the soldering resist 5 contact can be ensured, it is possible to improve the adhesive force of the board | substrate main body 3 and the soldering resist 5. FIG. Further, since the stress due to the difference in thermal expansion coefficient between the chip 8 and the strip substrate 12 is likely to concentrate around the mounting area of the chip 8 during reflow, peeling of the solder resist 5 is likely to occur. Therefore, disconnection of the conductor pattern 4 and peeling of the solder resist 5 can be reduced by reducing the area of the dummy conductor pattern as much as possible or by adopting a structure in which the dummy conductor pattern is not formed. As shown in FIGS. 9 to 12, a large dummy conductor pattern 4 b having a substantially planar square shape is formed in the semiconductor device formation region DA, that is, in the center of the main surface and the back surface of the package substrate 2. Thus, by providing the large dummy conductor pattern 4b at the position where the back surface of the chip 8 (see FIG. 2) faces, the density of the conductor pattern 4 is improved and the heat generated by the chip 8 during operation is dissipated. It is possible to improve. A plurality of circular conductor film removal regions 14 are regularly arranged in the dummy conductor pattern 4 at the center. The conductor film removal region 14 is formed by removing a part of the conductor film (copper foil or the like). By providing such a conductor film removal region 14, the arrangement density of the conductor patterns 4 on the main surface and the back surface of the strip substrate 12 (that is, the package substrate 2) can be adjusted. In addition, since the contact area between the substrate body 3 and the solder resist 5 can be secured, the adhesive strength between the substrate body 3 and the solder resist 5 can be further improved.

  Of the conductor pattern 4a for wiring on the main surface of the strip substrate 12 (main surface of the package substrate 2) in FIG. 10, the bonding wire 10 is bonded to the wide conductor pattern 4a1 (4) having a substantially rectangular plane. Pattern part to be processed. Further, of the wiring conductor pattern 4a, the wide conductor pattern 4a2 (4) having a substantially elliptical shape in a plane is a pattern portion where the through hole is arranged. Further, among the conductive patterns 4a for wiring on the back surface of the strip substrate 12 (the back surface of the package substrate 2) of FIG. 11, the relatively wide conductor pattern 4a3 (4) has the through holes disposed therein and the bumps. It is a pattern part to which the electrode 7 is joined.

  Next, the arrangement of the solder resist 5 in the semiconductor device formation area DA on the main surface and the back surface of the strip substrate 12 will be described. FIG. 13 is an overall plan view of the semiconductor device formation area DA (that is, the main surface (chip mounting surface) of the package substrate 2) on the main surface of the strip substrate 12. FIG. 14A is an enlarged plan view of the central portion of FIG. 13, FIG. 14B is a cross-sectional view taken along the line A7-A7 of FIG. 13A, and FIG. FIG. Further, FIG. 15 shows an overall plan view of the semiconductor device formation area DA (that is, the back surface (package mounting surface) of the package substrate 2) on the back surface of the strip substrate 12. In FIG. 13, FIG. 14A and FIG. 15, the solder resist 5 is hatched for easy understanding of the arrangement of the solder resist 5.

  As described above, the solder resist 5 is deposited almost uniformly on the semiconductor device formation regions DA (that is, the main surface and the back surface of the package substrate 2) on the main surface and the back surface of the strip substrate 12. In other words, the solder resist 5 is deposited on the main surface and the back surface with approximately the same thickness and approximately the same area. In particular, the solder resist 5 is also formed in the region without the conductor pattern 4 in order to minimize the heat shrinkage difference between the main surface and the back surface of the region without the conductor pattern 4. As a result, the amount of thermal contraction of the main surface and the back surface of the strip substrate 12 (package substrate 2) can be made constant, so that the semiconductor device 1 is formed in the semiconductor device formation region DA by heat treatment during the manufacturing process of the semiconductor device 1, that is, the package substrate. Substrate warpage, undulation, etc. in 2 can be reduced. Therefore, the flatness of the strip substrate 12 and the package substrate 2 can be improved.

  Further, in the present embodiment, as shown in FIGS. 13 and 14, the solder resist 5 is left around the vent hole 6 so as to surround the vent hole 6, and the resist having a circular frame shape so as to surround the periphery. A removal region 15a is formed. The resist removal region 15a functions as a dam for preventing clogging with the adhesive 9. That is, if the resist removal region 15a is not provided, when the chip 8 is fixed to the main surface of the package substrate 2 via the adhesive 9, the adhesive 9 is pressed by the pressing force from the chip 8 to the package substrate 2. It flows along the main surface of the gas and closes the vent hole 6. On the other hand, by providing the resist removal region 15a, as shown in FIG. 14C, the swept adhesive 9 accumulates and is trapped in the resist removal region 15a. Clogging can be prevented.

  In FIG. 13, the bonding wire connecting conductor pattern 4a1 is exposed from the plurality of rectangular resist removal regions 15b. In FIG. 15, the bump electrode connecting conductor pattern 4a3 is exposed from a plurality of circular resist removal regions 15c.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 16 to 20 and FIGS. 23 to 29 are cross-sectional views of main parts during the manufacturing process of the semiconductor device.

  The manufacturing method of the semiconductor device according to the present embodiment is a manufacturing method of a MAP (Mold Array Package) method in which a plurality of chips 8 mounted on the strip substrate 12 are collectively sealed.

  First, as shown in FIG. 16, after the strip substrate 12 is prepared, an adhesive 9 such as an insulating paste is used in the chip mounting region of the main surface of the strip substrate 12 as shown in FIG. Then, the chip 8 is mounted. The dimensions of the chip 8 are, for example, length × width = 5 mm × 5 mm to 8 mm × 8 mm and a thickness of about 0.28 mm.

  Subsequently, as shown in FIG. 18, the bonding pads of the chip 8 and the wiring conductor pattern 4a1 on the main surface of the strip substrate 12 are electrically connected by, for example, bonding wires 10 made of gold. At this time, for example, a well-known wire bonder using both ultrasonic vibration and thermocompression bonding was used.

  Thereafter, as shown in FIGS. 19 and 20, the strip substrate 12 after the wire bonding step is conveyed to the molding die 16. At this time, since the strip substrate 12 has a rigid structure as described above, the strip substrate 12 can be safely transported without worrying about deformation and dents. FIG. 20 shows a cross-sectional view of a plane orthogonal to FIG.

  In the present embodiment, the molding die 16 has a collective mold structure in which a plurality of chips 8 on the main surface of the strip substrate 12 can be collectively sealed with resin. A plurality of vacuum suction holes 17 are provided in the lower mold 16 a of the sealing mold 16. The vacuum suction hole 17 is used for the strip substrate 12 in a sealing step (a step from setting the strip substrate 12 to the molding die 16 to sealing a plurality of chips 8 on the strip substrate 12 with a sealing resin). A hole for holding the extremely thin strip substrate 12 firmly by sucking and adsorbing the back surface (package mounting surface) side of the substrate, and in particular, suppressing warpage, distortion, etc. of the strip substrate 12 due to the heat of the lower mold 16a. It is.

  The upper die 16b is provided with a cavity 16c, a cull block 16d, and a gate 16e. The cavity 16c is a resin injection region corresponding to a molding part. In the present embodiment, there is provided a large cavity 16c that can be collectively sealed without dividing the plurality of chips 8 of the strip substrate 12. That is, the cavity 16c can accommodate a plurality of chips 8 in one cavity 16c. Further, the cull block 16d is a recess provided in the mold for supplying a molding material injected by a plunger, which will be described later, to the cavity 16c, and a resin portion that has remained and solidified in the recess. The gate 16 e is an injection port through which molten resin is injected into the cavity 16 c in the molding die 16. The upper die 16b is provided with an ejector pin 18 so as to protrude into the cavity 16c. The ejector pins 18 are members for releasing the strip substrate 12 from the molding die 16 after the sealing step. The ejector pins 18 are arranged in the outer periphery of a group (product area) of the semiconductor device formation area DA, that is, in an area that is finally cut and not left in the semiconductor device 1. This is because when the ejector pins 18 are pressed against the sealing member formed on the strip substrate 12 and the strip substrate 12 is taken out, marks and scratches of the ejector pins 18 remain on the sealing member. It is considered so as not to be done.

  An example of the molding die 16 is shown in FIGS. FIG. 21 is an overall perspective view of the molding die 16, and FIG. 22 shows a molding surface of the lower die 16 a of the molding die 16. FIG. 21 shows the molding surfaces of the lower mold 16a and the upper mold 16b so that they can be easily seen, and does not show the open / closed state of the lower mold 16a and the upper mold 16b.

  Here, the molding die 16 capable of sealing the two strip substrates 12 in one sealing step is illustrated. A plurality of pot / plunger portions 16f are arranged along the longitudinal direction of the lower die 16a at the center in the width direction on the molding surface of the lower die 16a. The pot of the pot / plunger portion 16f is a molding material supply port, and the plunger is a component that injects the molding material in the pot into the cavity 16c and holds it under pressure. The strip substrates 12 are placed on both sides of the row of the pot / plunger portions 16f.

  The plurality of vacuum suction holes 17 are regularly arranged in the mounting area of the strip substrate 12 on the molding surface of the lower mold 16a (indicated by black circles). The arrangement of the vacuum suction holes 17 is preferably outside the group of regions (product regions) of the semiconductor device formation region DA in the plane of the strip substrate 12. This is because a small protrusion may be formed in the sealing resin due to vacuum suction of the back surface of the strip substrate 12 during the resin sealing process as will be described later. This is to avoid being left behind. However, in the present embodiment, the planar size of the strip substrate 12 may be large, and from the viewpoint of ensuring vacuum flatness of the strip substrate 12 by securing the strip substrate 12 with vacuum, the center of the strip substrate 12 in the width direction is secured. The vacuum suction holes 17 are also arranged at positions corresponding to the line (center line). Since this center line corresponds to a cutting area, which will be described later, is a region that will be cut, is it left in the final semiconductor device 1 even if the protrusion is formed on the line immediately after the sealing process? Moreover, it is because it can be made very small so that the appearance does not deteriorate even if left. From the viewpoint of achieving such an object, the lower mold 16a may be made of a porous material, and the back surface of the strip substrate 12 may be vacuumed almost uniformly within the entire surface. In this case, since the entire back surface of the strip substrate 12 can be vacuum-sucked, the problem of the protrusion does not occur. That is, the yield reduction of the semiconductor device 1 due to the protrusion can be avoided.

  On the other hand, on the molding surface of the upper die 16b, a plurality of the cull blocks 16d are arranged along the longitudinal direction of the upper die 16b at the center in the width direction. In addition, cavities 16c are arranged on both sides of the cull block 16d row on the molding surface of the upper die 16b. Each cull block 16d and the cavities 16c on both sides thereof communicate with each other through a gate 16e.

  Next, as shown in FIG. 23, after the strip substrate 12 is placed on the molding surface of the lower mold 16a, the temperature of the lower mold 16a is set to, for example, about 175 ° C. for about 20 seconds with respect to the strip substrate 12. The preheating process is performed. This processing has the purpose of calming the deformation of the strip substrate 12 due to heat.

  In the present embodiment, as described above, the structure of the strip substrate 12 itself has a structure in which warpage, undulation, distortion, and the like (hereinafter abbreviated as warpage) due to thermal stress or the like are unlikely to occur. Thereby, when the strip board | substrate 12 is mounted in the shaping die 16, the said curvature etc. of the strip board | substrate 12 which generate | occur | produces due to a heat conductive mechanism can be reduced. As described above, not only the overall flatness of the strip substrate 12 but also the flatness of each individual semiconductor device formation region DA can be ensured.

  Next, as shown in FIG. 24, the temperature of the lower mold 16a and the upper mold 16b is set to about 175 ° C., for example, and the back surface of the strip substrate 12 is adsorbed by the vacuum suction hole 17 to The mold 16a is brought into close contact with the molding surface. At this time, in this embodiment, since the strip substrate 12 is extremely thin as described above, the strip substrate 12 can be vacuum-sucked well. As described above, in this embodiment, the warp caused by the heat treatment can be further reduced by vacuum-sucking the back surface of the strip substrate 12 in the sealing process. For this reason, even if the planar area of the strip substrate 12 becomes larger due to a request for an increase in the number of products to be acquired, or even when the thickness of the strip substrate 12 is further reduced due to a demand for thinness of the semiconductor device, it is caused by the heat treatment. Resin sealing can be performed in a state in which the entire strip substrate 12 and the flatness of each semiconductor device formation area DA are ensured without causing the warp or the like. Note that the arrows shown in the vacuum suction holes 17 in FIG. 24 and subsequent figures indicate the direction of vacuum suction.

  Next, as shown in FIG. 25, while maintaining the above temperature and vacuum suction treatment, for example, an epoxy resin and a low molecular resin sealing resin are poured into the cavity 16c of the upper mold 16b, and the strip substrate 12 By integrally sealing the plurality of chips 8 on the main surface, the bonding wires 10 and the like, an integral cubic sealing member 11 containing the plurality of chips 8 is formed on the main surface side of the strip substrate 12. . At this time, in the present embodiment, since the flatness of the strip substrate 12 is high, leveling resin sealing is possible. Therefore, the incidence of appearance defects of the semiconductor device 1 can be reduced, and the yield of the semiconductor device 1 can be improved. Subsequently, as shown in FIG. 26, the ejector pin 18 of the upper die 16b is protruded toward the cavity 16c while the temperature of the lower die 16a and the upper die 16b is kept as described above, and the sealing after the sealing step is performed. The strip substrate 12 having the member 11 is taken out from the molding die 16. The sealing member 11 at this stage includes a plurality of chips 8. In the sealing member 11, the sealing member 11 is filled without a gap between adjacent semiconductor device formation regions.

  Next, as shown in FIG. 27, solder bumps 7 </ b> A are connected to the conductor pattern 4 (4 a 3) for wiring in each semiconductor device formation area DA on the back surface of the strip substrate 12. In order to connect the solder bumps 7A to the conductor pattern 4, a plurality of solder bumps 7A formed in advance in a hole shape are held by using the tool 19, and in this state, the solder bumps 7A are immersed in a flux bath and their After applying the flux on the surface, the solder bumps 7A are temporarily attached to the corresponding conductor pattern 4 (4a3) using the adhesive force of the flux.

  The solder bump 7A is made of a lead / tin alloy, and its diameter is, for example, about 0.5 mm. The solder bumps 7A may be connected to the solder bumps 7A in one semiconductor device formation area DA at the same time, but from the viewpoint of improving the throughput of the bump connection process, a plurality of semiconductor device formation areas DA are provided. It is desirable to connect the solder bumps 7A all together. In this case, since the tool 19 having a large area is used, if the strip substrate 12 is warped or deformed, there may be a problem that some solder bumps 7A are not joined to the conductor pattern 4. On the other hand, in the present embodiment, warpage, deformation, and the like that occur in the strip substrate 12 in the steps up to here are extremely small. Therefore, a plurality of solder bumps 7A in a plurality of semiconductor device formation areas DA are respectively corresponding to the plurality of solder bumps 7A. It is possible to connect to the conductor pattern 4 (4a3) simultaneously and accurately. Further, in consideration of variations in the degree of warpage and deformation, when mounting a solder bump, it is possible to connect with higher accuracy by using a device having a mechanism for forcibly clamping the entire strip substrate 12 and maintaining flatness. it can.

  Thereafter, the solder bumps 7A are heated and reflowed at a temperature of about 235 ± 5 ° C. to adhere to the conductor pattern 4 (4a3), and after forming the bump electrodes 7 as shown in FIG. The bump residue process is completed by removing the flux residue and the like remaining on the surface using a neutral detergent or the like.

  Next, the strip substrate 12 is cut to obtain a plurality of the semiconductor devices 1 shown in FIGS. In order to obtain the semiconductor device 1 from the strip substrate 12, as shown in FIG. 29, the strip substrate 12 is cut from the back surface of the strip substrate 12 by using a dicing blade 20 in the same manner as when the semiconductor wafer is divided into chips 8. .

  Thus, in the present embodiment, it is possible to reduce the unit price of the strip substrate 12 by increasing the number of products acquired per area of the strip substrate 12 on the premise of collective molding. In addition, since the mold 16 does not require a variety of shapes, the initial cost can be reduced. Furthermore, since batch processing can be performed over a plurality of steps, the manufacturing cost of the semiconductor device 1 can be reduced.

  Next, an example of an electronic device having the semiconductor device 1 manufactured in this way is shown in FIGS. FIG. 30 is a plan view of a part of the electronic device 21, and FIG. 31 is a side view thereof.

  The electronic device 21 is a memory card, for example. However, the application example of the semiconductor device 1 of the present embodiment is not limited to the memory card, and can be applied in various ways. For example, the semiconductor device 1 is mounted on a circuit board that constitutes a logic circuit or a general printed wiring board. The present invention can also be applied to a circuit.

  As with the package substrate 2 of the semiconductor device 1, the mounting substrate 22 constituting the electronic device 21 is made of, for example, glass / epoxy resin, and the main surface (package mounting surface) has a plurality of FBGA types. The semiconductor device 1 is mounted via the bump electrodes 7 with the back surface (package mounting surface) facing the main surface (package mounting surface) of the mounting substrate 21. By making the constituent material of the mounting substrate 22 the same as the material of the substrate body 3 of the package substrate 2 of the semiconductor device 1, the difference in thermal expansion coefficient between the semiconductor device 1 and the mounting substrate 22 can be reduced, and the heat caused by the difference can be reduced. Since the generation of stress can be reduced, the mounting reliability of the plurality of semiconductor devices 1 can be improved.

  Here, a memory circuit such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a flash memory (EEPROM: Electric Erasable Programmable Read Only Memory) is formed in each semiconductor device 1. The memory circuit of the semiconductor device 1 is electrically connected to the wiring of the mounting substrate 22 through the bump electrode 7 on the back surface (package mounting surface), thereby forming a memory circuit having a predetermined capacity as a whole on the mounting substrate 22. Has been.

  A TQFP (Thin Quad Flat Package) type semiconductor device 23 is mounted on the main surface of the mounting substrate 22. The semiconductor device 23 is electrically connected to the wiring of the mounting substrate 22 through gull-wing leads protruding from the four side surfaces of the package body. The semiconductor device 1 is incorporated in a memory circuit having a predetermined capacity formed on the mounting substrate 22 and has a function of controlling the operation of the memory circuit. A plurality of external terminals 24 are arranged at one end of the mounting substrate 22 along the side. The external terminal 24 is electrically connected to the wiring on the mounting substrate 22 and has a function of electrically connecting a memory circuit having a predetermined capacity formed on the mounting substrate 22 and an external device. Yes. The total height of the semiconductor devices 1 and 23 is approximately the same.

(Embodiment 2)
In the second embodiment, another example of the method for manufacturing the semiconductor device will be described. 32 and 33 show a state in which the strip substrate 12 is conveyed to the molding die 16. 33 is a cross-sectional view of a plane orthogonal to FIG.

  In the present embodiment, a laminating mechanism 25 is provided in the molding die 16. The laminating mechanism unit 25 includes a laminating film 25a and a winding reel 25b. The laminate film 25a is made of a highly heat-resistant insulating film formed to have a size that almost entirely covers the inner wall surface of the cavity 16c of the upper mold 16b2, and includes a lower mold 16a2 of the molding die 16, an upper mold 16b2, It is interposed between

  In the present embodiment, the lower mold 16a2 of the molding die 16 is not provided with a vacuum suction hole. The other lower mold structure is the same as the lower mold described in the first embodiment. In the present embodiment, a plurality of vacuum suction holes 26 are arranged in the upper mold 16b2. The vacuum suction hole 26 is a hole for adsorbing the laminate film 25a to the cavity 16c side of the upper mold 16b2 in the resin sealing process. The plane position of the vacuum suction hole 26 is the same as that of the vacuum suction hole 17 (see FIGS. 19 to 22) formed in the lower mold 16a of the first embodiment for almost the same reason. That is, the vacuum suction holes 26 are preferably arranged in the peripheral region around the product region of the strip substrate 12. This is for avoiding the possibility that a small protrusion (hole mark) due to the vacuum suction hole 26 may be formed in the sealing resin by vacuum suction during the resin sealing step. However, in the present embodiment, since all the chips 8 on the strip substrate 12 are collectively sealed, the area of the cavity 16c may be large, and vacuum suction is performed so as not to cause wrinkles or the like in the laminate film 25a. There is a need. For example, the vacuum suction hole 26 may be disposed at a position corresponding to the center line (center line) in the width direction of the strip substrate 12. Since this center line corresponds to a cutting area, which will be described later, is a region that will be cut, does it remain in the final semiconductor device 1 even if the hole mark is formed on the line immediately after the sealing process? Moreover, it is because it can be made very small so that the appearance does not deteriorate even if left. From the viewpoint of achieving such an object, the upper die 16b2 may be configured by a multi-hole structure or a porous material, and the upper surface of the laminate film 25a may be vacuumed almost uniformly within the entire surface. In this case, since the entire upper surface of the laminate film 25a can be vacuum-sucked, it is possible to avoid a decrease in yield of the semiconductor device 1 due to the hole trace. Further, the upper die 16b2 is not provided with an ejector pin. This will be described later. The other upper mold structure is the same as the upper mold described in the first embodiment.

  First, as shown in FIG. 34, after the strip substrate 12 is placed on the molding surface of the lower mold 16a2 of the molding die 16 as described above, the temperature of the lower mold 16a2 is set as in the first embodiment. For example, the strip substrate 12 is preheated for about 20 seconds while being set at about 175 ° C., for example. This processing has the purpose of calming the deformation of the strip substrate 12 due to heat.

  In the present embodiment, as described above, the structure of the strip substrate 12 itself has a structure in which the warp caused by thermal stress or the like is unlikely to occur. Therefore, when the strip substrate 12 is mounted on the molding die 16, The warp of the strip substrate 12 generated due to the conductive mechanism can be reduced. As described above, not only the overall flatness of the strip substrate 12 but also the flatness of each individual semiconductor device formation region DA can be ensured.

  Subsequently, as shown in FIG. 35, after the temperatures of the lower die 16a2 and the upper die 16b2 are set to about 175 ° C., for example, the upper surface of the laminate film 25a (the surface facing the upper die 16b2) is formed by the vacuum suction hole 26. By adsorbing, the laminate film 25a is brought into close contact with the upper mold 16b2. In addition, the arrow attached | subjected to the vacuum suction hole 26 after FIG. 35 has shown the direction of vacuum suction.

  Subsequently, as shown in FIG. 36, for example, an epoxy resin and a low molecular resin sealing resin are poured into the cavity 16 c of the upper mold 16 b 2 while maintaining the above temperature and vacuum suction treatment, By integrally sealing the plurality of chips 8 on the main surface, the bonding wires 10 and the like, the integral sealing member 11 including the plurality of chips 8 is molded on the main surface side of the strip substrate 12. Here, as in the first embodiment, since the flatness of the strip substrate 12 is high, level resin sealing is possible. Therefore, the incidence of appearance defects of the semiconductor device 1 can be reduced, and the yield of the semiconductor device 1 can be improved. Note that the arrows in FIG. 36 indicate the direction of vacuum suction.

  Subsequently, as shown in FIG. 37, in the state where the temperature of the lower mold 16a2 is kept as described above, the vacuum suction to the laminate film 25a is stopped, and the tension of the laminate film 25a is used to perform the sealing process. The strip substrate 12 having the sealing member 11 is taken out from the molding die 16. At this time, the laminate film 25a is interposed between the inner wall surface of the cavity 16c of the upper mold 16b2 and the surface of the sealing member 11, and the upper mold 16b2 and the sealing member 11 are not in direct contact with each other. When removing 11 from the cavity 16c, the sealing member 11 can be peeled from the upper die 16b2 with a relatively small force because a force is applied to the surface instead of a point on the surface of the sealing member 11. Therefore, in the present embodiment, there is no need to provide the upper die 16b2 with an ejector pin for taking out the strip substrate 12 after sealing. Therefore, the ejector pin is provided on the strip substrate 12 (sealing member 11) side as an arrangement region of the ejector pin. The area that had been used can be used effectively. Moreover, since the releasability between the sealing member 11 and the upper mold 16b2 can be improved, a larger-sized resin can be sealed. In addition, since the frequency of cleaning inside the mold 16 can be reduced, the manufacturing cost of the semiconductor device 1 can be reduced. Since the subsequent steps are the same as those described in the first embodiment, description thereof will be omitted.

(Embodiment 3)
In the third embodiment, another example of the method for manufacturing the semiconductor device will be described. FIG. 38 shows a state where the strip substrate 12 is conveyed to the molding die 16.

  In the third embodiment, the molding mechanism 16 is provided with the laminating mechanism 25 described in the second embodiment. The structure of the lower mold 16a of the molding die 16 is the same as that described in the first embodiment. That is, a plurality of vacuum suction holes 17 are arranged in the lower mold 16a as in the first embodiment. The upper mold 16b2 is the same as that described in the second embodiment. That is, a plurality of vacuum suction holes 26 are also arranged in the upper die 16b2 in the same manner as in the second embodiment.

  First, as shown in FIG. 39, after the strip substrate 12 is placed on the molding surface of the lower mold 16a of the molding die 16 as described above, the temperature of the lower mold 16a2 is set at about 175 ° C., for example. The strip substrate 12 is preheated for about 20 seconds. This processing has the purpose of calming the deformation of the strip substrate 12 due to heat. Also in the present embodiment, as in the first and second embodiments, the warpage of the strip substrate 12 can be reduced, and the overall flatness of the strip substrate 12 and the individual semiconductor device formation region DA unit. Can be ensured.

  Subsequently, as shown in FIG. 40, the back surface of the strip substrate 12 is adsorbed by the vacuum suction holes 17 in a state where the temperatures of the lower mold 16a and the upper mold 16b2 are set to about 175 ° C., for example. At this time, also in this embodiment, since the strip substrate 12 is extremely thin, the strip substrate 12 can be vacuum-sucked well. As described above, also in this embodiment, the warp caused by the heat treatment can be further reduced by vacuum-sucking the back surface of the strip substrate 12 in the sealing process. For this reason, even if the planar area of the strip substrate 12 becomes larger due to a request for an increase in the number of products to be acquired, or even when the thickness of the strip substrate 12 is further reduced due to a demand for thinness of the semiconductor device, it is caused by the heat treatment. The resin sealing can be performed in a state in which the entire strip substrate 12 and the flatness of each semiconductor device formation area DA are ensured without causing warping or the like. In addition, the arrow attached | subjected to the vacuum suction hole 17 after FIG. 40 has shown the direction of vacuum suction.

  Subsequently, as shown in FIG. 41, while the temperature of the lower mold 16a and the upper mold 16b2 is set to about 175 ° C., for example, and the vacuum suction state in the lower mold 16a is maintained, the upper surface of the laminate film 25a The surface facing the upper mold 16b2 is sucked by the vacuum suction hole 26, and the laminate film 25a is brought into close contact with the upper mold 16b2. In addition, the arrow attached to the vacuum suction hole 26 in FIG. 41 and subsequent figures indicates the direction of vacuum suction.

  Subsequently, as shown in FIG. 42, for example, an epoxy resin and a low molecular resin sealing resin are poured into the cavity 16c of the upper mold 16b2 while maintaining the temperature and the vacuum suction state, and the strip substrate 12 By integrally sealing the plurality of chips 8 on the main surface, the bonding wires 10 and the like, the integral sealing member 11 including the plurality of chips 8 is molded on the main surface side of the strip substrate 12. Here, as in the first embodiment, since the flatness of the strip substrate 12 is high, level resin sealing is possible. Therefore, the incidence of appearance defects of the semiconductor device 1 can be reduced, and the yield of the semiconductor device 1 can be improved.

  Subsequently, as shown in FIG. 43, in the state where the temperature of the lower mold 16a2 is kept as described above, the vacuum suction to the laminate film 25a is stopped and the laminate film 25a is used as in the second embodiment. Then, the strip substrate 12 having the sealing member 11 after the sealing step is taken out from the molding die 16. At this time, for the same reason as in the second embodiment, the sealing member 11 can be peeled from the upper mold 16b2 with a relatively small force. Therefore, also in the present embodiment, since the ejector pins can be eliminated as in the second embodiment, the arrangement area of the ejector pins can be effectively utilized. Further, since the frequency of cleaning inside the molding die 16 can be reduced, the manufacturing cost of the semiconductor device 1 can be reduced. Moreover, in the present embodiment, warpage of the strip substrate 12 due to heat can be suppressed or prevented, and the releasability of the sealing member 11 is improved, so that the strip substrate 12 and the sealing member 11 are increased in size. Since the obstructing factor can be reduced, the strip substrate 12 and the sealing member 11 can be further increased in size. Therefore, an increase in the amount of the semiconductor device 1 that can be obtained from one strip substrate 12 and an increase in the number of chips that can be mounted in the semiconductor device formation region can be expected. For this reason, it becomes possible to further promote cost reduction and performance improvement of the semiconductor device 1. Since the subsequent steps are the same as those described in the first embodiment, description thereof will be omitted.

(Embodiment 4)
In this embodiment, a modified example of the structure of the semiconductor device will be described.

  FIG. 44 shows a cross-sectional view of a semiconductor device 1 according to another embodiment of the present invention. In FIG. 44, the vent hole is eliminated and the chip 8 is fixed by using an adhesive 9 made of a hard paste material or a resin paste of the same quality as the resin sealing material so that it can cope with a high temperature cycle. is there.

  FIG. 45 shows a cross-sectional view of a semiconductor device 1 which is still another embodiment of the present invention. In FIG. 45, in order to make it less susceptible to the thermal shrinkage of the solder resist 5, the temperature resistability is improved by partially removing the solder resist 5.

(Embodiment 5)
In the present embodiment, a modified example of the structure of the strip substrate will be described.

  FIG. 46 shows a plan view of a modification of the strip substrate 12. 46A shows the chip mounting surface of the strip substrate 12, and FIG. 46B shows the package mounting surface on the back surface thereof. In FIG. 46, a part is hatched for easy understanding of the drawing.

  In the present embodiment, a plurality of reinforcing patterns 13 a are arranged along the outer periphery of the strip substrate 12 as in the first embodiment. However, in this embodiment, the reinforcing patterns 13a to 13c (13) are all formed as a solid pattern. Also in this case, similarly to the first embodiment, the mechanical strength of the strip substrate 12 can be ensured, and warpage, distortion, and the like due to heat treatment at the time of manufacturing the semiconductor device 1 can be suppressed, and the flatness thereof is ensured. Therefore, good sealing is possible during the sealing step, and the yield of the semiconductor device 1 can be improved. Further, by arranging the reinforcing pattern 13a in a divided manner, it is possible to disperse and release a relatively strong thermal stress between adjacent semiconductor device areas DA in the strip substrate 12 as in the first embodiment. Therefore, the overall flatness of the strip substrate 12 can be ensured. Further, it is possible to suppress or prevent the afterimage distortion from occurring in the reinforcing pattern 13a. Furthermore, since the flatness for each semiconductor device formation area DA of the strip substrate 12 can be ensured, resin sealing can be performed satisfactorily, and the yield of the semiconductor device 1 can be improved. In addition, since the reinforcing pattern 13a does not exist on the cutting line of the strip substrate 12, it is possible to prevent the occurrence of conductive foreign matter (flash) or the like of the reinforcing pattern 13a when the strip substrate 12 is cut, and to prevent a short circuit failure caused by the foreign matter. Can be prevented.

(Embodiment 6)
In the present embodiment, a modified example of the structure of the strip substrate will be described. FIG. 47 shows a plan view of a modification of the strip substrate 12. 47A shows the chip mounting surface of the strip substrate 12, and FIG. 47B shows the package mounting surface on the back surface thereof. In FIG. 46, a part is hatched for easy understanding of the drawing.

  In the present embodiment, the reinforcing pattern 13d (13) is arranged in the peripheral region near the long side on the main surface and the back surface of the strip substrate 12. In addition, reinforcing patterns 13e (13) are arranged in the peripheral region near the short sides of the main surface and the back surface of the strip substrate 12.

  The reinforcing pattern 13 d is not divided between the semiconductor device formation areas DA, and extends along the longitudinal direction of the strip substrate 12. The reinforcing pattern 13d is formed in a tile pattern as in the first embodiment. However, in this case as well, the structure is not limited to a tile shape as long as the structure can be expanded and contracted, and various modifications can be made. The reinforcing pattern 13e extends along the width direction of the strip substrate 12, and is also formed in a tile shape. These reinforcing patterns 13d and 13e are made of the same conductive material (copper foil or the like) as the reinforcing pattern 13a of the first embodiment.

  According to the present embodiment, as in the first embodiment, the mechanical strength of the strip substrate 12 can be ensured, and the reinforcing pattern 13d can be expanded and contracted during the heat treatment, so that the semiconductor device 1 Since the thermal stress due to the heat treatment during the manufacturing process can be relaxed and the occurrence of afterimage distortion can be suppressed or prevented, the flatness of the strip substrate 12 can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to third, first, third, fifth, and sixth embodiments, one vent hole is arranged at the center of the package substrate (semiconductor device formation region). However, the present invention is not limited to this. A plurality may be provided.

  In the first embodiment, when a plurality of semiconductor chips are collectively sealed with resin, the strip substrate is vacuum-sucked to the lower mold. However, the normal resin sealing is not performed without vacuum suction. You may stop. In this case, since the strip substrate has a structure strong against thermal stress as described above, it is possible to perform resin sealing in a state in which flatness is ensured.

  In the above description, the case where the invention made mainly by the present inventor is applied to the FBGA type semiconductor device, which is the field of use as the background, has been described. However, the present invention is not limited to this. For example, CSP, BGA, LGA The present invention can also be applied to a (Land Grid Array) type semiconductor device and a manufacturing method thereof.

  The present invention can be applied to the semiconductor device manufacturing industry.

1 Semiconductor Device 2 Package Substrate 3 Substrate Body 4 Conductor Pattern 4m Conductor Pattern 5 Solder Resist (Protective Film)
6 Bent hole 7 Bump electrode 8 Semiconductor chip 9 Adhesive 10 Bonding wire 11 Sealing member 12 Strip substrate (first substrate)
13, 13a to 13e Reinforcement pattern 14 Conductive film removal region 15a to 15c Resist removal region 16 Mold 16a, 16a2 Lower die 16b, 16b2 Upper die 16c Cavity 16d Cull block 16e Gate 16f Pot / plunger portion 17 Vacuum suction hole 18 Ejector Pin 19 Tool 20 Dicing blade 21 Electronic device 22 Mounting substrate 23 Semiconductor device 24 External terminal 25 Laminating mechanism 25a Laminating film 25b Reel 26 Vacuum suction hole DA Semiconductor device forming region

Claims (2)

A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a wiring board including an upper surface, a lower surface formed on the opposite side of the upper surface, and a conductor pattern formed on the lower surface;
(B) After the step (a), mounting a semiconductor chip on the upper surface of the wiring substrate and electrically connecting the semiconductor chip to the conductor pattern;
(C) A step of forming a bump electrode on a part of the conductor pattern after the step (b);
here,
In the step (c), the bump electrode is formed on the part of the conductor pattern by placing the solder on the part of the conductor pattern and then heating the solder.
The lower surface of the wiring board is covered with a lower surface side insulating film,
The part of the conductor pattern is exposed from the lower surface side insulating film,
Other parts of the conductor pattern other than the part are covered with the lower surface side insulating film,
The upper surface of the wiring board is covered with an upper surface side insulating film,
The covering state of the upper surface side insulating film is substantially uniform with the covering state of the lower surface side insulating film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the solder is a tin (Sn) -silver (Ag) -based lead-free solder.