JP2014120942A - Encryption circuit protected against side channel attack by differential logic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential logic circuit for achieving power consumption flattening during logical transition, by improving the circuitry of a differential logic circuit for encryption and a control method therefor.SOLUTION: In a differential logic circuit including a flip-flop circuit consisting of a circuit interconnecting the inputs and outputs of two inverter circuits, and an input circuit of NMOS transistor, a transistor is arranged between a power supply potential and the differential logic circuit, a transistor is also arranged between a GND potential and the differential logic circuit, output of the logic circuit is set at a predetermined potential, and a transistor is arranged in order to equalize the node potential in the logic circuit.

Description

The present invention relates to a cryptographic circuit protected from observation attacks. It is especially applied to protect cryptographic circuits from differential power analysis attacks.

The main purpose of cryptography is the secrecy of information by means of encryption and dual operations, ie decryption. Encryption and decryption often implement an encryption algorithm AES (Advanced Encryption Standard) proposed in the 1990s. An encryption circuit using AES is used in a non-contact IC card or the like, and is realized by a logic circuit.

As the roaming capability of the means for communication and information processing increases, new attacks on the AES algorithm are considered. It is a side channel attack called a DPA (Differential Power Analysis) attack in which cryptographic information is leaked by observing the temporal behavior of the energy consumption of the logic circuit constituting the cryptographic circuit.

For side-channel attacks, the difference is based on power consumption, which is a factor of information leakage, that is, concealment by making the current fluctuation constant when data transitions, and masking that makes leakage random and unpredictable. A dynamic logic circuit has been proposed in Non-Patent Document 1 and the like.
For example, K.K. Tiri, M.M. Akmal, and, I.I. Verbauwede, “A dynamic and differential CMOS logic with signal independent power consumption to whistle differential power analysis on smarts.” European Conf. Solid-state Circuits, pp. 403-406, Sept. 2002.

However, the conventional differential logic circuit such as Non-Patent Document 1 has a large current fluctuation at the time of input transition and a large amount of power consumption. Therefore, there is a problem that current is easily detected in a DPA attack and encryption information is easily leaked. is there.

In order to solve these problems, there is an adiabatic differential logic circuit that realizes a circuit configuration for slowly charging using an adiabatic charging method and reduces the maximum current (for example, Non-Patent Documents 2 and 3). ).
M.M. Khatir, and A.K. Moradi, “Secure adiabatic logic: A low-energy DPA-resistive logic style,” Cryptology ePrint Archive, Report 2008/123, 2008. D. -B. Choi. K. E. Kim, K.K. -S. Chung, and D.C. K. Kim. “Symmetric adiabatic logic circuits against differential power analysis.” ETRI Journal, vol. 32, no. 1, pp. 166-168. Feb. 2010.

          The adiabatic differential logic circuits of Non-Patent Documents 2 and 3 reduce the maximum peak current by adiabatic charging, but have a drawback that they are vulnerable to DPA attacks because there are still current fluctuations at the time of input transition.

Therefore, the present invention provides a MOS switch for equalizing current fluctuation at the time of input transition at the node and performs adiabatic switching, thereby reducing power consumption and input compared to a conventional adiabatic differential logic circuit. It is to reduce current fluctuation at the time of transition.

FIG. 1 is a first embodiment of the present invention. This circuit includes a flip-flop circuit composed of an inverter composed of MP2 and MN2 and an inverter composed of MP3 and MN1 and NMOS switches MN5 and MN6 for controlling differential inputs, which are used in a conventional differential logic circuit. And a PMOS switch MP1 for controlling the power supply, an NMOS switch MN8 for controlling the ground signal, and an NMOS switch MN7 for equalizing the equivalent load capacitance of all nodes. In this circuit, low power consumption can be achieved by the Eval signal, and current fluctuation at the time of input signal transition can be made uniform by the Disc signal.

The operation of the circuit is divided into four stages as shown in FIG.

Charge sharing stage: The cycle of the DISCH signal is set to ½ of the period of the input signal (Input), and the input transition is completed at this stage. At this time, the power supply voltage signal (Vpc) is in a low level state, and the input signal (In) applied to the gate of the transistor MN5 (or MN6) is gradually increased (or decreased). . When these voltage changes, the equivalent load capacities of all the nodes are equal, and the current distribution is uniform. At this stage, the output (Output) holds the previous state.

Evaluation stage: At this stage, since the Disc signal is already in the low state, the transistor MP1 is turned on, and the signal of the power supply Vpc is applied to the flip-flop circuit. Therefore, the output rises gradually following Vpc.

Hold stage: During this stage, the Eval signal is slowly present, so that the differential logic circuit is disconnected from the ground signal by the transistor MN8, and the output maintains the previous Eval state.

Recovery stage: At this stage, since the Disc signal is still in the low state, the output is also gradually reduced in accordance with the gentle decrease in the power supply Vpc.

In this circuit, the equivalent load capacity of all nodes is made uniform by the charge sharing stage, and adiabatic switching is realized by the evaluation stage, the hold stage, and the recovery stage to achieve low power consumption.

FIG. 4 shows a second embodiment of the present invention. This circuit controls the power supply to the flip-flop circuit composed of the inverter composed of MP2 and MN2 and the inverter composed of MP3 and MN1 and the NMOS switches MN5 and MN6 for controlling the differential input as in the first embodiment. PMOS switch MP1, NMOS switch MN8 for controlling the ground signal, and NMOS switch MN7 for equalizing the equivalent load capacitance of all nodes. Further, by adding the transistors MN3 and MN4 for controlling the Cx signal, the equivalent load capacities at all nodes can be further averaged. By setting the input waveform of the circuit of the second aspect to FIG. 4, the output waveform Output of FIG. 4 can be obtained.

FIG. 5 is an RC equivalent circuit of the conventional adiabatic differential logic circuit group for encryption (2N-2N2P, ECRL, SAL, and SyAL) and the circuit of the present invention (CSSAL). This figure shows the distribution of the equivalent additional capacitance at the nodes when the transistor is transitioning. If the additional capacitance is uniform at all the nodes, the current distribution is uniform and the current fluctuation is small. It means that. From the figure, it can be seen that in the circuit of the present invention, RC circuits are uniformly distributed at all nodes.

FIG. 6 shows a state of circuit simulation of current fluctuations in a conventional adiabatic differential logic circuit group for encryption and the circuit of the present invention. The process used for the simulation is a 0.18 μm standard CMOS process. From the figure, it can be seen that the circuit of the present invention has a current peak value lower than that of the conventional circuit and less fluctuation in current.

According to the present invention, the power consumption at the time of calculation can be made constant regardless of the transition, compared with the conventional adiabatic secure differential logic circuit.

The present invention achieves low power consumption by adiabatically charging and discharging the circuit shown in FIG. 1, and uniformizing the node load capacity in the circuit, thereby uniformly changing the power consumption at the time of transition. Can be achieved.

          The present invention is an adiabatic differential logic circuit for encryption itself, and has no other use.

1 is a first embodiment of the present invention. It is an example of the input-output waveform of the 1st aspect of this invention. It is a 2nd aspect of this invention. It is an example of the input-output waveform of the 2nd aspect of this invention. It is RC equivalent circuit of the conventional differential logic circuit and the differential logic circuit of this invention. It is a mode of the change of the power supply current at the time of input transition of the conventional differential logic circuit and the differential logic circuit of the present invention.

Claims (3)

In a flip-flop circuit configured by a circuit in which the input and output of two inverter circuits are interconnected, and a differential logic circuit having an NMOS transistor as an input circuit,
A transistor is disposed between a power supply potential and the differential logic circuit, and a transistor is disposed between a GND potential and the differential logic circuit, and the output of the logic circuit is set to a predetermined potential.
In order to make the node potential in the logic circuit uniform, the transistor is arranged.
A differential logic circuit characterized by that. In the differential logic circuit according to claim 1,
Adiabatic operation during logical transition,
A differential logic circuit characterized by that. The differential logic circuit according to claim 1,
Equalize the equivalent load capacity at all nodes at the time of logic transition,
A differential logic circuit characterized by that.