JP2014107333A - Nitride semiconductor template, nitride semiconductor template manufacturing method and light-emitting element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit the occurrence of surface defects while improving crystallinity.SOLUTION: A nitride semiconductor template comprises: a substrate having a plurality of salient rows in each of which a plurality of salients are arranged in a row at predetermined intervals; and a group III nitride semiconductor layer arranged on the substrate on the surface where the salients rows are arranged, in which the plurality of salient rows includes a first salient row in which adjacent salients are arranged at first intervals and a second salient row in which adjacent salients are arranged at second intervals different from the first intervals.

Description

  The present invention relates to a nitride semiconductor template, a method for manufacturing a nitride semiconductor template, and a method for manufacturing a light emitting device.

  For example, a semiconductor light emitting device such as a light emitting diode (LED) (hereinafter also simply referred to as “light emitting device”) includes a nitride semiconductor template including a substrate containing, for example, sapphire. The light emitting element forms a light emitting portion by sequentially growing an n type semiconductor layer such as a gallium nitride (GaN) layer, a light emitting layer, and a p type semiconductor layer on the surface of the nitride semiconductor template, and forms an n type semiconductor layer. The p-type semiconductor layer is formed by forming an external extraction electrode. In such a light emitting element, it is an important issue how efficiently light generated in the light emitting layer can be extracted. That is, it is important to improve the light extraction efficiency (light emission output) of the light emitting element.

  In view of this, a technique for performing uneven processing on a substrate included in a nitride semiconductor template is disclosed. For example, there is disclosed a technique for performing uneven processing on the surface of a substrate such as a crystal substrate as a first layer or a so-called PSS (Patterned Sapphire Substrate) (see, for example, Patent Document 1 and Patent Document 2). Thereby, light confinement inside the light emitting element can be reduced. Therefore, the light extraction efficiency of the light emitting element can be improved, and the luminance of the light emitting element can be increased.

JP 2002-280611 A JP 2011-91374 A

  However, the characteristics of the nitride semiconductor template, that is, the crystallinity of the nitride semiconductor template changes depending on the spacing between adjacent convex portions formed on the surface of the above-described crystal substrate or PSS substrate. The crystallinity of the nitride semiconductor template greatly affects the characteristics of the light emitting element. When the characteristics of the nitride semiconductor template change, the characteristics of the light emitting element change. The index of crystallinity is the half width (FWHM) of the maximum diffraction peak of the (0004) plane measured by X-ray diffraction (XRD). That is, when the interval between the convex portions on the substrate is changed, the half width of the (0004) plane of the nitride semiconductor template is changed.

  Specifically, when the interval between the convex portions of the substrate is narrowed, the half width of the (0004) plane of the nitride semiconductor template tends to be widened. That is, when the interval between the convex portions of the substrate becomes narrow, many crystal defects are generated in the nitride semiconductor template, and the crystallinity of the nitride semiconductor template tends to be lowered. A light emitting device using such a nitride semiconductor template may not be able to improve light extraction efficiency because the internal quantum efficiency decreases.

  On the other hand, when the distance between the convex portions of the substrate is increased, the half width of the (0004) plane of the nitride semiconductor template tends to be reduced. That is, the crystallinity of the nitride semiconductor template tends to be good. However, surface defects such as pits may occur on the surface of the nitride semiconductor template. A light-emitting element using a substrate with a surface defect may have a low light extraction efficiency or a low reverse voltage or ESD (Electro-Static Discharge), which is one of the causes of light-emitting element failures. There was a case. In addition, even if the initial failure of the light emitting element does not occur, there is a possibility that the possibility of a problem in reliability becomes very large.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a nitride semiconductor template, a method for manufacturing a nitride semiconductor template, and a method for manufacturing a light emitting element that can suppress the occurrence of surface defects while solving the above-described problems and improving crystallinity. And

In order to solve the above problems, the present invention is configured as follows.
According to the first aspect of the present invention, a substrate having a plurality of convex portions arranged by arranging a plurality of convex portions in a row at a predetermined interval, and a surface of the substrate on which the convex portions are provided. A group III nitride semiconductor layer provided thereon, and a plurality of the convex part rows, the first convex part row in which the adjacent convex parts are arranged at a first interval, and the adjacent convex part There is provided a nitride semiconductor template comprising a second row of convex portions arranged at a second interval different from the first interval.

  According to the second aspect of the present invention, the first interval or the plurality of convex portions constituting the first convex portion row and the plurality of convex portions constituting the second convex portion row The nitride according to the first aspect, in which the first convex row and the second convex row are arranged so that a regular hexagon having one side of the shorter one of the second intervals is formed. A semiconductor template is provided.

  According to the third aspect of the present invention, the first interval and the second interval are each 5 μm or less, and the thickness of the group III nitride semiconductor layer is 4 μm or more and 10 μm or less. Alternatively, a nitride semiconductor template of the second aspect is provided.

  According to a fourth aspect of the present invention, the group III nitride semiconductor layer includes a first nitride semiconductor layer and a second nitride semiconductor layer, and the first nitride semiconductor layer and the second nitride semiconductor layer are provided. Each of the semiconductor semiconductor layers contains different additives, or one of the first nitride semiconductor layer and the second nitride semiconductor layer contains an additive, and the other is added. The nitride semiconductor template according to any one of the first to third aspects, which does not contain an object.

  According to a fifth aspect of the present invention, there is provided the nitride semiconductor template according to any one of the first to fourth aspects, wherein the surface resistivity of the group III nitride semiconductor layer is 10Ω / □ or more and 25Ω / □ or less. Is done.

  According to the sixth aspect of the present invention, in the group III nitride semiconductor layer, the half width of the maximum diffraction peak of the (0004) plane measured by X-ray diffraction is from 50 seconds to 100 seconds. A nitride semiconductor template according to any of the fifth aspects is provided.

  According to a seventh aspect of the present invention, there is provided the nitride semiconductor template according to any one of the first to sixth aspects, wherein the group III nitride semiconductor layer is mainly composed of GaN.

  According to an eighth aspect of the present invention, the nitriding according to any one of the first to seventh aspects, wherein an AlN layer as a buffer layer is provided between the substrate and the group III nitride semiconductor layer. A semiconductor template is provided.

  According to a ninth aspect of the present invention, there is provided the nitride semiconductor template according to the eighth aspect, wherein the buffer layer has a thickness of 10 nm to 100 nm.

  According to a tenth aspect of the present invention, there is provided the nitride semiconductor template according to any one of the first to ninth aspects, wherein the convex portion has any one of a pyramid shape, a conical shape, and a hemispherical shape.

  According to an eleventh aspect of the present invention, there is provided the nitride semiconductor template according to any one of the first to tenth aspects, wherein the height of the convex portion is not less than 0.5 μm and not more than 3.0 μm.

  According to the twelfth aspect of the present invention, the first convex portion row in which the adjacent convex portions are arranged at the first interval, and the adjacent convex portion at the second interval different from the first interval. A step of forming the plurality of protrusions on the substrate so as to form a second protrusion row arranged; and a group III nitride semiconductor layer on the substrate provided with the plurality of protrusions There is provided a method of manufacturing a nitride semiconductor template having a step of growing and forming a layer by hydride vapor phase epitaxy.

  According to a thirteenth aspect of the present invention, a step of forming a light emitting unit comprising an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the nitride semiconductor template of any one of the first to twelfth aspects; Forming an exposed region for exposing the nitride semiconductor template in the light emitting portion, and forming a first electrode on the surface of the light emitting portion and forming a second electrode in the exposed region. A method for manufacturing a light-emitting element is provided.

  According to the nitride semiconductor template, the method for manufacturing a nitride semiconductor template, and the method for manufacturing a light emitting device according to the present invention, it is possible to suppress the occurrence of surface defects while improving the crystallinity.

It is a section schematic diagram of the nitride semiconductor template concerning one embodiment of the present invention. It is a schematic block diagram of the board | substrate with which the nitride semiconductor template which concerns on one Embodiment of this invention is provided, (a) shows the top view of a board | substrate, (b) shows the longitudinal cross-sectional schematic diagram of a board | substrate, (c) is The upper surface partial enlarged view of a board | substrate is shown. It is a graph which shows the appropriate film thickness value of a buffer layer. It is a schematic block diagram of the hydride vapor phase growth apparatus used suitably by one Embodiment of this invention. It is a section schematic diagram of a light emitting element concerning one embodiment of the present invention. It is a cross-sectional schematic diagram of the epitaxial wafer for light emitting elements which forms the light emitting element which concerns on one Example of this invention. It is the upper surface partial enlarged view of the board | substrate with which the nitride semiconductor template which concerns on the comparative example of this invention is provided.

  Hereinafter, a nitride semiconductor template and a semiconductor light emitting element (semiconductor light emitting device) using the nitride semiconductor template according to an embodiment of the present invention will be described.

(1) Nitride Semiconductor Template First, the nitride semiconductor template according to the present embodiment will be described with reference mainly to FIGS. FIG. 1 is a schematic cross-sectional view of a nitride semiconductor template according to this embodiment. FIG. 2 is a schematic configuration diagram of a substrate included in the nitride semiconductor template according to the present embodiment.

  As shown in FIG. 1, the nitride semiconductor template 10 according to the present embodiment is configured by growing a buffer layer 12 and a group III nitride semiconductor layer 13 on a substrate 11.

  The substrate 11 is not particularly limited as long as it is made of a material that can be formed by growing the group III nitride semiconductor layer 13 on the substrate 11. For example, a sapphire substrate such as PSS (Patterned Sapphire Substrate) may be used. Note that PSS is a substrate in which a minute uneven structure is formed on the surface of a sapphire substrate by etching treatment (plasma treatment). For example, as shown in FIG. 2A, the substrate 11 is formed in a substantially circular shape when viewed from above. In addition, the board | substrate 11 may be shape | molded, for example in shapes, such as a substantially rectangular shape, when it is a top view.

  As shown in FIG. 2B, a plurality of convex portions 14 are provided on one surface of the substrate 11, that is, the surface with which the buffer layer 12 is in contact. The convex portion 14 is formed in a hemispherical shape, for example, as shown in FIG. Further, as shown in FIG. 2C, the convex portions 14 are provided in a row at a predetermined interval on the substrate 11 to form a convex portion row 15. The substrate 11 is provided with a plurality of convex portion rows 15. The plurality of convex portion rows 15 includes a first convex portion row 17 in which adjacent convex portions 14 are arranged at a first interval d1, and a second interval d2 in which adjacent convex portions 14 are different from the first interval d1. 2nd convex part row | line | column 18 distribute | arranged.

  Thereby, generation | occurrence | production of the surface defect of the nitride semiconductor template 10 can be suppressed, improving the crystallinity of the nitride semiconductor template 10. FIG. Therefore, as described later, when the light emitting element 50 such as a blue light emitting diode (blue LED) is formed using the nitride semiconductor template 10, the light extraction efficiency of the light emitting element 50 can be improved.

  For example, as shown in FIG. 2C, a plurality of convex portions 14 constituting the first convex portion row 17 and a plurality of convex portions 14 constituting the second convex portion row 18 have a first interval d1 or The first convex row 17 and the second convex portion are formed such that a regular hexagon having one side of the shorter interval (the first interval d1 in the present embodiment) of the second intervals d2 is formed. Each of the rows 18 may be arranged on the substrate 11. That is, the convex portion 14 has a parallelogram formed by one regular hexagon and two regular triangles formed on two opposite sides of the regular hexagon, as shown by a one-dot chain line in FIG. It is good to be formed on the board | substrate 11 so that it may be repeated synchronously. Thereby, generation | occurrence | production of the surface defect of the nitride semiconductor template 10 can be suppressed more, improving the crystallinity of the nitride semiconductor template 10 more.

  The first interval d1 and the second interval d2 are each 5 μm or less, preferably 0.5 μm or more and 5.0 μm or less. If the distance between adjacent convex portions 14 and 14 constituting the first convex portion row 17 and the second convex portion row 18 is too narrow, it may be difficult to improve the crystallinity of the nitride semiconductor template 10. This is because when the group III nitride semiconductor layer 13 is grown on the substrate 11, island-like growth in the initial stage of growth is reduced, and the group III nitride semiconductor layer 13 is quickly flattened. Further, if the spacing between the convex portions 14 and 14 exceeds 5 μm, the crystallinity of the nitride semiconductor template 10 can be improved, but surface defects are likely to occur in the nitride semiconductor template 10.

  The height h of the convex portion 14 is 0.5 μm or more and 3.0 μm or less, preferably 0.5 μm or more and 2.0 μm or less. When the height h of the convex portion 14 is less than 0.5 μm, the height of the concave portion formed in the group III nitride semiconductor layer 13 is reduced due to the convex portion 14 of the substrate 11. For this reason, when the group III nitride semiconductor layer 13 is grown on the substrate 11, island-like growth in the initial stage of growth is reduced, and the group III nitride semiconductor layer 13 is quickly flattened. For this reason, it may be difficult to improve the crystallinity of the nitride semiconductor template 10. When the height h of the convex portion 14 exceeds 3.0 μm, the group III nitride semiconductor layer 13 becomes slow to be flat when the group III nitride semiconductor layer 13 is grown on the substrate 11. Therefore, surface defects such as pits are likely to occur on the surface of the group III nitride semiconductor layer 13. In order to suppress the occurrence of surface defects, it is necessary to increase the thickness of the group III nitride semiconductor layer 13.

  As shown in FIG. 1, for example, an aluminum nitride (AlN) layer is provided as the buffer layer 12 on the surface of the substrate 11 provided with the protrusions 14. The constituent material of the buffer layer 12 is appropriately selected according to the purpose and application. The thickness of the buffer layer 12 is preferably 10 nm or more and 100 nm or less. Since the number of crystal defects in the buffer layer 12 varies depending on the thickness of the buffer layer 12, the thickness of the buffer layer 12 has an appropriate value. That is, as shown in FIG. 3, if the buffer layer 12 is too thick or too thin, the half-value width (FWHM) of the diffraction peak value by X-ray diffraction becomes wide. As a result, the crystallinity of the nitride semiconductor template 10 may be reduced.

  A group III nitride semiconductor layer 13 mainly composed of gallium nitride (GaN) is provided on the buffer layer 12. That is, a group III nitride semiconductor layer 13 such as gallium nitride (GaN), indium gallium nitride (InGaN), or gallium aluminum nitride (AlGaN) is provided on the buffer layer 12.

  Irregularities corresponding to the irregularities formed on the substrate 11 are formed on the surface of the group III nitride semiconductor layer 13 on the substrate 11 side. Thereby, the crystallinity of the group III nitride semiconductor layer 13 is controlled. Therefore, the crystallinity of nitride semiconductor template 10 can be improved.

  Thus, in the group III nitride semiconductor layer 13 in which the unevenness corresponding to the unevenness formed in the substrate 11 is formed, the half-value width of the maximum diffraction peak on the (0004) plane (XRD) measured by X-ray diffraction (XRD) ( FWHM) is 50 seconds or more and 100 seconds or less. That is, the crystallinity of the nitride semiconductor template 10 can be improved. Therefore, the light extraction efficiency of the light emitting element 50 formed using the nitride semiconductor template 10 is improved. If the FWHM is less than 50 seconds, the crystallinity of the nitride semiconductor template 10 can be improved, but surface defects may occur in the nitride semiconductor template 10. Moreover, when FWHM exceeds 100 seconds, the crystallinity of the nitride semiconductor template 10 may fall.

  The group III nitride semiconductor layer 13 includes a first nitride semiconductor layer 20 and a second nitride semiconductor layer 21 in order from the substrate 11 side. The first nitride semiconductor layer 20 and the second nitride semiconductor layer are additive layers containing a predetermined concentration of impurities (impurities). The first nitride semiconductor layer 20 and the second nitride semiconductor layer 21 each contain different additives. Alternatively, any one of the first nitride semiconductor layer 20 and the second nitride semiconductor layer 21 is an additive layer containing a predetermined additive, and the other is an undoped layer containing no additive. Also good. In addition, as an additive contained in the first nitride semiconductor layer 20 and the second nitride semiconductor layer 21, for example, silicon (Si), magnesium (Mg), or the like can be used.

  The thickness of group III nitride semiconductor layer 13 (that is, the total thickness of first nitride semiconductor layer 20 and second nitride semiconductor layer 21) is preferably 4 μm or more and 10 μm or less. Further, considering reproducibility and the like, the thickness of the group III nitride semiconductor layer 13 is preferably 5 μm or more and 9 μm or less. Thereby, generation | occurrence | production of a surface defect can be suppressed more, improving the crystallinity of the nitride semiconductor template 10 more.

  When the thickness of the group III nitride semiconductor layer 13 is less than 4 μm, the crystallinity of the group III nitride semiconductor layer 13 may be lowered. That is, since the nitride semiconductor template 10 is a portion where current flows in the lateral direction, it needs to have low resistance. For this reason, when the thickness of the group III nitride semiconductor layer 13 is less than 4 μm, it is necessary to add (dope) a high concentration additive or increase the amount of the additive to be added in order to reduce the resistance. Arise. That is, the carrier concentration of the group III nitride semiconductor layer 13 may need to be increased. As a result, the FWHM may exceed 100 seconds, and the crystallinity of the group III nitride semiconductor layer 13 may decrease. When the resistance of the group III nitride semiconductor layer 13 is not reduced, the crystallinity can be improved even if the thickness of the group III nitride semiconductor layer 13 is less than 4 μm. However, for example, when the light emitting element 50 such as a light emitting diode (LED) is formed using the nitride semiconductor template 10 including the group III nitride semiconductor layer 13 that is not low resistance, it is one of the characteristics of the light emitting element 50. The drive voltage (forward voltage (Vf)) may increase. That is, the nitride semiconductor template 10 including the group III nitride semiconductor layer 13 that is not low resistance may not be used for the light emitting element 50.

  When the thickness of the group III nitride semiconductor layer 13 exceeds 10 μm, the FWHM can be reduced to 100 seconds or less, and the crystallinity of the group III nitride semiconductor layer 13 can be improved. Further, the resistance can be reduced without increasing the carrier concentration of the group III nitride semiconductor layer 13. Therefore, when the light emitting element 50 is formed using the nitride semiconductor template 10 including the group III nitride semiconductor layer 13 having a film thickness exceeding 10 μm, an increase in the forward voltage can be suppressed. However, the substrate 11 and the group III nitride semiconductor layer 13 are formed of different materials. For this reason, if the thickness of the group III nitride semiconductor layer 13 exceeds 10 μm, the nitride semiconductor template 10 may be greatly warped. When the light emitting element 50 is formed using the nitride semiconductor template 10 in which such a warp has occurred, there may be a problem in the growth of the light emitting layer 52 as a light emitting portion grown on the nitride semiconductor template 10. As a result, the light emission output of the light emitting element 50 may decrease, that is, the light extraction efficiency may decrease. Further, for example, when the light emitting layer 52 is formed with an InGaN / GaN multiple quantum well structure, the light emitting element 50 using the nitride semiconductor template 10 in which the warp has occurred is affected by the warp. The concentration of indium (In) contained may be non-uniform in the plane. Therefore, the in-plane distribution of the emission wavelength of the light emitting element 50 may deteriorate, and the yield may decrease. Further, since the thickness of the group III nitride semiconductor layer 13 is increased, the manufacturing cost may be increased.

  The group III nitride semiconductor layer 13 (nitride semiconductor template 10) preferably has a surface specific resistance of 10Ω / □ or more and 25Ω / □ or less. Thereby, generation | occurrence | production of a surface defect can be suppressed, improving the crystallinity of the nitride semiconductor template 10. FIG. The surface specific resistance of the group III nitride semiconductor layer 13 is preferably low, but in order to reduce the surface resistivity, the film thickness of the group III nitride semiconductor layer 13 is increased or the carrier concentration of the group III nitride semiconductor layer 13 is increased. Therefore, the crystallinity of the nitride semiconductor template 10 may be reduced or surface defects may occur.

  The group III nitride semiconductor layer 13 is formed by growing on the substrate 11 by a vapor phase growth method. Examples of the vapor phase growth method include a hydride vapor phase epitaxy (HVPE), a metal-organic vapor phase epitaxy (MOVPE), and a molecular beam epitaxy (MBE). Various methods such as these can be used. In particular, since the HVPE method has a high growth rate for growing crystals on the substrate 11, when the HVPE method is used, the manufacturing time of the nitride semiconductor template 10 can be shortened. Therefore, the manufacturing cost can be reduced.

  Here, a hydride vapor phase epitaxy apparatus (HVPE apparatus) 30 for growing a group III nitride semiconductor layer 13 on the substrate 11 will be described with reference to FIG. FIG. 4 shows a schematic configuration diagram of the HVPE apparatus 30.

  As shown in FIG. 4, the HVPE apparatus 30 includes a reaction furnace 31 made of, for example, quartz. A first heater 32 and a second heater 33 for heating the inside of the reaction furnace 31 are provided on the outer periphery of the reaction furnace 31. The region in the reaction furnace 31 that is mainly heated by the first heater 32 functions as the raw material portion 34, and the region in the reaction furnace 31 that is mainly heated by the second heater 33 functions as the growth portion 35. The raw material section 34 is a space that is heated to, for example, 600 ° C. to 900 ° C. by the first heater 32 and generates a group III source gas by reacting a reaction gas described later with Ga or Al. The growth section 35 is heated to, for example, about 1100 ° C. by the second heater 33 and is supplied into the reaction furnace 31 from a first group III source gas supply pipe 40 or a second group III source gas supply pipe 41 described later. The group III source gas is reacted with the group V source gas supplied into the reaction furnace 31 from a group V source gas supply pipe 39 to be described later, and a GaN layer which is a group III nitride semiconductor layer 13 on the substrate 11 It is a space to grow.

  The growth unit 35 in the reaction furnace 31 is provided with a susceptor 36 as a substrate support unit that supports the substrate 11 in the reaction furnace 31. The substrate 11 is supported on the susceptor 36 such that the growth surface faces the gas supply port. The susceptor 36 is made of, for example, carbon, and the surface is covered with silicon carbide (SiC). The susceptor 36 is provided with a rotating shaft 37 made of, for example, high-purity quartz. By rotating the rotary shaft 37, the susceptor 36 is rotated at a predetermined speed (for example, 3r / min to 100r / min), that is, the substrate 11 is rotated.

  A doping gas supply pipe 38, a group V source gas supply pipe 39, a first group III source gas supply pipe 40, and a second group III source gas supply pipe 41 are connected to the reaction furnace 31, respectively. The doping gas supply pipe 38, the group V source gas supply pipe 39, the first group III source gas supply pipe 40, and the second group III source gas supply pipe 41 are each preferably formed of, for example, high-purity quartz. .

A doping gas supply source is connected to the doping gas supply pipe 38. From the doping gas supply pipe 38, dichlorosilane (SiH ₂ Cl) diluted to a predetermined concentration (for example, 100 ppm) with, for example, nitrogen (N ₂ ) gas, argon (Ar) gas, hydrogen (H ₂ ) gas, or the like as a doping gas. ₂ ) Gas is supplied to the growth section 35 in the reaction furnace 31. In addition to this, for example, SiHCl ₃ gas, SiH ₃ Cl gas, SiCl ₄ gas, or a gas obtained by diluting a mixed gas thereof with N ₂ gas or Ar gas may be used as the doping gas.

In addition, from the doping gas supply pipe 38, for example, H ₂ gas, N ₂ gas, or a mixed gas thereof as a carrier gas may be supplied along with the doping gas. Further, when no additive is added (doping), for example, H ₂ gas, N ₂ gas, or a mixed gas of H ₂ gas and N ₂ gas is introduced into the reaction furnace 31 from the doping gas supply pipe 38. You may supply. Further, from the doping gas supply pipe 38, after the group III nitride semiconductor layer 13 is grown on the substrate 11, as a cleaning gas for removing deposits and the like attached in the reaction furnace 31, for example, HCl gas or H _Two gases, N ₂ gas, or the like may be supplied into the reaction furnace 31.

A V group source gas supply source is connected to the V group source gas supply pipe 39. From the group V source gas supply pipe 39, for example, ammonia (NH ₃ ) gas or the like is supplied as a group V source gas to the growth section 35 in the reaction furnace 31.

From the group V source gas supply pipe 39, for example, hydrogen (H ₂ ) gas, N ₂ gas, or a mixed gas thereof as a carrier gas may be supplied in parallel with the group V source gas. Note that only the carrier gas may be supplied into the reaction furnace 31 from the group V source gas supply pipe 39.

  The first group III source gas supply pipe 40 is connected to a Ga solution tank 42 in which a Ga solution (Ga melt) is stored and a reactive gas supply source. The Ga solution tank 42 is provided in the raw material part 34 in the reaction furnace 31 described later. The Ga solution tank 42 may be made of, for example, high-purity quartz. First, for example, hydrogen chloride (HCl) gas is supplied as a reaction gas from the first group III source gas supply pipe 40 into the Ga solution tank 42. By supplying the reaction gas into the Ga solution tank 42, GaCl gas, which is a group III source gas, is generated. Then, GaCl gas is supplied from the first group III source gas supply pipe 40 to the growth section 35 in the reaction furnace 31.

From the first group III source gas supply pipe 40, for example, H ₂ gas, N ₂ gas, or a mixed gas thereof may be supplied as a carrier gas in parallel with the group III source gas.

  An Al solution tank 43 in which an Al solution (Al melt) is stored and a reaction gas supply source are connected to the second group III source gas supply pipe 41. The Al solution tank 43 is provided in the raw material section 34 in the reaction furnace 31 described later. The Al solution tank 43 is preferably made of, for example, high-purity quartz. From the second group III source gas supply pipe 41, first, for example, HCl gas is supplied as a reaction gas into the Al solution tank 43. By supplying the reaction gas into the Al solution tank 43, AlCl gas that is a group III source gas is generated. Then, AlCl gas is supplied from the first group III source gas supply pipe 40 to the growth section 35 in the reaction furnace 31.

For example, hydrogen (H ₂ ) gas, N ₂ gas, or a mixed gas thereof as a carrier gas may be supplied from the second group III source gas supply pipe 41 along with the group III source gas. Good.

  An exhaust pipe 44 is connected to the reaction furnace 31. The exhaust pipe 44 is configured to discharge the gas in the reaction furnace 31 to the outside of the reaction furnace 31.

  By using such an HVPE apparatus 30, the group III nitride semiconductor layer 13 can be formed on the substrate 11 by hydride vapor phase growth. Further, the growth rate of the group III nitride semiconductor layer 13 can be increased to 60 μm / hr or more, preferably about 300 μm / hr.

(2) Method for Manufacturing Nitride Semiconductor Template Next, a method for manufacturing the above-described nitride semiconductor template 10 according to an embodiment of the present invention will be described.

(Unevenness forming process)
In the method for manufacturing the nitride semiconductor template 10 according to the present embodiment, first, a sapphire substrate such as PSS is prepared. And the uneven | corrugated process is given to the board | substrate 11, and the predetermined convex part 14 is formed in the surface in which the buffer layer 12 of the board | substrate 11 is provided. That is, a plurality of convex portions 14 are formed on the substrate 11, the first convex row 17 in which the convex portions 14 adjacent on the substrate 11 are arranged at the first interval d <b> 1, and the adjacent convex portions 14 are the first. 2nd convex part row | line | column 18 distribute | arranged by the 2nd space | interval d2 different from the space | interval d1 of this is formed.

(Substrate loading process)
The substrate 11 on which the convex portions are formed is carried into the reaction furnace 31 and placed (loaded) on the susceptor 36.

(Buffer layer forming step)
An AlN layer having a predetermined thickness (for example, 10 nm or more and 100 nm or less) is grown and formed as the buffer layer 12 on the surface of the substrate 11 on which the unevenness is formed, using, for example, the HVPE apparatus 30 shown in FIG. That is, the substrate 11 is heated to a predetermined temperature (for example, 1100 ° C.) by the second heater 33, and the raw material portion 34 of the reaction furnace 31 is heated by the first heater 32.

When the substrate 11 reaches a predetermined temperature and the raw material portion 34 of the reaction furnace 31 reaches a predetermined temperature, HCl, which is a reactive gas, is exhausted from the exhaust pipe 44 into the second group III source gas supply pipe 41. Gas supply is started, HCl gas is supplied into the Al solution tank 43, and generation of AlCl gas is started. Then, AlCl gas is supplied into the reaction furnace 31 from the second group III source gas supply pipe 41. At this time, for example, H ₂ gas or N ₂ gas may be supplied as a carrier gas to the second group III source gas supply pipe 41. In parallel with the supply of the AlCl gas into the reaction furnace 31, NH ₃ gas is supplied into the reaction furnace 31 as a group V source gas from the group V source gas supply pipe 39. At this time, for example, H ₂ gas may be supplied as a carrier gas to the group V source gas supply pipe 39. Then, an AlCl gas that is a group III source gas and an NH ₃ gas that is a group V source gas are reacted in the growth part 35 in the reaction furnace 31 to buffer a predetermined thickness (for example, 20 nm) on the substrate 11. An AlN layer as the layer 12 is grown and formed. When the thickness of the AlN layer reaches a predetermined thickness, the supply of AlCl gas and NH ₃ gas into the reaction furnace 31 is stopped.

(Group III nitride semiconductor layer formation process)
Next, a group III nitride semiconductor layer 13 having a predetermined thickness (for example, 4 μm or more and 10 μm or less) is formed on the AlN layer as the buffer layer 12. That is, first, the first nitride semiconductor layer 20 is formed on the AlN layer. For example, using the HVPE apparatus 30 shown in FIG. 4, the supply of HCl gas, which is a reaction gas, is started into the first group III source gas supply pipe 40 while exhausting from the exhaust pipe 44, and HCl is introduced into the Ga solution tank 42. The gas is supplied, and the generation of GaCl gas, which is a group III source gas, is started. Then, GaCl gas is supplied into the reaction furnace 31 from the first group III source gas supply pipe 40. At this time, for example, H ₂ gas or N ₂ gas may be supplied as a carrier gas to the first group III source gas supply pipe 40. In parallel with the supply of GaCl gas into the reaction furnace 31, NH ₃ gas as a group V source gas is supplied into the reaction furnace 31 from the group V source gas supply pipe 39. At this time, for example, H ₂ gas may be supplied as a carrier gas to the group V source gas supply pipe 39. Then, a GaCl gas that is a group III source gas and an NH ₃ gas that is a group V source gas are reacted in the growth part 35 in the reaction furnace 31 to form a first nitride semiconductor layer 20 on the substrate 11. A GaN layer having a predetermined thickness (for example, 20 nm) which is an undoped layer to which no additive is added (dope) is grown and formed. When the thickness of the GaN layer reaches a predetermined thickness, the supply of GaCl gas and NH ₃ gas into the reaction furnace 31 is stopped.

Next, the second nitride semiconductor layer 21 is grown and formed on the first nitride semiconductor layer 20. That is, for example, using the HVPE apparatus 30 shown in FIG. 4, the supply of HCl gas, which is a reaction gas, is started into the first group III source gas supply pipe 40 while exhausting from the exhaust pipe 44. HCl gas is supplied to the substrate and generation of GaCl gas, which is a group III source gas, is started. Then, GaCl gas is supplied into the reaction furnace 31 from the first group III source gas supply pipe 40. At this time, for example, H ₂ gas or N ₂ gas may be supplied as a carrier gas to the first group III source gas supply pipe 40. In parallel with the supply of GaCl gas into the reaction furnace 31, NH ₃ gas as a group V source gas is supplied into the reaction furnace 31 from the group V source gas supply pipe 39. At this time, for example, H ₂ gas may be supplied as a carrier gas to the group V source gas supply pipe 39. Further, in parallel with the supply of GaCl gas and the supply of NH ₃ gas into the reaction furnace 31, for example, SiH ₂ Cl ₂ gas is supplied as nitrogen (N ₂ ) gas or argon (Ar) from the doping gas supply pipe 38 as a doping gas. ) Start supplying gas diluted with gas. Then, Si is added (doping) as an impurity while reacting the GaCl gas, which is a group III source gas, and the NH ₃ gas, which is a group V source gas, in the growth section 35 in the reaction furnace 31. Then, a GaN layer having a predetermined thickness (for example, 20 nm), which is a doped layer doped with Si, is formed on the substrate 11 as the second nitride semiconductor layer 21 by growth. When the thickness of the GaN layer reaches a predetermined thickness, the supply of GaCl gas, NH ₃ gas, and doping gas into the reaction furnace 31 is stopped.

(Purge process)
After stopping the supply of GaCl gas, NH ₃ gas, and doping gas into the reaction furnace 31, a group V source gas supply pipe 39, a first group III source gas supply pipe 40, and a second group III source gas supply pipe The supply of an inert gas such as N ₂ gas is started from at least one of 41. Thereby, the inside of the reaction furnace 31 is purged with N ₂ gas, and residual gas and reaction products remaining in the reaction furnace 31 are removed. Further, the heating by the first heater 32 and the second heater 33 is stopped, and the temperature in the reaction furnace 31 and the substrate 11 is lowered.

(Substrate unloading process)
When the purge step is completed and the temperature in the reaction furnace 31 and the substrate 11 is lowered to a predetermined temperature, the substrate 11 is detached from the susceptor 36 and the substrate 11 is taken out of the reaction furnace 31, and the nitride according to the present embodiment. The manufacturing process of the semiconductor template 10 is finished.

(3) Light-Emitting Element Next, a light-emitting element 50 using the above-described nitride semiconductor template 10 will be described mainly with reference to FIG. FIG. 5 is a schematic cross-sectional view of the light emitting device 50 according to the present embodiment.

  As shown in FIG. 5, the light emitting element 50 includes a light emitting unit on the nitride semiconductor template 10. That is, the light-emitting element 50 is formed by growing an n-type semiconductor layer 51, a light-emitting layer 52, and a p-type semiconductor layer 53 in this order on the nitride semiconductor template 10 as a light-emitting portion.

  As the n-type semiconductor layer 51, for example, an n-type GaN layer is grown and formed. The n-type semiconductor layer 51 contains a predetermined concentration of a predetermined n-type impurity. As the n-type impurity, for example, silicon (Si), selenium (Se), tellurium (Te), or the like can be used. The thickness of the n-type semiconductor layer 51 is preferably about 10 μm or more and 15 μm or less. Thereby, the crystallinity of the nitride semiconductor template 10, that is, the crystallinity of the group III nitride semiconductor layer 13 can be improved and further improved.

  The light emitting layer 52 is composed of a multiple quantum well (MQW) layer composed of a barrier layer and a well layer. That is, the light emitting layer 52 is, for example, a multi-quantum structure in which an InGaN layer is a well layer, a GaN layer having a larger band gap than the well layer, for example, a quantum barrier layer, and a well layer and a quantum barrier layer are alternately stacked. It has a well (MQW) structure. The light emitting layer 52 may have a single quantum well (SQW) structure. The light emitting layer 52 is composed of an undoped compound semiconductor to which no impurity is added. The thickness of the light emitting layer 52 is preferably about several hundred nm.

  As the p-type semiconductor layer 53, for example, a p-type AlGaN layer and a p-type GaN layer are formed by being grown in order from the light emitting layer 52 side. Each of the p-type semiconductor layers 53 includes a predetermined concentration of a predetermined p-type impurity. As the p-type impurity, for example, magnesium (Mg), zinc (Zn), carbon (C), or the like can be used. The thickness of the p-type semiconductor layer 53 is preferably 200 nm or more and 500 nm or less.

  In addition, as a growth method of the n-type semiconductor layer 51, the light emitting layer 52, and the p-type semiconductor layer 53, various vapor phase growth methods can be used. For example, a vapor phase growth method such as an organic metal compound vapor phase growth method (MOCVD (MOVPE) method) or a molecular beam epitaxy method (MBE method), or a hydride vapor phase growth method (HVPE method) can be used. Among these, according to the MOVPE method, a product having good crystallinity can be obtained quickly.

  A first electrode 54 is provided on the surface of the p-type semiconductor layer 53. The first electrode 54 is configured by laminating, for example, a nickel (Ni) layer and a gold (Au) layer in order from the p-type semiconductor layer 53 side.

  An electrode pad 55 is formed on the first electrode 54. The electrode pad 55 is formed smaller than the first electrode 54. The electrode pad 55 may be formed in substantially the same shape as the first electrode 54. The electrode pad 55 is formed by laminating, for example, a titanium (Ti) layer and an Au layer in order from the first electrode 54 side. The electrode pad 55 is configured as an electrode pad for wire bonding, for example.

  In the light emitting portion, an exposed region 56 that exposes the surface of the nitride semiconductor template 10, that is, the group III nitride semiconductor layer 13, is formed. A second electrode 57 is provided in the exposed region 56. The second electrode 57 is configured by laminating, for example, a Ti layer and an aluminum (Al) layer in order from the n-type semiconductor layer 52 side. The second electrode 57 is configured as a die bonding electrode, for example.

(4) Manufacturing method of light emitting element Next, the manufacturing method of the light emitting element which concerns on this embodiment is demonstrated.

(Light emitting part forming step)
A light emitting portion is grown and formed on the nitride semiconductor template 10. That is, first, an n-type GaN layer, for example, is grown as the n-type semiconductor layer 51 on the surface of the group III nitride semiconductor layer 13 (second nitride semiconductor layer 21) by, for example, MOVPE. On the n-type semiconductor layer 51, as the light emitting layer 52, an MQW layer composed of an InGaN layer as a well layer and a GaN layer as a quantum barrier layer is grown by, for example, the MOVPE method. Then, on the light emitting layer 52, for example, a p-type AlGaN layer and a p-type GaN layer are sequentially grown from the light emitting layer 52 side by, for example, the MOVPE method as the p-type semiconductor layer 53.

(Exposed region forming process)
Next, an exposed region 56 that exposes the nitride semiconductor template 10 (the second nitride semiconductor layer 21 included in the group III nitride semiconductor layer 13) is formed in the light emitting portion formed on the nitride semiconductor template 10. That is, for example, a resist pattern is formed at a predetermined position on the upper surface of the light emitting unit, that is, the upper surface of the p-type semiconductor layer 53. Subsequently, using the resist pattern as a mask, the p-type semiconductor layer 53, the light emitting layer 52, and the n-type semiconductor layer 51 are partially removed by etching (for example, RIE (Reactive Ion Etching)). Note that the etching of the p-type semiconductor layer 53, the light emitting layer 52, and the n-type semiconductor layer 51 may be performed simultaneously or separately. As a result, an exposed region 56 where the nitride semiconductor template 10 is exposed is formed at a predetermined position of the light emitting portion. For example, as shown in FIG. 5, the exposed region 56 is a predetermined region of the second nitride semiconductor layer 21 included in the nitride semiconductor template 10 in addition to the p-type semiconductor layer 53, the light emitting layer 52, and the n-type semiconductor layer 51. Etching may be performed at a position to provide a recess having a predetermined depth.

(First electrode forming step)
Next, the first electrode 54 is formed on a part of the upper surface of the p-type semiconductor layer 53. Specifically, a resist pattern having a predetermined shape is formed on the p-type semiconductor layer 53 by using, for example, a photolithography method. Subsequently, for example, Ni and Au are vapor-deposited in this order by vacuum vapor deposition or sputtering, and then the resist pattern is removed by lift-off. Thereby, the first electrode 54 having a predetermined shape is formed on a part of the upper surface of the p-type semiconductor layer 53.

  Subsequently, for example, Ti and Au are vapor-deposited in this order on the first electrode 54 by, for example, a lift-off method using a photolithography method, a vacuum vapor deposition method, a sputtering method, or the like to form an electrode pad 55.

(Second electrode forming step)
Next, the second electrode 57 is formed on a part of the nitride semiconductor template 10 (that is, the second nitride semiconductor layer 21) exposed from the exposed region 56. Specifically, a resist pattern having a predetermined shape is formed on the second nitride semiconductor layer 21 exposed from the exposed region 56 using, for example, a photolithography method. Subsequently, for example, Ti and Al are vapor-deposited in this order by vacuum vapor deposition or sputtering, and then the resist pattern is removed by lift-off. As a result, the second electrode 56 having a predetermined shape is formed on a part of the second nitride semiconductor layer 21 exposed from the exposed region 56.

  And the light emitting element 50 which concerns on this embodiment is obtained, and the manufacturing process is complete | finished.

(5) Effects according to the present embodiment According to the present embodiment, the following one or more effects are achieved.

(A) According to the present embodiment, the substrate 11 is provided with a plurality of convex portion rows 15 formed by arranging a plurality of convex portions 14 in a row at a predetermined interval. The plurality of convex portion rows 15 includes a first convex portion row 17 in which adjacent convex portions 14 are arranged at a first interval d1, and a second interval d2 in which adjacent convex portions 14 are different from the first interval d1. 2nd convex part row | line | column 18 distribute | arranged. A group III nitride semiconductor layer 13 is provided on the side of the substrate 11 where the convex row 15 is provided. Thereby, generation | occurrence | production of the surface defect of the nitride semiconductor template 10 can be suppressed, improving the crystallinity of the nitride semiconductor template 10. FIG. Therefore, the light extraction efficiency of the light emitting element 50 formed using the nitride semiconductor template 10 can be improved. That is, the nitride semiconductor template 10 can play a role of improving crystallinity by reducing crystal defects and increasing the internal quantum efficiency and a role of reducing the forward voltage (Vf).

(B) According to the present embodiment, the first interval d1 and the second interval d2 are each 5 μm or less. Further, the thickness of the group III nitride semiconductor layer 13 is not less than 4 μm and not more than 10 μm. Thereby, generation | occurrence | production of the surface defect of the nitride semiconductor template 10 can be suppressed more, improving the crystallinity of the nitride semiconductor template 10 more.

(C) According to this embodiment, the height of the convex portion 14 is not less than 0.5 μm and not more than 3.0 μm. Thereby, generation | occurrence | production of the surface defect of the nitride semiconductor template 10 can be suppressed more, improving the crystallinity of the nitride semiconductor template 10 more.

(D) According to the present embodiment, the half width of the maximum diffraction peak of the (0004) plane measured by X-ray diffraction of the group III nitride semiconductor layer 13 (nitride semiconductor template 10) is 50 seconds or more and 100 seconds. There are few crystal defects and it has favorable crystallinity.

(E) According to the present embodiment, the surface specific resistance of the group III nitride semiconductor layer 13 (nitride semiconductor template 10) is 10Ω / □ or more and 25Ω / □ or less. Thereby, generation | occurrence | production of the surface defect of the nitride semiconductor template 10 can be suppressed more, improving the crystallinity of the nitride semiconductor template 10 more.

(F) According to the present embodiment, the group III nitride semiconductor layer 13 is formed on the substrate 11 by the HVPE method using the hydride vapor phase epitaxy (HVPE) apparatus 30. Thereby, the growth rate of the group III nitride semiconductor layer 13 can be increased, and productivity can be improved. Therefore, the manufacturing cost of the nitride semiconductor template 10 can be suppressed.

(G) According to the present embodiment, the n-type semiconductor layer 51, the light-emitting layer 52, and the p-type semiconductor layer 53 are grown on the group III nitride semiconductor layer 13 as the light-emitting portion using the nitride semiconductor template 10 described above. Thus, the light emitting element 50 is formed. Thereby, the light extraction efficiency of the light emitting element 50 can be improved.

(Other embodiments)
As mentioned above, although one Embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, A various change is possible in the range which does not deviate from the summary.

  In the above-described embodiment, the plurality of convex portion rows 15 includes the first convex portion row group 17 in which the adjacent convex portions 14 and 14 are arranged at the first interval d1, and the adjacent convex portions 14 and 14 are the second. Although the case where it provided with the 2nd convex part row | line | column 18 distribute | arranged by the space | interval d2 of this was demonstrated, it is not limited to this. That is, for example, the plurality of convex portion rows 15 includes a first convex portion row group 17 in which the adjacent convex portions 14 and 14 are arranged at the first interval d1, and an adjacent convex portion 14 and 14 in the second interval d2. A second convex portion row 18 arranged adjacent to each other, and a third convex portion row group in which adjacent convex portions 14 and 14 are arranged at a third interval different from the first interval d1 and the second interval d2. It may be provided.

  In the above-described embodiment, for example, as shown in FIG. 2C, the shape of the convex portion 14 is a hemispherical shape, but is not limited thereto. In addition, the shape of the convex portion 14 may be, for example, a pyramid shape, a conical shape, or the like.

  Although the buffer layer 12 is provided in the above embodiment, the present invention is not limited to this. That is, the buffer layer 12 may be omitted as necessary.

  In the above-described embodiment, the hot wall type HVPE apparatus 30 is used, but a cold wall type HVPE apparatus 30 may be used.

  Next, examples of the present invention will be described, but the present invention is not limited to these examples.

Example 1
[Production of nitride semiconductor templates]
In Example 1, PSS having a thickness of 900 μm and a diameter of 100 mm (4 inches) was used as the substrate 11. Further, on the substrate 11, the first convex row 17 in which the adjacent convex portions 14 are arranged at intervals of 2 μm (first interval), and the adjacent convex portions 14 are at intervals of 4 μm (second interval). And a second convex row 18 arranged in the above. Further, of the first interval d1 or the second interval d2, the plurality of projections 14 constituting the first projection row 17 and the plurality of projections 14 constituting the second projection portion row 18 are: The first convex row 17 and the second convex row 18 are respectively formed on the substrate 11 so that a regular hexagon having a shorter interval (the first interval d1 in the present embodiment) as one side is formed. Arranged.

Next, using the HVPE apparatus 30 shown in FIG. 4, an AlN layer having a thickness of 20 nm was grown as the buffer layer 12 on the surface of the substrate 11 on which the convex portions 14 were formed. That is, first, the substrate 11 is placed on the susceptor 36. Subsequently, nitrogen is introduced into the reaction furnace 31 from at least one of the doping gas supply pipe 38, the group V source gas supply pipe 39, the first group III source gas supply pipe 40, or the second group III source gas supply pipe 41. Gas (pure nitrogen gas) was supplied, the inside of the reaction furnace 31 was purged, and the inside of the reaction furnace 31 was put into a nitrogen atmosphere. Then, 3 sml of hydrogen (H ₂ ) is supplied from any of the doping gas supply pipe 38, the group V source gas supply pipe 39, the first group III source gas supply pipe 40, or the second group III source gas supply pipe 41. While the mixed gas of the gas and 7 sml of nitrogen (N ₂ ) gas is supplied into the reaction furnace 31, the raw material portion 34 in the reaction furnace 31 is heated to about 850 ° C. by the first heater 32, and the second heater 33 The substrate 11 (growth part 35 in the reaction furnace 31) was heated to about 1100 ° C. and held for 10 minutes. At this time, the pressure in the reaction furnace 31 was normal pressure (1 atm). Note that the temperature of the substrate 11 and the pressure in the reaction furnace 31 were maintained at the above-described temperature and pressure until the later-described group III nitride forming step was completed. When the temperature of the substrate 11 reaches a predetermined temperature, 50 sccm of hydrogen chloride (HCl) gas is supplied from the first group III source gas supply pipe 40 into the Al solution tank 43, and the group III source gas AlCl is supplied. Gas was generated. Then, AlCl gas was supplied into the reaction furnace 31. The second group III source gas supply pipe 41 was supplied with ₂ slm H ₂ gas and 1 slm N ₂ gas as carrier gas together with HCl gas. In parallel with the supply of the AlCl gas from the second group III source gas supply pipe 41 into the reaction furnace 31, 50 sccm of ammonia (NH ₃ ) gas is supplied as a group V source gas from the group V source gas supply pipe 39. It was supplied into the reaction furnace 31. Note that 1 slm H ₂ gas was allowed to flow through the group V source gas supply pipe 39 as a carrier gas together with the NH ₃ gas. Then, the AlN gas that is the group III source gas and the NH ₃ gas that is the group V source gas are reacted in the growth unit 35 in the reaction furnace 31 to grow an AlN layer on the substrate 11. The growth time of the AlN layer was 45 seconds. Thus, an AlN layer having a thickness of 20 nm was grown on the substrate 11 and formed.

Subsequently, the group III nitride semiconductor layer 13 including the first nitride semiconductor layer 20 and the second nitride semiconductor layer 21 was formed on the AlN layer as the buffer layer 12. First, an undoped GaN layer to which no additive was added was formed as the first nitride semiconductor layer 20 on the AlN layer. That is, 50 sccm of HCl gas was supplied from the first group III source gas supply pipe 40 into the Ga solution tank 42 to generate a group III source gas, GaCl gas. Then, GaCl gas was supplied into the reaction furnace 31. The first group III source gas supply pipe 40 was supplied with ₂ slm H ₂ gas and 1 slm N ₂ gas as carrier gas together with HCl gas. In parallel with the supply of GaCl gas from the first group III source gas supply pipe 40 into the reaction furnace 31, 2 slm ammonia (NH ₃ ) gas is supplied as a group V source gas from the group V source gas supply pipe 39. It was supplied into the reaction furnace 31. Note that 1 slm H ₂ gas was allowed to flow through the group V source gas supply pipe 39 as a carrier gas together with the NH ₃ gas. Then, a GaCl gas, which is a group III source gas, is reacted with NH ₃ gas, which is a group V source gas, in the growth section 35 in the reaction furnace 31 to grow a GaN layer on the AlN layer. The growth rate of the GaN layer was 60 μm / hr, and the growth time of the GaN layer was 6 minutes. Thus, a GaN layer having a thickness of 5 μm was grown on the AlN layer.

Subsequently, a GaN layer in which silicon (Si) as an additive is added as the second nitride semiconductor layer 21 on the undoped GaN layer that is the first nitride semiconductor layer 20 (hereinafter also referred to as Si-doped GaN layer). .) Was formed. That is, 50 sccm of HCl gas was supplied from the first group III source gas supply pipe 40 into the Ga solution tank 42 to generate a group III source gas, GaCl gas. Then, GaCl gas was supplied into the reaction furnace 31. The first group III source gas supply pipe 40 was supplied with ₂ slm H ₂ gas and 1 slm N ₂ gas as carrier gas together with HCl gas. In parallel with the supply of GaCl gas from the first group III source gas supply pipe 40 into the reaction furnace 31, 2 slm NH ₃ gas is supplied from the group V source gas supply pipe 39 as a group V source gas to the reactor 31. Supplied in. Note that 1 slm H ₂ gas was allowed to flow through the group V source gas supply pipe 39 as a carrier gas together with the NH ₃ gas. In parallel with the supply of GaCl gas and NH ₃ gas into the reaction furnace 31, a predetermined amount of SiH ₂ Cl ₂ gas diluted with N ₂ gas was supplied into the reaction furnace 31 from the doping gas supply pipe 38. Then, in the growth section 35 in the reaction furnace 31, a GaCl gas that is a Group III source gas, an NH ₃ gas that is a Group V source gas, and a SiH ₂ Cl ₂ gas that is a doping gas are reacted to form a first nitriding. A Si-doped GaN layer is grown on the physical semiconductor layer 20. The growth rate of the Si-doped GaN layer was 60 μm / hr, and the growth time of the GaN layer was 2 minutes. Thereby, a Si-doped GaN layer having a thickness of 2 μm was grown on the GaN layer.

Thereafter, heating in the reaction furnace 31 by the first heater 32 and the second heater 33 is stopped. Then, for example, while supplying ₂ slm NH ₃ gas and 8 slm N ₂ gas into the reaction furnace 31 from the group V source gas supply pipe 39, the temperature of the substrate 11 is cooled to near room temperature, and the nitride semiconductor template 10 was obtained. This was used as the sample of Example 1.

  Thereafter, nitrogen gas is introduced into the reaction furnace 31 from at least one of the doping gas supply pipe 38, the group V source gas supply pipe 39, the first group III source gas supply pipe 40, or the second group III source gas supply pipe 41. (Pure nitrogen gas) was supplied, the inside of the reaction furnace 31 was purged, and the inside of the reaction furnace 31 was made a nitrogen atmosphere. And the nitride semiconductor template 10 which is the sample of Example 1 was carried out from the reaction furnace 31.

[Evaluation of nitride semiconductor template]
The nitride semiconductor template 10 which is the sample of Example 1 was inspected for the presence or absence of pits (surface defects) using a surface inspection apparatus. The inspection range was a range excluding the outer peripheral portion 2 mm of the nitride semiconductor template 10. As a result, it was confirmed that pits of 1 μm or more were not generated. Moreover, when the surface of the sample of Example 1 was observed with an optical microscope, the generation of pits could not be confirmed.

  The sample of Example 1 was confirmed to have a full width at half maximum (FWHM) of the maximum diffraction peak of the (0004) plane measured by X-ray diffraction of 73.8 seconds. That is, it was confirmed that the nitride semiconductor template 10 has good crystallinity.

  Moreover, the surface specific resistance of the sample of Example 1 was measured using a non-contact specific resistance measuring device. As a result, it was confirmed that the surface specific resistance was 19Ω / □.

  In addition, ten nitride semiconductor templates 10 similar to the sample of Example 1 described above were manufactured and evaluated in the same manner. As a result, it was confirmed that 2 to 5 pits were generated in 2 out of 10 nitride semiconductor templates 10, but it was confirmed that no pit was generated in the remaining 8 sheets. .

[Production of light-emitting elements]
Next, a light emitting portion was grown by the MOVPE method on the nitride semiconductor template 10 as the sample of Example 1. That is, the n-type semiconductor layer 51, the light emitting layer 52, and the p-type are formed on the second nitride semiconductor layer 21 of the nitride semiconductor template 10 that is the sample of Example 1 from the second nitride semiconductor layer 21 side. The semiconductor layer 53 was epitaxially grown in order. Specifically, first, the nitride semiconductor template 10 which is the sample of Example 1 is carried into the MOVPE apparatus. Then, an n-type GaN layer is grown and formed as the n-type semiconductor layer 51 on the Si-doped GaN layer as the second nitride semiconductor layer 21. On the n-type GaN layer, as the light emitting layer 52, an InGaN layer that is a well layer and a GaN layer that is a quantum barrier layer were grown to form a multiple quantum well layer. Then, a p-type AlGaN layer and a p-type GaN layer were sequentially grown on the light-emitting layer 52 from the light-emitting layer 52 side as the p-type semiconductor layer 53. Then, for example, an epitaxial wafer for a light emitting element as shown in FIG. 6 was manufactured.

  The 1st electrode 54 and the 2nd electrode 57 were formed in the epitaxial wafer for light emitting elements. That is, first, predetermined positions of the p-type semiconductor layer 53, the light emitting layer 52, and the n-type semiconductor layer 51 are partially removed by etching (for example, RIE) to expose the nitride semiconductor template 10 that is the sample of Example 1. An exposed region 56 to be formed was formed. Then, Ni and Au were sequentially deposited on a part of the upper surface of the p-type semiconductor layer 53 from the p-type semiconductor layer 53 side to form a Ni / Au translucent electrode as the first electrode 54. Next, an electrode pad 55 was formed on the Ni / Au translucent electrode. Next, Ti and Al were sequentially deposited from the side of the nitride semiconductor template 10 on a part of the nitride semiconductor template 10 exposed from the exposed region 56 to form a Ti / Al electrode as the second electrode 57. . And the blue LED (light emitting element) using the sample of Example 1 was obtained.

[Evaluation of light emitting element]
The light emission characteristics of the light emitting element using the sample of Example 1 were evaluated at an electric current of 20 mA. As a result, it was confirmed that the emission peak wavelength was about 450 nm, the forward voltage was 3.25 V, and the emission output was 30 mW. That is, the light-emitting element using the sample of Example 1 having good crystallinity and suppressed generation of surface defects has improved internal quantum efficiency and increased light output (light extraction efficiency has improved). ) Was confirmed.

In addition, a reliability test of the light-emitting element using the sample of Example 1 was performed. That is, an energization test of 1000 hr was performed at room temperature under an energization current of 50 mA. As a result, the relative output was 98%, and it was confirmed that the device had high reliability characteristics. The relative output is a value calculated by the following formula 1.
(Expression 1) Relative output = (light emission output after energization for 168 hours / initial light emission output) × 100

(Example 2)
The second embodiment is the same as the first embodiment except that the thickness of the group III nitride semiconductor layer 13 is different from that of the first embodiment within the range of 4 μm to 10 μm. Thus, the nitride semiconductor template 10 was manufactured. This was used as the sample of Example 2. The evaluation of the nitride semiconductor template which is the sample of Example 2 was confirmed to have almost the same result as Example 1. Further, a light emitting device was manufactured using the sample of Example 2 in the same manner as in Example 1 described above. The evaluation of this light emitting element was confirmed to be almost the same result as in Example 1.

(Example 3)
In Example 3, the height h of the convex portion 14 provided on the substrate 11 is within a range of 0.5 μm or more and 3.0 μm or less, and other points except that the thickness is different from that of Example 1 are described above. A nitride semiconductor template 10 was manufactured in the same manner as in Example 1. This was used as the sample of Example 3. The evaluation of the nitride semiconductor template which is the sample of Example 3 was confirmed to have almost the same result as Example 1. Further, in the same manner as in Example 1 described above, a light emitting device was manufactured using the sample of Example 3. The evaluation of this light emitting element was confirmed to be almost the same result as in Example 1.

(Comparative Example 1)
In the first comparative example, for example, as shown in FIG. 7, the other points except that the adjacent convex portions are arranged at intervals of 2 μm are provided on the substrate. In the same manner as in No. 1, a nitride semiconductor template was manufactured. This was used as a sample of Comparative Example 1. Further, in the same manner as in Example 1 described above, a light emitting element was manufactured using the sample of Comparative Example 1.

[Evaluation of nitride semiconductor template]
The nitride semiconductor template, which is the sample of Comparative Example 1, was inspected for the presence or absence of pits (surface defects) using a surface inspection apparatus. The inspection range was a range excluding the outer peripheral portion 2 mm of the nitride semiconductor template. As a result, it was confirmed that several hundred pits of 1 μm or more and 3 μm or less were generated. Further, when the surface of the sample of Comparative Example 1 was observed with an optical microscope, it was confirmed that pits were generated on the surface of the sample of Comparative Example 1. Further, it was confirmed that pits were not generated locally on the surface of the sample of Comparative Example 1, but were generated on the entire surface of the sample of Comparative Example 1.

  The sample of Comparative Example 1 was confirmed to have a full width at half maximum (FWHM) of the maximum diffraction peak of the (0004) plane measured by X-ray diffraction of 117.6 seconds. That is, in Comparative Example 1, the FWHM was about 44 seconds wider than that in Example 1, and it was confirmed that the nitride semiconductor template had many crystal defects and reduced crystallinity.

  Moreover, the surface specific resistance of the sample of Comparative Example 1 was measured using a non-contact specific resistance measuring device. As a result, it was confirmed that the surface specific resistance was 19Ω / □.

[Evaluation of light emitting element]
The light emission characteristics of the light emitting element using the sample of Comparative Example 1 were evaluated at an electric current of 20 mA. As a result, the emission peak wavelength was about 450 nm, the forward voltage was 3.22 V, and the emission output was 18 mW. That is, since the FWHM of the nitride semiconductor template which is the sample of Comparative Example 1 is wide and there are many crystal defects, it was confirmed that the light emitting device using the sample of Comparative Example 1 had a reduced internal quantum efficiency.

  In addition, a reliability test of the light-emitting element using the sample of Comparative Example 1 was performed. That is, an energization test of 1000 hr was performed at room temperature under an energization current of 50 mA. As a result, the relative output was 87%, and it was confirmed that the reliability characteristics were low. The relative output was calculated by the above equation 1.

(Comparative Example 2)
In Comparative Example 2, the nitride array is the same as in Example 1 described above except that the protrusions provided on the substrate are all arranged with an interval of 4 μm between adjacent protrusions. A semiconductor template was produced. This was used as a sample of Comparative Example 2. Further, in the same manner as in Example 1 described above, a light emitting device was manufactured using the sample of Comparative Example 2.

[Evaluation of nitride semiconductor template]
The sample of Comparative Example 1 has a half-width (FWHM) of the maximum diffraction peak of the (0004) plane measured by X-ray diffraction of 72.5 seconds, which is about the same as the FWHM of the sample of Example 1. confirmed. However, when the surface of the sample of Comparative Example 2 was observed with an optical microscope, it was confirmed that more pits were generated on the surface of the sample of Comparative Example 2 than in Comparative Example 1.

  Moreover, the surface specific resistance of the sample of Comparative Example 2 was measured using a non-contact specific resistance measuring device. As a result, it was confirmed that the surface specific resistance was 16Ω / □, which was the same as the sample of Example 1 and the sample of Comparative Example 1.

[Evaluation of light emitting element]
The light emission characteristics of the light emitting element using the sample of Comparative Example 2 were evaluated at an electric current of 20 mA. As a result, the emission peak wavelength was about 450 nm, the forward voltage was 3.23 V, and the emission output was 20 mW. That is, since many surface defects such as pits were generated in the sample of Comparative Example 2, it was confirmed that the internal quantum efficiency of the light emitting device using the sample of Comparative Example 1 was lowered.

  In addition, a reliability test of the light-emitting element using the sample of Comparative Example 2 was performed. That is, an energization test of 1000 hr was performed at room temperature under an energization current of 50 mA. As a result, the relative output was 62%, and it was confirmed that the reliability characteristics were low. The relative output was calculated by the above equation 1.

  A plurality of samples similar to the sample of Comparative Example 2 described above are manufactured, and a plurality of light emitting elements using the same sample as the sample of Comparative Example 2 are manufactured, and the same evaluation as in Example 1 (Comparative Example 2) is performed. It was. It was confirmed that the same sample as in Comparative Example 2 had a sample with a large number of pits and a sample with almost no pits. In addition, it was confirmed that a light emitting element using a sample similar to the sample of Comparative Example 2 has many light emitting elements with extremely low reverse voltage (Vr). In addition, it was confirmed that light-emitting elements using a sample similar to the sample of Comparative Example 2 sometimes have extremely low reliability characteristics. That is, a light emitting element using a sample similar to the sample of Comparative Example 2 is divided into a light emitting element with high and reliable characteristics and a light emitting element with extremely low light emitting output and extremely low reliability characteristics, and the yield is high. Confirmed to be very low. This means that a light-emitting element using a sample with almost no pits has good reliability characteristics, and a light-emitting element using a sample with many pits has extremely low reliability characteristics. it is conceivable that.

DESCRIPTION OF SYMBOLS 10 Nitride semiconductor template 11 Substrate 13 Group III nitride semiconductor layer 14 Convex part 15 Convex part row 17 First convex part row 18 Second convex part row d1 1st space | interval d2 2nd space | interval

Claims (13)

A substrate having a plurality of protrusions arranged with a plurality of protrusions arranged in a line at a predetermined interval;
A group III nitride semiconductor layer provided on the surface of the substrate provided with the convex row,
The plurality of convex portion rows are arranged such that the adjacent convex portions are arranged at a first interval, and the adjacent convex portions are arranged at a second interval different from the first interval. A nitride semiconductor template comprising: a second convex row. The shorter one of the first interval and the second interval due to the plurality of protrusions forming the first protrusion row and the plurality of protrusions forming the second protrusion row. 2. The nitride semiconductor template according to claim 1, wherein the first convex portion row and the second convex portion row are arranged so that a regular hexagon having one side as a side is formed. The first interval and the second interval are each 5 μm or less,
3. The nitride semiconductor template according to claim 1, wherein a thickness of the group III nitride semiconductor layer is 4 μm or more and 10 μm or less. The group III nitride semiconductor layer includes a first nitride semiconductor layer and a second nitride semiconductor layer,
The first nitride semiconductor layer and the second nitride semiconductor layer contain different additives, respectively, or added to either the first nitride semiconductor layer or the second nitride semiconductor layer. The nitride semiconductor template according to any one of claims 1 to 3, wherein a material is contained and the other is free of additives. 5. The nitride semiconductor template according to claim 1, wherein a surface resistivity of the group III nitride semiconductor layer is 10Ω / □ or more and 25Ω / □ or less. 6. The group III nitride semiconductor layer according to claim 1, wherein a half width of a maximum diffraction peak of a (0004) plane measured by X-ray diffraction is 50 seconds or more and 100 seconds or less. The nitride semiconductor template as described. 7. The nitride semiconductor template according to claim 1, wherein the group III nitride semiconductor layer contains GaN as a main component. The nitride semiconductor template according to any one of claims 1 to 7, wherein a buffer layer is provided between the substrate and the group III nitride semiconductor layer. The nitride semiconductor template according to claim 8, wherein the buffer layer has a thickness of 10 nm to 100 nm. The nitride semiconductor template according to any one of claims 1 to 9, wherein the convex portion has any one of a pyramid shape, a conical shape, and a hemispherical shape. 11. The nitride semiconductor template according to claim 1, wherein a height of the convex portion is not less than 0.5 μm and not more than 3.0 μm. Formed is a first convex row in which adjacent convex portions are arranged at a first interval, and a second convex row in which the adjacent convex portions are arranged at a second interval different from the first interval. A step of forming a plurality of the convex portions on the substrate;
A method for producing a nitride semiconductor template, comprising: forming a group III nitride semiconductor layer by hydride vapor phase growth on the substrate provided with a plurality of protrusions. Forming a light emitting unit comprising an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer on the nitride semiconductor template according to claim 1;
Forming an exposed region in the light emitting portion for exposing the nitride semiconductor template;
Forming a first electrode on the surface of the light emitting portion and forming a second electrode in the exposed region.

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