JP2014106339A - Drive circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the set ring time of a DAC(Digital/Analog Converter) without increasing a chip size.SOLUTION: A drive circuit device 100 for generating a drive signal for driving a video display device in accordance with an input video signal includes: a precharge circuit 151 for inputting a bit signal of l bits (l is an integer which is 2 or more) corresponding to the video signal, and for outputting a signal indicating a gradation level which is equal to or more than a gradation level whose generation is desired on the basis of the bit signal; and a digital/analog conversion circuit 17 for performing the analog conversion of the signal output by the precharge circuit 151, and for precharging a voltage value indicating the gradation level which is equal to or more than the desired gradation level, and for dropping a voltage, and for outputting a drive signal having the voltage value indicating the desired gradation level.

Description

  The present invention relates to a drive circuit device.

  In recent years, a liquid crystal display device using a liquid crystal panel is used as a display device. In an inversion driving panel such as a liquid crystal display device, a process of charging a display pixel on the positive electrode side (H side) and a process of charging a display pixel on the negative electrode side (L side) with respect to a common voltage (Vcom) are temporally performed. Alternately. Therefore, the display driver needs to selectively perform H-side output and L-side output for the same gradation input. The H-side output and the L-side output differ only in output polarity and are symmetrical voltage values with respect to the common voltage, so that the configuration of the output circuit is also symmetric.

  FIG. 5 is an arrangement image diagram of a schematic configuration block of the display drive driver. In order to simplify the drawing, only the configuration related to the H-side output is shown. The display driver is supplied with gamma supply voltages VGMH_1 to VGMH_N. The H-side gamma circuit is configured with a ladder resistor. The H-side gamma circuit generates gradation levels VH_00 to VH_FF by dividing the supplied gamma supply voltages VGMH_1 to VGMH_N by a ladder resistor. The gradation levels VH_00 to VH_FF are supplied to the H-side DAC_1 to DAC_2n. Each gradation level is connected to a selection switch provided in 2n DAC (Digital Analog Converter) circuits. The H-side DAC selects one gradation from VH_00 to VH_FF according to the display data. The selected gradation level is impedance-converted by the buffer amplifier circuit, and is output from the output terminals S1_o to S2n_o via the output SW.

  In the arrangement of each block, a gamma circuit is arranged at the center of the chip. The DAC circuit is arranged above and below the gamma circuit. Note that the number of DAC circuits arranged above and below is approximately the same. Here, the gradation level wiring wired from the gamma circuit to the DAC circuit is a very long wiring in the vertical direction.

  FIG. 6 is a diagram illustrating an example of a resistance component of each part from the gamma supply voltage terminal to the input terminal of the s1_O buffer amplifier in the 1440-output display driver. In FIG. 6, (1) is a resistance value from the gamma voltage supply terminal VGMH to the H side gamma circuit output, (2) is a resistance value from the H side gamma circuit output to the input of the H side DAC_1, and (3) is The resistance value of the H-side DAC_1, (4) is the resistance value from the output of the H-side DAC_1 to the input terminal of the buffer amplifier 1.

  Here, CASE1 is a resistance value when the H-side DAC_1 selects a gradation level generated through the ladder resistor in the H-side gamma circuit, like the gradation level VH_FE. CASE2 is a resistance when the resistance width is doubled in order to lower the resistance value of the gradation level wiring of (2) under the conditions of CASE1. CASE3 is a resistance value when the gamma supply voltage is directly at the gradation level as in the gradation level VH_FF. CASE 4 is a resistance when the wiring width is doubled in order to lower the resistance value of the gradation level wiring of (2) under the conditions of CASE 3.

  Looking at CASE1, it can be seen that the part (1) is very large. In CASE3, it can be seen that the resistance value of the gradation level generated by the ladder resistance in the H-side gamma circuit is very large because the resistance of (1) is almost lost. In CASE2 and CASE4, the part (2) is halved. This is an effect of reducing the wiring resistance value by doubling the wiring width at the gradation level.

  FIG. 7 is a configuration diagram of a related analog input liquid crystal driving device according to Patent Document 1. The circuit preceding the amplifier is a sample-and-hold circuit that holds an input analog signal. However, when replaced with a current mainstream digital input driver, this part becomes a DAC circuit. A precharge switch for switching between the DAC circuit output and the precharge level VDD2 is provided between the DAC and the buffer amplifier. The precharge switch is controlled by a precharge control signal PRC. When the signal PRC is H, the precharge switch is turned ON and the precharge level VDD2 is supplied to the input terminal of the buffer amplifier.

  FIG. 8 is an operation timing chart of the related driving device. In the precharge period (t0 to t2) set at the beginning of the display period, the driving device activates (Hi) the precharge flag / PRC of the input of the drive amplifier that drives the display panel, and precharges the DAC output voltage. Precharge to level VDD2. When the precharge flag PRC becomes inactive (after t2), the DAC output outputs a desired voltage (voltage corresponding to a desired gradation level 9AH) VH_9A.

Japanese Patent Laid-Open No. 2000-200069

  When the parasitic capacitance from the gamma circuit to the input of the buffer amplifier 1 is C, and the resistance from the gamma circuit to the input of the buffer amplifier 1 through the DAC is R, the settling time of the input signal of the buffer amplifier 1 (the input of the buffer amplifier 1) The time during which the voltage stabilizes is a value proportional to the time constant τ = CR, and the input capacitance C is a constant value. That is, the settling time of the input signal of the buffer amplifier is proportional to the resistance component R. Therefore, in order to shorten the settling time of the input signal of the buffer amplifier, it is effective to widen the gradation level wiring width and reduce the wiring resistance as in CASE 2 shown in FIG. However, if the wiring widths of all the gradation levels are increased, there is a problem that the chip area of the display driver is increased.

In addition, the analog input liquid crystal driving device disclosed in Patent Document 1 requires a precharge switch composed of a high-voltage element having a large element size on the chip layout, so that there is a problem that the chip size increases. By precharging to the power supply voltage VDD2, the supply wiring becomes low resistance, and the precharge settling time (from time t0 to t1) can be shortened. However, the precharge level (VDD2) and a desired voltage level (for example, When the voltage difference from the voltage corresponding to 9AH is large, the time (time t2 to t3) required for the change to the desired gradation level after the end of the precharge becomes longer in the gradation corresponding to CASE1 in FIG. As a result, there is a problem that the settling time becomes long.
Therefore, it has been desired to shorten the DAC settling time without increasing the chip size.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A drive circuit device according to the present invention is a drive circuit device that generates a drive signal for driving a video display device in accordance with an input video signal, and inputs a bit signal corresponding to the video signal, and the bit A precharge circuit that outputs a signal indicating a gradation level that is greater than or equal to a gradation level that is desired to be generated based on the signal, and analog conversion of the signal output by the precharge circuit to achieve a level that exceeds the desired gradation level And a digital-analog conversion circuit that outputs a drive signal having a voltage value indicating a desired gradation level after precharging a voltage value indicating the gradation level.

  The settling time of the DAC can be shortened without increasing the chip size.

1 is a block diagram showing a configuration of a drive circuit device 100 according to a first exemplary embodiment. FIG. 3 is an equivalent circuit diagram for one gradation of a latch circuit and a precharge circuit according to the first exemplary embodiment; FIG. 2 is an equivalent circuit diagram for two outputs of a gamma circuit, a DAC circuit, a buffer amplifier circuit, and a positive / negative switch according to the first embodiment. 3 is a timing chart of the drive circuit device 100 according to the first exemplary embodiment. It is an arrangement image diagram of a schematic configuration block of a related display drive driver. It is a figure which shows the resistance component of each part in the related display driver. It is a figure which shows the principal part of the related analog input liquid crystal drive device. It is a timing chart of a related drive circuit device.

Embodiment 1 FIG.
A driver circuit of the display device according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a block diagram of the configuration of the drive circuit according to the first embodiment.

  The drive circuit device 100 includes a comparator circuit 11, a serial / parallel converter circuit 12 (S / P Converter), a shift register circuit 13, a data register circuit 14, a latch circuit 15, a level shift circuit 16, and a DAC circuit. 17 (D / A Converter: digital-analog conversion circuit), a gamma circuit 18 (GM), and a buffer amplifier circuit 19 (Buffer Amp.).

  The comparator circuit 11 receives a clock signal CLK and data signals D0 to D2 (DATA) which are externally small amplitude differential signals, and converts them into a large amplitude single-ended signal. Here, the data signals D0 to D2 are video signals having video information. The comparator circuit that receives the clock signal CLK is referred to as a first comparator circuit 11a, and the comparator circuit that receives data signals D0 to D2 is referred to as second comparator circuits 11b to 11d. The first comparator circuit 11 a outputs the comparator output signal generated by the conversion to the serial / parallel conversion circuit 12 and the shift register circuit 13. The second comparator circuits 11b to 11d output signals generated by receiving the data signals D0 to D2 to the serial / parallel conversion circuit 12. A signal (comparator output signal) output from the comparator circuit 11 to the serial / parallel conversion circuit 12 is output serially.

  The serial / parallel conversion circuit 12 receives signals from the first comparator circuit 11 a and the second comparator circuits 11 b to 11 d and outputs them to the data register circuit 14. More specifically, the serial / parallel conversion circuit 12 converts the comparator output signals serially input from the comparator circuits 11a to 11d into parallel data. The serial / parallel conversion circuit 12 outputs a signal converted into parallel data to the data register circuit 14.

  The shift register circuit 13 receives the signal from the first comparator circuit 11 a and outputs it to the data register circuit 14. The shift register circuit 13 operates based on the clock CLK input via the first comparator circuit 11a.

  The data register circuit 14 receives signals from the serial / parallel conversion circuit 12 and the shift register circuit 13, respectively. Specifically, the data register circuit 14 stores the parallel data of the serial / parallel conversion circuit 12 in synchronization with the output of the shift register circuit 13. The data register circuit 14 outputs the stored data to the latch circuit 15 for each gradation. In other words, the data register circuit 14 outputs a bit signal separated for each bit to the latch circuit 15.

  The latch circuit 15 includes a precharge circuit 151. The latch circuit 15 and the precharge circuit 151 have gradation level wirings that transmit a plurality of gradations separately for each bit. The latch circuit 15 receives the bit signal output from the data register circuit 14 and the control signal STB from the outside. More specifically, the latch circuit 15 latches the gradation data for the number of outputs input from the data register circuit 14 in synchronization with the control signal STB input from the outside. The latch circuit 15 outputs the latched bit signal to the precharge circuit 151.

  The precharge circuit 151 receives the latched bit signal and an external precharge control signal PRC. The precharge circuit 151 converts the value of the data included in the latched bit signal based on the precharge control signal PRC and outputs it to the level shift circuit 16. More specifically, the precharge circuit 151 always outputs the upper m bits (m is a natural number less than 1) of the l bit (l is an integer of 2 or more) without changing, that is, as it is. . Further, when the precharge control signal PRC is active (Hi) during the precharge period, the precharge circuit 151 fixes and outputs the lower n bits (n is 1−m) at the Hi level. Further, when the precharge period ends and the precharge control signal PRC is inactive (Low), the precharge circuit 151 outputs the lower n bits without conversion. Note that the precharge circuit 151 is not provided in the latch circuit 15 but may be provided in another location.

  The level shift circuit 16 receives the signal output from the precharge circuit 151. The level shift circuit 16 converts the voltage level of the input signal and outputs it to the DAC circuit 17.

  The DAC circuit 17 receives the signal output from the level shift circuit 16. The DAC circuit 17 receives an analog reference level from the gamma circuit 18. The DAC circuit 17 converts the digital data input from the level shift circuit 16 into an analog signal based on the input analog reference level. More specifically, during the precharge period, the DAC circuit 17 precharges a voltage value indicating a gradation level according to a bit signal in which the lower n bits are fixed to Hi in the precharge circuit 151. The DAC circuit 17 precharges using the analog reference level supplied from the gamma circuit 18 so that the gradation level is based on the bit signal output without conversion by the precharge circuit 151 after the precharge period. By dropping from the voltage, an analog signal having a voltage indicating a desired gradation level is generated. The DAC circuit 17 outputs an analog signal having a voltage indicating a desired gradation level to the buffer amplifier circuit 19.

  The gamma circuit 18 receives the gradation correction voltage VGM_IN from the outside. Here, VGM_IN supplies the gamma circuit 18 with at least four voltages of the maximum gradation and minimum gradation of the positive gradation and the minimum gradation and maximum gradation of the negative gradation. In addition to this, VGM_IN supplies a voltage corresponding to an intermediate gradation as the gradation correction voltage VGM. The gamma circuit 18 supplies an analog reference level to the DAC circuit 17 via the gradation level wiring. Here, the gamma circuit 18 has a plurality of gradation level wirings for transmitting the analog reference level to the DAC circuit 17. Here, the gray level wiring in the DAC circuit 17 has a wiring width of a gray level wiring that transmits an analog reference level used as a precharge level compared to other gray level wirings that are not used for precharging. Wide and low wiring resistance is desirable. The gamma circuit 18 will be described in detail later.

  The buffer amplifier circuit 19 receives an analog signal from the DAC circuit 17. Typically, a plurality of buffer amplifier circuits 19 are provided. Typically, the buffer amplifier circuit 19 buffers the analog signal input from the DAC circuit 17 by a voltage follower circuit. The buffer amplifier circuit 19 outputs the buffered analog signal as a drive signal to a video display device (not shown).

  Next, the operation of the drive circuit device 100 will be described.

  The comparator circuit 11 receives a clock signal CLK and data signals D0 to D2 which are externally small amplitude differential signals and converts them into a large amplitude single-ended signal. Specifically, the first comparator circuit 11 a outputs a signal generated by receiving the clock signal CLK to the serial / parallel conversion circuit 12 and the shift register circuit 13. The second comparator circuits 11b to 11d output signals generated by receiving the data signals D0 to D2 to the serial / parallel conversion circuit 12.

  The serial / parallel conversion circuit 12 converts the comparator output signal serially input from the second comparator circuits 11 b to 11 d into parallel data and outputs the parallel data to the data register circuit 14.

  For example, the shift register circuit 13 receives a signal from the first comparator circuit 11 a, shifts the digit of the stored data, and outputs it to the data register circuit 14.

  The data register circuit 14 stores the parallel data of the serial / parallel conversion circuit 12 in synchronization with the output of the shift register circuit 13. The data register circuit 14 outputs a bit signal corresponding to the stored parallel data to the latch circuit 15.

  The latch circuit 15 receives the bit signal output from the data register circuit 14 and the control signal STB from the outside. The precharge circuit 151 changes the value of the bit signal input from the latch circuit 15 based on the precharge control signal PRC and outputs the value to the level shift circuit 16. FIG. 2 is an example of an equivalent circuit diagram for one gradation of the latch circuit 15 and the precharge circuit 151. The latch circuit 15 is composed of eight latches which are the number of bits of one data signal. The precharge circuit 151 includes eight gradation level wirings and six OR gates. Here, the eight gradation level lines are composed of two through wirings and six fixed wirings. The six fixed wirings are connected to the corresponding six OR gates, respectively.

  Specifically, the latch circuit 15 stores the output data DR [7: 0] of the data register circuit 14 which is the previous stage circuit as LTO [7: 0] in synchronization with the STB signal, and outputs it to the precharge circuit 151. . The precharge circuit 151 always outputs the upper 2-bit latch output LDR [7: 6] as it is as the gradation signal LDR [7: 6]. The precharge circuit 151 inputs the lower 6-bit latch output LTO [5: 0] to one input terminal of each OR gate, and inputs the precharge control signal PRC in common to the other terminal. The precharge circuit 151 outputs the latch circuit output LTO [5: 0] as it is at the time of non-precharge (PRC = L) as the lower 6 bits LDR [5: 0] of the gradation signal, and at the time of precharge ( LDR [5: 0] = 111111 is output to PRC = H). In other words, the precharge circuit 151 outputs the gradation level of the lower 6 bits with the Hi level fixed value.

  The level shift circuit 16 receives the signal output from the precharge circuit 151. The level shift circuit 16 converts the voltage level of the input signal and outputs it to the DAC circuit 17.

  The gamma circuit 18 supplies an analog reference level to the DAC circuit 17. During the precharge period, the DAC circuit 17 outputs an analog voltage based on a bit signal in which the lower 6 bits are set to the Hi level. After the precharge period, the DAC circuit 17 converts the bit signal input from the level shift circuit 16 into analog data based on the analog reference level input from the gamma circuit 18. The buffer amplifier circuit 19 buffers the data input from the DAC circuit 17 and outputs it.

  Here, FIG. 3 is an equivalent circuit diagram for two outputs of the DAC circuit 17, the gamma circuit 18, the buffer amplifier circuit 19, and the positive / negative changeover switch provided at the subsequent stage of the buffer amplifier circuit 19.

  The gamma circuit 18 includes an H-side gamma circuit 18a that generates a positive gamma voltage and an L-side gamma circuit 18b that generates a negative gamma voltage. The DAC circuit 17 includes an H-side DAC circuit 17a that outputs one positive gradation voltage from a positive gamma voltage VH and a gradation signal LDR (not shown), a negative gamma voltage VL, and a gradation signal. The L-side DAC circuit 17b outputs one negative gradation voltage from an LDR (not shown). The buffer amplifier circuit 19 includes an H-side buffer amplifier circuit 19a that buffers positive gradation voltages and an L-side buffer amplifier circuit 19b that buffers negative gradation voltages. The positive / negative switching switch selects and outputs the output of the H-side buffer amplifier circuit 19a and the output of the L-side buffer amplifier circuit 19b according to the polarity control signal (not shown) according to the polarity of the output terminal Sn.

  Here, the H-side gamma circuit 18a divides the H-side gradation correction voltages VGM11 to 1 supplied from the outside by a ladder resistor and outputs positive-side (H-side) gradation levels VH_00 to VH_FF. At this time, the H-side gradation correction voltage VGM includes an H-side gradation correction voltage corresponding to the minimum gradation (00000000b) and the maximum gradation (11111111b), but the lower 6 bits are hexadecimal 3F (111111b). It is preferable to include three (00111111b, 01111111b, 10111111b) H-side gradation voltages. The H-side DAC circuit 17a selects one gradation level from the H-side 256 gradation levels VH_00 to VH_FF according to the gradation signal LDR (not shown), and outputs the selected gradation level to the H-side buffer amplifier circuit 19a. The H-side buffer amplifier circuit 19a buffers the output voltage of the H-side DAC circuit 17a with an operational amplifier having a voltage follower circuit configuration, and outputs the buffered voltage to one input terminal of the positive / negative switch.

  Further, the L-side gamma circuit 18b divides the L-side gradation correction voltages VGM12 to 22 supplied from the outside by a ladder resistor and outputs negative side (L-side) gradation levels VL_00 to VL_FF. At this time, the L-side gradation correction voltage VGM includes an L-side gradation correction voltage corresponding to the minimum gradation (00000000b) and the maximum gradation (11111111b), but the lower 6 bits are hexadecimal 3F (111111b). It is preferable to include three L-side gradation voltages. The L-side DAC circuit 17b selects one gradation level from the L-side 256 gradation levels VL_00 to VL_FF according to the gradation signal LDR (not shown), and outputs the selected gradation level to the L-side buffer amplifier circuit 19b. The L-side buffer amplifier circuit 19b buffers the output voltage of the L-side DAC circuit 17b with an operational amplifier having a voltage follower circuit configuration, and outputs the buffered voltage to the other input terminal of the positive / negative switch.

  Next, the drive timing of each component of the drive circuit device 100 will be described. FIG. 4 is a timing chart of the drive circuit device 100.

  The period from t0 to t1 is a precharge period (PRC = H) of the DAC circuit 17. In this period, the precharge circuit 151 outputs a signal in which the lower 6 bits of the latch data DR [7: 0] are H. That is, the upper 2 bits DR [7: 6] is the data as it is, and DR [5: 0] is “111111”.

  Here, the slope of the precharge waveform output from the precharge circuit 151 is smaller than the slope of the precharge voltage in the related drive circuit shown in FIG. This is because the related drive circuit supplies a precharge voltage to the power supply voltage VDD2 using a high withstand voltage switch, but the drive circuit 100 according to the present embodiment performs precharge using the gradation level wiring. This is because the potential difference is small.

  The level shift circuit 16 converts the voltage level of the bit signal output from the precharge circuit 151 and outputs it to the DAC circuit 17. The DAC circuit 17 selects and outputs the gray level according to the data in which the upper 2 bits DR [7: 6] whose level is converted are unchanged and the lower 6 bits are fixed to Hi. For example, as shown in FIG. 4, the DAC circuit 17 outputs VH_BF as an output waveform. Note that the gradation level VH_BF has the same potential as the gamma voltage level VGM5 supplied from the outside.

  At t2, the DAC precharge period ends (PRC = L). At this time, the latch circuit 15 outputs the latch data DR [7: 0] without conversion, and the level shift circuit 16 converts the gradation level and outputs it to the DAC circuit 17.

  At times t2 to t3 after the end of precharge, the DAC circuit 17 changes the voltage output from VH_BF to a gradation level voltage VH_9A that is a voltage of a desired gradation level corresponding to DR [7: 0]. After time t3, the DAC circuit 17 outputs the gradation level voltage VH_9A.

  At time t2 to t3, the time to reach the desired gradation level voltage after the end of precharge is shorter than t2 to t3 in the related drive circuit shown in FIG. This is because the time required to reach the desired gradation level is shortened because the voltage difference between the voltage of the desired gradation level and the precharge voltage is small. Therefore, in the drive circuit device 100, the time required for the settling time (t0 to t3) can be shortened. Here, by appropriately switching the precharge level for each display data, the potential difference between the precharge level and the desired output voltage can be reduced, and the settling time of the DAC output voltage can be increased.

  Therefore, the drive circuit device 100 can be precharged using the gradation level wiring. At this time, in the drive circuit device 100, by setting the lower n bits of the multi-bit data signal to a fixed value and setting the precharge level, it is not necessary to add a high voltage element having a large element size that causes an increase in the chip area. . Therefore, the drive circuit device 100 does not need to be added with a high voltage element having a large element size, which causes an increase in chip area, and can be configured by adding a low voltage element (OR gate) with a small size, thereby reducing the chip size. can do. Further, the drive circuit device 100 can reduce the potential difference between the desired voltage and the precharge level by appropriately switching the precharge level for each display data, and can shorten the settling time. Further, in the gradation level wiring for transmitting the analog reference level from the gamma circuit 18 to the DAC circuit 17, the driving circuit device 100 increases the wiring width of the gradation level wiring only for the gradation level set to the precharge level. By lowering, the settling time can be shortened without increasing the chip size.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary. For example, the drive circuit device 100 has been described as being provided with three second comparator circuits 11b that receive the data signals D0 to D2, but the number is not limited thereto. For example, the DAC circuit 17 and the buffer amplifier circuit 19 may be an integrated circuit.

11 Comparator circuit 12 Serial / parallel conversion circuit 13 Shift register circuit 14 Data register circuit 15 Latch circuit 151 Precharge circuit 16 Level shift circuit 17 Digital analog conversion circuit 18 Gamma circuit 19 Buffer amplifier circuit 100 Drive circuit device

Claims (6)

A drive circuit device that generates a drive signal for driving a video display device according to an input video signal,
A bit signal of 1 bit (l is an integer of 2 or more) corresponding to the video signal is input, and a signal indicating a gray level higher than a gray level desired to be generated based on the bit signal is output. A precharge circuit;
After the analog output of the signal output from the precharge circuit is performed and a voltage value indicating a gradation level higher than a desired gradation level is precharged, the voltage is dropped to have a voltage value indicating a desired gradation level. A digital-to-analog converter circuit that outputs a drive signal;
A drive circuit device comprising: The precharge circuit does not change the gradation level of the upper m bits (m is a natural number less than 1) of the bit signal consisting of 1 bit, and each gradation level of the lower n bits (n is 1−m). To generate a signal that is changed to Hi,
The drive circuit device according to claim 1. The precharge circuit receives a precharge control signal input from the outside,
When the precharge control signal is Hi, a signal in which each gradation level of the lower n bits of the bit signal is changed to Hi is output, and when the precharge control signal is Low, the lower n bits Output without changing the signal,
The drive circuit device according to claim 2. The precharge circuit includes at least one OR circuit,
Each of the OR circuits has a lower n-bit signal of the bit signal supplied for each bit as one input and the precharge control signal as the other input.
The drive circuit device according to claim 2 or claim 3. A gamma circuit that receives at least four gradation correction voltages from outside, generates an analog reference level, and outputs the analog reference level to the digital analog circuit;
The gradation level wiring for transmitting the analog reference level from the gamma circuit to the digital analog circuit is:
When performing precharging, the wiring resistance of the gradation level wiring that transmits the analog reference level used as the gradation level for precharging is lower than the gradation level wiring that is not used when performing precharging.
The drive circuit device according to any one of claims 1 to 4. A first comparator circuit for inputting an external clock signal and converting it to a large-amplitude single-ended signal;
A second comparator circuit for inputting a video signal from outside and converting it into a large amplitude single-ended signal;
A serial-parallel conversion circuit for converting signals serially input from the first and second comparator circuits into parallel data;
A shift register circuit that shifts the digit of the signal input from the first comparator circuit to the left and right;
A data register circuit that stores the parallel data of the serial-parallel conversion circuit in synchronization with the output of the shift register circuit and outputs the bit signal;
Based on a control signal input from the outside, a latch circuit that latches the bit signal for each bit and outputs it to the precharge circuit;
A level shift circuit that inputs a signal from the precharge circuit and changes a voltage level of the signal;
A buffer amplifier circuit that buffers the signal input from the digital-analog conversion circuit and outputs the signal to the video display device; and
The digital-analog conversion circuit converts the signal input from the level shift circuit into an analog signal based on the analog reference level input from the gamma circuit.
The drive circuit device according to claim 1.

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