JP2014105360A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which suppresses decomposition reaction of an additive caused on the surface of an anode electrode.SOLUTION: The method of manufacturing a semiconductor device comprises processes of: forming grooves VH in a second interlayer insulating film IL2 formed on a semiconductor wafer WA; forming a metal film MF in the grooves VH and on the second interlayer insulating film IL2; and removing the metal film MF formed on the second interlayer insulating film IL2 to embed the metal film MF in the grooves VH. The process of forming the metal film MF comprises steps of: placing the semiconductor wafer WA on a support part having a cathode electrode so that the outer periphery of the semiconductor wafer WA is brought into contact with the cathode electrode; immersing the semiconductor wafer WA in a treatment tank having an anode electrode; and subjecting the semiconductor wafer WA to electrolytic plating. The anode electrode is obtained by covering the surface of a metal material ISAN with a conductive organic film CPOF.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and is a technique applicable to a method for manufacturing a semiconductor device having a step of forming a metal film using plating, for example.

One of wiring materials in semiconductor devices is Cu. Below, the method of forming Cu wiring is demonstrated.
First, an interlayer insulating film is formed over a substrate over which a semiconductor element such as a transistor is formed. Next, a groove for providing a wiring layer and a via layer is formed in the interlayer insulating film, and a barrier metal film and a metal seed film are formed on the substrate. Then, a thick metal film is formed thereon using a plating method.

  When a metal thick film is formed on a substrate on which grooves are formed by using a plating method, an organic additive is added to the plating solution for the purpose of bottom-up growth and planarization.

  Patent Document 1 discloses a plating apparatus used for forming a thick metal film. Specifically, a configuration is described in which a film is disposed between the cathode electrode and the anode electrode in order to prevent the additive from moving to the anode electrode side.

US Pat. No. 6,568,299

  However, even when the metal film is formed using the plating apparatus described in Patent Document 1, the additive contained in the plating solution may gradually pass through the film and move to the anode electrode side. . The additive that has moved to the anode electrode side is decomposed by transferring electrons on the surface of the anode electrode. When the additive is decomposed, voids are generated, which may cause defects such as insufficient metal plating and decomposition products taken into the metal film. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the anode electrode used when forming the metal film is a metal material whose surface is covered with a conductive organic film.

  According to the embodiment, it is possible to provide a method for manufacturing a semiconductor device that suppresses defects caused by decomposition of additives.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the manufacturing apparatus of the semiconductor device which concerns on this embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment.
The semiconductor device manufacturing method according to the present embodiment includes a step of forming a trench VH in the second interlayer insulating film IL2 formed on the semiconductor wafer WA, and a metal in the trench VH and on the second interlayer insulating film IL2. A step of forming a film MF, and a step of burying the metal film MF in the trench VH by removing the metal film MF formed on the second interlayer insulating film IL2. In this manufacturing method, the step of forming the metal film MF includes the steps of placing the semiconductor wafer WA on the support portion having the cathode electrode so that the outer peripheral portion is in contact with the cathode electrode, and in the processing tank having the anode electrode. A step of immersing the semiconductor wafer WA, and a step of subjecting the semiconductor wafer WA to an electrolytic plating process. At this time, the anode electrode is obtained by coating the surface of the metal material ISAN with the conductive organic film CPOF. Further, according to the present embodiment, the conductivity of the conductive organic film CPOF is preferably lower than that of the metal material forming the anode electrode. By carrying out like this, the defect which arises by decomposition | disassembly of an additive can be suppressed still more highly.

Hereinafter, the method for manufacturing the semiconductor device according to the present embodiment will be described in detail with an example.
The manufacturing method according to the present embodiment is not particularly limited, but can be used, for example, when manufacturing a semiconductor device described below. Specifically, the semiconductor device has a multilayer wiring structure, and a first interlayer is formed on a semiconductor substrate SUB on which a transistor TR such as an element isolation region EIL and a MOSFET (Metal Oxide Field Effect Transistor) is formed. A contact COM that connects the insulating film IL1, the gate electrode GE, and the wiring layer is formed (FIG. 1A). Note that the transistor TR according to the present embodiment is provided with a gate electrode GE and the like. In this semiconductor device, a first wiring structure INC1 is formed on the first interlayer insulating film IL1. Further, a second interlayer insulating film IL2 in which a groove VH (via groove and wiring groove) for forming the second wiring structure is formed is provided on the first wiring structure INC1. The contact COM material according to the present embodiment is not particularly limited, and for example, tungsten.

  First, an element isolation film is formed on the semiconductor substrate SUB. Thereby, the element formation region EIL is isolated. The element isolation film is formed using, for example, the STI method, but may be formed using the LOCOS method. Next, a gate insulating film and a gate electrode GE are formed on the semiconductor substrate SUB located in the element formation region EIL. The gate insulating film may be a silicon oxide film or a high dielectric constant film (for example, a hafnium silicate film) having a higher dielectric constant than that of the silicon oxide film. When the gate insulating film is a silicon oxide film, the gate electrode GE is formed of a polysilicon film. When the gate insulating film is a high dielectric constant film, the gate electrode GE is formed of a laminated film of a metal film (for example, TiN) and a polysilicon film. Further, when the gate electrode GE is formed of polysilicon, a polysilicon resistor may be formed on the element isolation film in the step of forming the gate electrode GE.

  Next, source and drain extension regions are formed in the semiconductor substrate SUB located in the element formation region EIL. Next, a sidewall is formed on the sidewall of the gate electrode GE. Next, impurity regions serving as a source and a drain are formed in the semiconductor substrate SUB located in the element formation region EIL. In this way, the MOS transistor TR is formed on the semiconductor substrate SUB.

  Next, a multilayer wiring layer is formed on the element isolation film and the MOS transistor TR. An electrode pad is formed on the uppermost wiring layer. Next, a protective insulating film (passivation film) is formed on the multilayer wiring layer. An opening located on the electrode pad is formed in the protective insulating film.

  Next, as shown in FIG. 1A, a trench VH for forming a second wiring structure is formed in the second interlayer insulating film IL2. The method for forming the groove VH is not particularly limited. For example, a method of forming a resist pattern and etching can be used.

  Next, as shown in FIG. 1C, a metal film MF is formed over the second interlayer insulating film IL2 and the trench VH. A method for forming the metal film MF will be described later.

  Next, as shown in FIG. 1D, the metal film MF formed on the second interlayer insulating film IL2 is removed. Here, as a method of removing the metal film MF, for example, a method of performing chemical mechanical polishing can be used.

  Next, a method for forming the metal film MF on the second interlayer insulating film IL2 and in the trench VH will be specifically described.

  When the trench VH provided in the second interlayer insulating film IL2 is filled with the metal film MF, first, the barrier metal film BM and the metal seed film are formed by, for example, a PVD (Physical Vapor Deposition) method (FIG. 1B). )). The method for forming the barrier metal film BM and the metal seed film is not limited to this.

  In the present embodiment, the material for forming the barrier metal film BM and the metal seed film is not particularly limited, and for example, the following materials may be used. Examples of a material used for forming the barrier metal film BM include a material such as TiN. Examples of the material for forming the metal seed film include a material such as Cu.

  Next, electrolytic plating is performed on the semiconductor wafer WA on which the barrier metal film BM and the metal seed film are formed. An apparatus for performing electrolytic plating will be described later with reference to FIG. As the apparatus used in the method for manufacturing a semiconductor device according to the present embodiment, the apparatus shown in FIG. 2 is preferably used. Further, examples of the metal element to be plated include elements such as Cu. The metal element to be plated is contained in the plating solution.

FIG. 2 is a cross-sectional view for explaining the semiconductor device manufacturing apparatus according to this embodiment.
As shown in FIG. 2, the manufacturing apparatus according to the present embodiment includes a plating chamber OC, a tank TNK that stores a plating solution, a pump POM that circulates the plating solution, a wafer holder WAH that holds a semiconductor wafer WA, A constant current power supply ECS.
The plating process chamber OC in this apparatus includes a plating process chamber inner tank OCT for holding a plating solution, and the plating process chamber OC is further provided with a circulation drain CD. The circulation drain CD is connected to the plating process chamber inner tank OCT. The plating processing chamber inner tank OCT includes an anode electrode and a diffuser plate DFD, and holds a plating solution therein.

  In FIG. 2, the arrows indicate the flow of the plating solution. The plating solution is sucked up from the tank TNK by the pump POM into the plating processing chamber inner tank OCT, passes through the diffuser plate DFD and reaches the semiconductor wafer WA, and then passes again through the plating processing chamber OC and the circulation drain CD. When returning to the tank TNK, there is a case where the tank TNK returns to the tank TNK again through the plating chamber OC and the circulation drain CD without passing through the diffuser plate DFD. Thus, by circulating the plating solution in the apparatus, the plating solution can be supplied uniformly to the surface of the semiconductor wafer WA.

Hereinafter, a method of forming the metal film MF in the groove VH using the above apparatus will be described in detail.
According to the method for manufacturing a semiconductor device according to the present embodiment, the semiconductor wafer WA on which the barrier metal film BM and the metal seed film are formed is first installed in the apparatus shown in FIG. At this time, the semiconductor wafer WA is placed on the support portion having the cathode electrode so that the outer peripheral portion is in contact with the cathode electrode.

  Further, the direction in which the semiconductor wafer WA is placed on the apparatus of FIG. 2 is not particularly limited, but the semiconductor wafer WA may be placed on the lower side and the anode electrode may be placed on the upper side through the plating solution. By doing so, it is possible to avoid the oxygen molecules generated on the surface of the anode electrode from approaching the semiconductor wafer WA using gravity.

  Next, the semiconductor wafer WA is immersed in a plating processing chamber inner tank OCT having an anode electrode and holding a plating solution therein. Then, electrolytic plating is performed on the immersed semiconductor wafer WA. By doing so, the semiconductor device according to the present embodiment can be obtained.

  In addition, according to the method for manufacturing a semiconductor device according to the present embodiment, the anode electrode used when performing the electrolytic plating process is one in which the surface of the metal material ISAN is covered with the conductive organic film CPOF. By doing so, the decomposition reaction of the additive occurring on the anode electrode surface can be suppressed. That is, defects caused by the decomposition of the additive can be suppressed.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the anode electrode formed of the metal material ISAN insoluble in water is used, and the surface of the anode electrode is formed on the conductive organic film CPOF. By covering with, it is possible to suppress decomposition of the additive due to electron transfer. The reason for this can be explained below. Defects such as insufficient metal plating due to the generation of voids, and decomposition products taken into the metal film are caused by the decomposition of the additive by the transfer of electrons on the electrode surface of the anode. On the other hand, in this embodiment, the anode electrode is formed of a metal material ISAN that is insoluble in water, and the anode electrode surface is covered with a conductive organic film CPOF. By doing so, the amount of electrons supplied to the anode electrode per unit time can be reduced. For this reason, it is thought that decomposition | disassembly of the additive by electron transfer can be suppressed.
Further, according to the present embodiment, it is possible to prevent the metal ions supplied from the plating solution from reaching the anode electrode and being deposited.

  Further, the water-insoluble metal material ISAN that forms the anode electrode according to the present embodiment is not particularly limited. For example, the metal material ISAN is formed of at least one component selected from the group consisting of platinum and titanium. It is preferable that By so doing, the decomposition reaction of the additive occurring on the anode electrode surface can be more effectively suppressed. That is, defects caused by decomposition of the additive can be further suppressed to a high degree.

  Although it does not specifically limit as a material which forms the electroconductive organic film CPOF which concerns on this embodiment, For example, it is preferable to use the material containing a polyacetylene. By so doing, the decomposition reaction of the additive occurring on the anode electrode surface can be more effectively suppressed. That is, defects caused by decomposition of the additive can be further suppressed to a high degree.

  In addition, the resistivity of the anode electrode according to this embodiment needs to be higher than that of the metal material ISAN that is insoluble in water forming the anode electrode. Thus, by increasing the resistivity of the anode electrode surface in contact with the plating solution, the amount of electrons exchanged per unit area can be limited. In addition, setting the resistivity of the anode electrode which concerns on this embodiment to 0.1-400 ohm / square is mentioned, for example. By doing so, the decomposition reaction of the additive occurring on the anode electrode surface can be more effectively suppressed. Furthermore, according to this embodiment, since the structure of the plating tank can be simplified as compared with the prior art, the maintenance of the plating tank can be performed by a simple method.

  Further, according to the method of manufacturing a semiconductor device according to the present embodiment, not only the anode electrode is formed of the metal material ISAN that is insoluble in water, but also the surface of the metal material is covered with the conductive organic film CPOF. Therefore, only the additive decomposition reaction can be suppressed without stopping the flow of elements and molecules in the plating solution. For this reason, it becomes difficult to produce the performance of a manufacturing apparatus changing with time.

  In addition, the anode electrode according to the present embodiment is formed of a metal material ISAN that is insoluble in water and covered with a conductive organic film CPOF. By causing an oxidation reaction on the surface of the anode electrode, oxygen is generated by the decomposition of water in the plating solution instead of elution of metal cations.

  On the other hand, according to the present embodiment, in FIG. 2, the plating solution is supplied from the central portion of the anode electrode to the plating processing chamber inner tank OCT, and the center of the diffuser plate DFD is disposed at a position close to the anode. It may be. By doing so, it is possible to provide an anode chamber structure ANCC that does not allow the generated oxygen to reach the semiconductor wafer WA but escapes to the periphery of the plating processing chamber inner tank OCT.

  In addition, according to the present embodiment, the element to be plated is provided with a supply tank (not shown) in a circulation system outside the tank, and for example, is eluted into the plating solution using an anode made of Cu. It may be adopted. At this time, by providing a filter in the circulation system so that the additive is not decomposed in the Cu supply tank, consumption of the additive in the plating solution can be minimized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SUB Semiconductor substrate EIL Element isolation region GE Gate electrode TR Transistor IL1 First interlayer insulating film IL2 Second interlayer insulating film COM Contact INC1 First wiring structure WA Semiconductor wafer BM Barrier metal film VH Groove MF Metal film OC Plating processing chamber CD Circulating drain OCT Plating chamber inner tank ANCC Anode chamber structure DFD Diffuser plate WAH Wafer holder TNK Tank POM Pump ECS Constant current power supply ISAN Metal material CPOF Conductive organic film

Claims (4)

Forming a groove in an insulating film formed on a semiconductor wafer;
Forming a metal film in the groove and on the insulating film;
Burying the metal film in the trench by removing the metal film formed on the insulating film;
Have
The step of forming the metal film includes
Placing the semiconductor wafer on a support having a cathode electrode such that an outer peripheral portion is in contact with the cathode electrode;
Immersing the semiconductor wafer in a treatment tank having an anode electrode;
Applying electrolytic plating to the semiconductor wafer;
With
The said anode electrode is a manufacturing method of the semiconductor device which coat | covers the surface of a metal material with the electroconductive organic film.   The method for manufacturing a semiconductor device according to claim 1, wherein the conductivity of the conductive organic film is lower than that of the metal material.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the metal material is formed of at least one component selected from the group consisting of platinum and titanium.   The method for manufacturing a semiconductor device according to claim 1, wherein the conductive organic film is formed of a material containing polyacetylene.

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