JP2014191846A5 - Semiconductor device and driving method of semiconductor device - Google Patents
Semiconductor device and driving method of semiconductor device Download PDFInfo
- Publication number
- JP2014191846A5 JP2014191846A5 JP2013067244A JP2013067244A JP2014191846A5 JP 2014191846 A5 JP2014191846 A5 JP 2014191846A5 JP 2013067244 A JP2013067244 A JP 2013067244A JP 2013067244 A JP2013067244 A JP 2013067244A JP 2014191846 A5 JP2014191846 A5 JP 2014191846A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- selection
- boost
- supplying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 8
Claims (5)
前記選択回路に前記第１の昇圧信号を供給することができる第１の昇圧信号回路と、
前記選択回路に前記第２の昇圧信号を供給することができる第２の昇圧信号回路と、を有し、
前記第１の昇圧信号回路は、前記選択信号を昇圧して、前記第１の昇圧信号を生成することができるブートストラップ回路を備え、
前記第２の昇圧信号回路は、前記選択信号を昇圧して前記第２の昇圧信号を生成することができるレベルシフタ回路と、クロック信号が供給され高電源電位を昇圧して供給することができるチャージポンプ回路を備える、半導体装置。 A low voltage supplied via a normally closed contact to which a first boost signal supplied via the first rectifier circuit or a second boost signal supplied via the second rectifier circuit or a selection signal is supplied. A selection circuit capable of supplying a power supply potential;
A first boost signal circuit capable of supplying the first boost signal to the selection circuit;
A second boost signal circuit capable of supplying the second boost signal to the selection circuit,
The first boost signal circuit includes a bootstrap circuit capable of boosting the selection signal and generating the first boost signal.
The second boost signal circuit is a level shifter circuit capable of generating the second boost signal by boosting the selection signal, and a charge capable of boosting and supplying a high power supply potential supplied with a clock signal. A semiconductor device including a pump circuit.
前記選択信号の反転信号を供給することができる第１のインバータ回路と、
前記選択信号が供給される前記ブートストラップ回路と、
前記ブートストラップ回路から供給される電位および低電源電位並びに前記反転信号が供給される第２のインバータ回路と、を備える請求項１記載の半導体装置。 The first boost signal circuit includes:
A first inverter circuit capable of supplying an inverted signal of the selection signal;
The bootstrap circuit to which the selection signal is supplied;
The semiconductor device according to claim 1, further comprising: a second inverter circuit to which a potential and a low power supply potential supplied from the bootstrap circuit and the inverted signal are supplied.
第１の電極が前記信号線と電気的に接続され、ゲートが前記第１の昇圧信号または前記第２の昇圧信号を供給することができる配線と電気的に接続され、第２の電極が記憶回路と電気的に接続される選択トランジスタと、を有し、
前記記憶回路は、前記選択トランジスタの前記第２の電極から供給される前記データ信号を記憶する、請求項１または請求項２記載の半導体装置。 A signal line capable of supplying a data signal;
The first electrode is electrically connected to the signal line, the gate is electrically connected to a wiring capable of supplying the first boosted signal or the second boosted signal, and the second electrode is a memory A selection transistor electrically connected to the circuit,
The storage circuit stores the data signals supplied from the second electrode of the selection transistor, the semiconductor device according to claim 1 or claim 2, wherein.
前記クロック信号を前記チャージポンプ回路に供給する第２のステップと、
前記選択信号を、前記第１の昇圧信号回路、前記第２の昇圧信号回路および前記選択回路に前記第１の昇圧信号の電位が前記第２の昇圧信号の電位より高くなる期間に供給する第３のステップと、を有する請求項１乃至請求項４のいずれか一に記載の半導体装置の駆動方法。 A first step of supplying the high power supply potential and the low power supply potential to the first boost signal circuit, the second boost signal circuit, and the selection circuit;
A second step of supplying the clock signal to the charge pump circuit;
The selection signal is supplied to the first boost signal circuit, the second boost signal circuit, and the selection circuit during a period in which the potential of the first boost signal is higher than the potential of the second boost signal. 5. The method for driving a semiconductor device according to claim 1 , comprising three steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013067244A JP6043668B2 (en) | 2013-03-27 | 2013-03-27 | Semiconductor device and driving method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013067244A JP6043668B2 (en) | 2013-03-27 | 2013-03-27 | Semiconductor device and driving method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014191846A JP2014191846A (en) | 2014-10-06 |
| JP2014191846A5 true JP2014191846A5 (en) | 2016-03-31 |
| JP6043668B2 JP6043668B2 (en) | 2016-12-14 |
Family
ID=51837962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013067244A Expired - Fee Related JP6043668B2 (en) | 2013-03-27 | 2013-03-27 | Semiconductor device and driving method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6043668B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0661795B1 (en) * | 1993-12-28 | 1997-07-16 | STMicroelectronics S.r.l. | Voltage booster, particularly for nonvolatile memories |
| JP3413298B2 (en) * | 1994-12-02 | 2003-06-03 | 三菱電機株式会社 | Semiconductor storage device |
| WO2006025081A1 (en) * | 2004-08-30 | 2006-03-09 | Spansion Llc | Semiconductor device and word line boosting method |
| JP5808937B2 (en) * | 2011-04-20 | 2015-11-10 | ラピスセミコンダクタ株式会社 | Internal power supply voltage generation circuit and internal power supply voltage generation method for semiconductor memory |
-
2013
- 2013-03-27 JP JP2013067244A patent/JP6043668B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2016076285A5 (en) | Semiconductor device | |
| JP2013009285A5 (en) | ||
| JP2012079399A5 (en) | ||
| JP2013009308A5 (en) | Semiconductor device | |
| JP2012257197A5 (en) | Semiconductor device | |
| JP2012160708A5 (en) | Method of driving storage element, and storage element | |
| JP2011171703A5 (en) | ||
| JP2012257192A5 (en) | Semiconductor device | |
| JP2015195075A5 (en) | ||
| JP2013008435A5 (en) | ||
| JP2016116220A5 (en) | ||
| EA032788B1 (en) | Scanning drive circuit | |
| JP2011181905A5 (en) | ||
| JP2012257200A5 (en) | Semiconductor device | |
| JP2014064453A5 (en) | Semiconductor device and electronic equipment | |
| JP2011166133A5 (en) | ||
| TW200707381A (en) | Electronic circuit, method of driving electronic circuit, electro-optical device, and electronic apparatus | |
| JP2012256813A5 (en) | Semiconductor device | |
| JP2013251893A5 (en) | Semiconductor device | |
| JP2011086363A5 (en) | ||
| JP2012238028A5 (en) | Method of driving light emitting device | |
| JP2012231462A5 (en) | ||
| EP2517355A4 (en) | Memory device, semiconductor device, and electronic device | |
| EP2526619A4 (en) | Signal processing circuit and method for driving the same | |
| JP2011227981A5 (en) | Semiconductor device |