JP2014168048A - Field effect transistor and method of manufacturing field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor that can relax concentration of an electric field on a source field plate, and also has a high breakdown voltage and high reliability.SOLUTION: A source field plate 17 electrically connected to a source electrode 11 extends over an inter-layer insulation film 23 toward a drain electrode 12 so as to cover a gate electrode 13. The source field plate 17 has an end marginal part on the side of the drain electrode 12 located more on the side of the drain electrode 12 than an end marginal part of the gate electrode 13 on the side of the drain electrode 12, and a boundary face between the inter-layer insulation film 23 and source field plate 17 is a flat plane.

Description

  The present invention relates to a field effect transistor and a method for manufacturing the field effect transistor, and more particularly to a field effect transistor in which a source electrode, a drain electrode, and a gate electrode are formed on a nitride semiconductor layer, and a method for manufacturing the field effect transistor.

  Conventional field effect transistors include those described in Patent Document 1 (Japanese Patent Laid-Open No. 2008-244001) and Patent Document 2 (Japanese Patent Laid-Open No. 2011-249439). In the field effect transistors described in Patent Documents 1 and 2, a source field plate electrically connected to a source electrode is formed on an insulating film so as to cover a gate electrode.

  As a result, the field effect transistor disclosed in Patent Document 1 can improve the breakdown voltage between the gate electrode and the drain electrode, suppress an increase in on-resistance due to a current collapse phenomenon, and reduce a leakage current.

  In the field effect transistor of Patent Document 2, the source field plate is extended to the drain electrode side, a part of the insulating film is opened, and the source field plate is buried in the opening to reduce the parasitic capacitance. ing.

  However, the field effect transistors of Patent Documents 1 and 2 have a problem in that the breakdown voltage with respect to the drain electrode deteriorates due to electric field concentration on the source field plate because the source field plate is close to the drain electrode. Further, in such a field effect transistor, a region where the drain voltage is low (300 V in Patent Document 1 and 60 V in Patent Document 2) is handled, and in a region where the drain voltage is high (for example, 600 V), withstand voltage and There is a problem that the reliability (lifetime) is significantly reduced.

JP 2008-244001A JP 2011-249439 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect transistor that can alleviate electric field concentration on a source field plate and has high breakdown voltage and high reliability.

In order to solve the above problems, the field effect transistor of the present invention is
A nitride semiconductor layer;
A source electrode and a drain electrode formed on or at least part of the nitride semiconductor layer and spaced apart from each other;
A gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
An insulating film formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
An interlayer insulating film formed on at least the insulating film and the gate electrode;
A source field plate electrically connected to the source electrode and extending on the interlayer insulating film toward the drain electrode so as to cover the gate electrode;
The edge of the source field plate on the drain electrode side is closer to the drain electrode than the edge of the gate electrode on the drain electrode side,
The interface between the interlayer insulating film and the source field plate is a flat surface.

In the field effect transistor of one embodiment,
The interlayer insulating film includes at least a first interlayer insulating film formed on the insulating film and the gate electrode, and a second interlayer insulating film formed on the first interlayer insulating film. ,
There is provided a planarizing film having an insulating property between the first interlayer insulating film and the second interlayer insulating film and filling a concave portion of the uneven surface of the first interlayer insulating film.

In the field effect transistor of one embodiment,
The planarization film fills the recesses on the concavo-convex surface of the first interlayer insulation film, whereby the projections of the first interlayer insulation film and the planarization film filling the recesses provide the second interlayer insulation film. The flat surface which touches is formed.

In the field effect transistor of one embodiment,
A contact hole formed on the interlayer insulating film and on the source electrode and the drain electrode;
The planarizing film is provided with a space from the contact hole.

In the field effect transistor of one embodiment,
The contact hole on the source electrode has a tapered surface inclined in the inner direction of the contact hole in a region adjacent to the second interlayer insulating film and is adjacent to the first interlayer insulating film. A region having a plane substantially perpendicular to the plane of the nitride semiconductor layer;
The contact hole on the drain electrode has a tapered surface inclined in the inner direction of the contact hole in a region adjacent to the second interlayer insulating film and is adjacent to the first interlayer insulating film. The region has a plane substantially perpendicular to the plane of the nitride semiconductor layer.

In the field effect transistor of one embodiment,
A third interlayer insulating film formed on the source field plate;
A source wiring layer formed on the source electrode and in the contact hole;
A drain wiring layer formed on the drain electrode and in the contact hole;
A source feeding metal electrically connected to the source electrode through the source wiring layer and extending on the third interlayer insulating film so as to cover at least a part of the source field plate;
A drain feeding metal that is electrically connected to the drain electrode through the drain wiring layer and extends on the third interlayer insulating film so as to cover at least a part of the source field plate;
The interface between the third interlayer insulating film and the source power supply metal and the interface between the third interlayer insulating film and the drain power supply metal are flat surfaces.

In the field effect transistor of one embodiment,
A space between the source field plate and the drain wiring layer is entirely filled with the third interlayer insulating film.

In the field effect transistor of one embodiment,
A gate field plate extending on the insulating film from the top of the gate electrode toward the drain electrode;
The distance in the direction along the plane of the nitride semiconductor layer from the edge portion on the drain electrode side of the gate field plate to the drain electrode or the conductive portion electrically connected to the drain electrode is L1, When the distance in the direction along the plane of the nitride semiconductor layer from the edge on the drain electrode side of the gate field plate to the edge on the drain electrode side of the source field plate is L2,
L2 / L1 ≧ 0.3 or more.

In the method of manufacturing a field effect transistor of the present invention,
A nitride semiconductor layer;
A source electrode and a drain electrode formed on or at least part of the nitride semiconductor layer and spaced apart from each other;
A gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
An insulating film formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
A first interlayer insulating film formed on at least the insulating film and the gate electrode;
A second interlayer insulating film formed on the first interlayer insulating film;
A source field plate electrically connected to the source electrode and extending on the second interlayer insulating film toward the drain electrode so as to cover the gate electrode;
The edge of the source field plate on the drain electrode side is closer to the drain electrode than the edge of the gate electrode on the drain electrode side,
A method of manufacturing a field effect transistor, wherein an interface between the second interlayer insulating film and the source field plate is a flat surface,
Forming the first interlayer insulating film on at least the insulating film and the gate electrode;
Forming a planarizing film on the uneven surface of the first interlayer insulating film;
Removing and flattening the upper side of the planarizing film and the upper side of the convex part of the irregular surface of the first interlayer insulating film;
Forming the second interlayer insulating film on the planarized first interlayer insulating film and on the planarized film.

Further, in the method of manufacturing a field effect transistor of one embodiment,
Forming a first hole portion as an upper portion of a contact hole on the source electrode and the drain electrode by performing wet etching on the second interlayer insulating film using an etching mask;
The lower part of the first hole portion formed on the source electrode and the drain electrode is dry-etched using the etching mask to expose a part of the source electrode and a part of the drain electrode. And a step of forming second hole portions which are the lower portions of the contact holes, respectively.

  As is clear from the above, according to the present invention, the edge of the source field plate on the drain electrode side is located closer to the drain electrode than the edge of the gate electrode on the drain electrode side, and the insulating film and the gate electrode By flattening the interface between the interlayer insulating film formed thereon and the source field plate extending on the interlayer insulating film toward the drain electrode so as to cover the gate electrode, electric field concentration on the gate electrode and Concentration of the electric field on the source field plate is alleviated and a step is eliminated at the interface between the interlayer insulating film and the source field plate, so that problems such as disconnection due to the step are eliminated. Thereby, a field effect transistor having a high breakdown voltage and high reliability can be realized.

FIG. 1 is a schematic plan view of a GaN-based HFET as an example of a field effect transistor according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the GaN HFET as seen from the line II-II in FIG. FIG. 3 is a schematic diagram showing the dimensions of each part of the cross section of the GaN-based HFET shown in FIG. FIG. 4 is a cross-sectional view of the GaN-based HFET as viewed from the line IV-IV in FIG. FIG. 5 is a schematic diagram showing the dimensions of each part of the cross section of the GaN-based HFET shown in FIG. FIG. 6 is a diagram showing the distance from the gate field plate end to the source field plate end of the GaN-based HFET. FIG. 7 is a diagram showing the results of an acceleration test of the GaN HFET. FIG. 8 is a cross-sectional view when the interface between the second interlayer insulating film of the GaN-based HFET and the source field plate is a flat surface. FIG. 9 is a cross-sectional view of the first comparative example when there is a recess having a depth of 240 nm at the interface between the second interlayer insulating film of the GaN-based HFET and the source field plate. FIG. 10 is a cross-sectional view of the second comparative example when there is a 770 nm deep recess at the interface between the second interlayer insulating film of the GaN-based HFET and the source field plate. FIG. 11 is a diagram showing the electric field strength at the end of the source field plate with respect to the depth of the recess at the interface between the second interlayer insulating film and the source field plate. FIG. 12 is a diagram showing the electric field intensity directly below the gate electrode with respect to the depth of the recess at the interface between the second interlayer insulating film and the source field plate. FIG. 13 is a cross-sectional view showing a manufacturing process of a GaN-based HFET as an example of a method for manufacturing a field effect transistor according to the present invention. FIG. 14 is a cross-sectional view showing the manufacturing process subsequent to FIG. FIG. 15 is a cross-sectional view showing the manufacturing process continued from FIG. FIG. 16 is a cross-sectional view showing the manufacturing process continued from FIG. FIG. 17 is a cross-sectional view showing the manufacturing process continued from FIG.

  The field effect transistor of the present invention will be described in detail below with reference to the illustrated embodiments.

[First Embodiment]
FIG. 1 is a schematic plan view of a normally-on type GaN HFET (heterojunction field effect transistor) as an example of the field effect transistor according to the first embodiment of the present invention. In FIG. 1, the source field plate, the source wiring layer, and the drain wiring layer are omitted for easy understanding.

  As shown in FIG. 1, the GaN-based HFET of the first embodiment is formed on a nitride semiconductor layer 10 formed on an Si substrate (not shown) and on the nitride semiconductor layer 10 and is spaced from each other. A source electrode 11 and a drain electrode 12 which are arranged to be open, and a gate electrode 13 formed between the source electrode 11 and the drain electrode 12 and on the nitride semiconductor layer 10 are provided. In FIG. 1, 31 is a source power supply metal electrically connected to the source electrode 11 via a contact portion 31a, and 32 is a drain power supply metal electrically connected to the drain electrode 12 via a contact portion 32a. is there.

  2 shows a cross-sectional view of the GaN-based HFET as viewed from the line II-II in FIG. 1, and FIG. 4 shows a cross-sectional view of the GaN-based HFET as viewed from the line IV-IV in FIG. In FIGS. 2 and 4, the actual dimensions of each part of the cross section of the GaN-based HFET do not match the dimensions on the drawings.

  As shown in FIGS. 2 and 4, a source electrode 11 and a drain electrode 12 made of Ti / Al are formed on the nitride semiconductor layer 10 at a distance from each other. A gate electrode 13 made of TiN is formed between the source electrode 11 and the drain electrode 12 on the nitride semiconductor layer 10 and on the source electrode 11 side.

  The nitride semiconductor layer 10 includes an undoped GaN layer 101 and an undoped AlGaN layer 102 that are sequentially formed on a Si substrate (not shown). 2DEG (two-dimensional electron gas) is generated at the interface between the undoped GaN layer 101 and the undoped AlGaN layer 102.

  The substrate is not limited to the Si substrate, and a sapphire substrate or SiC substrate may be used. A nitride semiconductor layer may be grown on the sapphire substrate or SiC substrate, or an AlGaN layer is grown on the GaN substrate. As described above, a nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor. Further, a buffer layer may be appropriately formed between the substrate and each layer. Further, an AlN layer having a thickness of about 1 nm may be formed as a hetero improvement layer between the undoped GaN layer 101 and the undoped AlGaN layer 102. Further, a GaN cap layer may be formed on the AlGaN layer 102.

  Here, the thickness of the undoped AlGaN layer 102 of the nitride semiconductor layer 10 is set to 10 nm, for example, and the source electrode 11 and the drain electrode 12 are annealed to enable ohmic contact. The thickness of the undoped AlGaN layer may be set to 30 nm, for example, and the ohmic contact portion of the undoped AlGaN layer may be preliminarily Si-doped so as to be n-type to enable ohmic contact of the electrode. Also, an ohmic contact is possible by forming a recess in the region of the undoped AlGaN layer where the source electrode is to be formed and the region where the drain electrode is to be formed, and depositing and annealing the source electrode and the drain electrode in this recess. It is good.

  The gate electrode 13 is in Schottky junction with the undoped AlGaN layer 102 of the nitride semiconductor layer 10.

  Further, a collapse suppression film 14 for suppressing current collapse is formed on the nitride semiconductor layer 10 between the source electrode 11 and the gate electrode 13 and between the drain electrode 12 and the gate electrode 13.

  For example, AlN can be used for the collapse suppression film 14. However, the single crystal AlN film is desirably polycrystalline or amorphous because it affects the two-dimensional electron gas.

Alternatively, a compound based on SiO ₂ or SiO such as SiO ₂ , SiOC, or SiON can be used for the collapse suppression film 14.

  Alternatively, the collapse suppression film 14 can be made of a Si-rich silicon nitride film. This Si-rich silicon nitride film is an SiN film having a Si Si ratio larger than that of a stoichiometric silicon nitride film of Si: N = 0.75: 1. For example, the composition ratio Si between Si and N : N = 1.1 to 1.9: 1, more preferably Si: N composition ratio Si: N = 1.3 to 1.5: 1.

In addition, an insulating film 15 made of stoichiometric SiN film is formed on the collapse suppression film 14. In the first embodiment, as an example, the insulating film 15 is made of a stoichiometric SiN film. However, for example, other oxide films such as a SiON film, a SiO ₂ film, an Al ₂ O ₃ film, and an AlN film are used. You may produce by.

  The gate electrode 13 includes a base portion 13a that is in Schottky junction with the undoped AlGaN layer 102 of the nitride semiconductor layer 10 and a gate field plate 13b that extends on the insulating film 15 from the base portion 13a toward the drain electrode 12 side. .

  The GaN-based HFET includes a first interlayer insulating film 21 formed on the insulating film 15 and the gate electrode 13, and a second interlayer insulating film 23 formed on the first interlayer insulating film 21. And a planarizing film 22 having an insulating property between the first interlayer insulating film 21 and the second interlayer insulating film 23 and filling the concave portion of the uneven surface of the first interlayer insulating film 21.

As a requirement of the planarizing film 22,
(i) Insulator
(ii) Even if the bottom surface is uneven, the top surface can be easily flattened.
(iii) Desirably, a material whose dielectric constant does not change greatly with respect to the material facing the lower surface (uneven shape side) of the planarizing film (unnecessary electric field concentration at the uneven shape). (Because it does not happen)
There is.

  In the first embodiment, SOG (Spin On Glass) satisfying the above (i) to (iii) is used, but a CMP (Chemical Mechanical Polish) method is used. Also good. Further, the material of the planarizing film depends on surrounding substances, but may be polyimide, BPSG (Boron Phosphorus Silicon Glass), or the like.

  The GaN-based HFET has a source wiring layer 16 electrically connected to the source electrode 11, and extends from the source wiring layer 16 toward the drain electrode 12 so as to cover the gate electrode 13, and the second interlayer And a source field plate 17 extending on the insulating film 23. The edge of the source field plate 17 on the drain electrode 12 side is closer to the drain electrode 12 than the edge of the gate electrode 13 on the drain electrode 12 side. The interface between the second interlayer insulating film 23 and the source field plate 17 is a flat surface.

  The GaN HFET has a drain wiring layer 18 electrically connected to the drain electrode 12, and extends from the drain wiring layer 18 toward the source electrode 11, and slightly over the second interlayer insulating film 23. And an extended drain field plate 19. The drain field plate 19 may be omitted.

  A third interlayer insulating film 24 is formed on the source field plate 17 and the drain field plate 19 so as to fill between the source field plate 17 and the drain field plate 19. In addition, a planarizing film 25 is formed in the third interlayer insulating film 24.

  A source power supply metal 31 (shown in FIG. 4) electrically connected to the source electrode 11 through the source wiring layer 16 covers the third interlayer insulating film 24 so as to cover a part of the source field plate 17. Extend to. A third interlayer insulating film is formed so that a drain feeding metal 32 (shown in FIG. 2) electrically connected to the drain electrode 12 through the drain wiring layer 18 covers a part of the source field plate 17. 24 extends over.

  The interface between the third interlayer insulating film 24 and the source power supply metal 31 and the interface between the third interlayer insulating film 24 and the drain power supply metal 32 are flat surfaces. A space between the source field plate 17 and the drain field plate 19 is filled with a third interlayer insulating film 24. If there is no drain field plate 19, the third interlayer insulating film 24 is completely filled between the source field plate 17 and the drain wiring layer 18.

  3 shows the dimensions of each part of the cross section of the GaN HFET shown in FIG. 2, and FIG. 5 shows the dimensions of each part of the cross section of the GaN HFET shown in FIG. As shown in FIGS. 3 and 5, the thickness of the lower planarizing film 22 is substantially dependent on the thickness of the gate field plate 13b of the gate electrode 13 (20 nm in this first embodiment), and the upper planarizing film 22 is flat. The film thickness of the chemical film 25 substantially depends on the thickness of the source field plate 17 (1.7 μm in the first embodiment).

  FIG. 6 shows a distance L2 from the end of the gate field plate 13b to the end of the source field plate 17 of the GaN HFET. In FIG. 6, L1 is the distance along the plane of the nitride semiconductor layer 10 from the edge of the gate field plate 13b on the drain electrode 12 side to the drain field plate 19, and L2 is the end of the gate field plate 13b ( The distance in the direction along the plane of the nitride semiconductor layer 10 from the end of the drain electrode 12 to the end of the source field plate 17 (the end of the drain electrode 12).

  In the first embodiment, the distance in the direction along the plane of the nitride semiconductor layer 10 from the edge of the gate field plate 13b on the drain electrode 12 side to the drain field plate 19 is L1, but the drain field In the absence of the plate 19, the distance between the end of the source field plate 17 and the drain wiring layer 18 that is closest to the end of the source field plate 17 and connected to the drain electrode 12. In the present invention, the drain field plate, the drain wiring layer, and the like are conductive portions that are electrically connected to the drain electrode.

  Here, FIG. 7 shows the result of the acceleration test of the GaN-based HFET performed at the distance L2 of 2 μm and 3 μm. In FIG. 7, the horizontal axis represents the life [time], and the vertical axis represents the number of failures / total number × 100 [%].

  This acceleration test was performed in a GaN-based HFET configured as shown in FIGS. 1 to 5 with an ambient temperature of 200 ° C., a source voltage of 0 V, a gate voltage of −10 V, and a drain voltage of 600 V.

  As shown in FIG. 7, the life when the number of failures when the distance L2 is 2 μm is 50% is 75 hours, and the number of failures when the distance L2 is 3 μm is 50%. The lifetime was 550 hours. That is, the lifetime of the GaN HFET having the distance L2 of 3 μm is increased by 7.3 times (≈550 / 75) as compared with the GaN HFET having the distance L2 of 2 μm.

  Next, FIG. 8 shows a cross-sectional view when the interface between the second interlayer insulating film 23 of the GaN-based HFET and the source field plate 17 is a flat surface. In FIG. 8, the same components as those shown in FIG. 2 are denoted by the same reference numerals. A1 is an electric field strength measurement region at the end of the source field plate 17 (an edge portion on the drain electrode 12 side), and B1 is an electric field strength measurement region immediately below the gate electrode 13.

  FIG. 9 is a cross-sectional view of the first comparative example when there is a recess having a depth of 240 nm at the interface between the second interlayer insulating film 123 of the GaN-based HFET and the source field plate 17. In FIG. 9, a buried portion 17 a is formed below the end of the source field plate 17 (the edge on the drain electrode 12 side) so as to fill the recess at the interface between the second interlayer insulating film 123 and the source field plate 17. ing. 9, the same components as those shown in FIG. 2 are denoted by the same reference numerals. A2 is an electric field strength measurement region at the end of the source field plate 17, and B2 is an electric field strength measurement region directly under the gate electrode 13.

  FIG. 10 shows a cross-sectional view of the second comparative example when the interface between the second interlayer insulating film 123 of the GaN-based HFET and the source field plate 17 has a recess having a depth of 770 nm. In FIG. 10, a buried portion 17 b is formed below the end of the source field plate 17 (the edge on the drain electrode 12 side) so as to fill the recess at the interface between the second interlayer insulating film 123 and the source field plate 17. ing. 10, the same components as those shown in FIG. 2 are given the same reference numerals. A3 is an electric field strength measurement region at the end of the source field plate 17, and B3 is an electric field strength measurement region directly under the gate electrode 13.

  The GaN HFETs of the first and second comparative examples shown in FIGS. 9 and 10 are for comparison with the present invention and are not field effect transistors of the present invention.

  FIG. 11 shows the electric field strength at the end of the source field plate 17 and the embedded portions 17a and 17b with respect to the depth of the recess at the interface between the second interlayer insulating films 23 and 123 of the GaN-based HFET and the source field plate 17. (Marked with ◆). Here, a silicon nitride film is used as the collapse suppression film 14 and the insulating film 15 of the GaN-based HFET.

  As shown in FIG. 11, as the interface between the second interlayer insulating films 23 and 123 and the source field plate 17 is flattened, the electric field strength at the end of the source field plate 17 is relaxed, and the breakdown voltage and reliability are improved. To do.

  FIG. 12 shows the electric field intensity directly below the gate electrode 13 with respect to the depth of the recess at the interface between the second interlayer insulating films 23 and 123 of the GaN-based HFET and the source field plate 17 (■ mark). Here, a silicon nitride film is used as the collapse suppression film 14 and the insulating film 15 of the GaN-based HFET.

  As shown in FIG. 12, the electric field intensity directly below the gate electrode 13 hardly changes regardless of whether the interface between the second interlayer insulating films 23 and 123 and the source field plate 17 is flattened or not. No change occurs.

  Next, a manufacturing process of a GaN-based HFET will be described with reference to FIGS. 13 to 17, the same reference numerals are assigned to the same components as those of the GaN HFET shown in FIGS. 1 to 5.

  In this manufacturing method, the flattening film formed on the first interlayer insulating film 21 is entirely etched, and the upper side of the convex portion of the uneven surface of the first interlayer insulating film 21 is removed and planarized. To do.

  First, an undoped GaN layer 101 and an undoped AlGaN layer 102 are formed in this order on a Si substrate (not shown) using MOCVD (metal organic chemical vapor deposition).

  Next, a silicon nitride film to be the collapse suppression film 14 is formed on the undoped AlGaN layer 102 by plasma CVD.

  This current collapse is particularly prominent in a GaN-based semiconductor element, and is a phenomenon in which the on-resistance of a transistor in a high voltage operation is significantly higher than the on-resistance of the transistor in a low voltage operation. .

  Thereafter, an SiN film to be the insulating film 15 is formed on the collapse suppression film 14 by plasma CVD (chemical vapor deposition).

  Next, by performing dry etching using a photoresist as a mask, a region in which the source electrode 11 and the drain electrode 12 are to be formed in the silicon nitride film to be the collapse suppression film 14 and the SiN film to be the insulating film 15, and The region where the base portion 13a of the gate electrode 13 is to be formed is removed, and the undoped AlGaN layer 102 is exposed in this region.

  Next, the photoresist is removed, and the collapse suppression film 14 is heat-treated (for example, at 500 ° C. for 30 minutes).

  Thereafter, TiN is sputtered over the entire surface, an etching mask (not shown) is formed in the gate electrode formation region where the gate electrode 13 is to be formed by photolithography, and dry etching or wet etching is performed using this etching mask to form the gate. The TiN film other than the electrode formation region is removed to form the gate electrode 13 made of TiN. The base portion 13 a of the gate electrode 13 is Schottky joined to the AlGaN layer 102.

  Next, a resist pattern (not shown) is formed in regions where the source electrode 11 and the drain electrode 12 are to be formed by photolithography, Ti and Al are sequentially deposited on the resist pattern, and Ti / Al is formed by lift-off. A source electrode 11 and a drain electrode 12 are formed.

  Next, the source electrode 11 and the drain electrode 12 are heat-treated (ohmic annealing) to form ohmic electrodes (for example, at 500 ° C. for 30 minutes).

Next, as shown in FIG. 13, a first interlayer insulating film 21 made of SiO ₂ is formed on the insulating film 15 and on the source electrode 11, the drain electrode 12, and the gate electrode 13, and the first interlayer insulating film is formed. An SOG film 122 to be the planarizing film 22 is formed on the film 21. Then, the entire SOG film 122 is etched.

  Next, as shown in FIG. 14, the planarization film 22 that fills the recesses on the uneven surface of the first interlayer insulating film 21 is formed by etching the SOG film 122 shown in FIG. 13.

Next, as shown in FIG. 15, a SiO ₂ film 123 is formed on the first interlayer insulating film 21. As a result, a planarizing film 22 is formed between the first interlayer insulating film 21 and the second interlayer insulating film 23 so as to fill the recesses on the uneven surface of the first interlayer insulating film 21. Then, the SiO ₂ film 123 is wet etched using the etching mask 110.

Next, as shown in FIG. 16, by wet etching of the SiO ₂ film 123 using an etching mask 110 shown in FIG. 15, the SiO ₂ film 123 on the upper source electrode 11 and drain electrode 12, the contact hole 200 (FIG. The first hole portions 201 which are upper portions of (shown in FIG. 17) are respectively formed. Then, dry etching is performed on the lower side of the first hole portion 201 formed on the source electrode 11 and the drain electrode 12 using the etching mask 110.

Then, as shown in FIG. 17, a part of the source electrode 11 and a part of the drain electrode 12 are exposed by dry etching of the SiO ₂ film 123 using the etching mask 110 shown in FIG. Second hole portions 202 to be lower portions are formed respectively. Thereby, contact holes 200 are formed on the source electrode 11 and the drain electrode 12, respectively.

  In the first hole portion 201 of the contact hole 200, a tapered surface 201 a that is inclined toward the inner side of the contact hole 200 is provided in a region adjacent to the second interlayer insulating film 23. In the second hole portion 202 of the contact hole 200, a surface 202 a that is substantially perpendicular to the plane of the nitride semiconductor layer 10 is provided in a region adjacent to the first interlayer insulating film 21.

  According to the GaN-based HFET having the above configuration, the edge of the source field plate 17 on the drain electrode 12 side is closer to the drain electrode 12 side than the edge of the gate electrode on the drain electrode 12 side, and the insulating film (14, 15) An interlayer insulating film (21, 23) formed on the gate electrode 13 and a source extending on the interlayer insulating film (21, 23) toward the drain electrode 12 so as to cover the gate electrode 13 By flattening the interface with the field plate 17, the electric field concentration on the gate electrode 13 and the electric field concentration on the source field plate 17 are alleviated. Furthermore, since there is no step at the interface between the interlayer insulating films (21, 23) and the source field plate 17, problems such as disconnection due to the step are solved. As a result, a GaN-based HFET having a high breakdown voltage and high reliability can be realized.

  Further, the planarization having an insulating property so as to fill the concave portion of the uneven surface of the first interlayer insulating film 21 between the first interlayer insulating film 21 and the second interlayer insulating film 23 of the interlayer insulating film. By forming the film 22, overetching by the planarizing film 22 using SOG or the like can be prevented, and the second interlayer insulating film 23 is laid on the planarizing film 22, thereby Adhesion can be improved.

  Further, by bringing the first interlayer insulating film 21 under the planarizing film 22 into contact with the second interlayer insulating film 23 on the planarizing film 22, the first and second interlayer insulating films 21, The adhesion between the 23 can be improved.

  In addition, since the planarizing film 22 is provided at a distance from the contact hole 200, the etching in the lateral direction can be prevented when the contact hole 200 is etched.

  Further, in the contact hole 200 on the source electrode 11 and the contact hole 200 on the drain electrode 12, a tapered surface 201 a that is inclined toward the inner side of the contact hole 200 is provided in a region adjacent to the second interlayer insulating film 23. Thus, disconnection due to a step is prevented. Further, in the contact hole 200 on the source electrode 11 and the contact hole 200 on the drain electrode 12, a surface 202 a substantially perpendicular to the plane of the nitride semiconductor layer 10 is formed in a region adjacent to the first interlayer insulating film 21. By providing, when the contact hole 200 is etched, the film between the first interlayer insulating film 21 below the planarizing film 22 and the second interlayer insulating film 23 on the planarizing film 22 can be prevented from peeling off or a step difference. .

  Further, by flattening the interface between the third interlayer insulating film 24 and the source power supply metal 31, the electric field concentration on the source power supply metal 31 is alleviated, and the third interlayer insulating film 24 and the drain power supply metal are reduced. By flattening the interface with 32, the electric field concentration on the drain feeding metal 32 is relaxed, and the reliability (life) of the withstand voltage and the reverse bias characteristic is further improved.

  In addition, since the space between the source field plate 17 and the drain wiring layer 18 is entirely filled with the third interlayer insulating film 24, a uniform potential distribution can be obtained and expansion / contraction due to temperature change is less likely to occur. , Improve product yield.

  Further, the drain electrode of the gate field plate 13b with respect to the distance L1 in the direction along the plane of the nitride semiconductor layer 10 from the edge of the gate field plate 13b on the drain electrode 12 side to the drain electrode 12 shown in FIG. By setting the ratio of the distance L2 in the direction along the plane of the nitride semiconductor layer 10 from the edge on the 12 side to the edge on the drain electrode 12 side of the source field plate 17 to 0.3 or more, reliability is improved. (Life) is further improved.

  Further, according to the method of manufacturing the GaN-based HFET having the above configuration, the first interlayer insulating film 21 under the planarizing film 22 and the second interlayer insulating film 23 on the planarizing film 22 are brought into contact with each other. The adhesion between the first and second interlayer insulating films 21 and 23 can be improved, and a GaN-based HFET having a high breakdown voltage and high reliability can be realized.

  Further, by preventing the interface between the first interlayer insulating film 21 below the planarizing film 22 and the second interlayer insulating film 23 on the planarizing film 22 from being exposed to wet etching, the interface is transmitted through the interface. The lateral etching of the planarizing film 22 can be prevented.

[Second Embodiment]
In the GaN-based HFET of the first embodiment, the silicon nitride film (SiN _x ) is used as the collapse suppression film 14 and the insulating film 15, whereas as an example of the field effect transistor of the second embodiment of the present invention. In the normally-on type GaN HFET, polycrystalline AlN was used as the collapse suppression film 14 and SiO ₂ was used as the insulating film 15. The GaN-based HFET of the second embodiment has the same configuration as the GaN-based HFET of the first embodiment except for the composition of the collapse suppression film 14 and the insulating film 15.

  The field strength results of the field effect transistor according to the second embodiment are indicated by Δ in FIGS.

In the GaN-based HFET of the second embodiment, as shown in FIGS. 11 and 12, the same result as that of the GaN-based HFET of the first embodiment is obtained, and the polycrystalline AlN used as the collapse suppression film 14 is obtained. It was also clarified that SiO ₂ used as the insulating film 15 has the same function as the SiN _x film.

In the first and second embodiments, the nitride semiconductor layer is composed of a GaN layer and an AlGaN layer, but Al _x In _y Ga _1-xy N (x ≧ 0, y ≧ 0, 0 ≦ x + y <1). It is also possible to include a GaN-based semiconductor layer represented by: That is, the GaN-based semiconductor layer may contain AlGaN, GaN, InGaN, or the like. In the first and second embodiments, the normally-on type HFET has been described. However, the normally-off type can achieve the same effect.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the first and second embodiments, and various modifications can be made within the scope of the present invention.

  That is, the present invention and the embodiment are summarized as follows.

The field effect transistor of this invention is
A nitride semiconductor layer 10;
A source electrode 11 and a drain electrode 12 formed on or in the nitride semiconductor layer 10 at least partially and spaced apart from each other;
A gate electrode 13 formed between the source electrode 11 and the drain electrode 12 and on the nitride semiconductor layer 10;
Insulating films (14, 15) formed on the nitride semiconductor layer 10 between the source electrode 11 and the gate electrode 13 and between the drain electrode 12 and the gate electrode 13;
An interlayer insulating film (21, 23) formed on at least the insulating film (14, 15) and the gate electrode 13;
A source field plate 17 electrically connected to the source electrode 11 and extending on the interlayer insulating film (21, 23) toward the drain electrode 12 so as to cover the gate electrode 13,
The edge of the source field plate 17 on the drain electrode 12 side is closer to the drain electrode 12 than the edge of the gate electrode 13 on the drain electrode 12 side,
The interface between the interlayer insulating films (21, 23) and the source field plate 17 is a flat surface.

  According to the above configuration, since the edge of the source field plate 17 on the drain electrode 12 side is closer to the drain electrode 12 than the edge of the gate electrode 13 on the drain electrode 12 side, electric field concentration on the gate electrode 13 is achieved. And the interlayer insulating film (21, 23) formed on the insulating films (14, 15) and the gate electrode 13 and the interlayer insulating film toward the drain electrode 12 so as to cover the gate electrode 13 By flattening the interface with the source field plate 17 extending on (21, 23), the electric field concentration on the source field plate 17 is alleviated. In addition, since there is no step at the interface between the interlayer insulating films (21, 23) and the source field plate 17, problems such as disconnection due to the step are solved. Thereby, a field effect transistor having a high breakdown voltage and high reliability can be realized.

In the field effect transistor of one embodiment,
The interlayer insulating film includes at least a first interlayer insulating film 21 formed on the insulating films (14, 15) and the gate electrode 13, and a second interlayer insulating film formed on the first interlayer insulating film 21. Interlayer insulating film 23, and
A planarizing film 22 having an insulating property is provided between the first interlayer insulating film 21 and the second interlayer insulating film 23 and fills the concave portion of the uneven surface of the first interlayer insulating film 21.

  According to the embodiment, the insulating property is provided so that the concave portion of the uneven surface of the first interlayer insulating film 21 is filled between the first interlayer insulating film 21 and the second interlayer insulating film 23 of the interlayer insulating film. By forming the flattening film 22 having, over-etching by the flattening film 22 using SOG or the like can be prevented, and the second interlayer insulating film 23 is laid on the flattening film 22, so that the source field Adhesion with the plate 17 can be improved.

In the field effect transistor of one embodiment,
The flattening film 22 fills the concave portions of the concave and convex surfaces of the first interlayer insulating film 21, whereby the convex portions of the first interlayer insulating film 21 and the flattening film 22 filling the concave portions are used for the second. A flat surface in contact with the interlayer insulating film 23 is formed.

  According to the embodiment, the first interlayer insulating film 21 under the planarizing film 22 and the second interlayer insulating film 23 on the planarizing film 22 are brought into contact with each other, whereby the first and second interlayers are contacted. The adhesion between the insulating films 21 and 23 can be improved.

In the field effect transistor of one embodiment,
A contact hole 200 formed on the interlayer insulating film and on the source electrode 11 and the drain electrode 12;
The planarizing film 22 is provided with a space from the contact hole 200.

  According to the embodiment described above, the planarization film 22 is provided at a distance from the contact hole 200, so that when the contact hole 200 is etched, lateral etching can be prevented.

In the field effect transistor of one embodiment,
The contact hole 200 on the source electrode 11 has a tapered surface 201a inclined in the inner direction of the contact hole 200 in a region adjacent to the second interlayer insulating film 23, and the first interlayer A region adjacent to the insulating film 21 has a surface 202a substantially perpendicular to the plane of the nitride semiconductor layer 10;
The contact hole 200 on the drain electrode 12 has a tapered surface 201a inclined in the inner direction of the contact hole 200 in a region adjacent to the second interlayer insulating film 23, and the first interlayer A region 202 a that is substantially perpendicular to the plane of the nitride semiconductor layer 10 is provided in a region adjacent to the insulating film 21.

  According to the above embodiment, in the contact hole 200 on the source electrode 11 and the contact hole 200 on the drain electrode 12, the taper that inclines toward the inner side of the contact hole 200 in the region adjacent to the second interlayer insulating film 23. By providing the surface 201a, disconnection due to a step is prevented, and a nitride semiconductor is formed in a region adjacent to the first interlayer insulating film 21 in the contact hole 200 on the source electrode 11 and the contact hole 200 on the drain electrode 12. By providing a surface 202 a substantially perpendicular to the plane of the layer 10, the first interlayer insulating film 21 below the planarizing film 22 and the second interlayer on the planarizing film 22 when the contact hole 200 is etched. Film peeling from the insulating film 23 and step defects can be prevented.

In the field effect transistor of one embodiment,
A third interlayer insulating film 24 formed on the source field plate 17,
A source wiring layer 16 formed on the source electrode 11 and in the contact hole 200;
A drain wiring layer 18 formed on the drain electrode 12 and in the contact hole 200;
A source feeding metal 31 that is electrically connected to the source electrode 11 through the source wiring layer 16 and extends on the third interlayer insulating film 24 so as to cover at least a part of the source field plate 17. When,
A drain feeding metal 32 that is electrically connected to the drain electrode 12 through the drain wiring layer 18 and extends on the third interlayer insulating film 24 so as to cover at least a part of the source field plate 17. And
The interface between the third interlayer insulating film 24 and the source power supply metal 31 and the interface between the third interlayer insulating film 24 and the drain power supply metal 32 are flat surfaces.

  According to the above embodiment, by flattening the interface between the third interlayer insulating film 24 and the source power supply metal 31, the electric field concentration on the source power supply metal 31 is alleviated, and the third interlayer insulating film 24. By flattening the interface between the drain feeding metal 32 and the drain feeding metal 32, the electric field concentration on the drain feeding metal 32 is alleviated, and the reliability (life) of the withstand voltage and the reverse bias characteristic is further improved.

In the field effect transistor of one embodiment,
A space between the source field plate 17 and the drain wiring layer 18 is completely filled with the third interlayer insulating film 24.

  According to the above embodiment, since the space between the source field plate 17 and the drain wiring layer 18 is entirely filled with the third interlayer insulating film 24, a uniform potential distribution can be obtained, and expansion / expansion due to a temperature change can be obtained. Shrinkage is unlikely to occur, improving the product yield.

In the field effect transistor of one embodiment,
A gate field plate 13b extending on the insulating film (14, 15) from the upper part of the gate electrode 13 toward the drain electrode 12 side;
In the direction along the plane of the nitride semiconductor layer 10 from the edge of the gate field plate 13b on the drain electrode 12 side to the drain electrode 12 or a conductive portion electrically connected to the drain electrode 12 The distance is L1, and the direction along the plane of the nitride semiconductor layer 10 from the edge of the gate field plate 13b on the drain electrode 12 side to the edge of the source field plate 17 on the drain electrode 12 side When the distance is L2,
L2 / L1 ≧ 0.3 or more.

  According to the above embodiment, the drain of the gate field plate 13b with respect to the distance L1 in the direction along the plane of the nitride semiconductor layer 10 from the edge on the drain electrode 12 side of the gate field plate 13b to the drain electrode 12 is described. By setting the ratio of the distance L2 in the direction along the plane of the nitride semiconductor layer 10 from the edge on the electrode 12 side to the edge on the drain electrode 12 side of the source field plate 17 to be 0.3 or more, (Life) is further improved.

In the method of manufacturing a field effect transistor of the present invention,
A nitride semiconductor layer 10;
A source electrode 11 and a drain electrode 12 formed on or in the nitride semiconductor layer 10 at least partially and spaced apart from each other;
A gate electrode 13 formed between the source electrode 11 and the drain electrode 12 and on the nitride semiconductor layer 10;
Insulating films (14, 15) formed on the nitride semiconductor layer 10 between the source electrode 11 and the gate electrode 13 and between the drain electrode 12 and the gate electrode 13;
A first interlayer insulating film 21 formed on at least the insulating films (14, 15) and the gate electrode 13,
A second interlayer insulating film 23 formed on the first interlayer insulating film 21;
A source field plate 17 electrically connected to the source electrode 11 and extending on the second interlayer insulating film 23 toward the drain electrode 12 so as to cover the gate electrode 13;
The edge of the source field plate 17 on the drain electrode 12 side is closer to the drain electrode 12 than the edge of the gate electrode 13 on the drain electrode 12 side,
A method of manufacturing a field effect transistor in which an interface between the second interlayer insulating film 23 and the source field plate 17 is a flat surface,
Forming the first interlayer insulating film 21 on at least the insulating films (14, 15) and the gate electrode 13;
Forming a planarization film 22 on the uneven surface of the first interlayer insulating film 21;
Removing and flattening the upper side of the planarizing film 22 and the upper side of the convex part of the irregular surface of the first interlayer insulating film 21;
Forming the second interlayer insulating film 23 on the planarized first interlayer insulating film 21 and the planarized film 22.

  According to the above configuration, a field effect transistor with high breakdown voltage and high reliability can be realized.

Further, in the method of manufacturing a field effect transistor of one embodiment,
By wet-etching the second interlayer insulating film 23 using the etching mask 110, the first hole portion 201 that is the upper portion of the contact hole 200 is formed on the source electrode 11 and the drain electrode 12, respectively. Process,
The lower part of the first hole portion 201 formed on the source electrode 11 and the drain electrode 12 is dry-etched using the etching mask 110, so that a part of the source electrode 11 and the drain electrode are formed. 12 is exposed to form a second hole portion 202 that becomes the lower portion of the contact hole 200.

  According to the embodiment, the interface between the first interlayer insulating film 21 below the planarizing film 22 and the second interlayer insulating film 23 on the planarizing film 22 is not exposed to wet etching, so that The lateral etching of the planarizing film 22 along the interface can be prevented.

DESCRIPTION OF SYMBOLS 10 ... Nitride semiconductor layer 11 ... Source electrode 12 ... Drain electrode 13 ... Gate electrode 13a ... Base part 13b ... Gate field plate 14 ... Collapse suppression film 15 ... Insulating film 16 ... Source wiring layer 17 ... Source field plate 17a, 17b ... Embedded Portion 18 ... Drain wiring layer 19 ... Drain field plate 21 ... First interlayer insulating film 22 ... Planarizing film 23, 123 ... Second interlayer insulating film 24 ... Third interlayer insulating film 25 ... Planarizing film 31 ... Source Feed metal 31a ... Contact portion 32 ... Drain feed metal 32a ... Contact portion 101 ... Undoped GaN layer 102 ... Undoped AlGaN layer 110 ... Etching mask 200 ... Contact hole 201 ... First hole portion 201a ... Tapered surface 202 ... Second hole portion 202a ... substantially vertical surface

Claims (5)

A nitride semiconductor layer;
A source electrode and a drain electrode formed on or at least part of the nitride semiconductor layer and spaced apart from each other;
A gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
An insulating film formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
An interlayer insulating film formed on at least the insulating film and the gate electrode;
A source field plate electrically connected to the source electrode and extending on the interlayer insulating film toward the drain electrode so as to cover the gate electrode;
The edge of the source field plate on the drain electrode side is closer to the drain electrode than the edge of the gate electrode on the drain electrode side,
A field effect transistor, wherein an interface between the interlayer insulating film and the source field plate is a flat surface. The field effect transistor according to claim 1.
The interlayer insulating film includes at least a first interlayer insulating film formed on the insulating film and the gate electrode, and a second interlayer insulating film formed on the first interlayer insulating film. ,
An electric field effect characterized by comprising a planarizing film having an insulating property between the first interlayer insulating film and the second interlayer insulating film and filling a concave portion of the uneven surface of the first interlayer insulating film Transistor. The field effect transistor according to claim 2.
The planarization film fills the recesses on the concavo-convex surface of the first interlayer insulation film, whereby the projections of the first interlayer insulation film and the planarization film filling the recesses provide the second interlayer insulation film. A field effect transistor, characterized in that a flat surface in contact with is formed. The field effect transistor according to claim 2 or 3,
A contact hole formed on the interlayer insulating film and on the source electrode and the drain electrode;
The field effect transistor according to claim 1, wherein the planarizing film is provided at a distance from the contact hole. A nitride semiconductor layer;
A source electrode and a drain electrode formed on or at least part of the nitride semiconductor layer and spaced apart from each other;
A gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
An insulating film formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
A first interlayer insulating film formed on at least the insulating film and the gate electrode;
A second interlayer insulating film formed on the first interlayer insulating film;
A source field plate electrically connected to the source electrode and extending on the second interlayer insulating film toward the drain electrode so as to cover the gate electrode;
The edge of the source field plate on the drain electrode side is closer to the drain electrode than the edge of the gate electrode on the drain electrode side,
A method of manufacturing a field effect transistor, wherein an interface between the second interlayer insulating film and the source field plate is a flat surface,
Forming the first interlayer insulating film on at least the insulating film and the gate electrode;
Forming a planarizing film on the uneven surface of the first interlayer insulating film;
Removing and flattening the upper side of the planarizing film and the upper side of the convex part of the irregular surface of the first interlayer insulating film;
And a step of forming the second interlayer insulating film on the planarized first interlayer insulating film and the planarized film.

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