JP2014165339A - Method of processing laminated wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of processing a laminated wafer, capable of highly accurately flattening a sealing resin.SOLUTION: The method of processing a laminated wafer including a wafer and a plurality of chips respectively laminated in regions on a surface of the wafer, which are defined by a plurality of scheduled division lines intersecting each other, includes: a sealing step of sealing the surface side of the laminated wafer with a sealing resin; and a polishing step of flattening the sealing resin by polishing it with a polishing pad while supplying a polishing slurry containing abrasive grains to the sealing resin surface of the laminated wafer after performing the sealing step.

Description

  The present invention relates to a method for processing a laminated wafer in which a plurality of chips are arranged on a wafer.

  In the manufacturing process of semiconductor devices, devices such as ICs and LSIs are formed in each region partitioned by dividing lines called streets on the surface of the semiconductor wafer. Then, individual semiconductor devices are manufactured by dividing the semiconductor wafer into chips along the planned dividing lines. The semiconductor device manufactured in this way is widely used in various electric appliances.

  In recent years, along with miniaturization and thinning of electrical equipment, semiconductor device packages are also required to be miniaturized and thin, and higher density of packaging is required. One technique for integrating a plurality of semiconductor devices in one package is a three-dimensional mounting in which a plurality of semiconductor device chips are stacked in the vertical direction and mounted.

  In conventional three-dimensional packaging, wire bonding is used to connect between semiconductor device chips or between a semiconductor device chip and an interposer. In connection by wire bonding, inductance and the like increase by the length of the wiring, so that there is a problem that it is not suitable for high-speed signal exchange, and it is necessary to stack chips so that wires do not touch semiconductor device chips and the like Therefore, there are problems such as difficulty in miniaturization.

  In recent years, as a new three-dimensional mounting technique, a mounting technique using a through-silicon via (TSV) instead of a wire has attracted attention. When the TSV technology is used, since the wiring length is shorter than that of the wire, the wiring resistance and inductance can be greatly reduced, and the power consumption can be greatly reduced.

  On the other hand, as a method for laminating semiconductor device chips, the following laminating techniques are being developed. The first stacking method is a stacking method in which a plurality of semiconductor device wafers are stacked, a through electrode passing through the stacked semiconductor device wafers is formed, and the wafers are connected to each other (Wafer on Wafer: WOW).

  The second stacking method is a method of mounting individual semiconductor device chips on a semiconductor device wafer via bumps (Chip on Wafer: COW). Individual laminated device chips are manufactured by dividing a wafer laminated by these lamination methods.

  In the COW method, in order to protect the semiconductor device chip stacked on the semiconductor device wafer, the semiconductor device chip stacked on the semiconductor device wafer is sealed with a sealing resin. Thereafter, the device on the semiconductor device wafer and the semiconductor device chip are connected by a Si through electrode (TSV).

  Furthermore, wiring connected to the semiconductor device chip and / or the semiconductor device on the semiconductor device wafer is formed on the sealing resin surface. If necessary, a new semiconductor device wafer or semiconductor device chip is stacked on the semiconductor device chip stacked on the first semiconductor device wafer.

JP 2012-209522 A JP 2009-095903 A

  In order to form the wiring layer on the resin sealing surface, the top surface of the sealing resin needs to be flat. However, for example, even if the sealing resin is ground using a grinding apparatus as disclosed in Patent Document 2, scratches and the like are formed on the surface to be ground of the sealing resin, and it is difficult to flatten the surface. is there.

  The present invention has been made in view of these points, and an object of the present invention is to provide a method for processing a laminated wafer that can planarize a sealing resin with high accuracy.

  According to the present invention, there is provided a method for processing a laminated wafer, comprising: a wafer; and a plurality of chips respectively laminated on each region on the surface of the wafer partitioned by a plurality of intersecting scheduled lines. A sealing step for sealing the surface side of the laminated wafer with a sealing resin, and after performing the sealing step, a polishing pad containing abrasive grains is supplied to the sealing resin surface of the laminated wafer with a polishing pad. And a polishing step for polishing and flattening the sealing resin.

  Preferably, in the method for processing a laminated wafer according to the present invention, after the sealing step is performed, before the polishing step is performed, a grinding liquid not containing abrasive grains is supplied to the sealing resin surface of the laminated wafer. However, the method further includes a grinding step of thinning the sealing resin to a predetermined thickness by grinding the sealing resin surface with a grinding means having a grinding wheel.

  In the method for processing a laminated wafer according to the present invention, since the sealing resin is polished with the polishing pad while supplying the polishing slurry containing abrasive grains to the sealing resin surface, no scratch is formed on the sealing resin surface. The sealing resin surface can be flattened with high accuracy.

  According to the second aspect of the present invention, since the sealing resin is thinned to a predetermined thickness by grinding before the polishing step is performed, the thickness of the laminated chip can be reduced, and the thickness is reduced to the predetermined thickness by grinding. By setting, processing time can be shortened compared with processing only by polishing.

It is a perspective view of a laminated wafer. It is sectional drawing explaining a sealing step. It is a partial cross section side view which shows a grinding step. It is a partial cross section side view which shows a grinding | polishing step.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, a perspective view of a laminated wafer 11 according to an embodiment of the present invention is shown. The laminated wafer 11 is bonded to the semiconductor device wafer 13 in which semiconductor devices 15 such as ICs and LSIs are formed in each region partitioned by a plurality of intersecting scheduled lines 5, and the semiconductor devices 15 of the semiconductor device wafer 13. And a plurality of semiconductor device chips 17 fixed by an agent or the like.

  As shown in the cross-sectional view of FIG. 2, each semiconductor device chip 17 has a semiconductor device 19 on its surface. The semiconductor device wafer 13 has a front surface 13a on which a plurality of semiconductor devices 15 are formed and a back surface 13b.

  In the laminated wafer processing method of the present invention, first, as shown in FIG. 2, a sealing step of sealing the surface side of the laminated wafer 11 with a sealing resin 21 is performed. An organic resin such as an epoxy resin can be used as the sealing resin 21. Alternatively, a sealing resin in which an inorganic filler is dispersed in an organic resin may be used.

  After performing the sealing step, a grinding step is performed in which the sealing resin surface is ground by a grinding unit (grinding means) having a grinding wheel to thin the sealing resin to a predetermined thickness. This grinding step will be described with reference to FIG.

  In FIG. 3, reference numeral 10 denotes a grinding unit (grinding means) of the grinding apparatus. The grinding unit 10 includes a spindle 12 that is rotationally driven by a motor, a wheel mount 14 fixed to the tip of the spindle 12, and a wheel mount 14. And a mounted grinding wheel 16. The grinding wheel 16 is configured by a plurality of grinding wheels 20 fixed to the lower end of an annular base 18.

  In this grinding step, the semiconductor device wafer 13 side of the laminated wafer 11 is sucked and held by the chuck table 22 of the grinding apparatus to expose the sealing resin 21. While supplying a grinding liquid such as pure water containing no abrasive grains from the grinding liquid supply nozzle 24 onto the surface of the sealing resin 21 of the laminated wafer 11, the chuck table 22 is rotated in the direction of arrow a at 300 rpm, for example. While rotating the wheel 16 in the arrow b direction at 6000 rpm, a grinding unit feeding mechanism (not shown) is operated to bring the grinding wheel 20 into contact with the surface of the sealing resin 21.

  Then, the grinding wheel 16 is ground by a predetermined amount at a predetermined grinding feed speed, and the sealing resin 21 is ground. The sealing resin 21 is ground to a desired thickness while measuring the thickness of the laminated wafer 11 with a contact or non-contact thickness gauge.

  When the sealing resin 21 is ground, scratches or the like may be formed on the surface of the sealing resin 21 to be ground, and sufficient flatness of the surface to be ground cannot be obtained. Therefore, in the method for processing a laminated wafer according to the present invention, after performing the grinding step, the polishing step of polishing the ground surface of the sealing resin 21 with the polishing pad is performed.

  This polishing step is performed by chemical mechanical polishing (CMP) using a polishing unit 26 as shown in FIG. In FIG. 4, the polishing unit 26 includes a spindle 28 that is rotationally driven, a wheel mount 30 that is fixed to the tip of the spindle 28, and a polishing wheel 32 that is attached to the wheel mount 30.

  The polishing wheel 32 is configured by bonding a polishing pad 36 such as a nonwoven fabric to the lower end portion of a base 34. Slurry supply holes are formed across the base 28 of the spindle 28, the wheel mount 30 and the polishing wheel 32.

  In the polishing step, the semiconductor device wafer 13 side of the laminated wafer 11 is sucked and held by the chuck table 38 of the polishing apparatus to expose the sealing resin 21 that has been ground. While supplying the slurry to the polishing pad 36 through the slurry supply hole of the polishing wheel 32, the chuck table 38 is rotated in the direction of arrow a, and the polishing pad 36 of the polishing wheel 32 is brought into contact with the grinding surface of the sealing resin 21. Then, the polishing surface of the sealing resin 21 is polished while the polishing wheel 32 is rotated in the direction of the arrow b to flatten the sealing resin 21.

  As the slurry supplied to the polishing pad 36, for example, pure water mixed with silica, ceria, alumina, zirconia or the like as abrasive grains is used. When this polishing step is performed, even if scratches are formed on the ground surface of the sealing resin 21 by grinding, the scratches can be removed by polishing, and the surface of the sealing resin 21 can be flattened with high accuracy. .

  After planarizing the sealing resin 21 by CMP, a Si through electrode (TSV) is formed to connect the semiconductor device 15 of the semiconductor device wafer 13 and the semiconductor device 19 of the semiconductor device chip 17. Further, a wiring is formed on the sealing resin 21.

  When the new semiconductor device chip or the semiconductor device wafer is stacked corresponding to the semiconductor device chip 17 stacked on the semiconductor device wafer 13, the wiring is connected to the stacked semiconductor device chip or the device of the semiconductor device wafer. Used to connect the semiconductor devices 15 and 19 on the side.

  In the embodiment described above, the semiconductor device chip is laminated on each semiconductor device of the semiconductor device wafer to constitute the laminated wafer. However, the laminated wafer is not limited to this, and the interposer wafer having no device is used. This includes a semiconductor device chip stacked thereon.

DESCRIPTION OF SYMBOLS 10 Grinding unit 11 Laminated wafer 15 Semiconductor device 16 Grinding wheel 17 Semiconductor device chip 19 Semiconductor device 20 Grinding wheel 21 Sealing resin 26 Polishing unit 32 Polishing wheel 36 Polishing pad

Claims (2)

A method for processing a laminated wafer, comprising: a wafer; and a plurality of chips each laminated on each area on the surface of the wafer divided by a plurality of intersecting scheduled lines,
A sealing step of sealing the surface side of the laminated wafer with a sealing resin;
After carrying out the sealing step, a polishing step for polishing and planarizing the sealing resin with a polishing pad while supplying a polishing slurry containing abrasive grains to the sealing resin surface of the laminated wafer;
A method for processing a laminated wafer, comprising: After performing the sealing step and before performing the polishing step,
While supplying a grinding liquid not containing abrasive grains to the sealing resin surface of the laminated wafer, the sealing resin surface is ground to a predetermined thickness by grinding the sealing resin surface with a grinding means having a grinding wheel. The method for processing a laminated wafer according to claim 1, further comprising a grinding step.

Images