JP2014003083A - Photodiode array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photodiode array capable of obtaining high opening ratio and preventing degradation of a bandwidth and an S/N ratio.SOLUTION: On a primary surface of an n-type InP substrate 1, a plurality of linear photodiodes 2 are parallelly arranged spaced apart from one another in a plan view facing the primary surface of the n-type InP substrate 1. Buried layers 12 are buried between the plurality of photodiodes 2. An isolation groove 13 having a V-shaped cross section is provided in each buried layer 12. A metal mirror 14 is provided on an inclined surface of the isolation groove 13. The metal mirror 14 reflects incident light incident from a rear surface of the n-type InP substrate 1 to guide the incident light to each light absorption layer 4 of the plurality of photodiodes 2. The bandgap of the buried layer 12 is wider than that of the light absorption layer 4.

Description

  The present invention relates to a photodiode array capable of realizing a large aperture ratio.

  One of the semiconductor light receiving elements is a photodiode. A photodiode is an element that detects light by applying a reverse bias voltage to a pn junction and taking out electron-hole pairs (photocarriers) generated by light incidence as current. An avalanche photodiode is a light-receiving element having a light absorption layer and an avalanche multiplication layer. Since it uses carrier multiplication by avalanche multiplication, it is possible to realize a higher sensitivity element than a photodiode. Is possible. The photodiode array is a plurality of photodiodes or avalanche photodiodes arranged one-dimensionally or two-dimensionally in a plane, and is used for a large-area optical sensor or the like.

  As an avalanche photodiode, there has been proposed an avalanche photodiode in which a concave portion is formed in a multiplication layer to provide a p-type diffusion region and an avalanche breakdown is caused at the center of the p-type diffusion region (see, for example, Patent Document 1). Thereby, edge breakdown due to electric field concentration at the end of the p-type diffusion region can be prevented. However, the formation of the recesses complicates the process and may cause variations in device characteristics. In addition, there has also been proposed a technique in which edge breakdown is suppressed by preventing an electrode and a multiplication layer from being adjacent to each other and further providing an electric field relaxation layer (see, for example, Patent Document 2).

  A photodiode in which a comb-type Schottky electrode is provided on a light absorption layer has been proposed (see, for example, Patent Document 3). However, since the light is received in a narrow depletion region formed near the electrode and cannot be received outside the depletion region and in a region shielded by the electrode, the aperture ratio is small.

  There has been proposed a photodiode in which a p-type layer epitaxially grown to have a mesa structure by etching instead of selectively forming a p-type region (see, for example, Patent Document 4). However, the pn junction interface is exposed on the side surface of the mesa, and there is a concern about reliability. Further, since the electrodes are wired in a matrix, the chip area is increased.

  A photodiode array has been proposed in which a light shielding film is provided to prevent deterioration of characteristics due to stray light incident between the arrays (see, for example, Patent Document 5). However, since current is injected from the p-type electrode disposed at the end of the light receiving region, the electric field is not uniformly applied at a position away from the electrode due to a voltage drop, and the band may be deteriorated. In addition, since the elements are not electrically separated, there is a risk of electrical crosstalk.

  In a front-illuminated photodiode array in which the arrays are not electrically separated (for example, see Patent Document 6), there is a risk of electrical crosstalk. Further, there is a concern that a slow response component is generated by the stray light incident between the arrays, the band is deteriorated, and the S / N ratio is lowered. In order to prevent this, it has been proposed to prevent the signal light from entering other than the light receiving portion by using a light shielding metal (see, for example, Patent Documents 5, 7, and 8) and to collect light in the opening by the light shielding metal. (For example, refer to Patent Document 9).

  In the back-illuminated photodiode array, since there is no electrode on the light incident surface, a high aperture ratio can be obtained as compared with the front-illuminated type (see, for example, Patent Document 10). However, a separation groove is formed for element isolation, and the area of the light receiving region is reduced by the amount of the separation groove, and the aperture ratio is lowered. The width of the separation groove needs to be narrowed in order to suppress the decrease in the aperture ratio, but it is difficult to make the width below a certain level because side etching occurs, and the bottom of the separation groove is covered with a surface protective film as the width is narrower There is concern about reliability because it is difficult. In addition, since a pn junction interface exists on the side surface of the separation groove formed by etching, there is a concern about reliability.

  On the other hand, it has been proposed to provide a light reflecting layer on the slope of the separation groove having a V-shaped cross section (see, for example, Patent Document 11). The light incident on the separation groove is reflected by the light reflection layer and guided to the light absorption layer. Accordingly, since the light incident on the separation groove can also contribute to the photocurrent, a high aperture ratio can be obtained.

JP 62-033482 A JP 2010-135360 A JP 2000-101130 A JP 2001-119004 A Japanese Patent Laid-Open No. 2002-1000079 JP 2009-38157 A JP 63-2111686 A JP-A-3-276769 JP 2007-281144 A JP 2007-281266 A Japanese Patent Laid-Open No. 62-36858

  In Patent Document 11, light is absorbed even in the p-HgCdTe layer provided in the separation groove region, and photocarriers are generated. Since the separation groove region is separated from the n-HgCdTe region electrically connected to the n-side electrode, the electric field applied to the separation groove region is weak. Accordingly, the photocarrier generated in the separation groove region moves by diffusion and appears as a component having a slow response speed. For this reason, there is a concern that the bandwidth is deteriorated. In addition, since this slow response component is superimposed at the bottom, there is a concern that the S / N ratio is deteriorated.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a photodiode array capable of obtaining a high aperture ratio and preventing deterioration in bandwidth and S / N ratio. Is what you get.

  A photodiode array according to the present invention includes a substrate, a plurality of photodiodes arranged in parallel and spaced apart from each other on the main surface of the substrate, and linear in a plan view facing the main surface of the substrate; An embedding layer embedded between a plurality of photodiodes and provided with an isolation groove having a V-shaped cross section, and provided on the slope of the isolation groove, reflects incident light incident from the back surface of the substrate to reflect the plurality of the plurality of photodiodes. And a first metal mirror led to the light absorption layer of the photodiode, wherein the band gap of the buried layer is wider than the band gap of the light absorption layer.

  According to the present invention, a high aperture ratio can be obtained, and deterioration of the band and S / N ratio can be prevented.

FIG. 1 is a plan view showing a photodiode array according to Embodiment 1 of the present invention. It is sectional drawing in alignment with I-II of FIG. It is the top view to which the area | region A of FIG. 1 was expanded. 6 is a cross-sectional view showing a photodiode array according to Comparative Example 1. FIG. 6 is a cross-sectional view showing a photodiode array according to Comparative Example 2. FIG. It is sectional drawing which shows the photodiode array which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the photodiode array which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the photodiode array which concerns on Embodiment 4 of this invention. It is a top view which shows the photodiode array which concerns on Embodiment 5 of this invention. It is a top view which shows the photodiode array which concerns on Embodiment 6 of this invention. It is the top view to which the area | region A of FIG. 10 was expanded. It is the top view to which the area | region B of FIG. 10 was expanded. It is a top view which shows the photodiode array which concerns on Embodiment 7 of this invention. It is a top view which shows the photodiode array which concerns on Embodiment 8 of this invention. It is a top view which shows the photodiode array which concerns on Embodiment 9 of this invention. It is sectional drawing along III-IV of FIG.

  A photodiode array according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view showing a photodiode array according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along the line I-II in FIG. FIG. 3 is an enlarged plan view of region A in FIG. On the main surface of the n-type InP substrate 1, a plurality of photodiodes 2 that are linear in a plan view facing the main surface of the n-type InP substrate 1 are arranged in parallel and spaced apart from each other.

In each photodiode 2, on the main surface of the n-type InP substrate 1, an n-type InP buffer layer 3, an undoped InGaAs light absorption layer 4 having a thickness of 2 μm to 3 μm, an undoped InP window layer 5 having a thickness of 1 μm to 2 μm, And the InGaAs contact layer 6 is laminated | stacked in order. A p-type impurity region 7 is provided in a part of the undoped InP window layer 5. The n-type InP substrate 1 has an impurity concentration of about 5 × 10 ¹⁸ cm ⁻³ and the p-type impurity region 7 has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

  A linear p-side electrode 8 made of Ti / Au or the like is provided on the InGaAs contact layer 6 and is electrically connected to the p-type impurity region 7 through the InGaAs contact layer 6. A surface protective film 9 made of SiN (silicon nitride) covers the undoped InP window layer 5. An n-side electrode 10 made of AuGe / Au is electrically connected to the back surface of the n-type InP substrate 1.

  The width w of the p-side electrode 8 is 5 μm. The distance a between the p-side electrode 8 and the outer end of the p-type impurity region 7 is 14.5 μm. The length b of the p-type impurity region 7 in the extending direction of the p-side electrode 8 is longer than the width c of the p-type impurity region 7. The p-type impurity region 7 is a rectangle or a rounded rectangle in plan view. The p-side electrode 8 extends in the long side direction of the p-type impurity region 7. The p-side electrode 8 is connected to an electrode pad 11 disposed on a region other than the p-type impurity region 7 of the undoped InP window layer 5. The connection portion between the p-side electrode 8 and the electrode pad 11 crosses the short side of the p-type impurity region 7. The p-side electrode 8 has no corners and is rounded.

  A buried layer 12 fills between the plurality of photodiodes 2. The buried layer 12 is provided with a separation groove 13 having a V-shaped cross section. A metal mirror 14 is provided on the slope of the separation groove 13. The material of the metal mirror 14 is Ti, Au, Ta, or a laminate of them.

  The metal mirror 14 reflects incident light incident from the back surface of the n-type InP substrate 1 and guides it to the light absorption layers 4 of the plurality of photodiodes 2. The incident light is, for example, light having a wavelength λ of 1.55 μm. The buried layer 12 is semi-insulating InP doped with Fe or Ru, and the band gap of the buried layer 12 is wider than the band gap of the light absorption layer 4.

  Next, a method for manufacturing the photodiode array according to the first embodiment of the present invention will be briefly described. First, an n-type InP buffer layer 3, an undoped InGaAs light absorption layer 4, an undoped InP window layer 5, and an InGaAs contact layer 6 are formed on the n-type InP substrate 1 using MOCVD (Metal Organic Chemical Vapor Deposition) method or the like. Epitaxial growth is performed sequentially.

  Next, the p-type impurity region 7 is formed by diffusing Zn into a part of the undoped InP window layer 5 to a depth reaching the light absorption layer 4. As a diffusion method, vapor phase diffusion or thermal diffusion using a mask or the like is used. For example, when thermal diffusion is performed, a SiN film (not shown) is formed on the undoped InP window layer 5, and an opening is formed in the SiN film in a region where the p-type impurity region 7 is formed. A diffusion source such as a ZnO film (not shown) is formed on the opening and the SiN film, and heat treatment is performed for a predetermined time using the SiN film as a mask. Note that impurities such as Cd and Be may be used instead of Zn.

Next, after removing the SiN film and the ZnO film, the InGaAs contact layer 6 is formed.
Next, after forming a vertical mesa by wet or dry etching, a semi-insulating semiconductor material having a wider band gap than the light absorption layer 4 is embedded and grown to fill the mesa portion, and the embedded layer 12 is formed.

  Next, in the buried layer 12, an isolation groove 13 for electrically isolating the photodiodes 2 is formed. At this time, the cross section of the separation groove 13 becomes V-shaped by using an etching solution whose etching rate in the direction parallel to the main surface of the n-type InP substrate 1 exceeds the etching rate in the direction perpendicular to the main surface. .

  Next, a surface protective film 9 that also functions as an antireflection film is formed on the surface of the undoped InP window layer 5 by plasma CVD or the like. An opening is formed in the surface protective film 9 at a location where the p-side electrode 8 is to be formed by combining photolithography technology and etching using hydrofluoric acid or the like. Next, a photoresist (not shown) is provided on the surface protective film 9 and patterned to form an opening in the photoresist immediately above the opening of the surface protective film 9 and in a region where the metal mirror 14 is to be formed. .

  Next, after forming a Ti / Au film by electron beam (EB) vapor deposition, an unnecessary portion of the Ti / Au film is lifted off together with a photoresist to form the p-side electrode 8 and the metal mirror 14. At this time, an electrode pad 11 connected to the p-side electrode 8 is simultaneously formed on the surface protective film 9. Thereafter, the back surface of the n-type InP substrate 1 is polished to form the n-side electrode 10. The photodiode array according to the first embodiment is manufactured through the above steps.

  Subsequently, the operation of the photodiode array according to the first embodiment will be described. When a bias voltage is applied from the outside so that the n-side electrode 10 is positive and the p-side electrode 8 is negative, a depletion layer 15 is formed. In this state, incident light incident from the back surface of the n-type InP substrate 1 passes through the n-type InP substrate 1 and is absorbed by the light absorption layer 4 to generate electron-hole pairs (photocarriers). Due to the electric field in the depletion layer 15, electrons move to the n-side electrode 10, and holes move toward the p-side electrode 8, whereby a current flows. Thereby, incident light can be detected as an electric current.

  Next, the effect of the first embodiment will be described in comparison with Comparative Examples 1 and 2. FIG. 4 is a cross-sectional view showing a photodiode array according to Comparative Example 1. In Comparative Example 1, the photodiodes 2 are separated by the separation groove 16 in order to prevent crosstalk between the photodiodes 2. The isolation groove 16 is not provided with the buried layer 12 or the metal mirror 14. For this reason, in Comparative Example 1, light incident on the separation groove 16 is not absorbed by the light absorption layer 4 and cannot contribute to the photocurrent. Accordingly, the aperture ratio is reduced by the width of the separation groove 16.

  On the other hand, in the first embodiment, the light incident on the separation groove 13 is reflected by the first metal mirror 14 formed on the V-shaped slope and guided to the light absorption layer 4. Therefore, the light incident on the separation groove 13 can also contribute to the photocurrent, so that a high aperture ratio can be obtained.

  FIG. 5 is a cross-sectional view showing a photodiode array according to Comparative Example 2. In Comparative Example 2, the photodiodes 2 are separated by the separation groove 13, and the metal mirror 14 is provided on the slope of the separation groove 13. Therefore, the light incident on the separation groove 13 can also contribute to the photocurrent, so that a high aperture ratio can be obtained. However, in Comparative Example 2, the light absorption layer 4 is provided up to the separation groove region. Since the separation groove region is separated from the p-type impurity region 7, the electric field applied to the separation groove region is weak. Accordingly, the photocarrier generated in the separation groove region moves by diffusion and appears as a component having a slow response speed. For this reason, there is a concern that the bandwidth is deteriorated. In addition, since this slow response component is superimposed at the bottom, there is a concern that the S / N ratio is deteriorated.

  On the other hand, in the first embodiment, the isolation trench region is buried with the buried layer 12, and the band gap of the buried layer 12 is wider than the band gap of the light absorption layer 4. For this reason, incident light reflected by the metal mirror 14 contributes to the generation of photo carriers only after reaching the light absorption layer 4, and no photo carrier is generated in the separation groove region. Therefore, since it is possible to prevent the generation of a slow response component, it is possible to prevent the deterioration of the band and the S / N ratio.

  Further, by using a material having a wide band gap as the buried layer 12, it is possible to reduce the leakage current through the midgap level at the interface between the surface protective film 9 and the buried layer 12, so that the S / N ratio and reliability can be reduced. Can be improved.

  The buried layer 12 is preferably a semi-insulating semiconductor. Thereby, since the isolation trench region has a high resistance, the region through which the current flows is limited, and the leakage current can be reduced.

  In addition, it is preferable that the width of the InGaAs contact layer 6 is widened so that the distance between the InGaAs contact layer 6 and the outer end of the p-type impurity region 7 is, for example, 1 to 5 μm. Thereby, since the resistance between the p-type impurity region 7 and the p-side electrode 8 is reduced, the series resistance of the photodiode can be reduced and the band can be improved.

The impurity concentration of the p-type impurity region 7 is preferably 1 × 10 ¹⁹ cm ⁻³ or more. Thereby, since the resistance of the p-type impurity region 7 is lowered, an electric field can be uniformly applied to the p-type impurity region 7. As a result, in-plane non-uniformity of the bandwidth and multiplication factor can be suppressed.

Embodiment 2. FIG.
FIG. 6 is a cross-sectional view showing a photodiode array according to Embodiment 2 of the present invention. A metal mirror 17 is provided on the upper surface of each of the plurality of photodiodes 2. Other configurations and manufacturing methods are the same as those in the first embodiment.

  The metal mirror 17 reflects incident light transmitted through the light absorption layer 4 and guides it to the light absorption layer 4 again. For this reason, the light receiving sensitivity can be improved. Further, if the light receiving sensitivity is made constant due to the effect of the metal mirror 17, the light absorption layer 4 can be made thin, so that the band can be improved.

Embodiment 3 FIG.
FIG. 7 is a sectional view showing a photodiode array according to Embodiment 3 of the present invention. Between the n-type InP buffer layer 3 and the light absorption layer 4, an avalanche multiplication layer 18 made of undoped AlInAs having a thickness of 0.15 μm to 0.4 μm, and a p-type InP electric field having a thickness of 0.03 μm to 0.06 μm. A relaxation layer 19 is provided. The impurity concentration of the p-type InP electric field relaxation layer 19 is 0.5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The photodiodes 2 are separated by a separation groove 13 formed from the surface of the epitaxial growth layer to a depth penetrating the avalanche multiplication layer 18. Other configurations and manufacturing methods are the same as those in the first embodiment.

  Subsequently, the operation of the photodiode array according to the second embodiment will be described. When a bias voltage is applied from the outside so that the n-side electrode 10 is positive and the p-side electrode 8 is negative, a depletion layer 15 is formed. In this state, incident light incident from the back surface of the n-type InP substrate 1 passes through the n-type InP substrate 1, n-type InP buffer layer 3, avalanche multiplication layer 18, and p-type InP electric field relaxation layer 19 to absorb light. It is absorbed in the layer 4 to generate electron-hole pairs. Due to the electric field in the depletion layer 15, electrons move toward the n-side electrode 10 and holes move toward the p-side electrode 8. When the bias voltage is sufficiently high, electrons in the avalanche multiplication layer 18 cause impact ionization to generate new electron-hole pairs, and positive feedback that causes the newly generated electrons and holes to cause further impact ionization occurs. . As a result, avalanche multiplication in which electrons and holes multiply like an avalanche occurs, and carriers are multiplied. As a result, it operates as a highly sensitive photodetecting element.

  Thus, since the plurality of photodiodes 2 are avalanche photodiodes, the sensitivity can be improved as compared with the first embodiment. Further, by providing the p-type InP electric field relaxation layer 19, edge breakdown can be prevented and uniform light receiving characteristics can be obtained. However, an AlInAs electric field relaxation layer may be used instead of the p-type InP electric field relaxation layer 19.

  It should be noted that the electric field concentration at the corner of the p-type impurity region 7 can be avoided by making the p-type impurity region 7 rounded rectangular and eliminating the corner. Further, similarly to the second embodiment, a metal mirror 17 may be provided on the upper surface of each of the plurality of photodiodes 2.

Embodiment 4 FIG.
FIG. 8 is a sectional view showing a photodiode array according to Embodiment 4 of the present invention. A semi-insulating InP substrate 20 doped with Fe or Ru is used instead of the n-type InP substrate 1 of the first embodiment, and an n-type InP contact layer 21 is inserted between the n-type InP buffer layer 3 and the light absorption layer 4. doing. The n-side electrode 10 is connected to the n-type InP contact layer 21. Other configurations and manufacturing methods are the same as those in the first embodiment. Thus, since the light absorption in a board | substrate can be reduced by using the semi-insulating InP board | substrate 20, the light quantity which injects into the light absorption layer 4 increases, and a light reception sensitivity can be improved.

Embodiment 5 FIG.
FIG. 9 is a plan view showing a photodiode array according to Embodiment 5 of the present invention. However, only one photodiode 2 is extracted and shown. The p-type impurity region 7 has a rectangular region 7a that is rectangular in plan view, and two semicircular regions 7b that are respectively joined to two short sides of the rectangular region 7a. Thus, by joining the semicircular region 7b to the rectangular region 7a and eliminating the corner, electric field concentration at the corner of the p-type impurity region 7 can be avoided, and uniform light receiving characteristics can be obtained. .

Embodiment 6 FIG.
FIG. 10 is a plan view showing a photodiode array according to Embodiment 6 of the present invention. However, only one photodiode 2 is extracted and shown. A semicircular electrode 22 is arranged on the semicircular p-type impurity region 7b. The semicircular electrode 22 is connected to the p-side electrode 8. Most of the semicircular p-type impurity region 7 b other than the end portion is shielded by the semicircular electrode 22, and the central portion of the rectangular region 7 a is also shielded by the p-side electrode 8. As a result, two rectangular impurity regions having a uniform band and multiplication factor in the plane can be realized.

  FIG. 11 is an enlarged plan view of region A in FIG. FIG. 12 is an enlarged plan view of region B in FIG. The p-side electrode 8 and the semicircular electrode 22 have no corners. As a result, electric field concentration at the corners of the p-side electrode 8 and the semicircular electrode 22 can be avoided, and edge breakdown and uneven light receiving characteristics can be avoided.

Embodiment 7 FIG.
FIG. 13 is a plan view showing a photodiode array according to Embodiment 7 of the present invention. However, only one photodiode 2 is extracted and shown. The p-side electrode 8 is connected to two different electrode pads 11. The electrode pad 11 is disposed on a region other than the p-type impurity region 7 of the undoped InP window layer 5. There are only two places where the connection portions of the p-side electrode 8 and the two electrode pads 11 cross the p-type impurity region 7. By injecting current from the two electrode pads 11 in this way, the in-plane electric field can be made uniform, and uniform multiplication characteristics can be obtained.

Embodiment 8 FIG.
FIG. 14 is a plan view showing a photodiode array according to the eighth embodiment of the present invention. A separation groove 13 and a metal mirror 14 are provided so as to surround the entire outer periphery of each photodiode 2. Thereby, electrical crosstalk between the photodiodes 2 can be further reduced.

Embodiment 9 FIG.
FIG. 15 is a plan view showing a photodiode array according to the ninth embodiment of the present invention. 16 is a cross-sectional view taken along the line III-IV in FIG. In the ninth embodiment, when the separation groove 13 is formed by etching in the fourth embodiment, the region where the electrode pad 11 is provided is etched.

  In the fourth embodiment, the electrode pad 11 and the n-type InP contact layer 21 have a capacitance proportional to the area of the electrode pad 11 with the light absorption layer 4 and the undoped InP window layer 5 interposed therebetween. On the other hand, according to the tenth embodiment, since the capacitance of the electrode pad 11 can be eliminated, the device capacitance can be reduced and the band can be improved.

1 n-type InP substrate (substrate)
2 Photodiode 4 Light absorption layer 12 Buried layer 13 Separation groove 14 Metal mirror (first metal mirror)
17 Metal mirror (second metal mirror)
20 Semi-insulating InP substrate (substrate)

Claims (5)

A substrate,
A plurality of photodiodes arranged in parallel and spaced apart from each other on the main surface of the substrate, and linear in a plan view facing the main surface of the substrate;
A buried layer embedded between the plurality of photodiodes and provided with a V-shaped separation groove in cross section;
A first metal mirror provided on the slope of the separation groove, and reflecting incident light incident from the back surface of the substrate and guiding it to the light absorption layers of the plurality of photodiodes;
The photodiode array according to claim 1, wherein a band gap of the buried layer is wider than a band gap of the light absorption layer.   The photodiode array according to claim 1, wherein the buried layer is a semi-insulating semiconductor.   3. The photodiode array according to claim 1, further comprising a second metal mirror provided on an upper surface of each of the plurality of photodiodes and configured to reflect the incident light and guide the light to the light absorption layer. .   The photodiode array according to claim 1, wherein the plurality of photodiodes are avalanche photodiodes.   The photodiode array according to claim 1, wherein the substrate is a semi-insulating substrate.

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