JP2014089996A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which can effectively inhibit the outflow of an underfill agent and effectively inhibit the occurrence of a void between connection terminals.SOLUTION: A wiring board according to the present embodiment in which a plurality of connection terminals with a semiconductor chip are formed on a laminate in which an insulation layer and a conductor layer are layered comprises: a solder resist layer provided on the laminate, in which a first opening having an outer edge at a position surrounding a mounting region of the semiconductor chip, and a second opening which exposes the connection terminals in the mounting region and has a bottom face at a position lower than a top edge of the connection terminals are formed.

Description

  The present invention relates to a wiring board having a plurality of connection terminals for connecting a semiconductor chip to a main surface.

  When a semiconductor chip (also referred to as a die) is mounted on a wiring board, the semiconductor chip is connected to electrodes on the wiring board by solder balls or the like. However, when a stress such as a temperature cycle, impact, or bending is applied after mounting, the connection reliability between the semiconductor chip and the wiring board may not be ensured. As a preventive measure, a sealing resin (underfill agent) is put in the gap between the semiconductor chip and the wiring board to relieve stress and reinforce to prevent falling off.

  By the way, many liquid compositions having high fluidity are used for the underfill agent in order to fill the gap between the semiconductor chip and the wiring board without any gap. However, if the fluidity of the underfill agent is high, the underfill agent may flow out from the vicinity of the periphery of the semiconductor chip and adhere to a conductor circuit disposed in the vicinity of the periphery of the semiconductor chip.

  Therefore, in order to prevent the underfill agent from flowing out from the vicinity of the periphery of the semiconductor chip, it is proposed to form a step that prevents the underfill agent from spreading over the portion where the semiconductor chip is mounted and the vicinity of the outside of the outer edge. There are some (see, for example, Patent Document 1).

JP 2001-244384 A

  By the way, in recent years, the density of the connection terminals has been increased, and the interval (pitch) between the connection terminals to be arranged has been narrowed. For this reason, a wiring board that employs NSMD (non-solder mask-defined) in which a plurality of connection terminals are arranged in the same opening of the solder resist has been proposed. When a plurality of connection terminals are arranged in the same opening at a narrow pitch, there is a possibility that the solder coated on the surface of the connection terminal flows out to the adjacent connection terminals and the connection terminals are short-circuited.

  However, in the invention disclosed in Patent Document 1, although it is possible to prevent the underfill agent from flowing out, it is difficult to prevent the generation of voids between the connection terminals. Further, it is impossible to prevent the solder coated on the connection terminal from flowing out to the adjacent connection terminal.

  The present invention has been made in response to the above-described circumstances, and provides a wiring board that can effectively suppress the outflow of an underfill agent and can effectively suppress the generation of voids between connection terminals. Objective.

In order to achieve the above object, the inventive substrate of the present invention comprises:
A wiring board in which a plurality of connection terminals with a semiconductor chip are formed on a laminate in which an insulating layer and a conductor layer are laminated, and a first opening having an outer edge at a position surrounding a mounting region of the semiconductor chip; A solder resist layer having a second opening that forms a bottom surface at a position lower than an upper end of the connection terminal is exposed on the stacked body while exposing the connection terminal in the mounting region. And

  According to the present invention, since the first opening having the outer edge is formed in the solder resist layer at the position surrounding the semiconductor chip mounting area, the underfill agent is prevented from flowing out of the semiconductor chip mounting area. can do. In addition, the solder resist layer is exposed to the connection terminal in the mounting region, and the second opening for forming the bottom surface is formed at a position lower than the upper end of the connection terminal, so that the wiring board is connected to the semiconductor chip. In this case, it is possible to suppress the generation of voids between the connection terminals of the underfill agent that fills the gap between the semiconductor chip and the wiring board. Furthermore, it is possible to suppress the solder coated on the connection terminals from flowing out to the adjacent connection terminals, and to suppress a short circuit between the connection terminals.

Note that in one embodiment of the present invention,
The solder resist layer is characterized in that the surface roughness of the wall surface and the bottom surface defining the first opening is rougher than the surface roughness outside the first opening.

  According to one aspect of the present invention, the surface roughness of the wall surface and the bottom surface defining the first opening is rougher than the surface roughness outside the first opening. For this reason, the underfill agent tends to spread inside the first opening, and the underfill agent hardly spreads outside the first opening. As a result, the underfill agent is easily filled in the gap between the wiring board and the semiconductor chip, and generation of voids can be suppressed. In addition, the underfill agent can be more effectively suppressed from flowing out of the semiconductor chip mounting area.

In another aspect of the present invention,
The surface roughness of the wall surface and the bottom surface that defines the first opening and the surface roughness of the wall surface and the bottom surface that define the second opening are substantially the same.

  According to another aspect of the present invention, the surface roughness of the wall surface and the bottom surface defining the first opening is substantially the same as the surface roughness of the wall surface and the bottom surface defining the second opening. The underfill agent tends to spread even inside. For this reason, the underfill agent is easily filled in the gaps between the connection terminals, and the generation of voids between the connection terminals can be more effectively suppressed.

In another aspect of the invention,
The solder resist layer has a surface roughness (Ra) outside the first opening of 0.02 μm to 0.25 μm.

  By setting the surface roughness (Ra) outside the first opening of the solder resist layer to 0.02 μm to 0.25 μm, it is more efficient that the underfill agent flows out from the first opening of the solder resist layer. Can be suppressed.

In another aspect of the invention,
The solder resist layer is characterized in that a surface roughness (Ra) of a wall surface and a bottom surface defining the first opening is 0.06 μm to 0.8 μm.

  By setting the surface roughness (Ra) inside the first opening of the solder resist layer to 0.06 μm to 0.8 μm, the flowability of the underfill agent is further improved. For this reason, the underfill agent is easily filled in the gap between the wiring board and the semiconductor chip, and the generation of voids can be more effectively suppressed.

  As described above, according to the present invention, it is possible to provide a wiring board capable of suppressing the outflow of the underfill agent and effectively suppressing the generation of voids between the connection terminals.

The top view (surface side) of the wiring board which concerns on embodiment. 1 is a partial cross-sectional view of a wiring board according to an embodiment. The expanded sectional view of the connecting terminal part by the side of the surface of the wiring board concerning an embodiment. The manufacturing process figure (core board | substrate process) of the wiring board which concerns on embodiment. The manufacturing process figure (build-up process) of the wiring board which concerns on embodiment. The manufacturing process figure (build-up process) of the wiring board which concerns on embodiment. The manufacturing process figure (solder resist layer process (surface side)) of the wiring board which concerns on embodiment. The formation method of the soldering resist layer of the wiring board which concerns on embodiment. The formation method of the soldering resist layer of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment (Solder resist layer process (back side)). The manufacturing process figure (plating process) of the wiring board which concerns on embodiment. The partial cross section figure which mounted the semiconductor chip in the wiring board concerning an embodiment. The expanded sectional view of the connection terminal part of the wiring board concerning other embodiments. The image of the wiring board surface which concerns on the Example which concerns on an Example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, an embodiment of the present invention will be described by taking a wiring board in which a build-up layer is formed on a core substrate as an example. However, a wiring in which a plurality of connection terminals with exposed upper surfaces and side surfaces are formed. Any substrate may be used. For example, a wiring substrate having no core substrate may be used.

(Embodiment)
FIG. 1 is a plan view (front side) of a wiring board 100 according to an embodiment. FIG. 2 is a partial cross-sectional view of the wiring board 100 taken along line I-I in FIG. FIG. 3 is an enlarged cross-sectional view of the connection terminal portion on the surface side of the wiring board according to the embodiment. In the following description, a side to which a semiconductor chip is connected is referred to as a front side, and a side to which a mother board, a socket or the like (hereinafter referred to as a mother board or the like) is connected is referred to as a back side.

(Configuration of wiring board 100)
A wiring substrate 100 shown in FIGS. 1 to 3 includes a build-up layer 3 (surface side) in which a plurality of connection terminals T1 between the core substrate 2 and a semiconductor chip (not shown) are formed and stacked on the surface side of the core substrate 2. And an opening 4a (first opening) stacked on the buildup layer 3 and having an outer edge at a position surrounding the mounting area of the semiconductor chip, and the connection terminal T1 is exposed in the mounting area, and the upper end of the connection terminal T1 A plurality of connection terminals T11 are formed between the solder resist layer 4 in which the opening 4b (second opening) for forming the bottom surface F3 is formed at a position lower than Z, and a mother board (not shown). A solder resist layer 1 that is laminated on the back surface side (back surface side) and an opening 14a that is laminated on the build up layer 13 and exposes at least a part of the connection terminal T11. And, equipped with a.

  The core substrate 2 is a plate-shaped resin substrate made of a heat-resistant resin plate (for example, a bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin), or the like. Core conductor layers 21 and 22 forming metal wirings L1 and L11 are formed on the front surface and the back surface of the core substrate 2, respectively. The core substrate 2 is formed with a through-hole 23 drilled by a drill or the like, and a through-hole conductor 24 for connecting the core conductor layers 21 and 22 to each other is formed on the inner wall surface thereof. Further, the through hole 23 is filled with a resin hole filling material 25 such as an epoxy resin.

(Structure on the front side)
The buildup layer 3 includes resin insulating layers 31 and 33 and conductor layers 32 and 34 stacked on the surface side of the core substrate 2. The resin insulating layer 31 is made of a thermosetting resin composition, and a conductor layer 32 forming the metal wiring L2 is formed on the surface. The resin insulating layer 31 is formed with a via 35 that electrically connects the core conductor layer 21 and the conductor layer 32. The resin insulating layer 33 is made of a thermosetting resin composition, and a conductor layer 34 having a plurality of connection terminals T1 is formed on the surface layer. The resin insulating layer 33 is formed with a via 36 that electrically connects the conductor layer 32 and the conductor layer 34. Here, the resin insulating layers 31 and 33 and the conductor layer 32 constitute a laminate.

  The vias 35 and 36 respectively include a via hole 37a, a via conductor 37b provided on the inner peripheral surface thereof, a via pad 37c provided to be electrically connected to the via conductor 37b on the bottom surface side, and a side opposite to the via pad 37c. A via land 37d projecting outward from the peripheral edge of the opening of the via conductor 37b.

  The connection terminal T1 is a connection terminal for connecting to a semiconductor chip. The connection terminal T1 is a so-called peripheral-type connection terminal arranged along the inner periphery of the semiconductor chip mounting region. The semiconductor chip is mounted on the wiring board 100 by being electrically connected to the connection terminal T1. The surface of each connection terminal T1 is roughened in order to improve adhesion with a solder resist layer 4 described later.

  A metal plating layer M is formed on the exposed surface of each connection terminal T1. When the semiconductor chip is mounted on the wiring substrate 100, the connection terminal of the semiconductor chip and the connection terminal T1 are electrically connected by reflowing the solder coated on the connection terminal of the semiconductor chip. The metal plating layer M is, for example, a single layer or a plurality of layers selected from metal layers such as a Ni layer, a Sn layer, an Ag layer, a Pd layer, and an Au layer (for example, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer).

  Further, instead of the metal plating layer M, OSP (Organic Solderability Preservative) treatment for rust prevention may be performed. Further, the exposed surface of the connection terminal T1 may be coated with solder. Further, after the exposed surface of the connection terminal T1 is covered with the metal plating layer M, the metal plating layer M may be coated with solder.

  The solder resist layer 4 has a film shape and is formed by laminating a photosensitive insulating resin functioning as a solder resist on the surface of the buildup layer 3. The solder resist layer 4 is laminated on the build-up layer 3 and exposes an opening 4a (first opening) having an outer edge at a position surrounding the semiconductor chip mounting area, and the connection terminal T1 in the mounting area. An opening 4b (second opening) for forming the bottom surface F3 is formed at a position lower than the upper end Z of the terminal T1. The opening 4b of the solder resist layer 4 has an NSMD shape in which a plurality of connection terminals T1 are arranged in the same opening.

  As shown in FIG. 3, in the solder resist layer 4, the surface roughness of the wall surface S1 and the bottom surface F2 defining the opening 4a is rougher than the surface roughness of the outer side F1 of the opening 4a. Further, in the solder resist layer 4, the surface roughness of the wall surface S1 and the bottom surface F2 that defines the opening 4a and the surface roughness of the wall surface S2 and the bottom surface F3 that define the opening 4b are substantially the same.

  The solder resist layer 4 preferably has a surface roughness (Ra) of the outer side F1 of the opening 4a of 0.02 μm to 0.25 μm, and the surface roughness of the wall surface S1 and the bottom surface F2 defining the opening 4a ( Ra) is preferably 0.06 μm to 0.8 μm. The surface roughness (Ra) of the wall surface S2 and the bottom surface F3 that define the opening 4b is also preferably 0.06 μm to 0.8 μm.

(Configuration on the back side)
The buildup layer 13 includes resin insulating layers 131 and 133 and conductor layers 132 and 134 laminated on the back side of the core substrate 2. The resin insulating layer 131 is made of a thermosetting resin composition, and a conductor layer 132 forming the metal wiring L12 is formed on the back surface. The resin insulating layer 131 is formed with a via 135 that electrically connects the core conductor layer 22 and the conductor layer 132. The resin insulating layer 133 is made of a thermosetting resin composition, and a conductor layer 134 having one or more connection terminals T11 is formed on the surface layer. In addition, a via 136 that electrically connects the conductor layer 132 and the conductor layer 134 is formed in the resin insulating layer 133.

  The vias 135 and 136 respectively include a via hole 137a, a via conductor 137b provided on the inner peripheral surface thereof, a via pad 137c provided to be electrically connected to the via conductor 137b on the bottom surface side, and a side opposite to the via pad 137c. A via land 137d projecting outward from the opening periphery of the via conductor 137b.

  The connection terminal T11 is used as a back surface land (PGA pad, BGA pad) for connecting the wiring board 100 to a mother board or the like, and is formed in an outer peripheral region excluding a substantially central portion of the wiring board 100. It is arranged in a rectangular shape so as to surround the central portion. Further, at least a part of the surface of the connection terminal T11 is covered with the metal plating layer M.

  The solder resist layer 14 has a film shape, and is formed by laminating a photosensitive insulating resin functioning as a solder resist on the surface of the buildup layer 13. The solder resist layer 14 is formed with an opening 14a exposing a part of the surface of each connection terminal T11. For this reason, each connection terminal T11 is in a state in which a part of the surface is exposed from the solder resist layer 14 through the opening 14a. That is, the opening 14a of the solder resist layer 14 has an SMD (solder mask defined) shape in which a part of the surface of each connection terminal T11 is exposed. Unlike the opening 4b of the solder resist layer 4, the opening 14a of the solder resist layer 14 is formed for each connection terminal T11.

  In the opening 14a, for example, a solder ball B made of solder that does not substantially contain Pb, such as Sn—Ag, Sn—Cu, Sn—Ag—Cu, or Sn—Sb, is connected to the connection terminal T11 via the metal plating layer M. It is formed so as to be electrically connected to. When the wiring board 100 is mounted on a mother board or the like, the connection terminals T11 are electrically connected to the connection terminals such as the mother board by reflowing the solder balls B of the wiring board 100.

(Method for manufacturing a wiring board)
2 and 4 to 11 are views showing manufacturing steps of the wiring board 100 according to the embodiment. Hereinafter, a method for manufacturing the wiring substrate 100 will be described with reference to FIGS. 2 and 4 to 11.

(Core substrate process: Fig. 4)
A copper clad laminate having a copper foil attached to the front and back surfaces of a plate-shaped resin substrate is prepared. Further, a drilling process is performed on the copper-clad laminate using a drill, and a through hole that becomes the through hole 23 is formed in advance at a predetermined position. Then, by performing electroless copper plating and electrolytic copper plating according to a conventionally known method, the through-hole conductor 24 is formed on the inner wall of the through-hole 23, and a copper plating layer is formed on both surfaces of the copper-clad laminate (FIG. 4A). )reference).

  Thereafter, the inside of the through-hole conductor 24 is filled with a resin hole filling material 25 such as an epoxy resin. Further, the copper plating formed on the copper foils on both sides of the copper clad laminate is etched into a desired shape, and the core conductor layers 21 and 22 forming the metal wirings L1 and L11 are respectively formed on the front and back surfaces of the copper clad laminate. Then, the core substrate 2 is obtained (see FIG. 4B). In addition, it is desirable to perform the desmear process which removes the smear of a process part after the through-hole 23 formation process.

(Build-up process: FIGS. 5 to 6)
On the front and back surfaces of the core substrate 2, film-like insulating resin materials mainly composed of an epoxy resin to be the resin insulating layers 31 and 131 are arranged so as to overlap each other. And this laminated body is pressurized and heated with a vacuum press-bonding hot press machine, and it crimps | bonds, heat-curing a film-form insulating resin material. Next, laser irradiation is performed using a conventionally known laser processing apparatus to form via holes 37a and 137a in the resin insulating layers 31 and 131, respectively (see FIG. 5A).

  Subsequently, after the surfaces of the resin insulating layers 31 and 131 are roughened, electroless plating is performed to form an electroless copper plating layer on the resin insulating layers 31 and 131 including the inner walls of the via holes 37a and 137a. Next, a photoresist is laminated on the electroless copper plating layer formed on the resin insulation layers 31 and 131, and exposure and development are performed to form a plating resist in a desired shape.

  Thereafter, copper is plated by electrolytic plating using the plating resist as a mask to obtain a desired copper plating pattern. Next, the plating resist is peeled off, the electroless copper plating layer existing under the plating resist is removed, and the conductor layers 32 and 132 forming the metal wirings L2 and L12 are formed. At this time, vias 35 and 135 including via conductors 37b and 137b, via pads 37c and 137c, and via lands 37d and 137d are also formed (see FIG. 5b).

  Next, on the conductor layers 32 and 132, film-like insulating resin materials mainly composed of an epoxy resin to be the resin insulating layers 33 and 133 are arranged so as to overlap each other. And this laminated body is pressurized and heated with a vacuum press-bonding hot press machine, and it crimps | bonds, heat-curing a film-form insulating resin material. Next, laser irradiation is performed using a conventionally known laser processing apparatus to form via holes 37a and 137a in the resin insulating layers 33 and 133, respectively (see FIG. 6A).

  Subsequently, in the same manner as when the conductor layers 32 and 132 are formed, the conductor insulating layers 33 and 133 having the via holes 37a and 137a are formed on the conductor layers 34 and 134 having the connection terminals T1 and T11 and the vias 36 and 136. Are formed respectively (see FIG. 6B).

(Solder resist layer process (front side): Fig. 7)
Next, a film-like photosensitive insulating resin to be the solder resist layer 4 is pressed and laminated on the buildup layer 3. Next, the laminated insulating resin exposes the opening 4a (first opening) having an outer edge at a position surrounding the mounting region of the semiconductor chip, the connection terminal T1 in the mounting region, and the upper end of the connection terminal T1. An opening 4b (second opening) for forming the bottom surface F3 is formed at a position lower than Z, and the solder resist layer 4 is obtained.

  In addition, it is preferable to roughen the surface (especially the side surface) of the connection terminal T1 before the insulating resin to be the solder resist layer 4 is pressed and stacked on the buildup layer 3. The surface of the connection terminal T1 can be roughened by, for example, processing with an etching solution such as MEC etch bond (manufactured by MEC).

(Opening method: FIGS. 8 and 9)
Next, a method for forming the openings 4a and 4b in the solder resist layer 4 will be described with reference to FIGS. Various methods such as printing, laminating, roll coating, and spin coating can be used as a method of coating the insulating resin that becomes the solder resist layer 4.

  First, on the surface of the buildup layer 3, after coating a photosensitive insulating resin to be the solder resist layer 4 (see FIG. 8A), inside the region to be the opening 4 a of the solder resist layer 4. The region (semiconductor chip mounting region) is masked to expose and develop the insulating resin, and the insulating resin to be the outer region of the opening 4a is photocured (see FIG. 8B).

  Next, the wiring substrate 100 being manufactured is immersed in an aqueous solution of sodium carbonate (concentration of 1% by weight) for a short time (a time that the insulating resin surface of the unexposed portion is slightly swollen) (see FIG. 8C). ). Thereafter, the insulating resin swollen by washing with water is emulsified (see FIG. 8D). Next, the swollen and emulsified insulating resin is removed from the wiring substrate 100 in the process of manufacture (see FIG. 9A).

  The above immersion and water washing are repeated once each or several times until the position of the upper end of the insulating resin that has not been photocured reaches a predetermined position.

  Next, the insulating resin is exposed and developed while masking the inner region of the region to be the opening 4b of the solder resist layer 4 later, and the insulating resin to be the outer region of the opening 4b is photocured (FIG. 9 ( b)).

  Next, the wiring substrate 100 being manufactured is immersed in an aqueous solution of sodium carbonate (concentration of 1% by weight) for a short time (a time that the insulating resin surface of the unexposed portion is slightly swollen) (see FIG. 9C). ). Then, the insulating resin swollen by washing with water is emulsified (see FIG. 9D). Next, the swollen and emulsified insulating resin is removed from the wiring substrate 100 in the process of manufacture (see FIG. 9E).

  The above immersion and water washing are repeated once each or several times until the position of the upper end of the insulating resin that has not been photocured is lower than the upper end of each wiring conductor T1. Thereafter, the insulating resin is cured by heat or ultraviolet rays.

  The surface of the build-up layer 3 is coated with a thin thermosetting insulating resin to be the solder resist layer 4 and thermally cured, and then the hardened insulating resin is polished so that the solder resist layer 4 The openings 4a and 4b may be formed. Alternatively, the solder resist layer 4 may be obtained by forming the openings 4a and 4b using a solvent that melts the insulating resin, followed by thermosetting. Further, after the surface of the buildup layer 3 is coated with a thermosetting insulating resin and thermally cured, the openings 4a and 4b are formed by dry etching by RIE (Reactive Ion Etching) or the like. Also good.

(Solder resist layer process (back side): FIG. 10)
Next, a photosensitive insulating resin to be the solder resist layer 14 is pressed and laminated on the buildup layer 13. The laminated insulating resin is exposed and developed to obtain a solder resist layer 14 having an SMD-shaped opening 14a that exposes a part of the surface of each connection terminal T11.

(Plating process: Fig. 11)
Next, the exposed surface of the connection terminal T1 is etched with sodium persulfate or the like to remove impurities such as an oxide film on the surface of the connection terminal T1. Thereafter, the metal plating layer M is formed on the exposed surfaces of the connection terminals T1 and T11 by electroless reduction plating using a reducing agent. When the metal plating layer M is formed on the exposed surface of the connection terminal T1 by electroless displacement plating, the metal on the exposed surface of the connection terminal T1 is replaced to form the metal plating layer M.

(Back-end process: Fig. 2)
The solder ball B is joined to the connection terminal T11 by placing the solder ball on the metal plating layer M formed on the connection terminal T11 and performing reflow.

  FIG. 12 is a partial cross-sectional view in which the semiconductor chip C is mounted on the wiring board 100 according to the embodiment. The wiring board 100 according to the embodiment exposes the opening 4a (first opening) having an outer edge at a position surrounding the mounting region of the semiconductor chip C, the connection terminal T1 in the mounting region, and the upper end of the connection terminal T1. And a solder resist layer 4 having an opening 4b (second opening) for forming a bottom surface F3 at a lower position.

  For this reason, as shown in FIG. 12, it is possible to suppress the underfill agent U from flowing out of the mounting region of the semiconductor chip C (outside the opening 4a). In addition, since the opening 4b (second opening) is formed in the solder resist layer 4, when the wiring board 100 is connected to the semiconductor chip C, the gap between the semiconductor chip C and the wiring board 100 is filled. It is possible to suppress the generation of voids between the connection terminals T1 of the underfill agent U to be obtained. Furthermore, the solder coated on the connection terminal T1 can be prevented from flowing out to the adjacent connection terminal T1, and a short circuit between the connection terminals T1 can be suppressed.

  Further, the surface roughness of the wall surface S1 and the bottom surface F2 defining the opening 4a is rougher than the surface roughness of the outer side F1 of the opening 4a. For this reason, the underfill agent U easily spreads inside the opening 4a, and the underfill agent U hardly spreads outside the opening 4b. As a result, the gap between the wiring substrate 100 and the semiconductor chip C is easily filled with the underfill agent U, and generation of voids can be suppressed. Further, it is possible to more effectively suppress the underfill agent U from flowing out of the mounting area of the semiconductor chip C (outside the opening 4a).

  Further, the surface roughness of the wall surface S1 and the bottom surface F2 defining the opening 4a (first opening) formed in the solder resist layer 4 of the wiring substrate 100, and the wall surface S2 and the bottom surface defining the opening 4b (second opening). Since the surface roughness of F3 is substantially the same, the underfill agent U tends to spread even inside the opening 4b (second opening). For this reason, it becomes easy to fill the gap between the connection terminals T1 with the underfill agent U, and generation of voids between the connection terminals T1 can be more effectively suppressed.

  Furthermore, since the outer surface roughness (Ra) of the opening 4a (first opening) of the solder resist layer 4 is 0.02 μm to 0.25 μm, the underfill agent U becomes the opening 4a of the solder resist layer 4 ( Flowing outward from the first opening) can be more efficiently suppressed.

  Further, since the surface roughness (Ra) of the wall surface S1 and the bottom surface F2 defining the opening 4a (first opening) of the solder resist layer 4 is 0.06 μm to 0.8 μm, the flowability of the underfill agent U. Will be improved. For this reason, the underfill agent U is easily filled in the gap between the wiring substrate 100 and the semiconductor chip, and the generation of voids can be more effectively suppressed.

(Other embodiments)
In the wiring substrate 100 described with reference to FIGS. 1 to 12, the upper surface F3 of the solder resist layer 4 filled between the connection terminals T1 is flat, but is filled between the connection terminals T1. The bottom surface F3 of the opening 4b of the solder resist layer 4 is not necessarily flat (flat). For example, as shown in FIG. 13, the bottom surface F3 of the opening 4b of the solder resist layer 4 is rounded. Even if it has a fillet shape, the same effect can be obtained.

  The present invention has been described in detail with specific examples. However, the present invention is not limited to the above contents, and various modifications and changes can be made without departing from the scope of the present invention. For example, in the above specific example, the embodiment is described in which the wiring substrate 100 is a BGA substrate connected to a mother board or the like via the solder balls B, but a so-called PGA (pin or land) is provided instead of the solder balls B The wiring board 100 may be connected to a motherboard or the like as a pin grid array (LGA) board or a land grid array (LGA) board.

  The inventors manufactured two wiring boards A and B by the manufacturing method of the wiring board 100 described with reference to FIGS. The solder resist layer 4 of the wiring board 100 was created by the method described with reference to FIGS. The wiring board A and the wiring board B are different in that different materials are used for the solder resist layer 4. The inventors manufactured the wiring boards A and B and then mounted a semiconductor chip to confirm the flowability of the underfill agent.

  FIG. 14 is an enlarged image of the surface of the wiring board according to the example. 14A is an enlarged image of the bottom surface F2 of the opening 4a of the solder resist layer 4 of the wiring board A. FIG. FIG. 14B is an enlarged image of the outer side F1 of the opening 4a of the solder resist layer 4 of the wiring board A.

  Next, the inventors measured the surface roughness of the produced wiring boards A and B. Table 1 shows the surface roughness (Ra) of the wiring boards A and B, and Table 2 shows the surface roughness (Rz) of the wiring boards A and B, respectively. Ra and Rz are averages of values measured at 18 points. From the measurement results in Tables 1 and 2 below, the surface roughness (Ra, Rz) of the bottom surface F2 of the opening 4a of the solder resist layer 4 is the same as that of the opening 4a of the solder resist layer 4 in both of the wiring boards A and B. It turns out that it is rougher than the surface roughness (Ra, Rz) of the outer side F1.

  Next, the inventors mounted a semiconductor chip on the produced wiring boards A and B, and confirmed that there is no problem in the flowability of the underfill agent. Further, it was confirmed that the underfill agent did not flow out from the opening 4a of the solder resist layer 4 to the outside.

  DESCRIPTION OF SYMBOLS 100 ... Wiring board, 2 ... Core board, 3 ... Build-up layer, 4 ... Solder resist layer, 4a, 4b ... Opening, 13 ... Build-up layer, 14 ... Solder resist layer, 14a ... Opening, 21, 22 ... Core conductor Layer, 23 ... through hole, 24 ... through hole conductor, 25 ... resin filling material, 31,33 ... resin insulating layer, 32,34 ... conductor layer, 35,36 ... via, 37a ... via hole, 37b ... via conductor, 37c ... via pad, 37d ... via land, 131, 133 ... resin insulating layer, 132,134 ... conductor layer, 135,136 ... via, 137a ... via hole, 137b ... via conductor, 137c ... via pad, 137d ... via land, B ... solder ball L1, L2 ... metal wiring, L11, L12 ... metal wiring, M ... metal plating layer, T1, T11 ... connection terminals.

Claims (5)

A wiring board in which a plurality of connection terminals with a semiconductor chip are formed on a laminate in which an insulating layer and a conductor layer are laminated,
A first opening having an outer edge at a position surrounding the mounting region of the semiconductor chip; and a second opening that exposes the connection terminal in the mounting region and forms a bottom surface at a position lower than the upper end of the connection terminal. A wiring board comprising a solder resist layer on which is formed.   2. The wiring board according to claim 1, wherein the solder resist layer has a surface roughness of a wall surface and a bottom surface defining the first opening, which is rougher than a surface roughness outside the first opening.   3. The surface roughness of the wall surface and the bottom surface defining the first opening and the surface roughness of the wall surface and the bottom surface defining the second opening are substantially the same. 4. Wiring board.   4. The solder resist layer according to claim 1, wherein a surface roughness (Ra) of the outer side of the first opening is 0.02 μm to 0.25 μm. 5. Wiring board.   5. The solder resist layer according to claim 1, wherein a surface roughness (Ra) of a wall surface and a bottom surface defining the first opening is 0.06 μm to 0.8 μm. The wiring board according to item 1.

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