JP2014041918A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of deterioration in data retention characteristics in a memory cell using a trench-gate FIN-FET, which is caused by an apparent phenomenon where a threshold voltage Vt of a cell transistor fluctuates depending on potential of adjacent trench gates (word lines).SOLUTION: In a semiconductor device, a decreased difference (ΔVt) in a threshold voltage caused by an influence of an adjacent trench gate is improved by forming a diffusion layer 103A to which an impurity having a conductivity type different from that of a channel region on each trench gate lateral face is introduced into a channel region (saddle fin 5) under a trench gate 300.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), in particular, a trench gate type FIN-FET.

  In recent years, with the miniaturization of transistors, there is a problem of a decrease in threshold voltage and deterioration of subthreshold characteristics due to a so-called short channel effect. As a high-performance transistor that suppresses this, a FIN-type FET in which a channel portion is processed into a fin shape has attracted attention. Furthermore, a trench gate type FIN-FET that combines a trench (recess) gate structure and a fin type structure in order to apply the FIN type FET to applications requiring low leakage current, such as a DRAM (Dynamic Random Access Memory) cell transistor. Have been proposed (Patent Document 1, Patent Document 2, Non-Patent Document 1, etc.).

  Patent Document 3 discloses a technique for suppressing a decrease in on-current by narrowing the lower width of the FIN while widening the upper width of the FIN.

JP 2008-47909 A JP 2008-16842 A JP 2011-54629 A

S-W Chung, et.al., Symposium on VLSI Tech.Dig., Pp. 32-33, 2006.

  Due to the progress of miniaturization of semiconductor devices, in a semiconductor device such as a DRAM having a memory cell having a storage element, the memory cell using a trench gate type FIN-FET depends on the potential of an adjacent trench gate (word line). As a result, the phenomenon that the threshold voltage Vt of the cell transistor fluctuates becomes obvious, and the problem that the data retention characteristic deteriorates has become serious. This is because, even when the word line of the target transistor is set to the low level and the transistor is in the off state, when the adjacent word line becomes high level and the adjacent transistor is turned on, the change in the potential distribution of the channel region It also affects the potential distribution in the channel region and lowers Vt. As a result, since the Ioff leakage of the transistor of interest increases and the data retention characteristics deteriorate, it is required to reduce this Vt decrease amount (ΔVt).

That is, according to one embodiment of the present invention,
An element isolation region formed on a semiconductor substrate having a first conductivity type;
A semiconductor region including each region surrounded by the element isolation region and arranged in the order of the first active region, the channel region, and the second active region in the first direction;
The channel region includes an upper surface, a first side and a second side;
The first side surface extends downward from a first terminal end of the upper surface of the channel region in a second direction intersecting the first direction;
The second side surface extends downward from a second terminal end of the upper surface of the channel region in the second direction;
A gate electrode covering the upper surface, the first side surface and the second side surface via a gate insulating film;
A first diffusion layer formed in the first active region;
A second diffusion layer formed in the second active region;
Provided is a semiconductor device comprising a portion having a second conductivity type different from the first conductivity type in the channel region.

Also, according to another embodiment of the present invention,
An element isolation region formed on a semiconductor substrate having the first conductivity type, and each region surrounded by the element isolation region and arranged in the order of a drain region, a channel region, and a source region There is a semiconductor area,
The drain region and the source region have a second conductivity type;
The channel region includes both a first conductivity type portion and a second conductivity type portion, and is sandwiched between the second conductivity type portion of the channel region and each of the drain and source regions. Comprising a portion of each first conductivity type;
A gate insulating film covering the channel region;
And a gate electrode covering the gate insulating film.

According to yet another embodiment of the invention,
A semiconductor device including a transistor including a saddle fin structure,
A groove having a predetermined depth in the active region of the semiconductor substrate of the first conductivity type;
An element isolation region that includes a receding isolation portion that surrounds the active region and forms a saddle fin structure in a groove of the active region;
The gate electrode of the transistor embedded in the trench and the recessed isolation portion;
A source / drain region that is a second conductivity type different from the first conductivity type and is formed on the active region opposite to the groove;
A channel portion of a first conductivity type sandwiched between the source / drain regions and facing the gate electrode;
The channel portion performs charge transfer between the source and drain via the saddle fin structure,
A semiconductor device is provided in which the saddle fin structure has the second conductivity type.

  In a MOSFET, a channel portion that is depleted when performing a depletion operation functions to inject carriers (electrons in the case of an NMOSFET) into a substrate. According to one embodiment of the present invention, By having a second conductivity type portion different from the first conductivity type, carrier injection in the second conductivity type portion can be reduced. In a memory cell using a fully depleted FIN-FET, in particular, a trench gate type FIN-FET structure, a channel region (saddle fin portion) under the trench gate (word line) is used as the first channel region on the side surface of the trench gate. By adopting the second conductivity type different from the conductivity type, carrier injection into the substrate can be reduced at that portion, and as a result, the difference (ΔVt) in the threshold voltage drop due to the influence of the adjacent trench gate can be improved. A semiconductor device having a memory cell with excellent data retention characteristics can be provided.

It is a top view which shows a part of semiconductor device which concerns on one Embodiment of this invention. FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A. Sectional drawing in the BB line of FIG. 1A is shown. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (A) is a top view, (B) is sectional drawing in the AA of (A), (C) is (A) ) Is a cross-sectional view taken along line B-B. It is a flowchart explaining the manufacturing process of Example 1 of this invention. It is a flowchart explaining the manufacturing process of Example 2 of this invention. It is a figure which shows the simulation result explaining the effect of this invention, (A) shows a threshold voltage characteristic, (B) shows SS characteristic, (C) shows (DELTA) Vt characteristic.

  The preferred embodiments of the present invention will now be described with reference to the drawings, but the present invention is not limited to these embodiments.

Embodiment 1
First, with reference to the plan view of FIG. 1A, the arrangement of main parts of the semiconductor device 1 of the present embodiment will be described. Here, a semiconductor device in which a first conductivity type is p-type, a second conductivity type is n-type, and a FIN-FET is configured as a MOSFET with a buried word line structure will be described.

  The semiconductor device 1 constitutes a DRAM having a memory cell region 2 and a peripheral circuit region (not shown) disposed around the semiconductor cell 100 on the semiconductor substrate 100. In FIG. 1A, a part of the memory cell region 2 is formed. Is shown. In this embodiment, the semiconductor substrate 100 is described as a silicon single crystal whose first conductivity type is p-type. However, the present invention is not limited to this, and a silicon single crystal or compound semiconductor whose first conductivity type is n-type. It may be.

  The memory cell region 2 includes a first element isolation region 200A extending in the X ′ direction (third direction) inclined in the X direction (second direction) and a Y direction (first direction) perpendicular to the X direction. And an island-shaped active region 101 including a semiconductor substrate 100 separated in the Y direction by the first element isolation region 200A and in the X ′ direction by the second element isolation region 200B. have.

  In FIG. 1A, the active region 101 is shown as a parallelogram having long sides in the X ′ direction. However, the present invention is not limited to this, and the active region 101 may be a long ellipse having four rounded corners. good. The plurality of active regions 101 have the same width in the Y direction and the width in the X direction. Further, the active regions 101 are repeatedly arranged in the X ′ direction and the Y direction at equal pitch intervals. The interval between the active regions 101 adjacent in the Y direction is not particularly limited. The interval between the active regions 101, that is, the width in the Y direction of the first element isolation region 200A may be the same as the width in the Y direction of the active region 101, or may be smaller than that. In the semiconductor device 1 according to the present embodiment, an active region 101 extending in the X ′ direction (third direction) inclined in the X direction (second direction) extends on a straight line in the Y direction, in which a bit line described later extends. Are arranged repeatedly. Two embedded word lines 300 (hereinafter referred to as a first word line 300A and a second word line 300B) extending linearly in the Y direction are arranged across the plurality of first element isolation regions 200A and the plurality of active regions 101. Has been. Although a part of the configuration is omitted in the drawing, the first word line 300A and the second word line 300B are arranged at equal intervals between the adjacent second element isolation regions 200B. That is, each second element isolation region 200B, the first word line 300A, and the second word line 300B are arranged with the same width and interval. The first word line 300A and the second word line 300B function as gate electrodes of corresponding transistors. As a result, one island-like active region 101 extending in the X ′ direction includes the second element isolation region 200B, the first capacitor contact connection region 4A adjacent to the first word line 300A, and the first word line 300A. The first saddle fin 5A that functions as a channel directly below, the bit line contact connection region 6 adjacent to the first word line 300A and the second word line 300B, and the second saddle fin 5B that functions as a channel directly below the second word line 300A. And a second capacitor contact connection region 4B adjacent to the second word line 300B and the second element isolation region 200B. The first capacitor contact connection region 4A, the first word line 300A, the first saddle fin 5A, and the bit line contact connection region 6 constitute a first memory cell transistor Tr1. The bit line contact connection region 6, the second word line 300B, the second saddle fin 5B, and the second capacitor contact connection region 4B constitute a second memory cell transistor TR2. Accordingly, the bit line contact connection region 6 is shared by the two memory cell transistors Tr1 and Tr2. A bit line contact plug 511 (here, circular for convenience) is provided on each bit line contact connection region 6, and a part of the configuration is omitted in the figure, but each bit line contact plug 511 has A bit line gate 500 (hereinafter referred to as BLG 500) that is connected and extends in the X direction is disposed. A capacitor contact 700 is provided in a region surrounded by the second element isolation region 200B and the first word lines 300A and BLG500, and the second element isolation region 200B and the second word lines 300B and BLG500, and each capacitor contact connection region 4A, 4B is electrically connected. A capacitor (not shown) is provided on each capacitance contact 700.

  Reference is now made to the cross-sectional views of FIGS. 1B and 1C. FIG. 1B is a cross-sectional view taken along line AA that bisects the active region 101 in the Y direction along the X ′ direction. FIG. 1C is a cross-sectional view taken along the line BB dividing the word line 300 in the X direction along the Y direction after the first interlayer insulating film 400 is formed. On the surface of the semiconductor substrate 100, second element isolation regions 200B extending in the Y direction (first direction) at equal intervals in the X direction (second direction) and including a liner nitride film and a main oxide film are arranged. Two word trenches 310 are arranged at equal intervals between adjacent second element isolation regions 200B. The word trench 310 is shallower in the first element isolation region 200A than the deepest part of the first element isolation region 200A (for example, about 2/3 of the depth of the first element isolation region 200A), and is shallower in the active region 101 (for example, , About 1/3 of the depth of the first element isolation region 200A), and forms a saddle fin 5 serving as a FIN-FET. Saddle fin 5 forms a channel of the transistor and has an upper surface, a first side surface, and a second side surface. Here, the shape in which the first side surface and the second side surface are inclined is shown; however, the shape is not limited to this, and a vertical shape may be used. In the present invention, a second conductivity type impurity (n-type impurity) different from the first conductivity type impurity (here, p-type) contained in the semiconductor substrate 100 is implanted into the active region 101 below the word trench 310, The dolphin 5 is made n-type (n-type diffusion layer 103A). Metal word lines 312 each composed of a barrier metal layer 312a and a metal layer 312b are buried in the word trench 310 with a gate insulating film 311 interposed therebetween. A cap insulating film 313 is disposed so as to cover the upper surface of the metal word line 312. The cap insulating film 313 protrudes higher than the surface of the semiconductor substrate 100. The structure formed in each word trench 310 becomes a word line 300. A first interlayer insulating film 400 is provided so as to embed between the cap insulating films 313. On the upper surface of the bit line contact connection region 8, a bit line contact plug 511 penetrating the first interlayer insulating film, a BLG lower layer 512 connected to the upper surface of the bit line contact plug 511 and extending in the X direction, a BLG upper layer 513, and a cap An insulating film 514 is laminated and formed in the shape of a wiring. In this embodiment, the bit line contact plug 511 and the BLG lower layer 512 are separated, but the bit line contact plug 511 and the BLG lower layer 512 may be integrally formed. A side wall insulating film 515 made of a silicon nitride film is provided on the side surfaces of the BLG lower layer 512, the BLG upper layer 513, and the cap insulating film 514. The BLG 500 is formed by the BLG lower layer 512, the BLG upper layer 513, the cap insulating film 514, and the side wall insulating film 515. Forming. A second interlayer insulating film 600 made of a silicon oxide film is provided on the entire surface so as to cover the BLG 500. A capacitor contact plug 700 is connected to the upper surface of the capacitor contact connection region 8 through the second interlayer insulating film 600 and the first interlayer insulating film 400. A stopper film 780 made of a silicon nitride film and a third interlayer insulating film 790 made of a silicon oxide film are provided on the entire surface including the upper surface of the capacitor contact plug 700. A cylinder hole 810 passing through the third interlayer insulating film 790 and the stopper film 780 is opened so as to reach the upper surface of the capacitor contact plug 700, and a lower electrode 811 is provided so as to cover the inside and bottom of the cylinder hole. As a result, the lower electrode 811 is connected to the upper surface of the capacitive contact plug 700. A capacitor insulating film 812 and an upper electrode 813 are provided so as to cover the surface of the lower electrode 811, and the capacitor 800 is configured by the lower electrode 811, the capacitor insulating film 812 and the upper electrode 813. A fourth interlayer insulating film 900 is provided so as to cover the capacitor 800. A wiring contact 910 that penetrates the fourth interlayer insulating film 900 is provided, and a wiring 920 is connected to the upper surface of the wiring contact 910. A protective insulating film 930 is provided over the entire surface so as to cover the wiring 920.

Next, the manufacturing process of the semiconductor device 1 according to this embodiment will be described with reference to FIGS.
In this embodiment, there are Example 1 and Example 2 in which the process order is partially changed around the n-type diffusion layer 103A formation process. Only the different processes will be described separately. 2 to 12, (A) is a plan view, (B) is a cross-sectional view taken along line AA of (A), and (C) is a cross-sectional view taken along line BB of (A).

  First, as shown in FIG. 2, an element isolation region 200 is formed on the semiconductor substrate 100 with a layout shown in the plan view of FIG. 2A using a known technique, and the surface of the semiconductor substrate 100 is formed as an active region 101. To divide. The element isolation region 200 is formed by forming an element isolation groove by dry etching, forming a liner nitride film, and then embedding a main oxide film. Next, a source / drain (SD) diffusion layer 102 is formed shallowly near the surface of the active region 101 by n-type impurity implantation. Thereafter, a mask film 301 which is a silicon nitride film is formed on the entire surface of the semiconductor substrate 100. Note that the plan view of FIG. 2A shows a state where the mask film 301 is transmitted. The same applies to FIGS. 3A, 4A, and 5A.

  Next, as shown in FIG. 3, the mask film 301 is etched by lithography and dry etching to form a pattern of the word trench 310, and the word trench 310 is formed by dry etching using the mask film 301 as a mask. Form. Here, it is desirable to use a double patterning method for patterning the mask film. The dry etching conditions are adjusted so that the depth of the word trench 310 is shallow in the active region 101 and deep in the element isolation region 200. The depth is preferably about 1/3 of the depth of the element isolation region 200 in the active region 101 and about 2/3 of the depth of the element isolation region 200 in the element isolation region 200. That is, a bowl-shaped convex part is left in the active region 101 of the word trench 310. This saddle-shaped convex portion becomes the saddle fin 5.

Next, the process of Example 1 is demonstrated using FIG. 4 and FIG.
In Example 1, after forming the word trench 310 as shown in FIG. 3, as shown in FIG. 4, an n-type impurity (for example, P, As) is implanted to form an n-type diffusion layer 103A. At this time, the n-type diffusion layer 103A is implanted to such a depth that all of the saddle fins 5 become n-type, and the implantation conditions are adjusted so as not to be implanted into the side walls of the word trench 310 as much as possible. The n-type impurity implanted to form the n-type diffusion layer 103A does not need to consider the contact resistance as in the SD diffusion layer 102, so that the introduction amount is small enough to change the conductivity type from p-type to n-type. Shows a sufficient effect, and an introduction amount smaller than that of the SD diffusion layer 102 is sufficient.

  Next, as shown in FIG. 5, the active region 101 including the n-type diffusion layer 103 </ b> A appearing on the surface of the word trench 310 is oxidized by thermal oxidation to form a gate oxide film 311.

  On the other hand, in Example 2, after forming the word trench 310 as shown in FIG. 2, the active region 101 appearing on the surface of the word trench 310 is oxidized by thermal oxidation to form a gate oxide film 311. As shown in FIG. 3, an n-type impurity (for example, P, As) is implanted to form an n-type diffusion layer 103A. In the second embodiment, since the gate insulating film 311 is provided, the n-type impurity is less likely to be implanted into the side wall of the word trench 310 than in the first embodiment.

  Next, as shown in FIG. 6, a barrier metal layer 312 a made of titanium nitride is thinly formed on the entire surface of the semiconductor substrate 100 including the inside of the word trench 310. Subsequently, a metal layer 312 b made of tungsten is formed on the entire surface of the semiconductor substrate 100 so as to bury the word trench 310.

  Next, as shown in FIG. 7, etching is performed so that the metal layer 312 b and the barrier metal layer 312 a in the word trench 310 remain only in a portion deeper than the SD diffusion layer 102 by tungsten etch back.

  Next, as shown in FIG. 8, the remaining portion of the word trench 310 is filled with a cap insulating film 313 that is a silicon oxide film.

  This can be realized by forming a silicon oxide film to fill the remaining portion of the word trench 310 and polishing the mask film 301 as a stop film by CMP.

  As a result, a metal word line 312 composed of the gate oxide film 311, the barrier metal layer 312a, and the metal layer 312b, and a buried word line 300 composed of the cap insulating film 313 are formed.

  As described above, in the steps from the formation of the mask film 301 to the formation of the cap insulating film 313, the flow proceeds according to the flow shown in FIG. 13 in the first embodiment and the flow shown in FIG.

  Next, as shown in FIG. 9, the mask film 301 is removed by a nitride film wet etch, and a first interlayer insulating film 400, which is a silicon oxide film, is formed and planarized by CMP. Although the cap insulating film 313 is exposed here, the first interlayer insulating film 400 may be left on the cap insulating film 313.

  Next, as shown in FIG. 10, a bit contact hole 510 that penetrates through the first interlayer insulating film 400 and reaches the portion sandwiched between the buried word lines 300 in the active region 101 is opened by lithography and dry etching. To do. Although an example in which the bit contact hole 510 is formed as a groove pattern extending in the Y direction is shown here, the present invention is not limited to this, and a hole pattern that exposes only the bit contact connection region 6 may be formed. Alternatively, a part of the cap insulating film 313 may be etched to form a wider bit contact hole 510.

  Next, as shown in FIG. 11, a BLG lower layer 512 is formed on the entire surface of the semiconductor substrate 100 so as to fill the bit contact hole 510, and a BLG upper layer 513 and a cap insulating film 514 are sequentially formed on the entire surface of the semiconductor substrate 100. To do. A polysilicon film or the like can be used as the BLG lower layer 512, and a metal film such as tungsten can be used as the BLG upper layer 513. A bit contact 511 is constituted by the BLG lower layer 512 in the bit contact hole 510.

  Next, as shown in FIG. 12, the cap insulating film 514, the BLG upper layer 513, and the BLG lower layer 512 are etched into a bit line gate pattern by lithography and dry etching, and a sidewall insulating film 515 is formed on the side surface thereof.

  As a result, the bit line gate 500 including the BLG lower layer 512, the BLG upper layer 513, the cap insulating film 514, and the sidewall insulating film 515 is formed.

  Thereafter, a second interlayer insulating film 600 is formed on the entire surface of the semiconductor substrate 100 so as to bury the bit line gate 500, and polished to the upper surface of the cap insulating film 514 by CMP.

  Next, by a known method, the second interlayer insulating film 600 and the first interlayer insulating film 400 are penetrated by lithography and dry etching, and are sandwiched between the buried word line 300 and the element isolation region 200 in the active region 101. A capacitor contact 700 that reaches a portion (first capacitor contact connection region 4A and second capacitor contact connection region 4B) is formed.

  Next, a stopper film 780 and a third interlayer insulating film 790 are sequentially formed, and a capacitor element (capacitor) 800 including a lower electrode 811, a capacitor insulating film 812, and an upper electrode 813 is formed by a known method. Here, the lower electrode 811 penetrates the stopper film 780 and the third interlayer insulating film 790 and is electrically joined to the upper surface of the capacitor contact 700.

  Next, a fourth interlayer insulating film 900 is formed on the capacitor 800, and a wiring contact 910 that penetrates the fourth interlayer insulating film 900 and reaches the upper electrode 813 is formed by lithography and dry etching.

  Next, the wiring 920 is formed so as to be connected to the upper surface of the wiring contact 910, and the entire surface of the semiconductor substrate 100 is covered with the protective insulating film 930, whereby the semiconductor device 1 shown in FIG.

  Here, the effect of the present invention will be described. FIG. 15 shows a threshold voltage: Vt (FIG. 15 (A)), subthreshold slope: SS (FIG. 15 (B)), adjacent word line as an effect of ion implantation after trench etching for a trench gate having a width of 30 nm. The simulation results of Vt difference: ΔVt (FIG. 15C) when Vpp is set to Vpp (on) and the adjacent word line is set to Vkk (off) are shown. When the semiconductor substrate 1 is implanted with boron at 115 keV and a dose of 5E13 as a second p-well, and p-type impurity implantation (BF2) is performed at 10 keV as a comparative example after trench etching (◯), in the present invention As an example, the second p-well is implanted with boron at 105 keV and a dose amount of 5E13, and the As implantation (□) as an n-type impurity after trench etching is performed while changing the dose amount.

  As shown in FIG. 15A, Vt is slightly reduced by BF2 injection (comparative example), but is further decreased by As injection. On the other hand, as shown in FIG. 15B, it can be seen that SS is reduced and improved by As implantation. And, as shown in FIG. 15C, ΔVt is greatly improved by As implantation, while BF2 implantation (comparative example) is worse than non-implantation (As dose = 0). I understand.

  In the above embodiments, the buried word line has been described as the trench gate. However, the present invention can be applied to other trench gate structures, for example, a recessed gate structure in which the gate structure is partially exposed from the surface of the semiconductor substrate. Further, as shown in Patent Document 3, the present invention can be applied to a structure in which the fin lower portion is thinner than the fin upper portion. The SD diffusion layer 102 is not limited to the embodiment described above formed in the semiconductor substrate, and may be a stacked structure (ESD structure) epitaxially grown on the semiconductor substrate. Further, the present invention can be applied not only to the trench gate structure but also to a FIN-FET structure in general, and further to a MOSFET including a planar type.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Memory cell 4 Capacity contact connection area 4A 1st capacity contact connection area 4B 2nd capacity contact connection area 5 Saddle fin 5A 1st saddle fin 5B 2nd saddle fin 6 Bit contact connection area 100 Semiconductor substrate 101 Active area 102 SD diffusion layer 103 channel 103A n-type diffusion layer 200 element isolation region 200A X 'direction element isolation region 200B Y direction element isolation region 300 buried word line 301 mask film 310 word trench 311 gate oxide film 312 metal word line 312a barrier metal layer 312b Metal layer 313 Cap insulating film 400 First interlayer insulating film 500 Bit line gate 510 Bit contact hole 511 Bit contact 512 BLG lower layer (Poly-Si)
513 BLG upper layer (W film)
514 Cap insulating film 515 Side wall insulating film 600 Second interlayer insulating film 700 Capacitor contact 780 Stopper film 790 Third interlayer insulating film 800 Capacitor 811 Lower electrode 812 Capacitor insulating film 813 Upper electrode 900 Fourth interlayer insulating film 910 Wiring contact 920 Wiring 930 Protective insulating film

Claims (14)

An element isolation region formed on a semiconductor substrate having a first conductivity type;
A semiconductor region including each region surrounded by the element isolation region and arranged in the order of the first active region, the channel region, and the second active region in the first direction;
The channel region includes an upper surface, a first side and a second side;
The first side surface extends downward from a first terminal end of the upper surface of the channel region in a second direction intersecting the first direction;
The second side surface extends downward from a second terminal end of the upper surface of the channel region in the second direction;
A gate electrode covering the upper surface, the first side surface and the second side surface via a gate insulating film;
A first diffusion layer formed in the first active region;
A second diffusion layer formed in the second active region;
A semiconductor device comprising a portion having a second conductivity type different from the first conductivity type in the channel region. Each of the first diffusion layer and the second diffusion layer has a second conductivity type;
A portion having the second conductivity type of the channel region, and a portion having the first conductivity type between each of the first diffusion layer and the second diffusion layer;
The semiconductor device according to claim 1. A groove extending continuously from the semiconductor region to the element isolation region in the second direction;
The upper surface of the channel region is at the bottom of the trench in the semiconductor region, and the gate electrode extends while continuously covering the bottom of the trench from the semiconductor region to the element isolation region,
The semiconductor device according to claim 2, further comprising an insulating film that continuously covers an upper surface of the gate electrode from the semiconductor region to the element isolation region.   The depth of the trench in the element isolation region is deeper than the depth of the trench in the semiconductor region, and the channel region at the bottom of the trench has a shape protruding from the insulating film of the element isolation region on both sides thereof. The semiconductor device according to claim 3.   The bottom of the trench in the element isolation region is formed to a depth of 2/3 of the depth of the element isolation region, and the bottom of the semiconductor region of the groove is a depth of 1/3 of the depth of the element isolation region. The semiconductor device according to claim 4 formed so far. A first contact plug on the first diffusion layer;
A first conductive layer on the first contact plug;
A second contact plug on the second diffusion layer;
A storage element on the two contact plugs;
The semiconductor device according to claim 4, further comprising:   The semiconductor device according to claim 6, wherein the storage element is a capacitive element including a lower electrode, a capacitive insulating film that covers the lower electrode, and an upper electrode that covers the capacitive insulating film. Two grooves are formed in the semiconductor region,
The first diffusion layer is disposed between the grooves;
8. The semiconductor device according to claim 4, wherein the second diffusion layer is disposed in each of two active regions facing the first diffusion layer via the two grooves. 9. An element isolation region formed on a semiconductor substrate having the first conductivity type, and each region surrounded by the element isolation region and arranged in the order of a drain region, a channel region, and a source region There is a semiconductor area,
The drain region and the source region have a second conductivity type;
The channel region includes both a first conductivity type portion and a second conductivity type portion, and is sandwiched between the second conductivity type portion of the channel region and each of the drain and source regions. Comprising a portion of each first conductivity type;
A gate insulating film covering the channel region;
And a gate electrode covering the gate insulating film. A groove extending in a second direction intersecting the first direction from the semiconductor region to the element isolation region;
The semiconductor device according to claim 9, wherein the gate electrode is embedded in the trench continuously from the semiconductor region to the element isolation region. A semiconductor device including a transistor including a saddle fin structure,
A groove having a predetermined depth in the active region of the semiconductor substrate of the first conductivity type;
An element isolation region that includes a receding isolation portion that surrounds the active region and forms a saddle fin structure in a groove of the active region;
The gate electrode of the transistor embedded in the trench and the recessed isolation portion;
A source / drain region that is a second conductivity type different from the first conductivity type and is formed on the active region opposite to the groove;
A channel portion of a first conductivity type sandwiched between the source / drain regions and facing the gate electrode;
The channel portion performs charge transfer between the source and drain via the saddle fin structure,
A semiconductor device, wherein the saddle fin structure has the second conductivity type. The upper surface of the gate electrode is disposed at a position recessed from the surface of the semiconductor substrate,
The semiconductor device according to claim 11, further comprising an insulating film on the upper surface of the gate electrode. A bit line electrically connected to one of the source / drain regions;
The semiconductor device according to claim 11, further comprising a storage element electrically connected to the other of the source / drain regions.   Two of the gate electrodes are disposed adjacent to each other in the active region, and one of the source / drain regions connected to the bit line is common and located between the gate electrodes, and the other of the source / drain regions is The semiconductor device according to claim 13, wherein the semiconductor device is located opposite to one of the source / drain regions via each gate electrode.

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