JP2013222745A - Electronic component and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component in which a crack is hard to generate in a conductor pattern between semiconductor elements, and provide a manufacturing method of the electronic component.SOLUTION: A pitch P1 between second bumps 77 arranged in a second area ED 2 which is positioned between semiconductor elements and is not strengthened by a semiconductor element is narrower than a pitch P2 between the second bumps 77 arranged in a first area ED 1 which is located immediately beneath a semiconductor element and is strengthened by a first semiconductor element 90A or a second semiconductor element 90B.

Description

The present invention relates to an electronic component in which a semiconductor element is mounted on a wiring board having a resin insulating layer and a conductor pattern and not including a core substrate, and a method for manufacturing the same.

In Patent Document 1, a wiring board without a core substrate, a semiconductor element mounted on the upper surface of the wiring board, an underfill resin filled between the wiring board and the semiconductor element, and the semiconductor element are sealed. An electronic component having a sealing resin is disclosed. FIG. 11 of Patent Document 1 shows an electronic component on which a plurality of semiconductor elements are mounted.

JP 2006-294692 A

The electronic component disclosed in Patent Document 1 is generally mounted on an external substrate such as a mother board. At this time, in a wiring board on which a plurality of semiconductor devices are mounted, a region immediately below each semiconductor element is restricted by a highly rigid semiconductor element made of silicon or the like. However, in the region between the semiconductor elements, the restraint by the semiconductor elements is relatively weak, and, for example, thermal stress tends to concentrate during or after mounting on the motherboard. As a result, a crack may occur in the conductor pattern existing in the region between the semiconductor elements. Such a problem becomes more conspicuous as the thickness of the wiring board (rewiring layer) of the electronic component decreases.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electronic component that easily suppresses occurrence of cracks in a conductor pattern at a predetermined location and a method for manufacturing the same. It is in.

The electronic component according to claim 1 has a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, and the first surface and the second surface opposite to the first surface. A wiring board comprising:
A first bump provided on the conductor pattern on the first surface side;
A second bump provided on the conductor pattern on the second surface side;
A first semiconductor element and a second semiconductor element mounted on the wiring board via the first bump;
An electronic component comprising:
The wiring board includes a first region located immediately below the first semiconductor element and the second semiconductor element on the second surface side, and a first area located between the first semiconductor element and the second semiconductor element. Two regions,
A technical feature is that a pitch of the second bumps located in the second region is smaller than a pitch of the second bumps located in the first region.

In the electronic component according to claim 1, the bump pitch is relatively reduced in a portion (second region) where the influence of the thermal stress is large and the wiring board (interlayer insulating layer forming the wiring board) is easily deformed. Many bumps are provided in the region. For this reason, the stress relaxation effect through a bump is exhibited. As a result, the stress generated in the second region of the wiring board is reduced, and the occurrence of cracks in the conductor pattern existing in the second region is easily suppressed.

It is a manufacturing-process figure of the electronic component which concerns on embodiment of this invention. It is a manufacturing-process figure of the electronic component of embodiment. It is a manufacturing-process figure of the electronic component of embodiment. It is a manufacturing-process figure of the electronic component of embodiment. It is a manufacturing-process figure of the electronic component of embodiment. It is sectional drawing of the electronic component of embodiment. It is sectional drawing which shows the state in which the electronic component of embodiment was mounted.

FIG. 6 is a cross-sectional view of the electronic component 100 according to the embodiment.
The electronic component 100 includes a wiring board 20 in which a conductor pattern and a resin insulating layer are laminated, a first semiconductor element (logic chip) 90A and a second semiconductor element (memory chip) 90B mounted on the wiring board 20. It consists of. The wiring board 20 has a first surface F and a second surface S opposite to the first surface, and is formed on the first resin insulating layer 50 and the first resin insulating layer 50. Conductive pattern 58, first resin insulating layer 50, second resin insulating layer 150 formed on first conductive pattern 58, and second conductive pattern 158 formed on second resin insulating layer 150. Have. A solder resist layer 70 is formed on the second resin insulating layer 150.

The pad 60P and the first conductor pattern 58 are connected via a first via conductor 60 formed in the first resin insulation layer 50. The first conductor pattern 58 and the second conductor pattern 158 are connected via a second via conductor 160 formed in the second resin insulation layer 150. First bumps 76 made of solder are formed on the second conductor pattern 158 through the openings 71 of the solder resist layer 70. The solder bumps 76 connect the pads 92 of the first semiconductor element 90A and the second semiconductor element 90B. A second bump 77 made of solder is formed on the pad 60 </ b> P at the bottom of the first via conductor 60.

The first resin insulation layer 50 and the second resin insulation layer 150 are a thermosetting resin, a photosensitive resin, a resin in which a photosensitive group is added to a part of the thermosetting resin, a thermoplastic resin, or these resins. Is a layer made of a resin composite or the like. The sealing resin 96 is made of an epoxy resin containing an inorganic filler such as silica and alumina having an average particle diameter of 4 μm, and the thermal expansion coefficient is adjusted to 20 ppm / ° C. or less.

The wiring board 20 includes a first region ED1 positioned immediately below the first semiconductor element 90A and the second semiconductor element 90B, and a second region ED2 positioned between the first semiconductor element 90A and the second semiconductor element 90B. have.
Immediately below the first region ED1 of the first semiconductor element 90A and the first region ED1 of the second semiconductor element 90B, the pitch P2 of the second bumps 77 is about 150 μm. In the second region ED2 between the first semiconductor element 90A and the second semiconductor element 90B, the pitch P2 of the second bumps 77 is about 90 μm. The bump 77D provided in the second region ED2 may be a signal bump, a ground bump, or a power bump, or a dummy bump that does not function in any of them. The second bumps 77 are all 45 μm in diameter and have the same diameter, that is, the same volume. Here, the distance D1 between the first semiconductor element 90A and the second semiconductor element 90B is about 200 μm, and the first semiconductor element 90A and the second semiconductor element 90B are formed to be 10 mm to 20 mm □.

FIG. 7 shows a state in which the electronic component 100 is mounted on the printed wiring board 200.
The printed wiring board 200 is formed on the core substrate 230 including the through-hole conductors 236, the interlayer resin insulating layer 250 including the via conductors 260 and the conductor patterns 258 formed on the core substrate, and the interlayer resin insulating layer 250. And an interlayer resin insulation layer 350 having via conductors 360 and conductor patterns 358. A solder resist layer 270 is provided on the interlayer resin insulation layer 250, and the pad 358P is exposed through the opening 271 of the solder resist layer. Solder bumps 272 for connecting to an external substrate are formed on the pad 358P on the lower surface side. The electronic component 100 is mounted on the pad 358 </ b> P on the upper surface side via the second bump 77.

In the electronic component of the embodiment, the first semiconductor element 90A, which is made of silicon or the like and has high rigidity, the first semiconductor element 90A that is reinforced by the second semiconductor element 90B, and the second bumps of the first region ED1 immediately below the second semiconductor element 90B. The pitch P1 of the second bumps 77 located in the second region ED2 between the semiconductor elements not reinforced by the semiconductor elements is narrower than the pitch P2 of 77 (per unit area of the solder bumps located in the first region ED1). Is less than the number of solder bumps located in the second region ED2 per unit area). Here, in the second region ED <b> 2 of the wiring board 20, the restraint of the semiconductor element is relatively weak and easily affected by the stress according to the thermal history. By providing many second bumps 77 in the second region ED2 where the influence of such thermal stress is relatively large, the stress relaxation effect through the second bumps is exhibited. As a result, the stress generated in the second region ED2 of the wiring board is reduced, and the occurrence of cracks in the conductor pattern existing in the second region is easily suppressed.

In the electronic component of the first embodiment, the volume of the second bump 77 in the first region ED1 is substantially the same as the volume of the second bump 77 in the second region ED2. By making the volume of the second bump uniform, thermal stress is uniformly generated for each bump. For this reason, it is easy to avoid problems such as thermal stress concentration on an arbitrary bump and cracks in the bump.

In the electronic component of the embodiment, the thickness of the wiring board 20 is 80 μm which is 100 μm or less. For this reason, the wiring length is short and suitable for high-speed operation of the semiconductor element. Here, the pitch P2 of the second bumps 77 in the first region ED1 is preferably 150 μm or less, and the pitch P1 of the second bumps 77 located in the second region ED2 is preferably 90 μm or less from the request of a fine pitch.

The melting point of the low melting point material such as solder forming the second bump 77 is lower than the melting point of the low melting point material forming the first bump 76. When the second bump is melted when the electronic component is mounted on the mother board, the first bump is not affected, and there is no possibility of reducing the connection reliability of the semiconductor element.

In the electronic component of the first embodiment, since the thermal expansion coefficient of the sealing resin 96 is as low as 20 ppm / ° C. or less, the thermal stress due to the sealing resin is further reduced, and uneven deformation due to the difference in thermal expansion coefficient is suppressed. Is done.

The difference in thermal expansion coefficient between the sealing resin 96 and the first semiconductor element 90A and the second semiconductor element 90B is desirably 30 ppm or less. Since the difference in coefficient of thermal expansion is small, the amount of warpage and deflection caused by the difference in thermal expansion is small, and cracks are hardly formed in the sealing resin.

In the electronic component of the first embodiment, the sealing resin 96 that seals the first semiconductor element 90A and the second semiconductor element 90B is also present between the first semiconductor element 90A and the second semiconductor element 90B and the wiring board 20. Filled. Since the wiring board is covered with the sealing resin having a lower thermal expansion coefficient than the underfill resin, the thermal stress caused by the sealing resin that can be applied to the wiring board is relatively small. For this reason, even if it is the wiring board 20 whose thickness is 100 micrometers or less, the edge part of a wiring board becomes difficult to warp, and the disconnection and peeling of a conductor pattern are suppressed. Further, the outermost resin insulation layer forming the wiring board is provided with a recess, and the total volume of the resin is reduced accordingly. As a result, the amount of warping at the end of the wiring board can be further reduced.

When the dummy bump 77D is provided in the second region ED2 between the semiconductor elements, the connection strength with the printed wiring board 200 can be increased by the dummy bump 77D. By providing many bumps in the second region where the influence of thermal stress is relatively large, the stress relaxation effect via the bumps is exhibited.

The manufacturing method of the electronic component of embodiment is shown by FIGS.
(1) First, a glass plate 30 having a thickness of about 1.1 mm is prepared (FIG. 1A).
The glass plate has a CTE of about 3.3 (ppm) or less so that the difference in coefficient of thermal expansion from the mounted silicon IC chip is small. It is desirable that the transmittance is 90% or more.

(2) A release layer 32 mainly made of a thermoplastic polyimide resin is provided on the glass plate 30 (FIG. 1B).

(3) The first insulating layer 50 is formed on the release layer 32 (FIG. 1C).

(4) An electrode body opening 51 that penetrates the first insulating layer 50 and reaches the release layer 32 is provided by a CO2 gas laser (see FIG. 1D).

(5) A conductor layer 52 made of TiN, Ti, and Cu is formed on the first insulating layer 50 by sputtering (FIG. 2A).

(6) A commercially available photosensitive dry film is affixed on the conductor layer 52, and after the photomask film is placed and exposed, it is developed with sodium carbonate to provide a plating resist 54 having a thickness of about 15 μm. (FIG. 2 (B)).

(7) Using the conductor layer 52 as a power feeding layer, electrolytic plating is performed to form an electrolytic plating film 56 (FIG. 2C).

(8) The plating resist 54 is peeled and removed. Then, the conductor layer 52 under the peeled plating resist is removed, and the first conductor pattern 58 and the first via conductor 60 including the conductor layer 52 and the electrolytic plating film 56 are formed (FIG. 2D).

(9) In the same manner as (3) to (8) above, the second resin insulation layer 150, the first conductor pattern 158, and the second via conductor 160 are formed on the first resin insulation layer 50 and the first conductor pattern 58. (FIG. 3A, FIG. 3B, FIG. 3C).

(10) A solder resist layer 70 having an opening 71 is formed (FIG. 3D).

(11) By forming the first bumps 76 with solder in the openings 71 of the solder resist layer 70, the intermediate body 100α is manufactured (FIG. 3E). This intermediate 100α is formed of a glass plate 30 and a wiring board 20 formed on the glass plate 30.

(12) The first semiconductor element 90A and the second semiconductor element 90B are mounted on the intermediate body 100α via the first bumps 76 (FIG. 4A). At this time, since the glass plate 30 has a thermal expansion coefficient close to that of the first semiconductor element 90A and the second semiconductor element 90B, the stress applied to the wiring board 20 is reduced.

(13) In the mold, the first semiconductor element 90A and the second semiconductor element 90B are sealed with a sealing resin 96 made of an epoxy resin containing a silica filler (FIG. 4B). At this time, the sealing resin 96 is filled between the first semiconductor element 90 </ b> A, the second semiconductor element 90 </ b> B, and the wiring board 20.

(14) A laser beam of 308 nm is transmitted through the glass plate 30 and irradiated to the release layer 32, and the release layer 32 is softened. And the glass plate 30 is slid with respect to the wiring board 20 (FIG. 5 (A)), and the glass plate 30 peels (FIG. 5 (B)).

(15) The peeling layer 32 is removed by ashing, and the pad 60P constituted by the bottom of the via conductor 60 is exposed (FIG. 5C).

(16) The second bump 77 and the dummy bump 77D are formed on the pad 60P, and the electronic component 100 is completed (FIG. 6). As described above, the pitch P2 of the second bumps 77 is about 150 μm in the first region ED1, and the pitch P2 of the second bumps 77 is about 90 μm in the second region ED2.

(17) The electronic component 100 is mounted on the printed wiring board 200 through the second bumps 77 by reflow (FIG. 7). At this time, the pitch P1 of the second bumps 77 located in the second region ED2 that is relatively weak in the restraint of the semiconductor element and is easily affected by the stress according to the thermal history is set to be relatively narrow. As a result, a relatively large number of second bumps 77 can be provided in the second region ED2, and thermal stress generated in the second region ED2 can be easily relaxed.
Further, as described above, the melting point of the low melting point material such as solder forming the second bump 77 is lower than the melting point of the low melting point material forming the first bump 76. When the second bump is melted when the electronic component is mounted on the mother board, the first bump is not affected, and there is no possibility of reducing the connection reliability of the semiconductor element.

In the above-described embodiment, an example in which two semiconductor elements are mounted on an electronic component has been described. However, the configuration of the present invention can be applied to solder bumps between semiconductor elements even when three or more semiconductor elements are mounted. The effect can be achieved by narrowing the pitch.

DESCRIPTION OF SYMBOLS 10 Electronic component 20 Wiring board 50 1st insulating layer 58 1st wiring pattern 60 1st via conductor 76 1st bump 77 2nd bump 90A 1st semiconductor element 90B 2nd semiconductor element 96 Sealing resin 200 Printed wiring board ED1 1st Area ED2 Second area

Claims (11)

A wiring board having a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, the wiring board comprising a first surface and a second surface opposite to the first surface;
A first bump provided on the conductor pattern on the first surface side;
A second bump provided on the conductor pattern on the second surface side;
A first semiconductor element and a second semiconductor element mounted on the wiring board via the first bump;
An electronic component comprising:
The wiring board includes a first region located immediately below the first semiconductor element and the second semiconductor element on the second surface side, and a first area located between the first semiconductor element and the second semiconductor element. Two regions,
The pitch of the second bumps located in the second region is smaller than the pitch of the second bumps located in the first region. The electronic component of claim 1, wherein:
The number of second bumps located in the second region per unit area is larger than the number of second bumps located in the first region per unit area. The electronic component of claim 1, wherein:
The pitch of the second bumps located in the first region is 150 μm or less, and the pitch of the second bumps located in the second region is 90 μm or less. The electronic component of claim 1, wherein:
The volume of the second bump in the first area is substantially the same as the volume of the second bump in the second area. The electronic component of claim 2, wherein:
The first semiconductor element and the second semiconductor element are sealed with a sealing resin,
The sealing resin is filled between the first semiconductor element, the second semiconductor element, and the wiring board. The electronic component of claim 5, wherein:
The thermal expansion coefficient of the sealing resin is 20 ppm / ° C. or less. The electronic component of claim 1, wherein:
The second bump located in the second region includes a dummy bump. The electronic component of claim 1, wherein:
The wiring board has a thickness of 100 μm or less. The electronic component of claim 1, wherein:
The melting point of the material forming the second bump is lower than the melting point of the material forming the first bump. A wiring board having a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, the wiring board comprising a first surface and a second surface opposite to the first surface;
A first bump provided on the conductor pattern on the first surface side;
A second bump provided on the conductor pattern on the second surface side;
A first semiconductor element and a second semiconductor element mounted on the wiring board via the first bump;
A method of manufacturing an electronic component comprising:
The wiring board includes a first region located immediately below the first semiconductor element and the second semiconductor element on the second surface side, and a first area located between the first semiconductor element and the second semiconductor element. Two regions,
The pitch of the second bumps located in the second region is made smaller than the pitch of the second bumps located in the first region. A method of manufacturing an electronic component according to claim 9, wherein:
The number of second bumps located in the second region per unit area is made larger than the number of second bumps located in the first region per unit area.

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